Charging delay reset circuit and electronic device

Abstract

The utility model relates to delay reset circuit technology discloses a charging delay reset circuit and electronic equipment, include: internal power supply end, external power supply end, first resistance, second resistance, third resistance, fourth resistance, fifth resistance, first electric capacity, second electric capacity, NMOS pipe, triode and reset output end, external power supply end is connected NMOS pipe's grid through first resistance, first electric capacity electrically in proper order, NMOS pipe's source is grounded, and second resistance is connected between NMOS pipe's grid and source, internal power supply end is connected triode's base through third resistance, second electric capacity, fourth resistance in proper order, MOS pipe's drain is connected between third resistance and second electric capacity, one end of fifth resistance is connected between second electric capacity and fourth resistance, the other end is grounded, triode's first conduction end is grounded, and triode's second conduction end is connected reset output end electrically, the utility model aims at providing a low cost, no dead machine risk's charging delay reset circuit.

Description

Technical Field

[0001] This utility model relates to the field of time-delay reset circuit technology, and in particular to a charging time-delay reset circuit and electronic device. Background Technology

[0002] During device charging, a reset operation is often required to ensure stable and reliable system operation. A reset restores the various modules of the electronic device to their initial state, clearing any abnormal data and errors, thus ensuring the device can start and function normally after charging.

[0003] Currently, charging reset circuits improve system stability and reliability by setting a certain delay time to allow the charging power supply to stabilize first, while also giving the various modules inside the device enough time to initialize and self-test before performing the reset operation.

[0004] However, existing delay-reset circuits suffer from problems such as complex structure and high cost. These circuits often require multiple integrated circuit chips or complex logic circuits to implement the delay function, which not only increases the design difficulty and manufacturing cost of the circuit, but also means that in practical applications, if the delay-reset circuit controlled by the chip malfunctions due to factors such as chip performance or external environment, the delay-reset function will not be triggered.

[0005] The above content is only used to help understand the technical solution of this utility model and does not represent an admission that the above content is prior art. Utility Model Content

[0006] This invention proposes a charging delay reset circuit and electronic device, aiming to provide a low-cost charging delay reset circuit with no risk of system crash.

[0007] To achieve the above objectives, this utility model proposes a charging delay reset circuit, comprising: an internal power supply terminal, an external power supply terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, an NMOS transistor, a transistor, and a reset output terminal; The external power supply terminal is connected to the gate of the NMOS transistor in sequence through the first resistor and the first capacitor. The source of the NMOS transistor is grounded, and the second resistor is connected between the gate and the source of the NMOS transistor. The internal power supply terminal is connected to the base of the transistor in sequence through the third resistor, the second capacitor, and the fourth resistor. The drain of the MOSFET is connected between the third resistor and the second capacitor. One end of the fifth resistor is connected between the second capacitor and the fourth resistor, and the other end of the fifth resistor is grounded. The first conducting terminal of the transistor is grounded, and the second conducting terminal of the transistor is electrically connected to the reset output terminal; the external power supply terminal is used to connect to the charging interface.

[0008] Optionally, the second resistor is an adjustable resistor.

[0009] Optionally, the second capacitor is an adjustable capacitor; And / or, the fourth resistor is an adjustable resistor; And / or, the fifth resistor is an adjustable resistor.

[0010] This invention further proposes an electronic device, including the charging delay reset circuit described above.

[0011] Optionally, the electronic device further includes a device chip, one pin of which is electrically connected to the reset output terminal of the charging delay reset circuit; the pin is internally provided with a pull-up resistor.

[0012] Optionally, the electronic device further includes a power module and a charging interface; the output terminal of the power module is electrically connected to the internal power supply terminal of the charging delay reset circuit, and the charging / discharging terminal of the power module and the external power supply terminal of the charging delay reset circuit are both electrically connected to the charging interface.

[0013] Optionally, the charging interface is a USB interface.

[0014] Optionally, the power supply module is powered by a lithium battery.

[0015] The beneficial effects of this utility model are as follows: It proposes a low-cost charging delay reset circuit with no risk of system crash, consisting only of an internal power supply terminal, an external power supply terminal, multiple resistors, capacitors, NMOS transistors, transistors, and a reset output terminal. Compared with existing designs that require multiple integrated circuit chips or complex logic circuits, it greatly simplifies the circuit design and reduces the difficulty of circuit design. In terms of cost, since it uses common and inexpensive electronic components, it avoids the use of expensive chips and effectively reduces manufacturing costs. In terms of reliability, based on the combination of basic electronic components, it is less affected by factors such as chip performance and external environment, and is less likely to fail to trigger the delay reset due to system crash.

[0016] This charging delay reset circuit cleverly achieves the charging delay reset function through reasonable RC delay and component combination, which can ensure stable and reliable reset operation of the device during the charging process, and ensure normal start-up and operation of the device after charging. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the charging delay reset circuit of this utility model; Figure 2 This is a schematic diagram of the structure of an embodiment of the electronic device of this utility model.

[0018] Explanation of reference numerals in the attached figures: R5: Fifth resistor C1: First capacitor C2: Second capacitor Q1: NMOS transistor Q2: Transistor RST: Reset output terminal VBUS: External power supply terminal VCC: Internal power supply terminal GND: Ground wire The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] The solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0020] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this utility model are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0021] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0022] Furthermore, descriptions involving terms such as "first" and "second" in this utility model are for descriptive purposes only (e.g., to distinguish identical or similar elements) and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, technical solutions from different embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If a combination of technical solutions is contradictory or impossible to implement, such a combination should be considered nonexistent and not within the scope of protection claimed by this utility model.

[0023] This utility model proposes a charging delay reset circuit, referring to... Figure 1 The charging delay reset circuit includes: internal power supply terminal VCC, external power supply terminal VBUS, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, first capacitor C1, second capacitor C2, NMOS transistor Q1, transistor Q2 and reset output terminal RST. The external power supply terminal VBUS is connected to the gate of NMOS transistor Q1 via the first resistor R1 and the first capacitor C1 in sequence. The source of NMOS transistor Q1 is grounded, and the second resistor R2 is connected between the gate and the source of NMOS transistor Q1. The internal power supply terminal VCC is connected to the base of transistor Q2 in sequence through the third resistor R3, the second capacitor C2, and the fourth resistor R4. The drain of the MOSFET is connected between the third resistor R3 and the second capacitor C2. One end of the fifth resistor R5 is connected between the second capacitor C2 and the fourth resistor R4, and the other end of the fifth resistor R5 is grounded. The first conducting terminal of transistor Q2 is grounded, and the second conducting terminal of transistor Q2 is electrically connected to the reset output terminal RST; the external power supply terminal VBUS is used to connect to the charging interface.

[0024] In this embodiment, the external power supply terminal VBUS is used to connect to the charging interface, providing external power to the circuit when the charging device is connected. This power supply is mainly used to control the conduction state of the NMOS transistor Q1, thereby affecting the subsequent delay and reset processes.

[0025] The internal power supply terminal VCC provides a stable power supply to the delay and reset control parts in the circuit, ensuring that components such as transistor Q2 can work normally, and is the energy source for generating the reset signal.

[0026] The first resistor R1 is connected between the external power supply terminal VBUS and the first capacitor C1. Its function is to limit the charging current of the first capacitor C1 to prevent excessive charging current from damaging the circuit. At the same time, together with the first capacitor C1, it determines the charging time constant of the first capacitor C1.

[0027] The first capacitor C1 and the first resistor R1 are connected in series to the gate of the NMOS transistor Q1. At the start of charging, the external power supply charges the capacitor through the first resistor R1. As charging progresses, the voltage across the capacitor gradually increases. When the voltage reaches the turn-on voltage of the NMOS transistor Q1, the NMOS transistor Q1 will turn on.

[0028] The second resistor R2 is connected between the gate and source of the NMOS transistor Q1, providing a discharge path for the first capacitor C1, enabling the first capacitor C1 to discharge quickly and ensuring that the NMOS transistor Q1 is reliably turned off.

[0029] The third resistor R3 is connected between the internal power supply terminal VCC and the second capacitor C2, which limits the charging current of the internal power supply terminal VCC to the second capacitor C2.

[0030] The second capacitor C2 is connected to the base of transistor Q2 via the fourth resistor R4. Its charging process determines the rise rate of the base voltage of transistor Q2, thereby affecting the conduction state of transistor Q2.

[0031] The fourth resistor R4 is connected between the second capacitor C2 and the base of the transistor Q2, which limits the current and prevents excessive current from flowing into the base of the transistor Q2, thus protecting the transistor Q2 from damage.

[0032] The fifth resistor R5 is connected at one end between the second capacitor C2 and the fourth resistor R4, and at the other end to ground GND. The fifth resistor R5 is a pull-down resistor, which ensures that the base of transistor Q2 is at a low level under normal conditions, such as no charging or other abnormalities, so that transistor Q2 is reliably turned off.

[0033] The gate of NMOS transistor Q1 is connected to the first capacitor C1, the source is connected to ground GND, and the drain is connected between the third resistor R3 and the second capacitor C2. When the first capacitor C1 charges and the gate-source voltage reaches the turn-on voltage, NMOS transistor Q1 turns on, shorting the second capacitor C2 to ground, causing the second capacitor C2 to discharge rapidly. When the first capacitor C1 discharges and the gate-source voltage falls below the turn-on voltage, NMOS transistor Q1 turns off, without affecting the charging process of the second capacitor C2.

[0034] The first conducting terminal of transistor Q2 is connected to ground GND, and its base is connected to the second capacitor C2 through the fourth resistor R4. The second conducting terminal is connected to the reset output terminal RST. The conduction and cutoff states of transistor Q2 are controlled by the base voltage. It conducts when the base voltage reaches a certain value, and is cut off otherwise. The reset function is achieved by outputting different level signals through the second conducting terminal.

[0035] The reset output terminal RST is connected to the second conducting terminal of transistor Q2. The reset output terminal RST is also connected to the relevant device (not shown in the figure) that requires delayed reset, and is used to output a reset signal.

[0036] When a low-level reset is required, transistor Q2 can be an NPN transistor, with its emitter as the first conducting terminal and its collector as the second conducting terminal. Thus, when transistor Q2 is off, it outputs a high-level signal; when it is on, it outputs a low-level signal. To achieve a high-level reset, the polarity of the reset signal can be reversed by changing the wiring of transistor Q2. For example, transistor Q2 can be a PNP transistor, with its emitter as the first conducting terminal and its collector as the second conducting terminal. When the PNP transistor is off, the reset output RST outputs a low-level signal; when it is on, the reset output RST outputs a high-level signal, thus achieving a high-level reset.

[0037] The input voltage of the external power supply terminal VBUS is greater than the turn-on voltage of the NMOS transistor Q1 (for example, since the turn-on voltage of the NMOS transistor Q1 is generally less than 4V, the external input voltage can be 5V). The parameters of the first RC circuit unit composed of the first resistor R1 and the first capacitor C1 only need to meet the requirement of accommodating the input voltage. This indicates that when designing the parameters of the first resistor R1 and the first capacitor C1, it is necessary to ensure that the first capacitor C1 will not be broken down due to excessively high input voltage, and that the first resistor R1 can withstand the corresponding power.

[0038] Similarly, the input voltage of the internal power supply terminal VCC must also be greater than the turn-on voltage of transistor Q2.

[0039] The following example uses a low-level reset signal output. Transistor Q2 is an NPN transistor, with its emitter as the first conducting terminal and its collector as the second conducting terminal. This illustrates the working principle of the charging delay reset circuit. When there is no power input at the external power supply terminal VBUS, the voltage of the first capacitor C1 near the NMOS transistor Q1 is less than the turn-on voltage of the NMOS transistor Q1, so the NMOS transistor Q1 is turned off. At this time, although the internal power supply terminal VCC can provide input voltage, because the second capacitor C2 and the fourth resistor R4 are grounded through the fifth resistor R5, the base voltage of the transistor Q2 will be pulled low, causing the transistor Q2 to turn off, and the reset output terminal RST will output a high level.

[0040] When the external power supply terminal VBUS is connected to the charging interface to start charging, the external power supply charges the first capacitor C1 through the first resistor R1. The voltage on the side of the first capacitor C1 closest to the external power supply terminal VBUS immediately becomes the external input voltage. Since the voltage difference across the capacitor cannot change abruptly, the voltage on the side of the first capacitor C1 closest to the NMOS transistor Q1 also becomes the external input voltage, causing the NMOS transistor Q1 to conduct. Since the source of the NMOS transistor Q1 is grounded, the voltage on the side of the second capacitor C2 closest to the NMOS transistor Q1 will then become low.

[0041] Subsequently, the second resistor R2 discharges, and the voltage of the first capacitor C1 near the NMOS transistor Q1 slowly decreases. When the voltage of the first capacitor C1 near the NMOS transistor Q1 is lower than the turn-on voltage of the NMOS transistor Q1, the NMOS transistor Q1 is turned off. At this time, due to the internal input voltage of the internal power supply terminal VCC, the voltage of the second capacitor C2 near the NMOS transistor Q1 will jump to a high level.

[0042] Because the voltage on the side of the second capacitor C2 closest to the NMOS transistor Q1 suddenly becomes high, and the voltage difference across the capacitor cannot change abruptly, the voltage on the side of the second capacitor C2 closest to the transistor Q2 will also become high, thus turning on the transistor Q2. Since the first conducting terminal of the transistor Q2 is connected to ground GND, the reset output terminal RST outputs a low level, thereby resetting the relevant devices connected to the reset output terminal RST.

[0043] Subsequently, the second capacitor C2 will gradually discharge through the grounded fifth resistor R5, while the fourth resistor R4 will also gradually discharge through the first conducting terminal of transistor Q2. This causes the voltage on the side of the second capacitor C2 closest to transistor Q2 to gradually decrease. When the voltage on the side of the second capacitor C2 closest to transistor Q2 is lower than the conduction voltage of transistor Q2, transistor Q2 will be turned off, and the reset output terminal RST will resume a high-level output. This will end the reset state of the relevant devices connected to the reset output terminal RST, thus completing the charging delay reset process.

[0044] As can be seen from the above charging delay reset process, the discharge rate of the voltage on the side of the second capacitor C2 closest to the transistor Q2 determines the reset duration. Therefore, by adjusting the values ​​of the second capacitor C2, the fifth resistor R5, and / or the fourth resistor R4, the discharge rate of the second capacitor C2 can be adjusted, indirectly adjusting the duration of the low-level signal output at the reset output terminal RST. Thus, the values ​​of the second capacitor C2, the fifth resistor R5, and / or the fourth resistor R4 can be selected according to the actual device's required reset duration; this embodiment does not impose any limitations on this. For example, with the resistance value unchanged, increasing the value of the second capacitor C2 slows down the capacitor's discharge rate, and conversely, decreasing the value of the second capacitor C2 speeds up the discharge rate. The fifth resistor R5 is one of the main discharge paths of the second capacitor C2; increasing the fifth resistor R5 slows down the discharge rate and increases the reset duration, and conversely, decreasing the fifth resistor R5 speeds up the discharge rate and shortens the reset duration. The fourth resistor R4 is another discharge path of the second capacitor C2; increasing the fourth resistor R4 slows down the discharge rate and increases the reset duration, and conversely, decreasing the fourth resistor R4 speeds up the discharge rate and shortens the reset duration.

[0045] Simultaneously, the discharge rate of the voltage on the side of the first capacitor C1 closest to the NMOS transistor Q1 can be adjusted via the second resistor R2, thereby adjusting the conduction duration of the NMOS transistor Q1 and indirectly adjusting the delay before the reset output terminal RST outputs a low-level signal. Therefore, the specific value of the second resistor R2 is selected according to the required delay time between the charging connection and the start of the reset, and this embodiment does not impose any limitations on this. For example, if a longer delay time is required, the resistance value of the second resistor R2 can be increased; if a shorter delay time is required, the resistance value of the second resistor R2 can be decreased.

[0046] In this way, external power supply insertion detection is achieved through resistors, capacitors, MOSFETs, and transistor Q2; pulse voltage output is achieved through an RC circuit; and pulse delay output is achieved through an RC delay circuit. Furthermore, the use of discrete components avoids the problems of difficult component selection and high costs. The pure circuit design avoids the system crashes that might occur when using a main control chip to control the delay.

[0047] In one embodiment, a low-cost, crash-free charging delay reset circuit is proposed, consisting only of an internal power supply terminal VCC, an external power supply terminal VBUS, multiple resistors, capacitors, an NMOS transistor Q1, a transistor Q2, and a reset output terminal RST. Compared to existing designs that require multiple integrated circuit chips or complex logic circuits, this greatly simplifies the circuit design and reduces the difficulty of circuit design. In terms of cost, since common and inexpensive electronic components are used, expensive chips are avoided, effectively reducing manufacturing costs. In terms of reliability, based on the combination of basic electronic components, it is less affected by chip performance and external environmental factors, and is less likely to fail to trigger the delay reset due to a crash.

[0048] This charging delay reset circuit cleverly achieves the charging delay reset function through reasonable RC delay and component combination, which can ensure stable and reliable reset operation of the device during the charging process, and ensure normal start-up and operation of the device after charging.

[0049] In one embodiment, the second resistor R2 is an adjustable resistor.

[0050] In this embodiment, the required delay time from charging input to the start of reset varies in different electronic devices. By setting the second resistor R2 as an adjustable resistor, it can be flexibly adjusted according to specific needs. For devices with high reset delay requirements, requiring a longer time for the charging power supply to stabilize and for internal modules to complete initialization and self-testing, the value of the second resistor R2 can be increased to extend the conduction time of the NMOS transistor Q1, thereby extending the delay time before the reset output terminal RST outputs a low-level signal. Conversely, if the device requires a shorter delay, decreasing the value of the second resistor R2 will quickly trigger the reset operation.

[0051] Different types and specifications of electronic devices have varying circuit characteristics and reset requirements. The adjustable second resistor R2 allows this charging delay reset circuit to be adapted to a variety of devices. There's no need to redesign the entire circuit for different devices; simply adjusting the value of the second resistor R2 allows the circuit to meet the delay reset requirements of various devices, greatly improving the circuit's versatility and applicability.

[0052] In one embodiment, based on the above embodiment, the second capacitor C2 is an adjustable capacitor; And / or, the fourth resistor R4 is an adjustable resistor; And / or, the fifth resistor R5 is an adjustable resistor.

[0053] In this embodiment, different electronic devices have significantly different requirements for reset duration. For example, some complex and large devices may require a longer reset time to ensure that each module can complete initialization and self-test; while some small and simple devices only require a shorter reset time. By adjusting the adjustable second capacitor C2, the fourth resistor R4, or the fifth resistor R5, the duration of the low-level signal output at the reset output terminal RST can be precisely adjusted, allowing the circuit to be flexibly adapted to the actual needs of specific devices, thus improving the circuit's versatility and applicability.

[0054] During the circuit development and debugging phase, engineers often need to experiment with different reset times to find the optimal operating state of the device. Adjustable capacitors and resistors provide great convenience, allowing engineers to quickly change their parameters and observe the circuit response and device operation. Timely adjustments and optimizations based on test results avoid repeated circuit design modifications caused by fixed parameters, significantly improving development efficiency and reducing development costs.

[0055] This utility model further proposes an electronic device, which includes a charging delay reset circuit. The specific structure of the charging delay reset circuit is as described in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the technical effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0056] In one embodiment, based on the above embodiments, referring to Figure 2 The electronic device also includes a device chip, one pin of which is electrically connected to the reset output terminal RST of the charging delay reset circuit; the pin is internally provided with a pull-up resistor.

[0057] In this embodiment, when the charging delay reset circuit operates as described previously, transistor Q2 turns on after the delay, causing a change in the RST level of the reset output terminal. Since the device chip pin has an internal pull-up resistor, this pin is normally at a high level. When the RST level of the reset output terminal changes, it affects the level state of the device chip pin.

[0058] If the charging delay reset circuit outputs a low level, it will pull down the level of the connected device chip pin, thereby triggering the device chip's reset operation, restoring the device chip to its initial state, and clearing any possible abnormal data and error states.

[0059] The presence of pull-up resistors ensures that the pin remains at a stable high level when no reset signal is received, preventing false resets caused by abnormal pin level fluctuations due to external interference or other factors. Furthermore, combined with the delay function of the charging delay reset circuit, the reset is performed only after the charging power supply has stabilized and the internal modules of the device have completed initialization and self-testing, further ensuring the stability and reliability of the electronic equipment system.

[0060] In one embodiment, based on the above embodiments, referring to Figure 2 The electronic device further includes a power module and a charging interface; the output terminal of the power module is electrically connected to the internal power supply terminal VCC of the charging delay reset circuit, and the charging and discharging terminals of the power module and the external power supply terminal VBUS of the charging delay reset circuit are both electrically connected to the charging interface.

[0061] In this embodiment, when the charging interface is connected to an external charging power source, the external power source charges the power module through the charging interface, enabling the power module to store energy. On the other hand, the external power source supplies power to the external power supply terminal VBUS of the charging delay reset circuit through the charging interface.

[0062] Upon receiving external power, the charging delay reset circuit, based on the characteristics of its internal delay circuit composed of resistors, capacitors, NMOS transistor Q1, and transistor Q2, begins a delay operation. During this process, the external power supply charges the first capacitor C1 through the first resistor R1. After a certain delay, once the charging power supply stabilizes and the internal modules of the device have completed initialization and self-test, the charging delay reset circuit outputs a reset signal.

[0063] The reset output terminal RST of the charging delay reset circuit transmits the reset signal to the pin of the device chip. Since the pin has an internal pull-up resistor, the reset signal will change the level state of the pin, thereby triggering the reset operation of the device chip, restoring the device chip to the initial state, and clearing any possible abnormal data and error states.

[0064] After the reset operation is completed, the device chip starts up normally and begins to work. The power module continuously provides stable power to all parts of the device to ensure the normal operation of the electronic equipment.

[0065] In one embodiment, the delay function of the charging delay reset circuit ensures that the reset operation is performed only after the charging power supply has stabilized, avoiding reset anomalies caused by power instability and improving system stability. Even if the device chip experiences an anomaly such as a system crash, the charging delay reset circuit, designed independently of the chip's main control, can still operate normally, ensuring the reliability of the reset function. The charging delay reset circuit is constructed using common basic electronic components, eliminating the need for multiple integrated circuit chips and complex logic circuits, thus reducing the design difficulty and manufacturing cost of the circuit.

[0066] Optionally, the charging interface is a USB interface, and the input voltage of the USB interface can be 5V.

[0067] Optionally, the power supply module is powered by a lithium battery. The charging delay reset circuit is applicable to electronic devices where the power supply module is powered by a lithium battery, especially for electronic devices where the lithium battery is inconvenient or non-removable. In products powered by lithium batteries and not removable, this embodiment can briefly power off or reset the internal circuitry to prevent the electronic product from freezing.

[0068] The above description is only a part or preferred embodiment of this utility model. Neither the text nor the drawings should limit the scope of protection of this utility model. All equivalent structural transformations made using the content of this utility model specification and drawings under the overall concept of this utility model, or direct / indirect applications in other related technical fields, are included within the scope of protection of this utility model.

Claims

1. A charging delay reset circuit, characterized in that, include: Internal power supply terminal, external power supply terminal, first resistor, second resistor, third resistor, fourth resistor, fifth resistor, first capacitor, second capacitor, NMOS transistor, transistor and reset output terminal; The external power supply terminal is connected to the gate of the NMOS transistor in sequence through the first resistor and the first capacitor. The source of the NMOS transistor is grounded, and the second resistor is connected between the gate and the source of the NMOS transistor. The internal power supply terminal is connected to the base of the transistor in sequence through the third resistor, the second capacitor, and the fourth resistor. The drain of the MOSFET is connected between the third resistor and the second capacitor. One end of the fifth resistor is connected between the second capacitor and the fourth resistor, and the other end of the fifth resistor is grounded; The first conducting terminal of the transistor is grounded, and the second conducting terminal of the transistor is electrically connected to the reset output terminal; the external power supply terminal is used to connect to the charging interface.

2. The charging delay reset circuit as described in claim 1, characterized in that, The second resistor is an adjustable resistor.

3. The charging delay reset circuit as described in claim 1, characterized in that, The second capacitor is an adjustable capacitor; And / or, the fourth resistor is an adjustable resistor; And / or, the fifth resistor is an adjustable resistor.

4. An electronic device, characterized in that, Includes the charging delay reset circuit as described in any one of claims 1-3.

5. The electronic device as claimed in claim 4, characterized in that, The electronic device also includes a device chip, one pin of which is electrically connected to the reset output terminal of the charging delay reset circuit; the pin is internally provided with a pull-up resistor.

6. The electronic device as claimed in claim 4 or 5, characterized in that, The electronic device further includes a power module and a charging interface; the output terminal of the power module is electrically connected to the internal power supply terminal of the charging delay reset circuit, and the charging and discharging terminals of the power module and the external power supply terminal of the charging delay reset circuit are both electrically connected to the charging interface.

7. The electronic device as claimed in claim 6, characterized in that, The charging interface is a USB interface.

8. The electronic device as claimed in claim 6, characterized in that, The power module is powered by a lithium battery.

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