A space-borne platform clock source module

Abstract

The utility model discloses a kind of satellite-borne platform clock source module, it is related to satellite communication field.It includes reference amplification branching unit, local oscillator phase-locked loop unit, clock phase-locked loop unit, clock processing unit and power supply unit, with 100MHz reference input port, 3695MHz first local oscillator signal output port, 3495MHz second local oscillator signal output port, 1568MHz first clock signal output port, 784MHz second clock signal output port, 196MHz third clock signal output port and power interface.The clock source module has the characteristics of compact design and high reliability, is particularly suitable as signal generation module on payload platform.

Description

Technical Field

[0001] This utility model relates to the field of satellite communication, and in particular to a spaceborne platform clock source module, which can be used on a payload platform to provide a local oscillator signal for analog frequency converter boards and a reference clock signal for digital boards. Background Technology

[0002] In recent years, with the rapid development of satellite communication systems, the demand for clock signals on satellite communication payloads has increased significantly. This includes local oscillator signals for analog frequency converters, clock signals for analog-to-digital converters (AD) and digital-to-analog converters (DA) on digital boards, and clock signals for FPGAs. Traditionally, the circuit providing the local oscillator signal is often placed together with the frequency converter circuit, and the circuit providing the clock signal is often placed together with the digital circuits. As a result, the local oscillator signal can contaminate the output signal through power supply and spatial paths, and the clock signal can contaminate the digital signal through the same paths. Utility Model Content

[0003] The purpose of this invention is to overcome the shortcomings of the aforementioned background technology and provide a clock source module for a spaceborne platform. This invention features a compact structure and high reliability.

[0004] The purpose of this utility model is achieved as follows:

[0005] A spaceborne platform clock source module includes a reference amplifier splitter unit, a local oscillator phase-locked unit, a clock phase-locked unit, a clock processing unit, and a power supply unit. It has a 100MHz reference input port, a 3695MHz first local oscillator signal output port, a 3495MHz second local oscillator signal output port, a 1568MHz first clock signal output port, a 784MHz second clock signal output port, a 196MHz third clock signal output port, and a power interface.

[0006] Furthermore, the reference amplification splitter unit includes an amplifier and a three-way power divider. The input terminal of the amplifier is connected to the 100MHz reference input port, the output terminal of the amplifier is connected to the common input terminal of the three-way power divider, the first and second output terminals of the three-way power divider are connected to the local oscillator phase-locked unit, and the third output terminal of the three-way power divider is connected to the clock phase-locked unit.

[0007] Furthermore, the local oscillator phase-locked unit includes a first phase-locked source and a second phase-locked source; the reference input terminal of the first phase-locked source is connected to the first output terminal of the three-way power divider of the reference amplification and splitting unit, and the output terminal is connected to the first local oscillator signal output terminal, with an output local oscillator signal frequency of 3695MHz; the reference input terminal of the second phase-locked source is connected to the second output terminal of the three-way power divider of the reference amplification and splitting unit, and the output terminal is connected to the second local oscillator signal output terminal, with an output local oscillator signal frequency of 3495MHz.

[0008] Furthermore, the clock phase-locked unit includes a third phase-locked source; the reference input terminal of the third phase-locked source is connected to the third output terminal of the three-way power divider of the reference amplifier splitter unit, and all three output terminals of the third phase-locked source are connected to the clock processing unit, with the frequency of the three output signals being 1568MHz.

[0009] Furthermore, the clock processing unit includes three processing channels, wherein:

[0010] The first processing channel is connected to the first output terminal of the clock phase-locked unit, including an amplifier and a low-pass filter, used to amplify and filter the 1568MHz signal, and the output terminal is connected to the first clock signal output port, with an output clock signal frequency of 1568MHz.

[0011] The second processing channel is connected to the second output terminal of the clock phase-locked unit and includes a frequency divider, an amplifier and a low-pass filter. It is used to divide, amplify and filter the 1568MHz signal. The output terminal is connected to the second clock signal output port and the output clock signal frequency is 784MHz.

[0012] The third processing channel is connected to the third output terminal of the clock phase-locked unit and includes an octet divider, amplifier, power divider and filter. It is used to divide, amplify and filter the 1568MHz signal. The output terminal is connected to the third clock signal output port and the output clock signal frequency is 196MHz.

[0013] Furthermore, the power supply unit receives an external +6V power supply, which is converted into +5V DC power by a linear regulator and then supplied to the reference amplification branch unit, the local oscillator phase-locked unit, the clock phase-locked unit, and the clock processing unit.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] This invention integrates the local oscillator signal generation circuit required for the frequency conversion channel and the clock signal circuit required for the digital board, resulting in a compact structure while minimizing signal crosstalk. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of this utility model.

[0017] Figure 2 This is a block diagram of the reference amplifier splitter unit.

[0018] Figure 3 This is the principle block diagram of the local oscillator phase-locked unit.

[0019] Figure 4 This is a block diagram of the principle of a clock phase-locked loop unit.

[0020] Figure 5 This is a block diagram of the clock processing unit. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings.

[0022] A spaceborne platform clock source module, such as Figure 1 As shown, it includes a reference amplification branch unit, a local oscillator phase-locked unit, a clock phase-locked unit, a clock processing unit, and a power supply unit. It has a 100MHz reference input port, a 3695MHz local oscillator signal output port A, a 3495MHz local oscillator signal output port B, a 1568MHz clock signal output port A, a 784MHz clock signal output port B, a 196MHz clock signal output port C, and a power interface.

[0023] like Figure 2 As shown, the reference amplification splitter unit includes an amplifier and a three-way power divider. The amplifier's input is connected to the 100MHz reference input port, and its output is connected to the common input of the three-way power divider. The outputs RF1 to RF3 of the three-way power divider are connected to the local oscillator phase-locked unit and the clock phase-locked unit. In this example, the amplifier is model BW20X, and the three-way power divider is model HE02X.

[0024] like Figure 3 As shown, the local oscillator phase-locked unit includes phase-locked source A and phase-locked source B. Phase-locked source A's reference input is connected to the RF1 output of the three-way power divider within the reference amplifier and splitter unit, and its output is connected to the module's local oscillator signal output terminal A, outputting a local oscillator signal with a frequency of 3695MHz. Phase-locked source B's reference input is connected to the RF2 output of the three-way power divider within the reference amplifier and splitter unit, and its output is connected to the module's local oscillator signal output terminal B, outputting a local oscillator signal with a frequency of 3495MHz. In this example, phase-locked source A is model PLS-3695; phase-locked source B is model PLS-3495.

[0025] like Figure 4As shown, the clock phase-locked unit includes a phase-locked source C. The reference input terminal of the phase-locked source C is connected to the RF3 output terminal of the three-way power divider in the reference amplifier splitter unit. The output terminals RF1 to RF3 of the phase-locked source C are connected to the clock processing unit, and the frequency of the three output signals is 1568MHz. In this example, the model of the phase-locked source C is PLS-1568.

[0026] like Figure 5 As shown, the clock processing unit contains three processing channels, of which:

[0027] The input terminal of processing channel A is connected to the output terminal RF1 of the clock phase-locked unit, which amplifies and filters the 1568MHz signal. The output terminal is connected to the clock signal output port A, and the output clock signal frequency is 1568MHz.

[0028] The input terminal of processing channel B is connected to the output terminal RF2 of the clock phase-locked unit, which performs frequency division, amplification and filtering on the 1568MHz signal. The output terminal is connected to the clock signal output port B, and the output clock signal frequency is 784MHz.

[0029] The input terminal of the processing channel C is connected to the output terminal RF3 of the clock phase-locked unit. It performs frequency division, amplification and filtering on the 1568MHz signal. The output terminal is connected to the clock signal output port C, and the output clock signal frequency is 196MHz.

[0030] In this example, the first processing channel A includes an amplifier and a low-pass filter, wherein the amplifier model is BW55X and the filter model is LPF-1568; the second processing channel B includes a frequency divider, an amplifier, and a low-pass filter, wherein the frequency divider model is BW440, the amplifier model is BW55X, and the filter model is LPF-784; the third processing channel C includes an eight-way frequency divider, an amplifier, a power divider, and a filter, wherein the eight-way frequency divider model is BW442, the amplifier model is BW20X, the power divider model is HEM02X, and the filter model is LPF-198.

[0031] The power supply unit receives an external +6V power supply, which is converted to +5V DC by a linear regulator and then supplies power to the reference amplifier branch unit, local oscillator phase-locked loop unit, clock phase-locked loop unit, and clock processing unit. The linear regulator can be an RSW120X model.

[0032] The components selected for this module must meet the relevant aerospace standards. The total radiation dose resistance of all active devices must be no less than 100 Krad (Si), and the single-particle radiation resistance must be no less than 75 MeV·cm⁻¹. 2 / mg.

[0033] By selecting components that meet aerospace standards and following the principle of minimum safety spacing in circuit design, the module has high reliability.

[0034] Here is a more specific example:

[0035] A spaceborne platform clock source module, such as Figure 1 As shown, it includes a reference amplification branch unit, a local oscillator phase-locked unit, a clock phase-locked unit, a clock processing unit, and a power supply unit.

[0036] The reference splitter amplification unit amplifies and splits the 100MHz reference signal into three channels, which are then fed into the local oscillator phase-locked unit (LOL-LLU) and the clock phase-locked unit (CLL-PLU). The LOL-PLU generates two LO signals required for the frequency conversion channel, namely 3695MHz and 3495MHz. The CLL-PLU generates three 1568MHz clock signals, which are then fed into the clock processing unit. In the clock processing unit, one 1568MHz clock signal is amplified and filtered before being output, another 1568MHz clock signal is divided by two, amplified, and filtered before being output at 784MHz, and the last 1568MHz clock signal is divided by eight, amplified, and filtered before being output at 196MHz.

[0037] like Figure 2 As shown, the reference amplifier splitter unit mainly consists of an amplifier and a three-way power divider. The amplifier gain is 19dB, the output 1dB compression point is 13dBm, and the single-sideband phase noise is -162dBc / Hz@1kHz, -170dBc / Hz@10kHz, and -172dBc / Hz@100kHz. The three-way power divider has a loss of 6dB. The three 100MHz reference signal levels output by the reference amplifier splitter unit must be above 5dBm.

[0038] like Figure 3 As shown, the local oscillator phase-locked unit (PLS) comprises two independent PLSs, model PLS-A and PLS-B. PLS-A uses a 100MHz reference signal, a 5MHz phase detection frequency, an output frequency of 3695MHz, and an output level of 5dBm. PLS-B uses a 100MHz reference signal, a 5MHz phase detection frequency, an output frequency of 3495MHz, and an output level of 5dBm. The isolation between the two local oscillator signals is greater than 50dB.

[0039] like Figure 4 As shown, the clock phase-locked unit mainly includes a phase-locked source PLS-C, which uses 100MHz as a reference signal, has a phase detection frequency of 2MHz, an output frequency of 1568MHz, and an output level of 3dBm.

[0040] like Figure 5As shown, the clock processing unit contains three independent processing channels, which correspond to the three 1568MHz outputs of the clock phase-locked unit.

[0041] Processing channel A amplifies and filters the first 1568MHz output. The amplifier amplifies the 1568MHz input signal, which has a level of only 3dBm, to no less than 10dBm. The filter is a low-pass filter composed of LC discrete components, which mainly filters out the higher harmonics of 1568MHz.

[0042] In this example, to prevent crosstalk between local oscillator signals and between clock signals, the structure is divided into cavities, and discrete LC circuits are used for filtering.

[0043] Processing channel B performs frequency division, amplification, and filtering on the second 1568MHz output. The frequency divider divides the 1568MHz signal into a 784MHz signal; the amplifier amplifies the 784MHz signal, which has a level of only -3dBm, to a level of not less than 10dBm; the filter is a low-pass filter composed of LC discrete components, mainly filtering out the higher harmonics of the 784MHz signal.

[0044] Processing channel C performs an octet division, amplification, and filtering on the second 1568MHz output. The octet divides the 1568MHz signal into a 196MHz signal; the amplifier amplifies the 784MHz signal, which has a level of only -4dBm, to a level of no less than 10dBm; the filter is a low-pass filter composed of LC discrete components, mainly filtering out the higher harmonics of the 196MHz signal.

[0045] The isolation between the three clock signals 1568MHz, 784MHz and 196MHz is greater than 50dB.

[0046] This clock source module features a compact design and high reliability, making it particularly suitable as a signal generation module on a payload platform.

[0047] It should be understood that the above description of the specific embodiments of this patent is merely an exemplary description provided to facilitate understanding of the patent solution by those skilled in the art, and does not imply that the scope of protection of this patent is limited to these specific examples. Those skilled in the art can obtain more specific embodiments without any creative effort by combining technical features, replacing some technical features, adding more technical features, etc., of the various examples listed in this patent, provided that they have a full understanding of the technical solution of this patent. All of these specific embodiments are within the scope of the claims of this patent, and therefore, these new specific embodiments should also be within the scope of protection of this patent.

Claims

1. A clock source module for a spaceborne platform, characterized in that, It includes a reference amplification branch unit, a local oscillator phase-locked unit, a clock phase-locked unit, a clock processing unit, and a power supply unit. It has a 100MHz reference input port, a 3695MHz first local oscillator signal output port, a 3495MHz second local oscillator signal output port, a 1568MHz first clock signal output port, a 784MHz second clock signal output port, a 196MHz third clock signal output port, and a power interface.

2. The spaceborne platform clock source module according to claim 1, characterized in that, The reference amplification splitter unit includes an amplifier and a three-way power divider. The input terminal of the amplifier is connected to the 100MHz reference input port, the output terminal of the amplifier is connected to the common input terminal of the three-way power divider, the first and second output terminals of the three-way power divider are connected to the local oscillator phase-locked unit, and the third output terminal of the three-way power divider is connected to the clock phase-locked unit.

3. A spaceborne platform clock source module according to claim 2, characterized in that, The local oscillator phase-locked unit includes a first phase-locked source and a second phase-locked source; the reference input terminal of the first phase-locked source is connected to the first output terminal of the three-way power divider of the reference amplification and splitting unit, and the output terminal is connected to the first local oscillator signal output terminal, with an output local oscillator signal frequency of 3695MHz; the reference input terminal of the second phase-locked source is connected to the second output terminal of the three-way power divider of the reference amplification and splitting unit, and the output terminal is connected to the second local oscillator signal output terminal, with an output local oscillator signal frequency of 3495MHz.

4. A spaceborne platform clock source module according to claim 2, characterized in that, The clock phase-locked unit includes a third phase-locked source; the reference input terminal of the third phase-locked source is connected to the third output terminal of the three-way power divider of the reference amplifier splitter unit, and all three output terminals of the third phase-locked source are connected to the clock processing unit, with the frequency of the three output signals being 1568MHz.

5. A spaceborne platform clock source module according to claim 1, characterized in that, The clock processing unit includes three processing channels, wherein: The first processing channel is connected to the first output terminal of the clock phase-locked unit, including an amplifier and a low-pass filter, used to amplify and filter the 1568MHz signal, and the output terminal is connected to the first clock signal output port, with an output clock signal frequency of 1568MHz. The second processing channel is connected to the second output terminal of the clock phase-locked unit and includes a frequency divider, an amplifier and a low-pass filter. It is used to divide, amplify and filter the 1568MHz signal. The output terminal is connected to the second clock signal output port and the output clock signal frequency is 784MHz. The third processing channel is connected to the third output terminal of the clock phase-locked unit and includes an octet divider, amplifier, power divider and filter. It is used to divide, amplify and filter the 1568MHz signal. The output terminal is connected to the third clock signal output port and the output clock signal frequency is 196MHz.

6. A spaceborne platform clock source module according to claim 1, characterized in that, The power supply unit receives an external +6V power supply, which is converted into +5V DC power by a linear regulator and then supplied to the reference amplification branch unit, the local oscillator phase-locked unit, the clock phase-locked unit, and the clock processing unit.

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