A router forwarding module supporting multi-protocol identification and priority scheduling

Abstract

The utility model discloses a router forwarding module of support multi-protocol identification and priority scheduling is provided for solving the problem that software operation exists delay in prior art, is difficult to satisfy the real-time transmission demand of key protocol data such as ModbusTCP, IEC104 in electric power scene, which comprises a forwarding module card body, and a protocol identification hardware circuit, a priority marking hardware circuit, a scheduling forwarding hardware circuit and a standard mPCIe interface integrated on the forwarding module card body. The standard mPCIe interface is used for realizing hot plug type hardware connection with the industrial grade router mainboard, the protocol identification hardware circuit is hardware connected with the standard mPCIe interface, the signal output end of the protocol identification hardware circuit is hardware connected with the priority marking hardware circuit, the signal output end of the priority marking hardware circuit is hardware connected with the scheduling forwarding hardware circuit, and the signal output end of the scheduling forwarding hardware circuit is hardware connected with the standard mPCIe interface.

Description

Technical Field

[0001] This utility model relates to the field of network communication equipment technology, and in particular to a router forwarding module that supports multi-protocol identification and priority scheduling. Background Technology

[0002] The router forwarding module is a core functional component of a router, primarily responsible for receiving and processing data streams in the network and forwarding data according to preset rules. It is crucial for ensuring efficient network data transmission. In industrial scenarios, it needs to adapt to specialized protocols in fields such as power and industrial control to ensure stable transmission of business data such as power distribution automation and substation monitoring in the ICT converged network. It is the core carrier for industrial-grade routers to achieve business adaptation.

[0003] Existing router forwarding modules have significant drawbacks: most rely on software to parse protocols and schedule data, resulting in software latency and making it difficult to meet the real-time transmission requirements of critical protocol data such as ModbusTCP and IEC104 in power scenarios; they also lack hardware-level priority scheduling mechanisms, making critical control messages easily blocked by ordinary data; some modules do not support hot-swapping, requiring power outages and router shutdowns during upgrades or maintenance, leading to industrial service interruptions; and protocol library updates depend on modifications to the main platform, resulting in poor flexibility. Utility Model Content

[0004] This invention addresses the problem that software operation delays in existing technologies make it difficult to meet the real-time transmission requirements of critical protocol data such as ModbusTCP and IEC104 in power scenarios. It provides a router forwarding module that supports multi-protocol identification and priority scheduling.

[0005] The technical solution adopted in this utility model is:

[0006] The router forwarding module that supports multi-protocol identification and priority scheduling disclosed in this embodiment includes a forwarding module card body, and a protocol identification hardware circuit, a priority marking hardware circuit, a scheduling and forwarding hardware circuit, and a standard mPCIe interface integrated on the forwarding module card body.

[0007] The standard mPCIe interface is used to achieve hot-swappable hardware connection with the motherboard of an industrial-grade router. The signal input terminal of the protocol identification hardware circuit and the signal output terminal of the standard mPCIe interface are connected by PCB traces. The signal output terminal of the protocol identification hardware circuit and the signal input terminal of the priority marking hardware circuit are connected by PCB traces. The signal output terminal of the priority marking hardware circuit and the signal input terminal of the scheduling and forwarding hardware circuit are connected by PCB traces. The signal output terminal of the scheduling and forwarding hardware circuit and the signal input terminal of the standard mPCIe interface are connected by PCB traces.

[0008] Furthermore, the protocol identification hardware circuit includes a port parsing hardware sub-circuit and a feature code matching hardware sub-circuit. The signal input terminal of the port parsing hardware sub-circuit is hardware-connected to the signal output terminal of the standard mPCIe interface. The signal output terminal of the port parsing hardware sub-circuit is hardware-connected to the signal input terminal of the feature code matching hardware sub-circuit. The signal output terminal of the feature code matching hardware sub-circuit is hardware-connected to the signal input terminal of the priority marking hardware circuit. Multi-protocol differentiation is achieved by parsing the data stream port number and matching the protocol feature code through the hardware circuit.

[0009] Furthermore, the priority labeling hardware circuit includes a QoS tag generation hardware sub-circuit. The signal input terminal of the QoS tag generation hardware sub-circuit is hardware-connected to the signal output terminal of the protocol identification hardware circuit, and the signal output terminal of the QoS tag generation hardware sub-circuit is hardware-connected to the signal input terminal of the scheduling and forwarding hardware circuit. It is used to generate high-priority QoS tags for data streams corresponding to ModbusTCP, IEC104, and DL / T860 protocols.

[0010] Furthermore, the scheduling and forwarding hardware circuit includes a hardware queue group and a queue scheduling hardware sub-circuit. The hardware queue group contains at least one high-priority hardware queue and at least one normal-priority hardware queue. The signal input terminal of the queue scheduling hardware sub-circuit is hardware-connected to the signal output terminal of the priority marking hardware circuit. The queue selection terminal of the queue scheduling hardware sub-circuit is hardware-connected to the enable terminals of the high-priority hardware queue and the normal-priority hardware queue, respectively. The signal output terminals of both the high-priority hardware queue and the normal-priority hardware queue are hardware-connected to the signal input terminals of the standard mPCIe interface.

[0011] Furthermore, it also includes a non-volatile storage hardware circuit, which is integrated on the forwarding module card body. Its data interface is hardware-connected to the storage interface of the protocol identification hardware circuit, and is used to store multi-protocol feature library data. It supports receiving upgrade data through the standard mPCIe interface to realize online updates of the protocol library hardware.

[0012] Furthermore, the standard mPCIe interface integrates a hot-swap control hardware sub-circuit. The power detection terminal of the hot-swap control hardware sub-circuit is hardware-connected to the power supply line of the industrial-grade router motherboard, and the signal buffer terminal of the hot-swap control hardware sub-circuit is hardware-connected to the signal pin of the standard mPCIe interface, enabling power-free plugging and unplugging of the forwarding module card body and the router motherboard.

[0013] Furthermore, the port resolution hardware sub-circuit includes a ModbusTCP dedicated port resolution circuit, and the feature code matching hardware sub-circuit includes an IEC104 feature code comparison circuit and a DL / T860 feature code comparison circuit. The signal output terminals of the ModbusTCP dedicated port resolution circuit, the IEC104 feature code comparison circuit, and the DL / T860 feature code comparison circuit are all hardware-connected to the signal input terminal of the priority marking hardware circuit.

[0014] Furthermore, the queue scheduling hardware sub-circuit includes a priority comparison hardware circuit. The signal input terminal of the priority comparison hardware circuit is hardware-connected to the QoS tag signal output by the priority tag hardware circuit, and the output terminal of the priority comparison hardware circuit is hardware-connected to the priority enable terminal of the high-priority hardware queue, ensuring that the data stream corresponding to the high-priority QoS tag enters the forwarding channel first.

[0015] Furthermore, it also includes a power supply voltage regulation hardware circuit. The power input terminal of the power supply voltage regulation hardware circuit is hardware connected to the power pin of the standard mPCIe interface, and its regulated output terminal is hardware connected to the power input terminals of the protocol identification hardware circuit, priority marking hardware circuit, scheduling and forwarding hardware circuit, and non-volatile storage hardware circuit, respectively, to provide a stable operating voltage.

[0016] Furthermore, the protocol identification hardware circuit, priority marking hardware circuit, and scheduling forwarding hardware circuit are all implemented using FPGA hardware. The signal transmission delay between each hardware circuit is ≤10μs, and the signal transmission rate of the standard mPCIe interface is ≥5Gbps.

[0017] The beneficial effects of this utility model are:

[0018] First, the router forwarding module disclosed in this utility model, which supports multi-protocol identification and priority scheduling, adopts three types of hardware circuits: protocol identification, priority marking, and scheduling forwarding, replacing the traditional software processing method. This avoids software parsing delays. The circuits are directly connected via PCB traces, resulting in a signal transmission delay of ≤10μs, significantly improving the identification and forwarding speed of critical power protocol data and ensuring the real-time performance of services such as distribution automation and substation monitoring. Second, the hardware queue scheduling mechanism clearly distinguishes between high-priority and ordinary-priority queues. Combined with QoS tag generation, it generates hardware sub-circuits that can specifically allocate high priority to ModbusTCP, IEC104, and DL / T860 protocol data, ensuring that critical control messages pass through first and avoiding blockage by ordinary data, thus improving the reliability of power service transmission. Third, the standard mPCIe interface supports hot-swapping. Combined with the plug-in card design, the router can be installed, maintained, or replaced without powering off, thus avoiding interruptions to industrial services. At the same time, the protocol library can be updated online through this interface without modifying the router's main platform, significantly reducing upgrade costs and operational complexity. This adapts to the long-term operation and flexible upgrade requirements of industrial scenarios, comprehensively improving the applicability of industrial-grade routers in power ICT converged networks. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 Block diagram of a router forwarding module to support multi-protocol identification and priority scheduling. Detailed Implementation

[0021] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0022] The following disclosure provides many different embodiments or examples for implementing various structures of this invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this invention.

[0023] The embodiments of the utility model will now be described in detail with reference to the accompanying drawings.

[0024] As attached Figure 1 As shown, the router forwarding module that supports multi-protocol identification and priority scheduling disclosed in this embodiment includes a forwarding module card body 2, and a protocol identification hardware circuit 4, a priority marking hardware circuit 5, a scheduling and forwarding hardware circuit 6, and a standard mPCIe interface 3 integrated on the forwarding module card body 2.

[0025] The standard mPCIe interface 3 is used to achieve hot-swappable hardware connection with the industrial router motherboard 1. The signal input terminal of the protocol identification hardware circuit 4 and the signal output terminal of the standard mPCIe interface 3 are connected by PCB traces. The signal output terminal of the protocol identification hardware circuit 4 and the signal input terminal of the priority marking hardware circuit 5 are connected by PCB traces. The signal output terminal of the priority marking hardware circuit 5 and the signal input terminal of the scheduling and forwarding hardware circuit 6 are connected by PCB traces. The signal output terminal of the scheduling and forwarding hardware circuit 6 and the signal input terminal of the standard mPCIe interface 3 are connected by PCB traces.

[0026] The data flow direction of the above scheme is as follows: the power scenario data flow is input to the protocol identification hardware circuit 4 through the standard mPCIe interface 3, and after protocol identification, the protocol identification signal is output to the priority marking hardware circuit 5. The priority marking hardware circuit 5 generates a data flow with QoS priority tags and outputs it to the scheduling and forwarding hardware circuit 6. The scheduling and forwarding hardware circuit 6 performs hardware queue scheduling based on the QoS priority tags and outputs it to the industrial router motherboard 1 through the standard mPCIe interface 3.

[0027] The working principle of the above scheme is as follows:

[0028] Step 1: Establish a hardware connection between the module and the industrial-grade router motherboard 1

[0029] 1.1 Operation: Connect the forwarding module card body 2 to the mPCIe slot of the industrial router motherboard 1 through the standard mPCIe interface 3 integrated on it to complete the physical hardware connection;

[0030] 1.2 Key Features: The standard mPCIe interface 3 supports hot-swapping, allowing module installation / removal without shutting down the router, ensuring continuous operation of the router's main platform;

[0031] 1.3 Function: To establish data transmission and power supply paths between the module and the router motherboard, laying the hardware foundation for subsequent data stream processing.

[0032] Step 2: The power scenario data stream is input to the module through the standard mPCIe interface 3.

[0033] 2.1 Data source: Power scenario data streams generated or received on the motherboard 1 of the industrial-grade router (including protocol data such as ModbusTCP, IEC104, DL / T860, etc., such as power distribution automation control commands and substation monitoring data).

[0034] 2.2 Signal Path: The data stream first enters the signal pin of the standard mPCIe interface 3, and after being buffered inside the interface, it is accurately transmitted to the signal input terminal of the protocol recognition hardware circuit 4 through the preset PCB traces.

[0035] 2.3 Hardware basis: The signal input terminal of the corresponding protocol identification hardware circuit 4 and the signal output terminal of the standard mPCIe interface 3 are connected by PCB traces to ensure that there is no software forwarding delay in data.

[0036] Step 3: Protocol Identification Hardware Circuit 4 Completes Protocol Type Differentiation

[0037] 3.1 Receiving Data: The protocol identification hardware circuit 4 receives the data stream transmitted in step 2 through the signal input terminal;

[0038] 3.2 Hardware Analysis: The circuit internally performs two operations through hardware logic (not software program):

[0039] Parse the port number of the data stream (e.g., identify the default port 502 for the Modbus TCP protocol);

[0040] Match the protocol signature of the data stream (such as the start character 0x68 of the IEC104 protocol and the APDU frame format features of the DL / T860 protocol).

[0041] 3.3 Generate Signal: Based on the parsing results, generate a protocol identification signal containing the protocol type identifier (e.g., identifying the data stream as IEC104 protocol).

[0042] 3.4 Signal Transmission: The protocol identification signal is transmitted to the signal input terminal of the priority marking hardware circuit 5 through PCB traces.

[0043] Step 4: Priority Marking Hardware Circuit 5 - Add QoS Priority Tags

[0044] 4.1 Receiving Signals: The priority marking hardware circuit 5 receives the protocol identification signal transmitted in step 3 to determine the protocol type corresponding to the current data stream;

[0045] 4.2 Tag Generation: Through the built-in QoS tag generation hardware logic, high-priority QoS tags are automatically generated for the data streams corresponding to key protocols in the power scenario (ModbusTCP, IEC104, DL / T860). (The tag information is directly written into the frame structure of the data stream through the hardware logic without software intervention.)

[0046] 4.3 Data Output: The data stream with high-priority QoS tags is transmitted to the signal input terminal of the scheduling and forwarding hardware circuit 6 through PCB traces.

[0047] Step 5: Scheduling and forwarding hardware circuit 6 performs queue scheduling according to priority.

[0048] 5.1 Receiving Data: The scheduling and forwarding hardware circuit 6 receives the data stream with QoS priority tags transmitted in step 4;

[0049] 5.2 Queue Allocation: The circuit internally pre-defines high-priority hardware queues and normal-priority hardware queues, and automatically determines the QoS label of the data stream through hardware logic.

[0050] Data streams with high-priority tags (such as IEC104 monitoring data) are assigned to high-priority hardware queues;

[0051] Other data streams without high-priority tags are assigned to ordinary-priority hardware queues;

[0052] 5.3 Priority Scheduling: Activate hardware queue scheduling logic to prioritize the forwarding channels of high-priority hardware queues, ensuring that critical control messages are processed first and avoiding transmission delays;

[0053] 5.4 Data Feedback: After scheduling is completed, the processed data stream is transmitted to the signal input terminal of the standard mPCIe interface 3 through PCB traces.

[0054] Step 6: The data stream is transmitted back to the router motherboard via the standard mPCIe interface 3.

[0055] 6.1 Receiving Data: Standard mPCIe interface 3 receives the priority-scheduled data stream transmitted in step 5;

[0056] 6.2 Backhaul path: The data stream is backhauled to the industrial-grade router motherboard 1 via a hardware connection to the router motherboard through an interface;

[0057] 6.3 Process Closure: After receiving the data, the router motherboard completes the subsequent transmission according to the power service requirements (such as sending to the substation monitoring terminal and distribution automation equipment). This completes the full hardware processing flow of data input → protocol identification → priority marking → scheduling and forwarding → data output.

[0058] Furthermore, the protocol identification hardware circuit 4 includes a port parsing hardware sub-circuit and a feature code matching hardware sub-circuit. The signal input terminal of the port parsing hardware sub-circuit is hardware-connected to the signal output terminal of the standard mPCIe interface 3. The signal output terminal of the port parsing hardware sub-circuit is hardware-connected to the signal input terminal of the feature code matching hardware sub-circuit. The signal output terminal of the feature code matching hardware sub-circuit is hardware-connected to the signal input terminal of the priority marking hardware circuit 5. The hardware circuit parses the data stream port number and matches the protocol feature code to achieve multi-protocol differentiation.

[0059] Furthermore, the priority labeling hardware circuit 5 includes a QoS tag generation hardware sub-circuit. The signal input terminal of the QoS tag generation hardware sub-circuit is hardware-connected to the signal output terminal of the protocol identification hardware circuit 4, and the signal output terminal of the QoS tag generation hardware sub-circuit is hardware-connected to the signal input terminal of the scheduling and forwarding hardware circuit 6. It is used to generate high-priority QoS tags for data streams corresponding to ModbusTCP, IEC104, and DL / T860 protocols.

[0060] Furthermore, the scheduling and forwarding hardware circuit 6 includes a hardware queue group and a queue scheduling hardware sub-circuit. The hardware queue group includes at least one high-priority hardware queue and at least one normal-priority hardware queue. The signal input terminal of the queue scheduling hardware sub-circuit is hardware-connected to the signal output terminal of the priority marking hardware circuit 5. The queue selection terminal of the queue scheduling hardware sub-circuit is hardware-connected to the enable terminals of the high-priority hardware queue and the normal-priority hardware queue, respectively. The signal output terminals of the high-priority hardware queue and the normal-priority hardware queue are both hardware-connected to the signal input terminal of the standard mPCIe interface 3.

[0061] Furthermore, it also includes a non-volatile storage hardware circuit, which is integrated on the forwarding module card body 2. Its data interface is hardware-connected to the storage interface of the protocol identification hardware circuit 4, and is used to store multi-protocol feature library data. It supports receiving upgrade data through the standard mPCIe interface 3 to realize online updates of the protocol library hardware.

[0062] Furthermore, the standard mPCIe interface 3 integrates a hot-swap control hardware sub-circuit. The power detection terminal of the hot-swap control hardware sub-circuit is hardware-connected to the power supply line of the industrial-grade router motherboard 1, and the signal buffer terminal of the hot-swap control hardware sub-circuit is hardware-connected to the signal pin of the standard mPCIe interface 3, so as to realize the power-free plugging and unplugging of the forwarding module card body 2 and the router motherboard.

[0063] Furthermore, the port resolution hardware sub-circuit includes a ModbusTCP dedicated port resolution circuit, and the feature code matching hardware sub-circuit includes an IEC104 feature code comparison circuit and a DL / T860 feature code comparison circuit. The signal output terminals of the ModbusTCP dedicated port resolution circuit, the IEC104 feature code comparison circuit, and the DL / T860 feature code comparison circuit are all hardware-connected to the signal input terminal of the priority marking hardware circuit 5.

[0064] Furthermore, the queue scheduling hardware sub-circuit includes a priority comparison hardware circuit. The signal input terminal of the priority comparison hardware circuit is hardware-connected to the QoS tag signal output by the priority tag hardware circuit 5. The output terminal of the priority comparison hardware circuit is hardware-connected to the priority enable terminal of the high-priority hardware queue, ensuring that the data stream corresponding to the high-priority QoS tag enters the forwarding channel first.

[0065] Furthermore, it also includes a power supply voltage regulation hardware circuit. The power input terminal of the power supply voltage regulation hardware circuit is hardware connected to the power pin of the standard mPCIe interface 3, and its regulated output terminal is hardware connected to the power input terminals of the protocol identification hardware circuit 4, priority marking hardware circuit 5, scheduling and forwarding hardware circuit 6, and non-volatile storage hardware circuit, respectively, to provide a stable operating voltage.

[0066] Furthermore, the protocol identification hardware circuit 4, the priority marking hardware circuit 5, and the scheduling and forwarding hardware circuit 6 are all implemented using FPGA hardware. The signal transmission delay between each hardware circuit is ≤10μs, and the signal transmission rate of the standard mPCIe interface 3 is ≥5Gbps.

Claims

1. A router forwarding module supporting multi-protocol identification and priority scheduling, characterized in that, It includes the forwarding module card body, as well as the protocol identification hardware circuit, priority marking hardware circuit, scheduling and forwarding hardware circuit and standard mPCIe interface integrated on the forwarding module card body; The standard mPCIe interface is used to achieve hot-swappable hardware connection with the motherboard of an industrial-grade router. The signal input terminal of the protocol identification hardware circuit is connected to the signal output terminal of the standard mPCIe interface via PCB traces. The signal output terminal of the protocol identification hardware circuit is connected to the signal input terminal of the priority marking hardware circuit via PCB traces. The signal output terminal of the priority marking hardware circuit is connected to the signal input terminal of the scheduling and forwarding hardware circuit via PCB traces. The signal output terminal of the scheduling and forwarding hardware circuit is connected to the signal input terminal of the standard mPCIe interface via PCB traces.

2. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 1, characterized in that, The protocol identification hardware circuit includes a port parsing hardware sub-circuit and a signature matching hardware sub-circuit. The signal input terminal of the port parsing hardware sub-circuit is hardware-connected to the signal output terminal of the standard mPCIe interface. The signal output terminal of the port parsing hardware sub-circuit is hardware-connected to the signal input terminal of the signature matching hardware sub-circuit. The signal output terminal of the signature matching hardware sub-circuit is hardware-connected to the signal input terminal of the priority marking hardware circuit. The hardware circuit parses the data stream port number and matches the protocol signature to achieve multi-protocol differentiation.

3. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 1, characterized in that, The priority labeling hardware circuit includes a QoS tag generation hardware sub-circuit. The signal input terminal of the QoS tag generation hardware sub-circuit is hardware-connected to the signal output terminal of the protocol identification hardware circuit, and the signal output terminal of the QoS tag generation hardware sub-circuit is hardware-connected to the signal input terminal of the scheduling and forwarding hardware circuit. It is used to generate high-priority QoS tags for data streams corresponding to ModbusTCP, IEC104, and DL / T860 protocols.

4. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 1, characterized in that, The scheduling and forwarding hardware circuit includes a hardware queue group and a queue scheduling hardware sub-circuit. The hardware queue group contains at least one high-priority hardware queue and at least one normal-priority hardware queue. The signal input terminal of the queue scheduling hardware sub-circuit is hardware-connected to the signal output terminal of the priority marking hardware circuit. The queue selection terminal of the queue scheduling hardware sub-circuit is hardware-connected to the enable terminal of the high-priority hardware queue and the normal-priority hardware queue, respectively. The signal output terminals of the high-priority hardware queue and the normal-priority hardware queue are both hardware-connected to the signal input terminal of the standard mPCIe interface.

5. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 1, characterized in that, It also includes non-volatile storage hardware circuitry, which is integrated on the forwarding module card body. Its data interface is hardware-connected to the storage interface of the protocol identification hardware circuitry, and is used to store multi-protocol feature library data. It supports online updates of the protocol library hardware by receiving upgrade data through the standard mPCIe interface.

6. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 1, characterized in that, The standard mPCIe interface integrates a hot-swap control hardware sub-circuit. The power detection terminal of the hot-swap control hardware sub-circuit is hardware-connected to the power supply line of the industrial-grade router motherboard, and the signal buffer terminal of the hot-swap control hardware sub-circuit is hardware-connected to the signal pins of the standard mPCIe interface, enabling power-free plugging and unplugging of the forwarding module card body and the router motherboard.

7. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 2, characterized in that, The port resolution hardware sub-circuit includes a ModbusTCP dedicated port resolution circuit, and the feature code matching hardware sub-circuit includes an IEC104 feature code comparison circuit and a DL / T860 feature code comparison circuit. The signal output terminals of the ModbusTCP dedicated port resolution circuit, the IEC104 feature code comparison circuit, and the DL / T860 feature code comparison circuit are all hardware-connected to the signal input terminals of the priority marking hardware circuit.

8. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 4, characterized in that, The queue scheduling hardware sub-circuit includes a priority comparison hardware circuit. The signal input terminal of the priority comparison hardware circuit is hardware-connected to the QoS tag signal output by the priority tag hardware circuit. The output terminal of the priority comparison hardware circuit is hardware-connected to the priority enable terminal of the high-priority hardware queue, ensuring that the data stream corresponding to the high-priority QoS tag enters the forwarding channel first.

9. The router forwarding module supporting multi-protocol identification and priority scheduling according to claim 5, characterized in that, It also includes a power supply voltage regulation hardware circuit. The power input terminal of the power supply voltage regulation hardware circuit is hardware connected to the power pin of the standard mPCIe interface, and its regulated output terminal is hardware connected to the power input terminals of the protocol identification hardware circuit, priority marking hardware circuit, scheduling and forwarding hardware circuit, and non-volatile storage hardware circuit, respectively, to provide a stable operating voltage.

10. The router forwarding module supporting multi-protocol identification and priority scheduling according to any one of claims 1-9, characterized in that, The protocol identification hardware circuit, priority marking hardware circuit, and scheduling forwarding hardware circuit are all implemented using FPGA hardware. The signal transmission delay between each hardware circuit is ≤10μs, and the signal transmission rate of the standard mPCIe interface is ≥5Gbps.

Images