A noise reduction design structure for phantom analog circuit

Abstract

The utility model relates to a kind of noise reduction design structure of phantom analog circuit, including boost unit, control unit and noise reduction unit, the boost unit is connected with outside input power supply, the voltage of input signal is boosted;The control unit is connected with the boost unit by boost input point, the output of control input signal is cut off;The noise reduction unit is connected with the control unit by boost output point, obtains output signal after input signal is noise reduced, and the output signal after noise reduction is output to outside;The noise reduction unit includes decoding output part and shunt, the alternating current signal is output to outside decoding in the decoding output part, the shunt is arranged between control unit and decoding output part, separates direct current signal from control unit with alternating current signal, to make direct current signal unable to enter decoding output part. The noise reduction design structure of phantom analog circuit using the utility model can greatly reduce the noise in circuit.

Description

Technical Field

[0001] This utility model relates to the field of circuit design, and in particular to a noise reduction design structure for a phantom analog circuit. Background Technology

[0002] In microphone circuits, due to the influence of internal microphone components, they cannot withstand excessive voltage. To improve the audio signal strength of the microphone output, a power amplifier design is usually adopted, which uses phantom analog circuits to amplify the power and thus achieve boost power supply.

[0003] However, the thermal noise and shot noise of internal components such as resistors and transistors in phantom analog circuits are directly superimposed on the power output, introducing background noise. This can also cause power ripple or electromagnetic interference (EMI) to enter sensitive microphone circuits, severely affecting the listening experience. Furthermore, due to the development and upgrading of modern microphones, mainstream products have increasingly higher current requirements; for example, Neumann microphones require 2-4mA. However, existing phantom analog circuits typically only provide 1-2mA of current. Therefore, the circuit's power supply capacity does not match the current demand, leading to unstable power supply voltage or overload, which also generates noise.

[0004] Therefore, reducing the background noise introduced by the phantom analog circuit power supply, so that the audio signal output by the microphone does not affect the listening experience and provides a better user experience, has become a necessary condition for the further development of microphones. Utility Model Content

[0005] Therefore, the purpose of this utility model is to provide a noise reduction design structure for a phantom analog circuit, which can significantly reduce the background noise in the circuit and improve the user experience.

[0006] A noise reduction design structure for a phantom analog circuit includes a boost unit, a control unit, and a noise reduction unit. The boost unit is connected to an external input power supply to boost the voltage of the input signal. The control unit is connected to the boost unit through a boost input point to control the output and cutoff of the input signal. The noise reduction unit is connected to the control unit through a boost output point to reduce the noise of the input signal and obtain an output signal, which is then output to the outside. The noise reduction unit includes a decoding output section and a shunt. The decoding output section outputs an AC signal to an external decoder. The shunt is located between the control unit and the decoding output section to separate the DC signal from the AC signal from the control unit, preventing the DC signal from entering the decoding output section.

[0007] Furthermore, the boost unit includes an input section and a power chip. The input section is connected to the power input pin of the power chip to provide 24V DC power to the power chip. The power output pin of the power chip is grounded through series resistors R1, R2, and R3. The output voltage of the power chip is thus obtained as follows: VOUT = 1.25 * (1 + R3 / (R1 + R2)) Among them, resistor R1 is 47Ω, resistor R2 is 1200Ω, resistor R3 is 47000Ω, and the calculated VOUT voltage is 48V.

[0008] Furthermore, the boost unit also includes a feedforward capacitor, which is disposed across the resistor R3. One end of the feedforward capacitor is connected to the control unit, and the other end is connected to the output feedback network pin of the power chip, so that high-frequency noise flows into the output feedback network pin of the power chip through the feedforward capacitor, thereby suppressing high-frequency noise.

[0009] Furthermore, the noise reduction unit also includes an analog output section, which is connected to the outside world and outputs the boosted signal from the control unit to the outside world.

[0010] Furthermore, the control unit includes a first transistor and a second transistor. The source of the first transistor is connected to the noise reduction unit, the drain of the first transistor is connected to the noise reduction unit, the source of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is connected to an external control power supply, and the drain of the second transistor is grounded.

[0011] Furthermore, the source and gate of the first transistor are connected by a resistor R9, and the source and drain of the first transistor are connected by a diode, with the diode conducting from the drain of the first transistor to the source; the gate and drain of the second transistor are connected by a resistor R8, and the gate of the second transistor is connected to an external control power supply through a resistor R6.

[0012] Furthermore, when the external control power input signal is a high level of 3.3V, the gate level of the second transistor is 0.7V higher than the drain level, thereby turning on the source and drain of the second transistor. The source level of the second transistor is the same as that of the drain. At this time, the gate level of the first transistor is lower than the source level, and the drain and source of the first transistor are turned on. The voltage at the boost output point is 48V, just like the voltage at the boost input point.

[0013] Furthermore, when the external control power input signal is low level 0V, the gate level and drain level of the second transistor are the same, and the source and drain of the second transistor are cut off. At this time, the gate level and source level of the first transistor are the same, and the drain and source of the first transistor are cut off, and the voltage at the boost output point F is 0V.

[0014] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a structural diagram of the boost unit of the noise reduction design structure of the phantom analog circuit of this utility model.

[0016] Figure 2 This is a structural diagram of the control unit of the noise reduction design structure of the phantom analog circuit of this utility model.

[0017] Figure 3 This is a structural diagram of the noise reduction unit in the noise reduction design structure of the phantom analog circuit of this utility model. Detailed Implementation

[0018] The noise reduction design structure of the phantom simulation circuit includes a boost unit, a control unit, and a noise reduction unit. The boost unit is connected to an external power supply to boost the voltage of the input signal. The control unit is connected to the boost unit to control the output and cutoff of the input signal. The noise reduction unit is connected to the control unit to reduce the noise of the input signal and obtain an output signal, which is then output to the outside world.

[0019] Please see Figure 1 The boost unit includes an input section, a power chip, and a feedforward capacitor. The input section includes multiple voltage nodes that input 24V and ±12V DC power into the circuit. Voltage node A serves as the power input for the power chip U2, voltage node B is connected to an external positive voltage of +12V, and voltage node C is connected to an external negative voltage of -12V. Power is supplied to the input section through voltage nodes B and C, and voltage node D is grounded. The voltage at voltage node A is 24V DC, thus providing 24V DC power to the power chip U2. The power chip U2 is a DC-C chip with two power input pins and pins 5 and 6 for power output. The power output pins are grounded through series resistors R1, R2, and R3. Therefore, the output voltage of the power chip U2 is: VOUT = 1.25 * (1 + R3 / (R1 + R2)) Among them, resistor R1 is 47Ω with a tolerance of 1%, resistor R2 is 1200Ω with a tolerance of 1%, and resistor R3 is 47000Ω with a tolerance of 1%. Therefore, the calculated VOUT voltage is 48V, which means the voltage at the boost input point E is 48V. This is understandable. Figure 1 The markings on each resistor indicate its name, resistance value, tolerance, and surface mount package. For example, in resistor R7, 47K indicates a resistance value of 47000Ω, 1% indicates the tolerance of the resistance value, and 0603 indicates the surface mount package of the resistor. The same applies to the other resistors, and will not be elaborated on here.

[0020] The feedforward capacitor C3 is connected across the two ends of resistor R3, with one end connected to the boost input point E and the other end connected to the output feedback network pin of power chip U2. The feedforward capacitor C3 ensures that the noise floor of the output voltage to the boost input point E is less than 60uV. Specifically, by setting the feedforward capacitor C3, high-frequency noise can enter the output feedback network pin of power chip U2 through the feedforward capacitor C3, which suppresses high-frequency noise, helps reduce output voltage fluctuations, and effectively reduces output power supply ripple. Compared to the existing technology where the noise floor of the output voltage to the boost input point E is 1.2mV, this invention, by adding the feedforward capacitor C3, can reduce the noise floor of the boosted 48V input voltage.

[0021] In particular, it transmits 48V DC power directly through the XLR line, providing a stable DC voltage and avoiding noise introduced by voltage fluctuations, thus eliminating voltage fluctuations and background noise issues associated with battery power.

[0022] Please see Figure 2The control unit includes a first transistor Q1 and a second transistor Q2. The source of the first transistor Q1 is connected to the boost input point E, and the drain of the first transistor Q1 is connected to the boost output point F. The source of the second transistor Q2 is connected to the gate of the first transistor Q1, and the gate of the second transistor Q2 is connected to the control voltage point S. The drain of the second transistor Q2 is grounded. Specifically, the source and gate of the first transistor Q1 are connected through a resistor R9, and the source and drain of the first transistor Q1 are connected through a diode D1. The conduction direction of the diode D1 is from the drain of the first transistor Q1 to the source. When the first transistor Q1 is turned off, the energy stored in the capacitor will attempt to maintain the current flow in the original direction, which may cause a high peak voltage to be applied across the first transistor Q1, thereby damaging the first transistor Q1. Therefore, by adding a fast-recovery diode D1 connected in reverse parallel with the first transistor Q1, a path can be provided to release the transient energy, thereby preventing the first transistor Q1 from being damaged by excessively high peak voltage. The gate and drain of the second transistor Q2 are connected by a resistor R8, and the gate of the second transistor Q2 is connected to the control voltage point S through a resistor R6. The control voltage point S is connected to an external control power supply in the low-level range.

[0023] Therefore, when the MCU_GPIO signal input at control voltage point S is high, that is, when the voltage at control voltage point S is high at 3.3V, the gate level of the second transistor Q2 is 0.7V higher than the drain level, thus making the source and drain of the second transistor Q2 conduct. The source level of the second transistor Q2 is the same as the drain level. At this time, the gate level of the first transistor Q1 is lower than the source level, so the drain and source of the first transistor Q1 are conducted. The voltage at the boost output point F is the same as that at the boost input point E, both being 48V. When the MCU_GPIO signal input at control voltage point S is low (i.e., the voltage at control voltage point S is low, 0V), the gate and drain levels of the second transistor Q2 are the same, thus turning off both the source and drain of the second transistor Q2. At this time, the gate and source levels of the first transistor Q1 are the same, therefore turning off both the drain and source of the first transistor Q1, and the voltage at the boost output point F is 0V. This allows for voltage control of the boost output point F, which experiences high voltage variations, through a low-voltage MCU_GPIO signal, reducing control complexity and improving operational safety.

[0024] Please see Figure 3The noise reduction unit includes an analog output section, a decoding output section, and a shunt. The analog output section is connected to the boost output point F, outputting the boosted signal from boost output point F to the outside. The decoding output section is also connected to boost output point F, outputting the AC signal from boost output point F to the outside. The shunt is positioned between the analog output section and the decoding output section, isolating DC signals from flowing into the decoding output section. Specifically, the analog output section is directly connected to an external microphone, thus inputting 48V voltage into the analog differential signal. The decoding output section uses two internal transistors to achieve dual-channel operational amplifier inversion output, outputting an AC signal with almost no DC signal at decoding output point L to the external audio codec DAC chip. This reduces or even eliminates the 48V power supply noise from entering the analog signal at decoding output point L, thereby ensuring that the audio output listening experience is not affected.

[0025] The noise reduction design structure of the phantom analog circuit of this utility model can significantly reduce the background noise level input to the control unit by adding a feedforward capacitor in the boost unit, and can effectively reduce the background noise of the audio output by adding a shunt in the noise reduction unit, thereby ensuring that the audio output listening experience is not affected.

[0026] The embodiments described above only illustrate the preferred implementation of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of this utility model, and this utility model also intends to include these modifications and variations.

Claims

1. A noise reduction design structure for a phantom analog circuit, characterized in that: The system includes a boost unit, a control unit, and a noise reduction unit. The boost unit is connected to an external input power supply to boost the voltage of the input signal. The control unit is connected to the boost unit through a boost input point to control the output and cutoff of the input signal. The noise reduction unit is connected to the control unit through a boost output point to reduce the noise of the input signal and output the noise-reduced signal to the outside. The noise reduction unit includes a decoding output section and a shunt. The decoding output section outputs an AC signal to an external decoder. The shunt is located between the control unit and the decoding output section to separate the DC signal from the AC signal from the control unit, preventing the DC signal from entering the decoding output section.

2. The noise reduction design structure of the phantom analog circuit according to claim 1, characterized in that: The boost unit includes an input section and a power chip. The input section is connected to the power input pin of the power chip, providing 24V DC power to the power chip. The power output pin of the power chip is grounded through a series resistor R1, R2, and R3. The output voltage of the power chip is: VOUT = 1.25 * (1 + R3 / (R1 + R2)) Among them, resistor R1 is 47Ω, resistor R2 is 1200Ω, resistor R3 is 47000Ω, and the calculated VOUT voltage is 48V.

3. The noise reduction design structure of the phantom analog circuit according to claim 2, characterized in that: The boost unit also includes a feedforward capacitor, which is set across the resistor R3. One end of the feedforward capacitor is connected to the control unit, and the other end is connected to the output feedback network pin of the power chip, so that high-frequency noise flows into the output feedback network pin of the power chip through the feedforward capacitor, thereby suppressing high-frequency noise.

4. The noise reduction design structure of the phantom analog circuit according to claim 3, characterized in that: The noise reduction unit also includes an analog output section, which is connected to the outside world and outputs the boost signal from the control unit to the outside world.

5. The noise reduction design structure of the phantom analog circuit according to claim 4, characterized in that: The control unit includes a first transistor and a second transistor. The source of the first transistor is connected to the noise reduction unit, the drain of the first transistor is connected to the noise reduction unit, the source of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is connected to an external control power supply, and the drain of the second transistor is grounded.

6. The noise reduction design structure of the phantom analog circuit according to claim 5, characterized in that: The source and gate of the first transistor are connected by a resistor R9, and the source and drain of the first transistor are connected by a diode, with the diode conducting from the drain of the first transistor to the source; the gate and drain of the second transistor are connected by a resistor R8, and the gate of the second transistor is connected to an external control power supply through a resistor R6.

7. The noise reduction design structure of the phantom analog circuit according to claim 6, characterized in that: When the external control power input signal is a high level of 3.3V, the gate level of the second transistor is 0.7V higher than the drain level, thus turning on the source and drain of the second transistor. The source level of the second transistor is the same as that of the drain. At this time, the gate level of the first transistor is lower than the source level, and the drain and source of the first transistor are turned on. The voltage at the boost output point is 48V, just like the voltage at the boost input point.

8. The noise reduction design structure of the phantom analog circuit according to claim 7, characterized in that: When the external control power input signal is low level 0V, the gate level and drain level of the second transistor are the same, and the source and drain of the second transistor are cut off. At this time, the gate level and source level of the first transistor are the same, and the drain and source of the first transistor are cut off. The voltage at the boost output point F is 0V.

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