A link healing protocol processing module and communication system for wireless APs
Patent Information
- Application Number
- CN202522570501.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2035-12-03
AI Technical Summary
[0004]本实用新型为解决现有技术中链路状态探测延迟高、自愈响应滞后，且软件层面的阈值比对与恢复动作执行实时性不足的问题，提供一种用于无线AP的链路自愈协议处理模块及通信系统
[0019]本实用新型公开的用于无线AP的链路自愈协议处理模块及通信系统通过嵌入无线AP内部的独立硬件架构设计，显著提升链路自愈性能与适配性：其一，依托MCU+FPGA协处理器统筹三大功能单元，通过硬件总线实现毫秒级联动，脱离主CPU多任务调度束缚，解决现有软件方案探测延迟高、响应滞后的缺陷，硬件级监测、比对与执行动作保障自愈实时性；其二，硬件存储单元支持自愈协议策略固件存储与远程升级，打破传统软件固化局限，可灵活适配不同应用场景；其三，UART/I2C硬件接口实现与主CPU高效交互，既不占用主CPU资源，又能实时反馈工作状态，结合硬件级恢复动作，大幅提升链路故障自愈成功率与稳定性，确保无线网络通信连续可靠。
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Abstract
Description
Technical Field
[0001] This utility model relates to the field of wireless communication technology, and in particular to a link self-healing protocol processing module and communication system for a wireless AP. Background Technology
[0002] Link self-healing technology of wireless APs is a key technology to ensure the stability of wireless networks. It refers to the automatic mechanism by which a wireless AP can detect the fault status, determine the fault type, and trigger recovery actions such as channel switching, power adjustment, and fast re-authentication when the communication link with the upstream device or terminal experiences faults such as signal attenuation, packet loss, or excessive latency, without manual intervention. This mechanism quickly repairs the link fault and restores normal communication.
[0003] Existing wireless AP link self-healing technologies mostly rely on the main CPU to implement through software algorithms, lacking an independent hardware processing module to coordinate the monitoring, judgment, and execution processes. The main CPU needs to handle multi-task scheduling, resulting in high latency in link status detection, delayed self-healing response, and insufficient real-time performance of threshold comparison and recovery actions at the software level. Utility Model Content
[0004] This invention addresses the problems of high link status detection delay, lagging self-healing response, and insufficient real-time performance of threshold comparison and recovery actions at the software level in existing technologies by providing a link self-healing protocol processing module and communication system for wireless APs.
[0005] The technical solution adopted in this utility model is:
[0006] The link self-healing protocol processing module for wireless AP provided by this utility model is embedded inside the wireless AP and includes a link monitoring unit, a protocol judgment unit, a self-healing execution unit and an MCU+FPGA coprocessor.
[0007] The output interface of the link monitoring unit is connected to the input interface of the protocol judgment unit, and the output interface of the protocol judgment unit is connected to the input interface of the self-healing execution unit.
[0008] The link monitoring unit, protocol judgment unit, and self-healing execution unit all communicate bidirectionally with the MCU+FPGA coprocessor via a hardware bus.
[0009] The MCU+FPGA coprocessor integrates a UART / I2C hardware communication interface, which establishes an interactive connection with the main CPU of the wireless AP through the UART / I2C hardware communication interface; the MCU+FPGA coprocessor is used to coordinate the communication interaction of the link monitoring unit, protocol judgment unit, and self-healing execution unit.
[0010] The MCU+FPGA coprocessor is configured with a hardware storage unit for remote protocol upgrades.
[0011] Furthermore, the link monitoring unit consists of an RF detection chip, a timer chip, and a filter amplification circuit. It is used to periodically detect the delay, packet loss rate, and signal strength parameters of the uplink link. The detection period is configured by the timer chip hardware.
[0012] Furthermore, the protocol judgment unit is configured with a threshold comparison circuit.
[0013] Furthermore, the threshold comparison circuit includes a comparator chip and a preset threshold storage register group, which is used to perform hardware-level comparison between the parameters collected by the link monitoring unit and the preset threshold stored in the register group, and output a trigger signal through the output interface when the threshold is exceeded.
[0014] Furthermore, the self-healing execution unit consists of a protocol processing chip, control logic circuits, and drive circuits; the self-healing execution unit is used to perform at least one hardware-level recovery action among fast re-authentication, channel switching, power adjustment, and multicast re-registration.
[0015] Furthermore, the hardware storage unit of the MCU+FPGA coprocessor includes a Flash chip and a RAM chip, which are used to store the self-healing protocol strategy firmware and temporary data of the upgrade program, respectively.
[0016] Furthermore, the hardware configuration detection period of the timer chip in the link monitoring unit is 10-100 milliseconds, and the preset threshold storage register group supports dynamic configuration of threshold parameters through the hardware interface.
[0017] Based on the same inventive concept, this utility model also provides a substation mobile operation communication system, which includes the aforementioned link self-healing protocol processing module for wireless AP.
[0018] The beneficial effects of this utility model are:
[0019] This utility model discloses a link self-healing protocol processing module and communication system for wireless APs. Through an independent hardware architecture design embedded within the wireless AP, it significantly improves the link self-healing performance and adaptability: First, relying on an MCU+FPGA coprocessor to coordinate the three functional units, it achieves millisecond-level linkage through a hardware bus, breaking free from the constraints of multi-task scheduling by the main CPU. This solves the defects of high detection latency and sluggish response in existing software solutions, and hardware-level monitoring, comparison, and execution actions ensure real-time self-healing. Second, the hardware storage unit supports firmware storage and remote upgrades for self-healing protocol strategies, breaking the limitations of traditional software rigidity and flexibly adapting to different application scenarios. Third, the UART / I2C hardware interface enables efficient interaction with the main CPU, without occupying main CPU resources, and can provide real-time feedback on the working status. Combined with hardware-level recovery actions, it greatly improves the success rate and stability of link fault self-healing, ensuring continuous and reliable wireless network communication. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a block diagram of the link self-healing protocol processing module used in wireless APs. Detailed Implementation
[0022] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0023] The following disclosure provides many different embodiments or examples for implementing various structures of this invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this invention.
[0024] The embodiments of the utility model will now be described in detail with reference to the accompanying drawings.
[0025] As attached Figure 1 As shown, the link self-healing protocol processing module for wireless AP provided in this embodiment is embedded inside the wireless AP, including a link monitoring unit 1, a protocol judgment unit 2, a self-healing execution unit 3, and an MCU+FPGA coprocessor 4.
[0026] The output interface of the link monitoring unit 1 is connected to the input interface signal of the protocol judgment unit 2, and the output interface of the protocol judgment unit 2 is connected to the input interface signal of the self-healing execution unit 3.
[0027] Link monitoring unit 1, protocol judgment unit 2, and self-healing execution unit 3 all communicate bidirectionally with MCU+FPGA coprocessor 4 via hardware bus;
[0028] The MCU+FPGA coprocessor 4 integrates a UART / I2C hardware communication interface, which establishes an interactive connection with the main CPU of the wireless AP through the UART / I2C hardware communication interface; the MCU+FPGA coprocessor 4 is used to coordinate the communication interaction of the link monitoring unit 1, the protocol judgment unit 2, and the self-healing execution unit 3.
[0029] The MCU+FPGA coprocessor 4 is equipped with a hardware storage unit for remote protocol upgrades.
[0030] The wireless AP link self-healing protocol processing module disclosed in this embodiment is embedded inside the wireless AP. The working principle is as follows: When the module is working, the link monitoring unit 1 collects the link status signal and transmits it to the protocol judgment unit 2. After judgment, the self-healing execution unit 3 is triggered to perform the recovery operation. The whole process is coordinated by the MCU+FPGA coprocessor 4. It works with each unit through the hardware bus, interacts with the main CPU through the UART / I2C interface, and the hardware storage unit ensures the storage and upgrading of the protocol to realize the link self-healing function.
[0031] Among them, the MCU+FPGA coprocessor 4 achieves overall coordination through the two-way communication capability of the hardware bus. Specifically, the MCU+FPGA coprocessor 4 first sends instructions such as start and periodic configuration to the link monitoring unit 1 to trigger the collection of link parameters and receive the collected data in real time. Then, combined with the self-healing protocol strategy in the hardware storage unit, it sends threshold comparison benchmark and judgment logic instructions to the protocol judgment unit 2 and receives the comparison results. Subsequently, based on the results, it sends targeted recovery action instructions to the self-healing execution unit 3 to control the implementation of the operation. The entire process interacts with the main CPU of the wireless AP through the UART / I2C hardware communication interface, receives configuration instructions and feeds back the module working status and self-healing results. At the same time, it relies on the hardware storage unit to manage the firmware storage and remote upgrade of the protocol strategy, realizing full-process control from monitoring, judgment, execution to configuration management.
[0032] Below is an example of a self-healing protocol strategy: The hardware storage unit of the MCU+FPGA coprocessor 4 pre-stores a "signal strength threshold self-healing strategy"—the preset link signal strength qualification threshold is -75dBm, and the backup channel is channel 11; the coprocessor sends a 100ms periodic signal strength acquisition command to the link monitoring unit 1 via the hardware bus. The monitoring unit transmits the acquired real-time signal strength parameters back to the coprocessor via the hardware bus. The coprocessor synchronously triggers the threshold comparison circuit of the protocol judgment unit 2 for comparison; if the signal strength acquired for two consecutive cycles is lower than -75dBm, the coprocessor... Immediately, a linkage command of "first adjust power, then switch channels" is issued to the self-healing execution unit 3 via the hardware bus. First, the execution unit is controlled to increase the transmission power by 3dBm. If the signal strength still does not meet the standard within the next acquisition cycle, the execution unit is controlled to switch to the backup channel 11. During the entire policy execution process, the coprocessor monitors, judges, and executes the timing of the actions of the unit in real time through the hardware bus. At the same time, the policy execution status is fed back to the main CPU of the wireless AP through the UART / I2C interface. All threshold parameters and backup channel information are stored in the hardware storage unit, which supports remote upgrade and update of policy content.
[0033] Furthermore, the link monitoring unit 1 consists of an RF detection chip, a timer chip, and a filter amplifier circuit, and is used to periodically detect the delay, packet loss rate, and signal strength parameters of the uplink link. The detection period is configured by the timer chip hardware.
[0034] The input terminal of the RF detection chip is the signal receiving interface of the input terminal of the link monitoring unit 1. This interface is hardware-connected to the uplink signal output terminal of the wireless AP to receive the raw RF signal and provide the input signal source for subsequent acquisition of delay, packet loss rate and signal strength parameters. The enable signal output terminal of the timer chip is connected to the trigger signal terminal of the RF detection chip. The parameter acquisition output terminal of the RF detection chip is connected to the input terminal of the filter amplifier circuit. The output terminal of the filter amplifier circuit serves as the output interface of the link monitoring unit 1, realizing the hardware linkage of periodic parameter acquisition and signal preprocessing.
[0035] Furthermore, the protocol judgment unit 2 is configured with a threshold comparison circuit.
[0036] Furthermore, the threshold comparison circuit includes a comparator chip and a preset threshold storage register group (which can be implemented via FPGA), used to perform hardware-level comparison between the parameters collected by the link monitoring unit 1 and the preset threshold stored in the register group, and output a trigger signal through the output interface when the threshold is exceeded.
[0037] The input terminal of the preset threshold storage register group is the input terminal of the threshold comparison circuit, and the output terminal of the comparator chip is the output terminal of the threshold comparison circuit.
[0038] The output of the preset threshold storage register group is connected to the input of the comparator chip, and the input of the comparator chip is connected to the output interface of the link monitoring unit 1. The threshold data interaction between the register group and the comparator chip is realized through the address bus, and the comparison result is output through the output of the comparator chip.
[0039] Furthermore, the self-healing execution unit 3 consists of a protocol processing chip, a control logic circuit, and a drive circuit; the self-healing execution unit 3 is used to perform at least one hardware-level recovery action among fast re-authentication, channel switching, power adjustment, and multicast re-registration.
[0040] The input terminal of the protocol processing chip is connected to the output interface of the protocol judgment unit 2. The output terminal of the protocol processing chip is connected to the input terminal of the control logic circuit. The output terminal of the control logic circuit is connected to the input terminal of the drive circuit. The output terminal of the drive circuit is used to trigger the hardware-level recovery action.
[0041] The working principle of protocol judgment unit 2 is as follows: The output interface of protocol judgment unit 2 outputs a threshold over-limit trigger signal, which is transmitted to the input end of the protocol processing chip through hardware lines; after receiving the threshold over-limit trigger signal, the protocol processing chip generates a control logic instruction for recovery action and outputs the control logic instruction to the control logic circuit; the control logic circuit performs hardware-level logic processing such as level conversion and timing synchronization on the control logic instruction to generate a drive signal, which is transmitted to the drive circuit; after the drive circuit amplifies the drive signal to the execution threshold, it triggers recovery actions such as fast re-authentication and channel switching through the output end, realizing rapid self-healing of uplink link faults without the need for main CPU intervention, ensuring the real-time performance of the self-healing response.
[0042] Furthermore, the hardware storage unit of the MCU+FPGA coprocessor 4 includes a Flash chip and a RAM chip, which are used to store the self-healing protocol strategy firmware and temporary data of the upgrade program, respectively.
[0043] The storage control bus, address bus, and data bus of the MCU+FPGA coprocessor 4 are bidirectionally connected to the corresponding interfaces of the Flash chip and RAM chip, respectively. The MCU+FPGA coprocessor 4 sends read and write instructions through the control bus, locates the storage unit through the address bus, and realizes the transmission and access of the self-healing protocol strategy firmware (Flash chip) and upgrade temporary data (RAM chip) through the data bus.
[0044] Furthermore, the hardware configuration detection period of the timer chip in the link monitoring unit 1 is 10-100 milliseconds, and the preset threshold storage register group supports dynamic configuration of threshold parameters through the hardware interface.
[0045] Based on the same inventive concept, this embodiment also provides a substation mobile operation communication system, which includes the aforementioned link self-healing protocol processing module for wireless APs.
Claims
1. A link self-healing protocol processing module for a wireless AP, characterized in that, Embedded inside the wireless AP, it includes a link monitoring unit, a protocol judgment unit, a self-healing execution unit, and an independent MCU+FPGA coprocessor; The output interface of the link monitoring unit is connected to the input interface of the protocol judgment unit, and the output interface of the protocol judgment unit is connected to the input interface of the self-healing execution unit. The link monitoring unit, protocol judgment unit, and self-healing execution unit all communicate bidirectionally with the MCU+FPGA coprocessor via a hardware bus. The MCU+FPGA coprocessor integrates a UART / I2C hardware communication interface, which establishes an interactive connection with the main CPU of the wireless AP through the UART / I2C hardware communication interface; the MCU+FPGA coprocessor is used to coordinate the communication interaction of the link monitoring unit, protocol judgment unit, and self-healing execution unit. The MCU+FPGA coprocessor is configured with a hardware storage unit for remote protocol upgrades.
2. The link self-healing protocol processing module for a wireless AP according to claim 1, characterized in that, The link monitoring unit consists of an RF detection chip, a timer chip, and a filter amplifier circuit. It is used to periodically detect the uplink delay, packet loss rate, and signal strength parameters. The detection period is configured by the timer chip hardware.
3. The link self-healing protocol processing module for a wireless AP according to claim 1, characterized in that, The protocol judgment unit is configured with a threshold comparison circuit.
4. The link self-healing protocol processing module for a wireless AP according to claim 3, characterized in that, The threshold comparison circuit includes a comparator chip and a preset threshold storage register group, which is used to perform hardware-level comparison between the parameters collected by the link monitoring unit and the preset threshold stored in the register group. When the threshold is exceeded, a trigger signal is output through the output interface.
5. The link self-healing protocol processing module for a wireless AP according to claim 1, characterized in that, The self-healing execution unit consists of a protocol processing chip, control logic circuits, and driver circuits; the self-healing execution unit is used to perform at least one hardware-level recovery action among fast re-authentication, channel switching, power adjustment, and multicast re-registration.
6. The link self-healing protocol processing module for a wireless AP according to any one of claims 1-5, characterized in that, The hardware storage unit of the MCU+FPGA coprocessor includes a Flash chip and a RAM chip, which are used to store the self-healing protocol strategy firmware and temporary data of the upgrade program, respectively.
7. The link self-healing protocol processing module for a wireless AP according to claim 3, characterized in that, The hardware configuration detection period of the timer chip in the link monitoring unit is 10-100 milliseconds, and the preset threshold storage register group supports dynamic configuration of threshold parameters through the hardware interface.
8. A mobile communication system for substation operations, characterized in that, Includes the link self-healing protocol processing module for wireless AP as described in any one of claims 1-7.