A circuit board structure for improving channel isolation of a phased array chip

Abstract

The utility model belongs to circuit board technical field relates to a kind of circuit board structure for improving phased array chip channel isolation degree, including multilayer dielectric substrate, and the dielectric substrate is equipped with chip pad, and chip pad place is welded with chip, and dielectric substrate is equipped with multiple transmission line connected with the chip, and the signal transmission line includes the microstrip line arranged in the dielectric substrate surface layer and the strip line arranged in the dielectric substrate inner layer, and the microstrip line is connected with the strip line through signal via, and multiple ground vias that pass through the dielectric substrate are arranged between the periphery of the chip and adjacent signal transmission line, and the isolation groove formed by the ground vias distributed on the both sides of the signal transmission line, and the periphery of the signal via is equipped with annular ground via arranged around it. The application can improve the isolation degree between the multiple channels of the chip, and avoid the signal crosstalk problem between the channels.

Description

Technical Field

[0001] This utility model relates to the field of circuit board technology, and in particular to a circuit board structure for improving the channel isolation of phased array chips. Background Technology

[0002] Phased array systems are widely used in modern radar, communications, and other fields. Their core component, the phased array chip, typically integrates multiple radio frequency channels. As system integration increases and channel spacing decreases, crosstalk between channels becomes increasingly prominent, severely impacting the system's isolation performance.

[0003] In existing technologies, methods such as adding grounding vias and optimizing wiring spacing are commonly used to improve the isolation between channels. However, traditional grounding via arrangements often fail to adequately consider the integrity of the signal return path, resulting in limited improvement in isolation. Furthermore, impedance discontinuities and high process complexity introduce additional signal loss and crosstalk when signals transition from the surface layer to the inner layer. Existing solutions often employ single-row grounding vias or non-optimized grounding PAD structures, which can suppress crosstalk to some extent, but still cannot meet the stringent requirements for channel isolation in high-performance phased array systems. Therefore, this invention proposes a circuit board structure for improving the channel isolation of phased array chips. Utility Model Content

[0004] The main objective of this invention is to provide a circuit board structure for improving the channel isolation of a phased array chip, so as to solve the problems mentioned in the background art.

[0005] This utility model achieves the above-mentioned objective through the following technical solution: A circuit board structure for improving the channel isolation of a phased array chip includes a multilayer dielectric substrate. The dielectric substrate has chip pads, and chips are soldered onto the chip pads. The dielectric substrate has multiple transmission lines connected to the chips. The signal transmission lines include microstrip lines on the surface of the dielectric substrate and striplines on the inner layer of the dielectric substrate. The microstrip lines are connected to the striplines through signal vias. Multiple grounding vias penetrating the dielectric substrate are provided around the chips and between adjacent signal transmission lines. Isolation trenches are formed by the grounding vias distributed on both sides of the signal transmission lines. Annular grounding vias are arranged around the signal vias.

[0006] Preferably, two rows of mutually interlocking grounding through holes are provided on both sides of the strip.

[0007] Preferably, in the two rows of grounding holes that are interlocked, adjacent grounding holes in the same row are interlocked, and grounding holes between the two rows are interlocked.

[0008] Preferably, the copper stud in the signal via extends downward from the surface of the dielectric substrate to the layer where the stripline is located.

[0009] The beneficial effects of this utility model are as follows: the isolation trench formed by the grounding vias distributed on both sides of the signal transmission line can significantly improve the isolation between channels and effectively suppress signal crosstalk between channels; the copper studs in the signal vias extend from the surface of the dielectric substrate downwards to the layer where the stripline is located, removing the residual studs that cause resonance, making the frequency response of the vias smooth and reducing the loss of the transmission link; the two rows of grounding vias are interlocked, thereby establishing a continuous and seamless shielding wall composed of metallized vias between the two signal lines, preventing electromagnetic fields from coupling through the dielectric "gap" between the vias, thereby minimizing crosstalk. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a circuit board structure used to improve the channel isolation of a phased array chip, as an example.

[0011] Figure 2 yes Figure 1 Enlarged view of point A in the middle.

[0012] The numbers in the image represent: 1. Dielectric substrate; 2. Chip pad; 3. Transmission line; 4. Microstrip line; 5. Stripline; 6. Signal via; 7. Ground via; 8. Isolation trench; 9. Ring-shaped ground via. Detailed Implementation

[0013] The present invention will be further described in detail below with reference to specific embodiments.

[0014] Example: like Figure 1 and Figure 2As shown, this utility model discloses a circuit board structure for improving the channel isolation of a phased array chip. It includes a multilayer dielectric substrate 1, on which chip pads 2 are provided, and chips are soldered. Multiple transmission lines 3 connected to the chips are provided on the dielectric substrate 1. Each signal transmission line 3 includes a microstrip line 4 on the surface of the dielectric substrate 1 and a stripline line 5 on the inner layer of the dielectric substrate 1. The microstrip line 4 is connected to the stripline line 5 through signal vias 6, providing a vertical interconnect channel for high-frequency signals and preventing interference during long-distance signal transmission on the surface. This also improves signal isolation around and adjacent to the chips. Multiple grounding vias 7 penetrating the dielectric substrate 1 are provided between the transmission lines 3. The isolation trenches 8 formed by the grounding vias 7 distributed on both sides of the signal transmission lines 3 form an electromagnetic shielding barrier between adjacent channels, which can effectively cut off and absorb electromagnetic energy coupled in space, fundamentally weakening the main path of crosstalk between channels. The signal vias 6 are surrounded by annular grounding vias 9, which provide an instantaneous and complete reference ground return path when the signal changes layers, preventing the signal energy from leaking outward or coupling with other channels when passing through this three-dimensional structure, and ensuring the purity of the signal at the "bottleneck".

[0015] The stripline 5 has two rows of interlocking grounding holes 7 arranged parallel to each other on both sides, thereby providing a wider and denser shielding wall, optimizing the return path, and improving isolation.

[0016] In the two rows of mutually tangentially arranged grounding vias 7, adjacent grounding vias 7 in the same row are mutually tangentially arranged, and grounding vias 7 between the two rows are mutually tangentially arranged, thereby achieving the maximum possible distribution density of grounding vias 7 per unit area. This is equivalent to establishing a continuous, seamless shielding wall composed of metallized vias between two signal lines, preventing electromagnetic fields from coupling through the dielectric "gap" between the vias, thereby minimizing crosstalk. The tangential and closely arranged grounding vias 7 provide the widest, shortest, and lowest impedance vertical interconnect path for the return current of the signal. The return current can return from the signal layer to the reference ground layer extremely smoothly through this dense "bridge" without being forced into a circuitous, high-inductance path.

[0017] The copper studs within the signal via 6 extend downwards from the surface of the dielectric substrate 1 to the layer containing the stripline 5. These studs can be eliminated through back-drilling, removing remnants that cause resonance and smoothing the frequency response of the via. This significantly reduces the total loss of the transmission link, particularly in high-frequency (e.g., millimeter-wave) applications, providing a cleaner transmission path for higher-speed digital signals or higher-frequency radio frequency signals. The signal via 6 has a fixed aperture obtained through simulation calculations, allowing its parasitic capacitance and inductance to be controlled at predictable and stable values. This enables the via structure to be considered a fixed-value impedance element. Through simulation calculations, this "fixed value" can be made as close as possible to the characteristic impedance of the transmission line, minimizing impedance abrupt changes, ensuring impedance continuity during signal transition from the surface to the inner layer, and reducing signal reflection.

[0018] The above descriptions are merely some embodiments of this utility model. For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of this utility model, and all such modifications and improvements fall within the protection scope of this utility model.

Claims

1. A circuit board structure for improving the channel isolation of a phased array chip, characterized in that: The device includes a multilayer dielectric substrate with chip pads on it. Chips are soldered onto the chip pads. The dielectric substrate has multiple transmission lines connected to the chips. The transmission lines include microstrip lines on the surface of the dielectric substrate and striplines on the inner layer of the dielectric substrate. The microstrip lines are connected to the striplines through signal vias. Multiple ground vias penetrating the dielectric substrate are provided around the chips and between adjacent transmission lines. Isolation trenches are formed by the ground vias distributed on both sides of the transmission lines. Annular ground vias are arranged around the signal vias.

2. The circuit board structure for improving the channel isolation of a phased array chip according to claim 1, characterized in that: The strip has two rows of mutually interlocking grounding holes arranged parallel to each other on both sides.

3. The circuit board structure for improving the channel isolation of a phased array chip according to claim 2, characterized in that: In the two rows of grounding holes that are interlocked, adjacent grounding holes in the same row are interlocked, and grounding holes between the two rows are interlocked.

4. The circuit board structure for improving the channel isolation of a phased array chip according to claim 1, characterized in that: The copper studs within the signal vias extend downwards from the surface of the dielectric substrate to the layer containing the stripline.

Images