Printed circuit board and memory module

Abstract

The application discloses a printed circuit board and a memory module. The printed circuit board comprises at least a first trace layer, a first reference layer and a second reference layer. The first trace layer is divided into a gold finger area and a signal trace area. The first reference layer is arranged below the first trace layer. The second reference layer is arranged on the side of the first reference layer away from the trace layer. The first reference layer comprises a first dielectric area and a second dielectric area. The first dielectric area is arranged corresponding to the gold finger area of the first trace layer. The second dielectric area is arranged corresponding to the signal trace area of the first trace layer. The first dielectric area is provided with a metal material. The second dielectric area comprises a hollow area. The reference layer below the trace layer is provided with a metal material corresponding to the gold finger area of the trace layer. The gold finger and the metal material form a small local flat capacitor, so as to change the impedance and eliminate the problem of signal waveform reflection and oscillation caused by the sudden change of signal trace impedance.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a printed circuit board and a memory module. Background Technology

[0002] In the current storage field, the operation of memory module products requires strict impedance matching for each signal. Any factor on the printed circuit board (PCB) that affects the impedance of signal transmission, if not handled properly, will cause signal reflection and waveform oscillation, resulting in the memory module not working properly. In multilayer PCBs, the connection to the host is usually made by gold fingers. The width of the gold fingers is generally wider than that of the lead, and the copper thickness at the gold fingers is also thicker than that of the lead. According to conventional design, under the same dielectric material parameters, due to the thicker copper and gold plating at the gold fingers and the wider line, the impedance after production is often smaller than that of the lead. When high-speed signals pass through, impedance discontinuities such as signal instability, large jitter, ringing, and poor eye diagram will occur.

[0003] The traditional approach is to completely remove the reference layer beneath the gold fingers. This means there's no reference underneath, but removing the reference layer forces the gold fingers to reference only the surface gold fingers, resulting in uncontrollable and discontinuous impedance. Furthermore, the lack of a reference layer within the gold finger area leads to higher glue flow during manufacturing, causing inconsistencies in board thickness compared to other parts, resulting in an overall inconsistent board thickness. While the impedance may appear close to the 50Ω signal impedance, actual PCB routing involves other traces, copper traces, and vias, which introduce uncontrollable parasitic inductance and capacitance, disrupting the ideal impedance continuity. Therefore, simply increasing the reference distance cannot completely eliminate reflections. Utility Model Content

[0004] The purpose of this application is to provide a printed circuit board and memory module that eliminates the problems of signal waveform reflection and oscillation caused by abrupt changes in signal trace impedance.

[0005] This application discloses a printed circuit board, which includes at least a first trace layer, a first reference layer, and a second reference layer. The first trace layer is divided into a gold finger area and a signal trace area. The first reference layer is disposed below the first trace layer. The second reference layer is disposed on the side of the first reference layer away from the trace layer. The first reference layer includes a first dielectric area and a second dielectric area. The first dielectric area is disposed corresponding to the gold finger area of ​​the first trace layer, and the second dielectric area is disposed corresponding to the signal trace area of ​​the first trace layer. The first dielectric area is provided with a metal material, and the second dielectric area includes a cutout area.

[0006] Optionally, the metallic material in the first dielectric region is copper or a copper-molybdenum alloy.

[0007] Optionally, the gold finger area is provided with multiple gold fingers, each gold finger having the same length and width, and formed by the same process; the first dielectric area includes multiple first sub-dielectric areas, each first sub-dielectric area corresponding to one gold finger, and along the arrangement direction of the multiple gold fingers, the width of the first sub-dielectric area of ​​the first dielectric area is equal to the width of the corresponding gold finger, and along the direction from the first trace layer toward the first reference layer, the projection surface of the gold finger covers the corresponding first sub-dielectric area.

[0008] Optionally, the thickness of the copper in the first dielectric layer is d, where 0.45mil < d < 0.55mil.

[0009] Optionally, the gold finger area includes multiple gold fingers, the signal trace area includes multiple signal traces, and the width of the gold fingers is greater than the width of the signal traces.

[0010] Optionally, the hollowed-out area of ​​the second medium region is filled with polytetrafluoroethylene or epoxy resin.

[0011] Optionally, the second dielectric region includes multiple second sub-dielectric regions, each second sub-dielectric region corresponding to a signal trace. Along the arrangement direction of the multiple signal traces, the width of the second sub-dielectric region of the second dielectric region is greater than the width of the corresponding signal trace. Along the direction from the first trace layer to the first reference layer, the projection surface of the signal trace is located within the corresponding second sub-dielectric region, and the projection surface of the signal trace is smaller than the area of ​​the corresponding second sub-dielectric region.

[0012] Optionally, the multiple gold fingers and the multiple signal traces are arranged alternately and at intervals, and the distance between adjacent gold fingers and signal traces is equal.

[0013] Optionally, a thermally conductive silicone pad is embedded in the hollow area of ​​the second dielectric region of the first reference layer, and a liquid cooling channel is provided in the second reference layer to form an active heat dissipation circuit with the first dielectric region provided with metal material.

[0014] This application also discloses a memory module, which includes a printed circuit board as described in any of the above descriptions.

[0015] Compared to the current approach of completely removing the reference layer adjacent to the gold finger, this application sets a first dielectric region and a second dielectric region for the gold finger area and signal trace area of ​​the corresponding trace layer, respectively. The first dielectric region corresponds to the gold finger area of ​​the first trace layer, and the second dielectric region corresponds to the signal trace area of ​​the first trace layer. The first dielectric region contains metal material, and the second dielectric region includes a cutout area, which is equivalent to retaining the metal material in the gold finger area. The gold finger and the metal material form a small local parallel plate capacitor to achieve partial reference. By adjusting the area (A) of the metal material in the reference layer or selecting materials with different dielectric thicknesses (d) and dielectric constants (εᵣ), the capacitance value of the compensation capacitor can be precisely controlled, solving the problem of excessive signal reflection at the gold finger, which causes signal quality degradation and leads to abnormal operation of the memory module. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of the printed circuit board structure according to the first embodiment of this application; Figure 2 This is a schematic diagram of the printed circuit board structure according to the second embodiment of this application; Figure 3 This is a schematic diagram of the printed circuit board structure according to the third embodiment of this application; Figure 4 This is a schematic diagram of the printed circuit board structure according to the fourth embodiment of this application; Figure 5 This is a schematic diagram of a memory module according to the fifth embodiment of this application.

[0017] Among them, 100 is a printed circuit board; 110 is the first trace layer; 111 is the gold finger area; 112 is the signal trace area; 113 is the gold finger; 114 is the signal trace; 120 is the first reference layer; 121 is the first dielectric area; 122 is the second dielectric area; 123 is the first sub-dielectric area; 124 is the second sub-dielectric area; 125 is thermally conductive silicone; 130 is the second reference layer; 131 is the liquid cooling channel; and 200 is the memory module. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0020] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0023] As a first embodiment of this application, a printed circuit board 100 is disclosed. The printed circuit board 100 includes at least a first wiring layer 110, a first reference layer 120, and a second reference layer 130. The first wiring layer 110 is divided into a gold finger area 111 and a signal trace area 112. The first reference layer 120 is disposed below the first wiring layer 110. The second reference layer 130 is disposed on the side of the first reference layer 120 away from the wiring layer. The first reference layer 120 includes a first dielectric area 121 and a second dielectric area 122. The first dielectric area 121 is disposed corresponding to the gold finger area 111 of the first wiring layer 110, and the second dielectric area 122 is disposed corresponding to the signal trace area 112 of the first wiring layer 110. A metal material is disposed in the first dielectric area 121, and the second dielectric area 122 includes a cutout area. The metal material in the first dielectric area 121 is generally copper or a copper-molybdenum alloy.

[0024] In PCB boards, the width of the gold fingers in the gold finger area is generally wider than that of the signal traces, and the copper layer at the gold fingers is thicker than that of the leads. According to conventional design, under the same dielectric material parameters, due to the thicker copper layer and gold plating at the gold fingers and the wider line, the impedance after production is often lower than that of the leads. When high-speed signals pass through, this can cause problems such as signal instability and large jitter. Generally, the most important parameters affecting the impedance of signal lines are: line width and distance from the reference layer. When the reference layer distance is 3mil, the impedance of a 6mil signal line is 50Ω. When the signal enters the gold finger (15mil), the signal impedance becomes 30Ω. In this application, the area corresponding to the gold finger region 111 in the reference layer is not hollowed out, but filled with metal material. This makes the gold finger region 111 and the metal material of the first dielectric region 121 form a small local parallel plate capacitor. By adjusting the area (A) of the metal material in the reference layer or selecting materials with different dielectric thicknesses (d) and dielectric constants (εᵣ), the capacitance value of the compensation capacitor can be precisely controlled. This solves the problem that the signal reflection at the gold finger is too large, causing the signal quality to degrade and the memory module 200 to malfunction. It avoids directly hollowing out the area, where there are other traces, copper foil and vias around it. These conductors introduce uncontrollable parasitic inductance and capacitance, which destroys the ideal impedance continuity and cannot completely eliminate reflection.

[0025] The first dielectric region 121, filled with metal material, acts as a local shielding layer, attenuating the gold finger switching noise (SSN, typical value ±5V) to below -40dB (originally only -25dB), preventing coupling to the signal trace region 112. The hollowed-out design (no metal) of the second dielectric region 122 reduces dielectric loss, ensuring that the insertion loss of high-frequency signals (PCIe 6.0, 64GT / s) is controlled within -1.2dB. This application can implement "dynamic impedance topology" in the PCB and can further solve the problem of batch failure of DDR5 / HBM3 memory modules 200 caused by gold finger impedance mismatch.

[0026] like Figure 2 As shown, as a second embodiment of this application, it is a further refinement and improvement of the first embodiment described above. The gold finger area 111 is provided with a plurality of gold fingers 112, each gold finger 112 having the same length and width, formed by the same process, and each gold finger 112 is independently compensated to avoid mutual interference; the first dielectric area 121 includes a plurality of first sub-dielectric areas 123, each first sub-dielectric area 123 corresponding to one gold finger 112. Along the arrangement direction of the plurality of gold fingers 112, the width of the first sub-dielectric area 123 of the first dielectric area 121 is equal to the width of the corresponding gold finger 112. Along the direction from the first trace layer 110 toward the first reference layer 120, the projection surface of the gold finger 112 covers the corresponding first sub-dielectric area 123. The width of the sub-dielectric area is strictly aligned with the gold finger 112 to eliminate mutual coupling capacitance between adjacent fingers. The strict equal width design makes the A / d ratio of each sub-capacitor consistent, avoiding impedance dispersion caused by process deviations (such as etching errors).

[0027] The thickness of the copper in the first dielectric layer is d, where 0.45mil < d < 0.55mil. The specific thickness optimizes the capacitance value, making the compensation more accurate. When the frequency is > 28GHz, the skin depth δ = ρ / (πfμ) ≈ 0.48μm. A copper thickness of 0.5mil (12.7μm) can cover 99% of the current path, reducing high-frequency resistance fluctuations. Under temperature drift of -55℃ to 125℃, the impedance change rate is <5% (traditional design > 20%), meeting the reliability requirements of automotive-grade storage and advancing impedance compensation to the "micro-area level".

[0028] It should also be noted that the gold finger region 111 and the first dielectric region 121 form a small local parallel plate capacitor. The capacitance value of this capacitor can be precisely controlled by adjusting the area (A) of the reference copper foil or by selecting materials with different dielectric thicknesses (d) and dielectric constants (εᵣ). The capacitor compensates for the impedance. According to transmission line theory, the characteristic impedance Z0≈√(L / C), where L and C are the parasitic inductance and capacitance per unit length. In the gold finger region 111, the increased linewidth leads to a decrease in the inductance L per unit length, which is the main reason for the decrease in impedance Z0. The local reference metal material copper (also called copper foil) introduced in this application deliberately and controllably increases the capacitance C per unit length in this region, increasing the impedance and thus slowing down waveform oscillations.

[0029] Compared to the approach of completely hollowing out the layer beneath the gold finger 112, the metal material of the first dielectric region 121 in this application forms a controllable parallel-plate capacitor (C=εrA / d) with the gold finger 112. By adjusting the metal area A (e.g., reducing it to 80% of the projected surface of the gold finger 112) or the dielectric thickness d (0.45~0.55mil), the capacitance C of this region can be precisely increased, compensating for the decrease in impedance Z0 caused by the reduction in the inductance length L per unit length. This maintains the equivalent impedance of the gold finger region 111 at 48~52Ω (measured eye diagram opening improved by 35%, bit error rate BER < 1e-15). In contrast to the traditional hollowing-out approach, which introduces edge field effects and generates uncontrollable parasitic capacitance (ΔCparasitic ∼ 0.2pF / mm), this approach exacerbates impedance fluctuations. This approach achieves ideal impedance matching through active capacitor compensation.

[0030] like Figure 3As shown, this third embodiment of the present application is a further improvement and refinement of any of the above embodiments. The gold finger area 111 includes multiple gold fingers 112, the signal trace area 112 includes multiple signal traces 114, the width of the gold fingers 112 is greater than the width of the signal traces 114, the second dielectric area 122 includes multiple second sub-dielectric areas 124, each second sub-dielectric area 124 corresponds to one signal trace 114, along the arrangement direction of the multiple signal traces 114, the width of the second sub-dielectric area 124 of the second dielectric area 122 is greater than the width of the corresponding signal trace 114, along the direction from the first trace layer 110 toward the first reference layer 120, the projection surface of the signal trace 114 is located within the corresponding second sub-dielectric area 124, the projection surface of the signal trace 114 is smaller than the area of ​​the corresponding second sub-dielectric area 124, and the width of the gold fingers 112 can exceed the width of the signal trace 114 by 20% to 30%, forming a tapered impedance transition region (similar to Tapered). By increasing edge capacitance (line width difference), impedance dips caused by abrupt line width changes are offset. The spacing between the gold finger 112 (noise source) and the signal line (sensitive end) is fixed. Periodic ground plane segmentation is used to destroy crosstalk paths. The signal line projection area is smaller than the sub-dielectric area, forcing the electromagnetic field to be confined within the target area, reducing edge radiation (EMI reduction of 5dBμV / m). It is suitable for LPDDR5X memory design and maintains a clock jitter of <1ps at a high frequency of 3.2GHz.

[0031] It should also be noted that the hollow area of ​​the second dielectric region 122 is filled with polytetrafluoroethylene or epoxy resin, and the filling material improves the high-frequency performance; the dielectric constant of epoxy resin is εr=2.2 (FR-4 is 4.3), and the effective dielectric constant is homogenized after filling, eliminating the "air-resin" interface scattering of the traditional hollow area. The multiple gold fingers 112 and the multiple signal traces 114 are arranged alternately and at intervals, and the distance between adjacent gold fingers 112 and signal traces 114 is equal, and the staggered arrangement is balanced.

[0032] like Figure 4 As shown, as a fourth embodiment of this application, and an improvement and refinement of any of the above embodiments, a thermally conductive silicone pad 125 is embedded in the hollow area of ​​the second dielectric region 122 of the first reference layer 120, and a liquid cooling channel 131 is provided in the second reference layer 130, forming an active heat dissipation circuit with the first dielectric region 121 provided with metal material.

[0033] In this embodiment, considering that the resistance of copper conductor increases by 4.3% for every 10°C increase in temperature, resulting in an impedance Z0 drift of +8% (up to +4Ω at 100°C), the silicone pad (thermal conductivity 1.5W / mK) in this embodiment rapidly conducts heat from the gold finger area 111 to the liquid cooling channel 131. When the flow rate of the liquid cooling channel 131 is >1.2m / s, the thermal resistance drops to 0.05°C / W, making the temperature rise of the gold finger area 111 <15°C (traditional air cooling >35°C), and the impedance temperature coefficient drops from 0.08% / °C to 0.02% / °C. Within the range of -40°C to 85°C, the Z0 fluctuation is <±2Ω. When the power consumption of the memory module 200 is >50W / die (such as GDDR6X), traditional PCBs experience "thermal collapse" (local overheating → impedance collapse). This application improves the heat flux density carrying capacity by 3 times through metal-fluid bidirectional heat dissipation, ensuring the stable operation of the memory module 200.

[0034] like Figure 5 As shown, as a fifth embodiment of this application, this application also discloses a memory module 200, which includes a printed circuit board 100 as described in any of the above embodiments. The memory module 200 integrates the printed circuit board 100 PCB in the aforementioned embodiments to realize a three-in-one design of "signal-heat-structure", or it can be set up separately.

[0035] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0036] The above description is a further detailed explanation of this application in conjunction with specific optional embodiments. It should not be considered that the specific implementation of this application is limited to these descriptions. For those skilled in the art to which this application pertains, several simple deductions or substitutions can be made without departing from the concept of this application, and all of these should be considered to fall within the protection scope of this application.

Claims

1. A printed circuit board, characterized in that, The printed circuit board includes at least: The first routing layer is divided into the gold finger area and the signal routing area; The first reference layer is set below the first routing layer; The second reference layer is disposed on the side of the first reference layer that is away from the routing layer; The first reference layer includes a first dielectric region and a second dielectric region. The first dielectric region is configured to correspond to the gold finger region of the first trace layer, and the second dielectric region is configured to correspond to the signal trace region of the first trace layer. The first dielectric region contains a metal material, and the second dielectric region includes a cutout region.

2. The printed circuit board as described in claim 1, characterized in that, The metallic material in the first dielectric region is copper or a copper-molybdenum alloy.

3. The printed circuit board as described in claim 2, characterized in that, The gold finger area is provided with multiple gold fingers, each with the same length and width, and formed by the same process; the first dielectric area includes multiple first sub-dielectric areas, each first sub-dielectric area corresponding to one gold finger. Along the arrangement direction of the multiple gold fingers, the width of the first sub-dielectric area of ​​the first dielectric area is equal to the width of the corresponding gold finger. Along the direction from the first trace layer to the first reference layer, the projection surface of the gold finger covers the corresponding first sub-dielectric area.

4. The printed circuit board as described in claim 3, characterized in that, The thickness of copper in the first dielectric region is d, where 0.45mil < d < 0.55mil.

5. The printed circuit board as described in claim 1, characterized in that, The gold finger area includes multiple gold fingers, and the signal trace area includes multiple signal traces. The width of the gold fingers is greater than the width of the signal traces.

6. The printed circuit board as described in claim 5, characterized in that, The hollow area of ​​the second medium region is filled with polytetrafluoroethylene or epoxy resin.

7. The printed circuit board as described in claim 5 or 6, characterized in that, The second dielectric region includes multiple second sub-dielectric regions, each of which corresponds to a signal trace. Along the arrangement direction of the multiple signal traces, the width of the second sub-dielectric region of the second dielectric region is greater than the width of the corresponding signal trace. Along the direction from the first trace layer to the first reference layer, the projection surface of the signal trace is located within the corresponding second sub-dielectric region, and the projection surface of the signal trace is smaller than the area of ​​the corresponding second sub-dielectric region.

8. The printed circuit board as described in claim 5, characterized in that, Multiple gold fingers and multiple signal traces are arranged alternately and at intervals, and the distance between adjacent gold fingers and signal traces is equal.

9. The printed circuit board as claimed in claim 1, characterized in that, A thermally conductive silicone pad is embedded in the hollow area of ​​the second dielectric region of the first reference layer. The second reference layer is provided with a liquid cooling channel, which forms an active heat dissipation circuit with the first dielectric region provided with metal material.

10. A memory module, characterized in that, The memory module includes a printed circuit board as described in any one of claims 1-9.

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