Circuit board structure and electronic device

Abstract

The application provides a circuit board structure and an electronic device, and relates to the technical field of electronic devices. The circuit board structure comprises a first structure layer and a second structure layer; the first structure layer is provided with a first through hole in the thickness direction thereof; the first structure layer comprises a plurality of first conductive layers which are stacked; the first through hole penetrates the plurality of first conductive layers in sequence; and at least one first signal trace layer is included in the plurality of first conductive layers; the second structure layer is stacked on the first structure layer and is provided with a second through hole in the thickness direction; the second structure layer comprises a plurality of second conductive layers which are stacked; the second through hole penetrates the plurality of second conductive layers in sequence; and at least one second signal trace layer is included in the plurality of second conductive layers; the first through hole and the first signal trace layer form a first signal transmission path; and the second through hole and the second signal trace layer form a second signal transmission path.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a circuit board structure and electronic equipment. Background Technology

[0002] As electronic device bus speeds increase, circuit board manufacturing processes need continuous optimization to meet the demands of high-speed buses. Traditional multi-layer stacked circuit board structures have excessively long via stubs during signal transmission, affecting signal integrity and transmission quality. Therefore, these problems urgently need to be addressed. Utility Model Content

[0003] The purpose of this application is to provide a circuit board structure and electronic device, and the technical solution is as follows:

[0004] The first aspect of this application provides a circuit board structure, including:

[0005] A first structural layer has a first through hole along its thickness direction. The first structural layer includes a plurality of first conductive layers stacked together. The first through hole passes through the plurality of first conductive layers in sequence. The plurality of first conductive layers includes at least one first signal trace layer.

[0006] The second structural layer is stacked on the first structural layer and has a second through hole along the thickness direction. The second structural layer includes a plurality of stacked second conductive layers. The second through hole passes through the plurality of second conductive layers in sequence. The plurality of second conductive layers includes at least one second signal trace layer.

[0007] The first through-hole and the first signal trace layer form the first signal transmission path;

[0008] The second through-hole and the second signal trace layer form the second signal transmission path.

[0009] In some embodiments, the aforementioned circuit board structure, wherein the projection of the first through hole along the thickness direction of the second structural layer is misaligned with that of the second through hole.

[0010] In some embodiments, the aforementioned circuit board structure, wherein the number of first conductive layers is equal to or not equal to the number of second conductive layers.

[0011] In some embodiments, the aforementioned circuit board structure includes at least a first top layer, a first bottom layer, and a first intermediate layer located at both ends in the thickness direction, and the first bottom layer is closer to the second structural layer relative to the first top layer; the first intermediate layer and / or the first bottom layer are configured as a first signal trace layer.

[0012] In some embodiments, the aforementioned circuit board structure includes a first intermediate layer consisting of three layers: a first reference layer, a first target layer, and a second reference layer. The first reference layer and the second reference layer are located on opposite sides of the first target layer in the thickness direction, and are used to provide a reference plane for signal transmission when the first target layer is configured as a first signal trace layer.

[0013] In some embodiments, the aforementioned circuit board structure includes at least a second top layer, a second bottom layer, and a second intermediate layer located at both ends in the thickness direction, and the second top layer is closer to the first bottom layer than the second intermediate layer; the second intermediate layer and / or the second top layer are configured as second signal trace layers.

[0014] In some embodiments, the aforementioned circuit board structure includes a second intermediate layer consisting of three layers: a third reference layer, a second target layer, and a fourth reference layer. The third and fourth reference layers are located on opposite sides of the second target layer in the thickness direction, and are used to provide a reference plane for signal transmission when the second target layer is configured as a second signal trace layer.

[0015] In some embodiments, the aforementioned circuit board structure further includes an isolation layer between the first bottom layer and the second top layer, the isolation layer being used for signal isolation between the first signal transmission path and the second signal transmission path.

[0016] In some embodiments, the aforementioned circuit board structure is wherein the first structural layer and the second structural layer are connected by lamination.

[0017] A second aspect of this application provides an electronic device, comprising:

[0018] The casing, which has an accommodating space inside;

[0019] A circuit board structure is disposed within an accommodating space, wherein the circuit board structure includes:

[0020] A first structural layer has a first through hole along its thickness direction. The first structural layer includes a plurality of first conductive layers stacked together. The first through hole passes through the plurality of first conductive layers in sequence. The plurality of first conductive layers includes at least one first signal trace layer.

[0021] The second structural layer is stacked on the first structural layer and has a second through hole along the thickness direction. The second structural layer includes a plurality of stacked second conductive layers. The second through hole passes through the plurality of second conductive layers in sequence. The plurality of second conductive layers includes at least one second signal trace layer.

[0022] The first through-hole and the first signal trace layer form the first signal transmission path;

[0023] The second through-hole and the second signal trace layer form the second signal transmission path.

[0024] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 The schematic diagram illustrates a circuit board structure according to an embodiment of this application;

[0027] Figure 2 The schematic diagram illustrates the structure of a first signal transmission path and a second signal transmission path of a circuit board structure provided in an embodiment of this application.

[0028] Figure 3 This illustration shows a schematic diagram of another circuit board structure provided in an embodiment of this application;

[0029] Figure 4 This schematic diagram illustrates a circuit board structure provided in this application where the first target layer is configured as a first signal trace layer in the first structural layer.

[0030] Figure 5 This schematic diagram illustrates a circuit board structure provided in this application where the first bottom layer is configured as a first signal trace layer in the first structural layer.

[0031] Figure 6 This schematic diagram illustrates a circuit board structure provided in this application where both the first bottom layer and the first target layer are configured as first signal trace layers in the first structural layer.

[0032] Figure 7 This schematic diagram illustrates a circuit board structure provided in this application where the second target layer is configured as a second signal trace layer in the second structural layer.

[0033] Figure 8 This schematic diagram illustrates the structure of a circuit board structure provided in this application when the second top layer is configured as a second signal trace layer in the second structural layer.

[0034] Figure 9 This schematic diagram illustrates a circuit board structure provided in this application where both the second top layer and the second target layer are configured as second signal trace layers.

[0035] Figure 10 The schematic diagram illustrates the structure of the isolation layer between the first bottom layer and the second top layer of a circuit board structure provided in an embodiment of this application.

[0036] Explanation of icon numbers:

[0037] 1. First structural layer; 11. First through-hole; 12. First conductive layer; 121. First signal trace layer; 122. First top layer; 123. First bottom layer; 124. First intermediate layer; 1241. First reference layer; 1242. First target layer; 1243. Second reference layer;

[0038] 2. Second structural layer; 21. Second through-hole; 22. Second conductive layer; 221. Second signal trace layer; 222. Second top layer; 223. Second bottom layer; 224. Second intermediate layer; 2241. Third reference layer; 2242. Second target layer; 2243. Fourth reference layer;

[0039] 3. First signal transmission path;

[0040] 4. Second signal transmission path;

[0041] 5. Isolation layer;

[0042] H, thickness direction. Detailed Implementation

[0043] The embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of this disclosure by way of example, but should not be used to limit the scope of this disclosure. This disclosure can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0044] These embodiments are provided to make the disclosure thorough and complete, and to fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, material composition, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0045] It should be noted that, in the description of this disclosure, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] Furthermore, the terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. "Vertical" is not strictly vertical, but within the permissible margin of error. "Parallel" is not strictly parallel, but within the permissible margin of error. Terms such as "including" or "contains" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well.

[0047] It should also be noted that, in the description of this disclosure, unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure depending on the specific circumstances. When a particular device is described as being located between a first device and a second device, an intermediary device may or may not be present between the particular device and the first or second device.

[0048] All terms used in this disclosure have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0049] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0050] Example 1

[0051] like Figure 1 and Figure 2As shown, the first aspect of this application provides a circuit board structure, including a first structural layer 1 and a second structural layer 2; the first structural layer 1 has a first through hole 11 formed along its thickness direction H, the first structural layer 1 includes a plurality of first conductive layers 12 stacked together, the first through hole 11 sequentially penetrates the plurality of first conductive layers 12, and the plurality of first conductive layers 12 includes at least one first signal trace layer 121; the second structural layer 2 is stacked on the first structural layer 1 and has a second through hole 21 formed along its thickness direction H, the second structural layer 2 includes a plurality of second conductive layers 22 stacked together, the second through hole 21 sequentially penetrates the plurality of second conductive layers 22, and the plurality of second conductive layers 22 includes at least one second signal trace layer 221; the first through hole 11 and the first signal trace layer 121 form a first signal transmission path 3; the second through hole 21 and the second signal trace layer 221 form a second signal transmission path 4.

[0052] Specifically, the circuit board structure provided in this application is divided into two independent structural layers: a first structural layer 1 and a second structural layer 2. The first structural layer 1 includes multiple stacked first conductive layers 12, and a first through-hole 11 is formed along the thickness direction H to pass through the multiple first conductive layers 12 sequentially. The first through-hole 11 can be a metallized conductive via, which can be formed by mechanical drilling followed by processes such as copper plating and electroplating to meet the signal transmission routing requirements. The second structural layer 2 includes multiple stacked second conductive layers 22, and a first through-hole 11 is formed along the thickness direction H to pass through the multiple first conductive layers 12 sequentially. The second through-hole 21 can be made using the same process as the first through-hole 11, and is not specifically limited. After forming the through-holes, the first structural layer 1 and the second structural layer 2 can be pressed together using a lamination process. Through-holes can be formed to mechanically fix the two structural layers together, and fasteners can be inserted into the through-holes to improve the stability of the first structural layer 1 and the second structural layer 2 after lamination.

[0053] To achieve signal transmission in the circuit board structure, this application includes at least one first signal trace layer 12 among multiple first conductive layers 12. The first through-hole 11 and the first signal trace layer 121 can form a first signal transmission path 3, allowing high-speed signals to be transmitted along the first signal transmission path 3. The multiple second conductive layers 22 include at least one second signal trace layer 221, and the second through-hole 21 and the second signal trace layer 221 form a second signal transmission path 4. Since the first through-hole 11 in this application only penetrates multiple first conductive layers 12 in the first structural layer 1 and does not extend to the second structural layer 2, and the second through-hole 21 only penetrates multiple second conductive layers 22 in the second structural layer 2 and does not extend to the first structural layer 1, the through-holes are independently installed within their respective structural layers. This allows the two structural layers to share the overall number of conductive layers required for the circuit board structure. Taking the first structural layer 1 as an example, the reduced number of conductive layers shortens the via stub length during signal transmission, and may even eliminate the via stub altogether. Via studs can generate resonance, and the resonant frequency is inversely proportional to the length of the via stud. That is, the longer the via stud, the more it affects the transmitted signal. When the resonant frequency falls within the signal spectrum, it will cause inter-symbol interference and affect the signal integrity during transmission. This application shortens or even eliminates the via stud length to avoid the resonant frequency falling within the signal spectrum, thereby improving signal integrity, suppressing signal reflection and inter-symbol interference, improving eye diagram opening and system bit error rate performance, and enabling the circuit board structure to stably support signal transmission. The same applies to the second structural layer 2.

[0054] The following example illustrates how the technical solution of this application can effectively reduce the number of via studs. For instance, in a circuit board structure with 10 conductive layers, in a traditional solution, when a high-speed signal needs to be transmitted on the 3rd layer, the length of the resulting via stud covers the 7 conductive layers from the 4th to the 10th layer. However, this application, by setting a first structural layer 1 with 5 first conductive layers 12 and a second structural layer 2 with 5 second conductive layers 22, ensures that when a high-speed signal needs to be transmitted on the 3rd layer of the first structural layer 1, the length of the resulting via stud is interrupted after covering the 4th and 5th layers of the first conductive layers 12. When a high-speed signal needs to be transmitted on the 5th layer of the first structural layer 1, no via stud is generated. The same principle applies to the transmission of signals on the second structural layer 2; both methods can shorten or even eliminate via studs, effectively improving signal integrity, suppressing signal reflection and inter-symbol interference, improving eye diagram opening and system bit error rate performance, and enabling the circuit board structure to stably support signal transmission.

[0055] In this application, the first signal transmission path 3 can be used to transmit differential signals with an effective data rate greater than or equal to 5Gbps, and the second signal transmission path 4 can be used to transmit differential signals with an effective data rate greater than or equal to 5Gbps. 5Gbps is an industry-recognized threshold for high-speed signals. Differential signals with an effective data rate greater than or equal to 5Gbps can meet the high-speed signal transmission requirements of protocols such as USB3.2Gen1 (Universal Serial Bus 3.2 Generation 1), USB3.2Gen2 (Universal Serial Bus 3.2 Generation 2), and PCIe Gen3-Gen6 (Peripheral Component Interconnect Express Generation 3-Generation 6).

[0056] The first aspect of this application provides a circuit board structure, including a first structural layer 1 and a second structural layer 2; the first structural layer 1 has a first through hole 11 formed along its thickness direction H, the first structural layer 1 includes a plurality of first conductive layers 12 stacked together, the first through hole 11 sequentially penetrates the plurality of first conductive layers 12, and the plurality of first conductive layers 12 includes at least one first signal trace layer 121; the second structural layer 2 is stacked on the first structural layer 1 and has a second through hole 21 formed along its thickness direction H, the second structural layer 2 includes a plurality of second conductive layers 22 stacked together, the second through hole 21 sequentially penetrates the plurality of second conductive layers 22, and the plurality of second conductive layers 22 includes at least one second signal trace layer 221; the first through hole 11 and the first signal trace layer 121 form a first signal transmission path 3; the second through hole 21 and the second signal trace layer 221 form a second signal transmission path 4. This application divides the entire circuit board structure into two independent structural layers: a first structural layer 1 and a second structural layer 2. Through-holes within each structural layer are independently located on their respective conductive layers. There is no electrical connection between the first structural layer 1 and the second structural layer 2. By distributing the number of conductive layers required for the overall circuit board structure through these two structural layers, the length of via studs in any structural layer during signal transmission is shortened, or even eliminated. This prevents the resonant frequency from falling within the signal spectrum, improving signal integrity, suppressing signal reflection and inter-symbol interference, and enhancing eye diagram opening and system bit error rate performance. This allows the circuit board structure to stably and effectively support signal transmission. Through the application of this application, the technical problem of excessively long via studs in traditional multi-layer stacked circuit board structures, which affect signal integrity and transmission quality during signal transmission, is solved.

[0057] like Figure 3As shown, in some embodiments, the projection of the first through hole 11 along the thickness direction H of the second structural layer 2 is misaligned with that of the second through hole 21.

[0058] Specifically, in order to effectively reduce the electromagnetic coupling between the first signal transmission path 3 and the second signal transmission path 4, this application sets the projection of the first through hole 11 along the thickness direction H of the second structural layer 2 to be staggered with that of the second through hole 21, so as to avoid crosstalk caused by high-frequency coupling. By staggering the arrangement of the first through hole 11 and the second through hole 21, the lateral spacing is increased, the overlapping area of ​​electric field and magnetic field is weakened, thereby suppressing crosstalk noise between structural layers.

[0059] In some embodiments, the number of first conductive layers 12 may be equal to or not equal to the number of second conductive layers 22.

[0060] Specifically, in some embodiments, the number of first conductive layers 12 can be set to be equal to the number of second conductive layers 22. The first structural layer 1 and the second structural layer 2 tend to be symmetrical in terms of physical thickness and thermal expansion characteristics, which is beneficial to maintaining the flatness of the overall board surface during the secondary lamination process. Furthermore, the symmetrical design with equal numbers can also achieve impedance matching and return path symmetry, enabling the circuit board structure to adapt to dual signal channel transmission systems with equivalent functions or similar signal densities, such as dual-path PCIe interconnect architecture, symmetrical memory channel layout, etc.

[0061] In other embodiments, the number of the first conductive layer 12 may be different from the number of the second conductive layer 22, so that the circuit board structure can flexibly adapt to the differentiated wiring requirements in electronic devices and meet the structural layer distribution under different wiring densities, thereby improving the targeting of signal wiring resource application and optimizing the wiring cost allocation in the circuit board structure.

[0062] like Figures 4 to 6 As shown, in some embodiments, the plurality of first conductive layers 12 include at least a first top layer 122, a first bottom layer 123 located at both ends of the thickness direction H, and a first intermediate layer 124 between the first top layer 122 and the first bottom layer 123, wherein the first bottom layer 123 is closer to the second structural layer 2 relative to the first top layer 122; the first intermediate layer 124 and / or the first bottom layer 123 are configured as a first signal routing layer 121.

[0063] Specifically, this application provides multiple first conductive layers 12, including at least a first top layer 122, a first bottom layer 123 located at both ends of the thickness direction H, and a first intermediate layer 124 between the first top layer 122 and the first bottom layer 123. The first top layer 122 can accommodate memory processors, pads, power networks, etc., and does not need to carry high-speed signals. This application can configure the first intermediate layer 124 as a first signal routing layer 121. The first intermediate layer 124 is located in the inner layer of the first structural layer 1, which can avoid interference sources such as pads and component pins on the surface of the circuit board structure, reduce impedance changes and crosstalk, and ensure signal quality.

[0064] This application can also configure the first bottom layer 123 as the first signal routing layer 121. Since the first bottom layer 123 is the boundary of the first structural layer 1 near the second structural layer 2, the first through-hole 11 is only formed within the first structural layer 1. When the high-speed signal terminates in the first bottom layer 123, its via path naturally ends there, without forming a via stump, fundamentally avoiding eye diagram closure and bit error rate degradation. In some embodiments, when the first bottom layer 123 is configured as the first signal routing layer 121, this application can also set the second conductive layer 22 in the second structural layer 2 near the first bottom layer 123 as the reference plane layer of the first bottom layer 123, thereby providing a signal return path, improving impedance stability, and ensuring stable transmission of high-speed signals.

[0065] like Figures 4 to 6 As shown, in some embodiments, the first intermediate layer 124 has three layers: a first reference layer 1241, a first target layer 1242, and a second reference layer 1243. The first reference layer 1241 and the second reference layer 1243 are located on both sides of the first target layer 1242 in the thickness direction H, respectively, and are used to provide a reference plane for signal transmission when the first target layer 1242 is configured as the first signal trace layer 121.

[0066] Specifically, in some embodiments, the first intermediate layer 124 is configured as three layers: a first reference layer 1241, a first target layer 1242, and a second reference layer 1243. The first target layer 1242 is configured as a first signal trace layer 121 for transmitting differential signals with an effective data rate of not less than 5Gbps. The first reference layer 1241 and the second reference layer 1243 are located on opposite sides of the first target layer 1242 in the thickness direction H, and can be either a GND (Ground) plane or a power plane, providing a reference plane for signal transmission when the first target layer 1242 is configured as the first signal trace layer 121. Because the first target layer 1242 is tightly sandwiched between two complete reference planes, its transmission line is in a fully shielded environment. The electromagnetic field is confined between the two reference layers, significantly reducing external radiation and sensitivity to external interference, providing high impedance stability, and reducing crosstalk effects, forming a stripline structure with excellent shielding performance and improving the integrity of signal transmission.

[0067] Furthermore, when the first target layer 1242 transmits differential signals with an effective data rate of not less than 5Gbps, the first reference layer 1241 and the second reference layer 1243 provide bidirectional return channels for the signal, ensuring the continuity of the signal return path, avoiding impedance abrupt changes and radiation enhancement, and ensuring signal transmission quality.

[0068] like Figures 7 to 9 As shown, in some embodiments, the plurality of second conductive layers 22 include at least a second top layer 222, a second bottom layer 223 located at both ends of the thickness direction H, and a second intermediate layer 224 between the second top layer 222 and the second bottom layer 223, wherein the second top layer 222 is closer to the first bottom layer 123 relative to the second intermediate layer 224; the second intermediate layer 224 and / or the second top layer 222 are configured as a second signal trace layer 221.

[0069] Specifically, this application provides multiple second conductive layers 22, including at least a second top layer 222, a second bottom layer 223 located at both ends of the thickness direction H, and a second intermediate layer 224 between the second top layer 222 and the second bottom layer 223. The second bottom layer 223 can be used to route low-speed control signal traces such as system management buses and debugging interfaces, and can also be provided with heat dissipation pads and heat dissipation vias to conduct heat generated by the circuit board structure to the external environment, thereby achieving heat dissipation for the circuit board structure and ensuring thermal reliability during signal transmission. This application can configure the second intermediate layer 224 as a second signal trace layer 221. The second intermediate layer 224 is located in the inner layer of the second structural layer 2, which can avoid interference sources such as pads and component pins on the surface of the circuit board structure, reduce impedance changes and crosstalk, and ensure signal quality.

[0070] This application can also configure the second top layer 222 as the second signal routing layer 221. Since the second top layer 222 is the boundary of the second structural layer 2 near the first structural layer 1, the second through-hole 21 is only formed within the second structural layer 2. When the high-speed signal terminates in the second top layer 222, its via path naturally ends there, without forming a via stump, fundamentally avoiding eye diagram closure and bit error rate degradation. In some embodiments, when the second top layer 222 is configured as the second signal routing layer 221, this application can also set the first conductive layer 12 in the first structural layer 1 near the second top layer 222 as the reference plane layer of the second top layer 222, thereby providing a signal return path, improving impedance stability, and ensuring stable transmission of high-speed signals.

[0071] like Figures 7 to 9 As shown, in some embodiments, the second intermediate layer 224 has three layers: a third reference layer 2241, a second target layer 2242, and a fourth reference layer 2243. The third reference layer 2241 and the fourth reference layer 2243 are located on both sides of the second target layer 2242 in the thickness direction H, respectively, and are used to provide a reference plane for signal transmission when the second target layer 2242 is configured as the second signal trace layer 221.

[0072] Specifically, in some embodiments, the second intermediate layer 224 is configured as three layers: a third reference layer 2241, a second target layer 2242, and a fourth reference layer 2243. The second target layer 2242 is configured as a second signal trace layer 221 for transmitting differential signals with an effective data rate of not less than 5Gbps. The third reference layer 2241 and the fourth reference layer 2243 are located on opposite sides of the second target layer 2242 in the thickness direction H, and can be either a GND (Ground) plane or a power plane, providing reference planes for signal transmission when the second target layer 2242 is configured as the second signal trace layer 221. Because the second target layer 2242 is tightly sandwiched between two complete reference planes, its transmission line is in a fully shielded environment. The electromagnetic field is confined between the two reference layers, significantly reducing external radiation and sensitivity to external interference, providing high impedance stability, and reducing crosstalk effects, forming a stripline structure with excellent shielding performance and improving the integrity of signal transmission.

[0073] Furthermore, when the second target layer 2242 transmits differential signals with an effective data rate of not less than 5Gbps, the third reference layer 2241 and the fourth reference layer 2243 provide bidirectional return channels for the signal, ensuring the continuity of the signal return path, avoiding impedance abrupt changes and radiation enhancement, and ensuring signal transmission quality.

[0074] like Figure 10As shown, in some embodiments, an isolation layer 5 is further provided between the first bottom layer 123 and the second top layer 222. The isolation layer 5 is used for signal isolation between the first signal transmission path 3 and the second signal transmission path 4.

[0075] Specifically, this application may further provide an isolation layer 5 between the first bottom layer 123 and the second top layer 222. The isolation layer 5 reflects or absorbs electromagnetic waves between the first structural layer 1 and the second structural layer 2, preventing crosstalk across structural layers and achieving signal isolation between the first signal transmission path 3 and the second signal transmission path 4, thereby improving the integrity and stability of signal transmission. The isolation layer 5 can be a high-dielectric material layer, a metal shielding film, etc., and is not specifically limited. By pressing the first structural layer 1 and the second structural layer 2 together, the isolation layer 5 located in the middle can also be cured and pressed together under high temperature and pressure using a prepreg, thereby enabling the isolation layer 5 to form a complete and stable circuit board structure with the first structural layer 1 and the second structural layer 2, establishing an effective isolation barrier between the first signal transmission path 3 and the second signal transmission path 4.

[0076] In some embodiments, the first structural layer 1 and the second structural layer 2 are connected by compression bonding.

[0077] Specifically, in order to achieve a complete and stable circuit board structure between the first structural layer 1 and the second structural layer 2, this application sets the first structural layer 1 and the second structural layer 2 to be connected by lamination. This can be achieved by first performing mechanical drilling and hole metallization processes on the first structural layer 1 and the second structural layer 2 respectively, so that the first through hole 11 is formed and terminates only inside the first structural layer 1, and the second through hole 21 is formed and terminates only inside the second structural layer 2. Then, the first structural layer 1 and the second structural layer 2 are aligned and stacked through a prepreg, and a second lamination is performed under high temperature and high pressure conditions to form a complete and stable circuit board structure.

[0078] Example 2

[0079] A second aspect of this application provides an electronic device, including a housing and a circuit board structure; the housing has an accommodating space; the circuit board structure is disposed within the accommodating space, wherein the circuit board structure includes: a first structural layer 1 and a second structural layer 2; the first structural layer 1 has a first through hole 11 formed along its thickness direction H, the first structural layer 1 includes a plurality of first conductive layers 12 stacked together, the first through hole 11 sequentially penetrates the plurality of first conductive layers 12, and the plurality of first conductive layers 12 includes at least one first signal trace layer 121; the second structural layer 2 is stacked on the first structural layer 1 and has a second through hole 21 formed along its thickness direction H, the second structural layer 2 includes a plurality of second conductive layers 22 stacked together, the second through hole 21 sequentially penetrates the plurality of second conductive layers 22, and the plurality of second conductive layers 22 includes at least one second signal trace layer 221; the first through hole 11 and the first signal trace layer 121 form a first signal transmission path 3; the second through hole 21 and the second signal trace layer 221 form a second signal transmission path 4.

[0080] For details on the specific structure of the circuit board, please refer to Embodiment 1, which will not be repeated here.

[0081] The electronic device provided in this application can be a server main unit, an AI acceleration card (Artificial Intelligence Acceleration Card), a GPU (Graphics Processing Unit) computing card, a TPU (Tensor Processing Unit) computing card, a network switch, a solid-state drive, etc., and is not limited to any specific device. As long as the circuit board structure of this application can shorten the length of the via residual stakes, improve signal integrity, and stably and with high quality support for signal transmission.

[0082] A second aspect of this application provides an electronic device, including a housing and a circuit board structure; the housing has an accommodating space; the circuit board structure is disposed within the accommodating space, wherein the circuit board structure includes: a first structural layer 1 and a second structural layer 2; the first structural layer 1 has a first through hole 11 formed along its thickness direction H, the first structural layer 1 includes a plurality of first conductive layers 12 stacked together, the first through hole 11 sequentially penetrates the plurality of first conductive layers 12, and the plurality of first conductive layers 12 includes at least one first signal trace layer 121; the second structural layer 2 is stacked on the first structural layer 1 and has a second through hole 21 formed along its thickness direction H, the second structural layer 2 includes a plurality of second conductive layers 22 stacked together, the second through hole 21 sequentially penetrates the plurality of second conductive layers 22, and the plurality of second conductive layers 22 includes at least one second signal trace layer 221; the first through hole 11 and the first signal trace layer 121 form a first signal transmission path 3; the second through hole 21 and the second signal trace layer 221 form a second signal transmission path 4. This application divides the entire circuit board structure into two independent structural layers: a first structural layer 1 and a second structural layer 2. Through-holes within each structural layer are independently located on their respective conductive layers. There is no electrical connection between the first structural layer 1 and the second structural layer 2. By distributing the number of conductive layers required for the overall circuit board structure through these two structural layers, the length of via studs in any structural layer during signal transmission is shortened, or even eliminated. This prevents the resonant frequency from falling within the signal spectrum, improving signal integrity, suppressing signal reflection and inter-symbol interference, and enhancing eye diagram opening and system bit error rate performance. This allows the circuit board structure to stably and effectively support signal transmission. Through the application of this application, the technical problem of excessively long via studs in traditional multi-layer stacked circuit board structures, which affect signal integrity and transmission quality during signal transmission, is solved.

[0083] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0084] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. In particular, as long as there is no structural conflict, the technical features mentioned in the various embodiments can be combined in any manner.

Claims

1. A circuit board structure, characterized in that, include: A first structural layer has a first through hole along its thickness direction. The first structural layer includes a plurality of first conductive layers stacked together. The first through hole passes through the plurality of first conductive layers in sequence. The plurality of first conductive layers includes at least one first signal trace layer. The second structural layer is stacked on the first structural layer and has a second through hole along the thickness direction. The second structural layer includes a plurality of stacked second conductive layers. The second through hole passes through the plurality of second conductive layers in sequence. The plurality of second conductive layers includes at least one second signal trace layer. The first through hole and the first signal trace layer form a first signal transmission path; The second through hole and the second signal trace layer form a second signal transmission path.

2. The circuit board structure according to claim 1, characterized in that, The projection of the first through hole onto the second structural layer along the thickness direction is misaligned with that of the second through hole.

3. The circuit board structure according to claim 1, characterized in that, The number of the first conductive layers may be equal to or not equal to the number of the second conductive layers.

4. The circuit board structure according to claim 1, characterized in that, The plurality of first conductive layers include at least a first top layer, a first bottom layer, and a first intermediate layer located at both ends of the thickness direction, and the first bottom layer is closer to the second structural layer relative to the first top layer; The first intermediate layer and / or the first bottom layer are configured as the first signal routing layer.

5. The circuit board structure according to claim 4, characterized in that, The first intermediate layer consists of three layers: a first reference layer, a first target layer, and a second reference layer. The first reference layer and the second reference layer are located on both sides of the first target layer in the thickness direction, respectively, and are used to provide a reference plane for signal transmission when the first target layer is configured as a first signal trace layer.

6. The circuit board structure according to claim 4, characterized in that, The plurality of second conductive layers include at least a second top layer, a second bottom layer located at both ends of the thickness direction, and a second intermediate layer between the second top layer and the second bottom layer, wherein the second top layer is closer to the first bottom layer relative to the second intermediate layer; The second intermediate layer and / or the second top layer are configured as the second signal routing layer.

7. The circuit board structure according to claim 6, characterized in that, The second intermediate layer consists of three layers: the third reference layer, the second target layer, and the fourth reference layer. The third reference layer and the fourth reference layer are located on both sides of the second target layer in the thickness direction, respectively, and are used to provide a reference plane for signal transmission when the second target layer is configured as the second signal trace layer.

8. The circuit board structure according to claim 7, characterized in that, An isolation layer is further provided between the first bottom layer and the second top layer, and the isolation layer is used to isolate the signals of the first signal transmission path and the second signal transmission path.

9. The circuit board structure according to claim 1, characterized in that, The first structural layer and the second structural layer are connected by compression bonding.

10. An electronic device, characterized in that, include: A housing having an accommodating space inside; A circuit board structure, wherein the circuit board structure is disposed within the accommodating space, and wherein the circuit board structure includes: A first structural layer has a first through hole along its thickness direction. The first structural layer includes a plurality of first conductive layers stacked together. The first through hole passes through the plurality of first conductive layers in sequence. The plurality of first conductive layers includes at least one first signal trace layer. The second structural layer is stacked on the first structural layer and has a second through hole along the thickness direction. The second structural layer includes a plurality of stacked second conductive layers. The second through hole passes through the plurality of second conductive layers in sequence. The plurality of second conductive layers includes at least one second signal trace layer. The first through hole and the first signal trace layer form a first signal transmission path; The second through hole and the second signal trace layer form a second signal transmission path.

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