A double-sided circuit board
Patent Information
- Application Number
- CN202521987250.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2035-09-16
AI Technical Summary
[0004]有鉴于此，本实用新型的一个目的是提出一种双面线路板及其制作方法,以解决现有技术中金属镀层在印刷种子层上结合稳定性不佳的问题
[0018]本申请通过在通孔的第一孔壁和第二孔壁上形成连续的镀敷种子层，而第三孔壁则依然为金属层原始的金属材质，进而使所形成在通孔内的第一金属镀层由于与第三孔壁之间金属之间的沉积结合，强化了通孔内的第一金属镀层在整个通孔孔壁上的结合力，提高了第一金属镀层在通孔内的结构稳定性和可靠性；另外，形成在金属层表面和印刷导电层表面的第一金属镀层与通孔内的第一金属镀层为一体化结构，因此第一金属镀层存在多向结合力的结构束缚，进一步提升了第一金属镀层的结构稳定性和可靠性。
Smart Images
Figure CN224909761U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electronic additive manufacturing technology, and in particular relates to a double-sided circuit board. Background Technology
[0002] Currently, electronic additive manufacturing has begun to be gradually applied and implemented. It mainly forms conductive patterns directly on the substrate through printing processes. Although it has advantages such as simple process, high efficiency and environmental protection compared to traditional etching, it still has shortcomings in terms of conductivity, solderability and oxidation resistance. Therefore, many manufacturers have begun to improve its process.
[0003] Among them, the improved scheme of first forming a patterned seed layer directly using the printing process, and then forming a patterned metal coating directly on the seed layer through the plating process can effectively solve the shortcomings of conductive paste in terms of conductivity, solderability, and oxidation resistance. However, the bonding stability of the metal coating on the printed seed layer still needs to be improved. Utility Model Content
[0004] In view of this, one objective of this utility model is to propose a double-sided circuit board and its manufacturing method to solve the problem of poor bonding stability of metal plating on the printing seed layer in the prior art.
[0005] In some illustrative embodiments, the method for fabricating the double-sided circuit board includes: providing a laminate comprising: a first insulating layer and a metal layer formed on a first surface of the first insulating layer; forming a patterned printed conductive layer on a second surface of the first insulating layer away from the metal layer; wherein the printed conductive layer and the metal layer partially overlap with respect to the first insulating layer; forming vias sequentially penetrating the printed conductive layer, the insulating layer, and the metal layer in the overlapping region to obtain a laminate with vias; wherein the via wall is composed of a first via wall of the printed conductive layer, a second via wall of the insulating layer, and a third via wall of the metal layer; forming a continuous plating seed layer on the first via wall and the second via wall; forming an integrated first metal plating layer on the surface of the metal layer and the printed conductive layer, the third via wall of the metal layer, and the plating seed layer; and performing a patterned etching process on the metal layer and the first metal plating layer thereon.
[0006] In some alternative embodiments, before forming a continuous plating seed layer on the first hole wall and the second hole wall, the method further includes: masking the second surface of the first insulating layer and the surface of the printed conductive layer to prevent the plating seed layer from adhering to the second surface of the first insulating layer and the surface of the printed conductive layer.
[0007] In some optional embodiments, the masking process for the second surface of the first insulating layer and the surface of the printed conductive layer includes: temporarily bonding the two perforated laminates together on the side where their respective printed conductive layers are located, thereby masking the second surface of their respective first insulating layers and the surface of their respective printed conductive layers; before forming an integrated first metal plating layer on the surface of the metal layer and the printed conductive layer, the third hole wall of the metal layer, and the plating seed layer, the process further includes: separating the two perforated laminates.
[0008] In some alternative embodiments, forming a continuous plating seed layer on the first hole wall and the second hole wall includes forming a continuous plating seed layer on the first hole wall of the printed conductive layer and the second hole wall of the first insulating layer by means of a black hole or black shadow process.
[0009] In some optional embodiments, after forming a continuous plating seed layer on the first hole wall of the printed conductive layer and the second hole wall of the first insulating layer by means of a black hole or shadow process, the method further includes: removing the plating seed layer attached to the surface of the metal layer and / or the third hole wall of the metal layer by means of a flash etching process.
[0010] In some alternative embodiments, after patterning the etching process of the metal layer and the first metal plating thereon, the method further includes forming a second insulating layer on the first insulating layer that covers a portion of the first metal plating.
[0011] In some alternative embodiments, the second insulating layer exposes a portion of the non-porous surface of the first metal plating; a second metal plating is formed on the exposed non-porous surface of the first metal plating.
[0012] Another objective of this invention is to provide a double-sided circuit board to solve the problems in the prior art.
[0013] In some illustrative embodiments, the double-sided circuit board includes: a first insulating layer, a patterned metal layer formed on a first surface of the first insulating layer, and a patterned printed conductive layer formed on a second surface of the first insulating layer away from the metal layer; the printed conductive layer and the metal layer partially overlap with each other across the first insulating layer, and a through-hole is formed in the overlapping area, sequentially penetrating the printed conductive layer, the insulating layer, and the metal layer; the hole wall of the through-hole is composed of a first hole wall of the printed conductive layer, a second hole wall of the insulating layer, and a third hole wall of the metal layer; a continuous plating seed layer is formed on the first hole wall and the second hole wall; and a first metal plating layer is integrally formed on the surface of the patterned metal layer and the printed conductive layer, the third hole wall of the metal layer, and the plating seed layer.
[0014] In some alternative embodiments, the double-sided circuit board further includes a second insulating layer formed on the first insulating layer that covers a portion of the first metal plating.
[0015] In some alternative embodiments, the second insulating layer exposes a portion of the non-porous surface of the first metal plating.
[0016] In some alternative embodiments, the double-sided circuit board further includes a second metal plating layer formed on the non-hole surface of the exposed first metal plating layer.
[0017] Compared with the prior art, this application has the following advantages:
[0018] This application forms a continuous seed layer on the first and second walls of a through-hole, while the third wall remains the original metal material of the metal layer. This strengthens the adhesion of the first metal plating within the through-hole to the entire through-hole wall due to the deposition and bonding between the first metal plating and the third wall, thus improving the structural stability and reliability of the first metal plating within the through-hole. Furthermore, the first metal plating formed on the surface of the metal layer and the printed conductive layer is an integrated structure with the first metal plating within the through-hole. Therefore, the first metal plating is structurally constrained by multi-directional bonding forces, further enhancing its structural stability and reliability. Attached Figure Description
[0019] Figure 1 This is a process example of the manufacturing method of the double-sided circuit board in the embodiments of this utility model. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0021] It should be noted that, where there is no conflict, the various technical features in the embodiments of this utility model can be combined with each other.
[0022] This utility model discloses a method for manufacturing a double-sided circuit board, specifically, as follows: Figure 1 As shown, Figure 1 This is a process example of the manufacturing method of the double-sided circuit board in this utility model embodiment. The manufacturing method of the double-sided circuit board includes:
[0023] Step S11: Provide a laminate, including: a first insulating layer 10 and a metal layer 20 formed on a first surface of the first insulating layer 10; wherein the metal layer 20 can be formed on the first insulating layer 10 by lamination or deposition.
[0024] Step S12: A patterned printed conductive layer 30 is formed on the second surface of the first insulating layer 10 away from the metal layer 20; wherein the printed conductive layer 30 and the metal layer 20 partially overlap through the first insulating layer 10.
[0025] Step S13: Form a through hole 40 in the overlapping area that sequentially penetrates the printed conductive layer 30, the first insulating layer 10 and the metal layer 20 to obtain a perforated laminate; wherein, the hole wall of the through hole 40 is composed of the first hole wall 41 of the printed conductive layer 30, the second hole wall 42 of the insulating layer 10 and the third hole wall 43 of the metal layer 20.
[0026] Step S14: A continuous plating seed layer 50 is formed on the first hole wall 41 and the second hole wall 42;
[0027] Step S15: An integrated first metal plating layer 60 is formed on the surface of the metal layer 20 and the printed conductive layer 30, the third hole wall 43 of the metal layer 20, and the plating seed layer 50.
[0028] Step S16: Perform patterned etching on the metal layer 20 and the first metal plating layer 60 thereon.
[0029] This application forms a continuous seed layer on the first and second walls of a through-hole, while the third wall remains the original metal material of the metal layer. This strengthens the adhesion of the first metal plating within the through-hole to the entire through-hole wall due to the deposition and bonding between the first metal plating and the third wall, thus improving the structural stability and reliability of the first metal plating within the through-hole. Furthermore, the first metal plating formed on the surface of the metal layer and the printed conductive layer is an integrated structure with the first metal plating within the through-hole. Therefore, the first metal plating is structurally constrained by multi-directional bonding forces, further enhancing its structural stability and reliability.
[0030] In this embodiment of the invention, the metal layer in the laminate can be one or more of gold, silver, copper, iron, nickel, zinc, and aluminum; the first insulating layer can be a rigid board or a flexible board. Rigid boards include, but are not limited to, FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (acrylic), etc.; flexible boards include, but are not limited to, PET, PVC, PU, PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.; for example, the laminate is a single-sided copper-clad laminate, the metal layer is copper foil, and the substrate is PI or PET. The copper foil is not limited to being formed on PI or PET by adhesive lamination or chemical / physical deposition.
[0031] The thickness of the metal layer in this embodiment ranges from 0.1 to 100 μm, and can be selected according to product performance requirements or process requirements, including but not limited to 0.1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, 30 μm, 40 μm, 60 μm, 80 μm, and 100 μm.
[0032] In this embodiment of the utility model, there is no explicit limitation on the thickness range of the substrate. The thickness range is sufficient to meet the product performance requirements, and is usually between 0.1 and 500 μm, including but not limited to 0.1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm, 200 μm, 250 μm, 300 μm, 400 μm, and 500 μm.
[0033] In some embodiments of the present invention, the printed conductive layer may be formed by printing with a low-temperature conductive paste; wherein the low-temperature conductive paste mainly includes resin and conductive filler; wherein the conductive filler is not limited to one or more of gold, silver, copper, iron, nickel, zinc, aluminum, palladium, conductive carbon black, and graphene. The printing process is not limited to screen printing, pad printing, inkjet printing, etc.
[0034] The conductive filler in the low-temperature conductive slurry of this utility model embodiment may further include a low-melting-point metal / alloy that can form an alloy phase with the metal layer and / or metal plating, thereby increasing the bonding strength between it and the metal layer and / or metal plating; wherein, the low-melting-point metal / alloy includes, but is not limited to, SnBi, Sn, and Bi.
[0035] The thickness of the printed conductive layer in this embodiment of the present invention can be from 0.1 to 100 μm; preferably, the upper limit of the thickness of the printed conductive layer is no more than 35 μm, for example, 1 μm, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 22 μm, 25 μm, 30 μm, 35 μm.
[0036] In some embodiments, before forming a continuous plating seed layer on the first hole wall and the second hole wall, the method may further include: masking the second surface of the first insulating layer and the surface of the printed conductive layer to prevent the plating seed layer from adhering to the second surface of the first insulating layer and the surface of the printed conductive layer.
[0037] The masking methods include, but are not limited to, applying masking materials or pasting masking materials.
[0038] Preferably, the masking treatment of the second surface of the first insulating layer and the surface of the printed conductive layer includes: temporarily bonding the two perforated laminates together on the side where their respective printed conductive layers are located, thereby masking the second surface of their respective first insulating layers and the surface of their respective printed conductive layers. Before forming an integrated first metal plating layer on the surface of the metal layer and the printed conductive layer, the third hole wall of the metal layer, and the plating seed layer, the treatment further includes: separating the two perforated laminates. This process can improve production efficiency.
[0039] In some embodiments, the two porous laminates can be temporarily bonded by temporary adhesive or film, and can be removed by tearing. In other embodiments, the temporary adhesive or film can be made of pressure-sensitive, pyrolytic, hydrolytic, or specific solvent-soluble materials, and can be processed according to the corresponding characteristics of the adhesive or film during removal and separation.
[0040] In some embodiments, a continuous plating seed layer is formed on the first and second hole walls, including: forming a continuous plating seed layer on the first hole wall of the printed conductive layer and the second hole wall of the first insulating layer using a black hole or black shadow process. Black hole and black shadow processes are currently mature precursor processes for via metallization. The black hole process mainly uses conductive carbon black to form the plating seed layer, while the black shadow process mainly uses graphene to form the plating seed layer.
[0041] In some embodiments, after forming a continuous plating seed layer on the first hole wall of the printed conductive layer and the second hole wall of the first insulating layer by means of a black hole or black shadow process, the method further includes: removing the plating seed layer attached to the surface of the metal layer and / or the third hole wall of the metal layer by means of a flash etching process.
[0042] This embodiment is primarily used to remove the plating seed layer on the third hole wall of a metal layer caused by black hole or shadow processes, thereby exposing the original metal material of the third hole wall. Furthermore, due to differences in the equipment used to perform black hole or shadow processes, some equipment may form a plating seed layer on the metal layer surface, while others, although not intended to form a plating seed layer, may still leave residue due to various factors. Therefore, this embodiment can also effectively remove this residue.
[0043] In some embodiments, after patterning the etching process of the metal layer and the first metal plating thereon, the method further includes forming a second insulating layer on the first insulating layer that covers a portion of the first metal plating. The second insulating layer may be made of solder resist ink or a cover film such as PI or PET.
[0044] In some embodiments, the second insulating layer exposes a portion of the non-porous surface of the first metal plating; a second metal plating is formed on the exposed non-porous surface of the first metal plating. The exposed non-porous surface of the first metal plating mainly refers to electrode portions intentionally designed into the product, such as gold fingers or solder pads, primarily used for connecting external devices.
[0045] The plating processes for the first and second metal coatings in this embodiment are not limited to electroplating or chemical plating; preferably, the first metal coating can be formed by electroplating, and the second metal coating can be formed by chemical plating. The material of the first and / or second metal coatings can be one or more of gold, silver, copper, iron, nickel, zinc, aluminum, and nickel. The thickness of the first and / or second metal coatings can range from 1 to 50 μm, for example, 1 μm, 2 μm, 5 μm, 6 μm, 10 μm, 15 μm, 20 μm, 30 μm, 50 μm, etc.
[0046] In this embodiment of the invention, the patterning in the patterned printed conductive layer, the metal layer, and the first metal plating layer thereon is the pattern of the target circuit.
[0047] Another objective of this invention is to provide a double-sided circuit board to solve the problems in the prior art.
[0048] Continue to participate in the exhibition Figure 1 The double-sided circuit board in this embodiment includes: a first insulating layer 10, a patterned metal layer 20 formed on a first surface of the first insulating layer 10, and a patterned printed conductive layer 30 formed on a second surface of the first insulating layer 10 away from the metal layer 20; the printed conductive layer 30 and the metal layer 20 partially overlap with each other across the first insulating layer 10, and a through hole 40 is formed in the overlapping area, which sequentially penetrates the printed conductive layer 30, the first insulating layer 10, and the metal layer 20; the hole wall of the through hole 40 is composed of a first hole wall 41 of the printed conductive layer 30, a second hole wall 42 of the insulating layer 10, and a third hole wall 43 of the metal layer 20; a continuous plating seed layer 50 is formed on the first hole wall 41 and the second hole wall 42; and a first metal plating layer 60 is integrally formed on the surface of the patterned metal layer 20 and the printed conductive layer 30, the third hole wall 43 of the metal layer 20, and the plating seed layer 50.
[0049] In some embodiments, the double-sided circuit board further includes a second insulating layer formed on the first insulating layer that covers a portion of the first metal plating.
[0050] In some embodiments, the second insulating layer exposes a portion of the non-porous surface of the first metal plating.
[0051] In some embodiments, the double-sided circuit board further includes a second metal plating layer formed on the non-hole surface of the exposed first metal plating layer.
[0052] The process, materials and parameters of the double-sided circuit board in this embodiment can be referred to the foregoing embodiments, and will not be repeated here.
[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. A double-sided circuit board, characterized in that, include: A first insulating layer, a patterned metal layer formed on a first surface of the first insulating layer, and a patterned printed conductive layer formed on a second surface of the first insulating layer away from the metal layer. The printed conductive layer and the metal layer overlap partially through the first insulating layer, and a through hole is formed in the overlapping area that sequentially penetrates the printed conductive layer, the insulating layer and the metal layer; The hole wall is composed of the first hole wall of the printed conductive layer, the second hole wall of the insulating layer, and the third hole wall of the metal layer; a continuous plating seed layer is formed on the first hole wall and the second hole wall; A first metal plating layer is formed integrally on the surface of the patterned metal layer and the printed conductive layer, the third hole wall of the metal layer, and the plating seed layer.
2. The double-sided circuit board according to claim 1, characterized in that, Also includes: A second insulating layer is formed on the first insulating layer, covering a portion of the first metal plating.
3. The double-sided circuit board according to claim 2, characterized in that, The second insulating layer exposes a portion of the non-porous surface of the first metal plating; The double-sided circuit board further includes a second metal plating layer formed on the non-hole surface of the exposed first metal plating layer.