Cavity plate and electronic device

Abstract

The disclosure provides a cavity plate and an electronic device, and relates to the technical field of electronic devices. The cavity plate comprises a non-cavity part, the non-cavity part comprising a plurality of metal layers and a non-cavity dielectric layer between two adjacent metal layers; and a cavity part, the cavity part being arranged in layers on the non-cavity part, and the cavity part being arranged on a main plate, the cavity part having a hollow area for placing elements in the middle, the cavity part comprising a plurality of metal layers and a cavity dielectric layer between two adjacent metal layers, the number of metal layers of the cavity part being different from the number of metal layers of the non-cavity part, the total thickness of the cavity dielectric layer being different from the total thickness of the non-cavity dielectric layer, or the material of at least one cavity dielectric layer being different from the non-cavity dielectric layer.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and more particularly to a cavity plate and an electronic device. Background Technology

[0002] In existing technologies, to avoid stress asymmetry caused by high temperatures during reflow, cavity plates typically employ a symmetrical structure. While this design can alleviate stress to some extent, it usually requires a large number of layers, resulting in high manufacturing costs and limiting its widespread market application.

[0003] Therefore, how to reduce the cost of cavity plates has become an urgent problem to be solved. Utility Model Content

[0004] This disclosure provides a cavity plate and an electronic device, the technical solution of which is as follows:

[0005] This application provides a cavity plate, comprising:

[0006] The non-cavity portion includes multiple metal layers and a non-cavity dielectric layer between two adjacent metal layers;

[0007] The cavity portion is stacked on the non-cavity portion and is used to be mounted on the motherboard. The cavity portion has a hollow area in the middle for placing components. The cavity portion includes multiple metal layers and a cavity dielectric layer between two adjacent metal layers. The number of metal layers in the cavity portion is different from the number of metal layers in the non-cavity portion. The total thickness of the cavity dielectric layer is different from the total thickness of the non-cavity dielectric layer, or at least one of the materials of the cavity dielectric layer is different from that of the non-cavity dielectric layer.

[0008] In this embodiment, the number of metal layers in the cavity portion is less than the number of metal layers in the non-cavity portion;

[0009] The total thickness of the cavity medium layer is greater than the total thickness of the non-cavity medium layer.

[0010] In this embodiment, the thickness of at least one of the cavity dielectric layers is greater than the thickness of the non-cavity dielectric layer; and / or

[0011] At least one of the cavity media layers is made of a different material than the non-cavity media layer.

[0012] In this embodiment, the plurality of non-cavity dielectric layers include a plurality of first dielectric layers;

[0013] The plurality of cavity dielectric layers include a second dielectric layer and a plurality of third dielectric layers, wherein the thickness of the second dielectric layer is greater than the thickness of the third dielectric layer, and the thickness of the third dielectric layer is equal to the thickness of the first dielectric layer.

[0014] In this embodiment, the second dielectric layer includes a plurality of dielectric sublayers, and at least a portion of the dielectric sublayers are made of a material different from that of the first dielectric layer.

[0015] In this embodiment, at least a portion of the material of the first dielectric layer is different from the material of the third dielectric layer.

[0016] In this embodiment, the total number of the plurality of dielectric sublayers and the plurality of third dielectric layers is equal to the total number of the plurality of first dielectric layers.

[0017] In this embodiment, it also includes:

[0018] An insulating layer is disposed between the non-cavity portion and the cavity portion.

[0019] On the other hand, this application also provides an electronic device, including: a motherboard; and a cavity board, the cavity board being disposed on the motherboard;

[0020] The cavity plate includes:

[0021] The non-cavity portion includes multiple metal layers and a non-cavity dielectric layer between two adjacent metal layers;

[0022] The cavity portion is stacked on the non-cavity portion. The cavity portion has a hollow area in the middle for placing components. The cavity portion includes multiple metal layers and a cavity dielectric layer between two adjacent metal layers. The number of metal layers in the cavity portion is different from the number of metal layers in the non-cavity portion. The total thickness of the cavity dielectric layer is different from the total thickness of the non-cavity dielectric layer, or at least one of the materials of the cavity dielectric layer is different from that of the non-cavity dielectric layer.

[0023] In this embodiment, the cavity portion is located on the motherboard, while the non-cavity portion is positioned away from the motherboard;

[0024] The non-cavity portion has radio frequency devices disposed on the side away from the motherboard.

[0025] The above description is only an overview of the technical solution of this disclosure. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, the preferred embodiments of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a cavity plate provided in this disclosure.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1. Cavity plate; 11. Non-cavity part; 111. Metal layer; 112. Non-cavity dielectric layer; 12. Cavity part; 121. Cavity dielectric layer; 122. Second dielectric layer; 1221. Dielectric sublayer; 123. Third dielectric layer; 13. Insulating layer. Detailed Implementation

[0030] The embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of this disclosure by way of example, but should not be used to limit the scope of this disclosure. This disclosure can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0031] These embodiments are provided to make the disclosure thorough and complete, and to fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, material composition, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0032] It should be noted that, in the description of this disclosure, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] Furthermore, the terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. "Vertical" is not strictly vertical, but within the permissible margin of error. "Parallel" is not strictly parallel, but within the permissible margin of error. Terms such as "including" or "contains" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well.

[0034] It should also be noted that, in the description of this disclosure, unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure depending on the specific circumstances. When a particular device is described as being located between a first device and a second device, an intermediary device may or may not be present between the particular device and the first or second device.

[0035] All terms used in this disclosure have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0036] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0037] In existing technologies, to avoid stress asymmetry caused by high temperatures during furnace reflow, cavity plates typically employ a symmetrical structure. While this design can alleviate stress to some extent, it usually requires a large number of layers, leading to high manufacturing costs and limiting its widespread market application. Therefore, this application provides a cavity plate in which the number of metal layers in the cavity portion differs from the number of metal layers in the non-cavity portion. Simultaneously, the total thickness of the cavity dielectric layer differs from the total thickness of the non-cavity dielectric layer, or at least one cavity dielectric layer uses a different material than the non-cavity dielectric layer. This reduces the total number of metal layers, thereby lowering manufacturing costs. Furthermore, by changing the material of the cavity dielectric layer or the non-cavity dielectric layer, the thickness, arrangement, and material selection of each dielectric layer in both the cavity and non-cavity portions can be customized, achieving stress balance among the layers and preventing stress concentration during high-temperature furnace reflow, thus ensuring stress symmetry between the cavity and non-cavity portions.

[0038] First aspect

[0039] like Figure 1 As shown, this application provides a cavity plate 1, comprising:

[0040] The non-cavity portion 11 includes multiple metal layers 111 and a non-cavity dielectric layer 112 between two adjacent metal layers 111.

[0041] A cavity portion 12 is stacked on the non-cavity portion 11 and is used to be mounted on the motherboard. The cavity portion 12 has a hollow area in the middle for placing components. The cavity portion 12 includes multiple metal layers 111 and a cavity dielectric layer 121 between two adjacent metal layers 111. The number of metal layers 111 in the cavity portion 12 is different from the number of metal layers 111 in the non-cavity portion 11. The total thickness of the cavity dielectric layer 121 is different from the total thickness of the non-cavity dielectric layer 112, or at least one of the materials of the cavity dielectric layer 121 is different from that of the non-cavity dielectric layer 112.

[0042] In this embodiment, the cavity board 1 is a multilayer printed circuit board (PCB) for embedded circuit design, which can improve the integration and signal integrity of the circuit and is widely used in high-frequency signal and high-density electronic products. This design can effectively shorten the signal path, reduce resistance and parasitic inductance, thereby improving the signal integrity of the circuit and reducing noise.

[0043] In this embodiment, the cavity portion 12 has a structure with a hollowed-out area, which can be a hollowed-out area that extends through the cavity portion 12 along its thickness direction. The cavity portion 12 includes an edge region surrounding the hollowed-out area. Components are placed in the hollowed-out area.

[0044] In this embodiment, the non-cavity portion 11 is a structure without any hollow areas. The non-cavity portion 11 includes multiple metal layers 111 and multiple non-cavity dielectric layers 112. The metal layers 111 may include any conductive metal such as copper, aluminum, silver, or their compounds. A non-cavity dielectric layer 112 is disposed between two adjacent metal layers 111. The non-cavity dielectric layer 112 may include at least one of EM-39B 1027RC69% and EM-39B 1080RC69%, where EM-39B represents the substrate material type, 1027 and 1080 represent the thickness code of the dielectric layer, and RC69% represents the resin content percentage, which is a parameter of resin content in a prepreg, indicating that the resin accounts for 69% (mass fraction) of the material. The non-cavity dielectric layer 112 may also include EM-390 0.152mm H / H (RTF), where EM-390 represents the substrate material type, 0.152mm represents the dielectric layer thickness, and H / H (RTF) represents the resin coating (RTF) on the double-sided modified (H / H) surface of the fiberglass cloth. Thus, the cavity dielectric layer 111 can improve the interlayer bonding force, thereby optimizing processability. The non-cavity dielectric layer 112 may also include EM-390 0.305mmT / T(RTF), where EM-390 represents the substrate material type, 0.305mm represents the dielectric layer thickness, and T / T(RTF) represents the double-sided resin treatment of the prepreg, thereby improving the interlayer bonding force with the upper and lower layers (same layer or substrate).

[0045] In this embodiment, the cavity portion 12 includes multiple metal layers 111 and multiple cavity dielectric layers 121. A cavity dielectric layer 121 is disposed between two adjacent metal layers 111. The cavity dielectric layer 121 can be disposed between two metal layers 111 of the cavity portion 12, or it can be disposed between one metal layer 111 of the cavity portion 12 and one metal layer 111 of the non-cavity portion 11 near the cavity portion 12.

[0046] In this embodiment, the cavity dielectric layer 121 may include substrates with different thicknesses. The cavity dielectric layer 121 may include EM-39B 1027RC69% and EM-39B 1080RC69%, where EM-39B represents the substrate material type, 1027 and 1080 represent the thickness codes of the dielectric layer, and RC69% represents the resin content percentage, a parameter indicating that the resin content in the prepreg is 69% (mass fraction). The cavity dielectric layer 121 may also include EM-3900.152mm H / H (RTF), where EM-390 represents the substrate material type, 0.152mm represents the dielectric layer thickness, and H / H (RTF) represents the resin coating (RTF) on the double-sided modified (H / H) surface of the fiberglass cloth. This allows the cavity dielectric layer 121 to improve interlayer bonding and optimize processability. The cavity dielectric layer 121 may also include EM-390 0.305mm... T / T(RTF), where EM-390 represents the substrate material type, 0.305mm represents the dielectric layer thickness, and T / T(RTF) represents the double-sided resin treatment of the prepreg, thereby improving the interlayer bonding force with the upper and lower layers (same layer or substrate).

[0047] In this embodiment, the number of copper foils in the non-cavity portion 11 is different from the number of copper foils in the cavity portion 12, thereby reducing the total number of copper foils in the cavity plate 1 as needed, thus reducing manufacturing costs.

[0048] In this embodiment, while the number of copper foils in the non-cavity portion 11 is different from the number of copper foils in the cavity portion 12, the total thickness of the cavity dielectric layer 121 is different from the total thickness of the non-cavity dielectric layer 112, or at least the material of the cavity dielectric layer 121 is different from that of the non-cavity dielectric layer 112. Thus, the number of copper foils can be reduced by adjusting the thickness of the cavity dielectric layer 121 or the non-cavity dielectric layer 112, or by changing the material of the cavity dielectric layer 121 or the non-cavity dielectric layer 112. This allows for the setting of the thickness, arrangement, and material selection of each dielectric layer in the cavity portion 12 and the non-cavity portion 11.

[0049] This application provides a cavity plate 1, which includes a cavity portion 12 and a non-cavity portion 11. The cavity portion 12 includes multiple metal layers 111 and a cavity dielectric layer 121 disposed between two adjacent metal layers 111. The non-cavity portion 11 includes multiple metal layers 111 and a non-cavity dielectric layer 112 disposed between two adjacent metal layers 111. The number of the cavity portion 12 and the number of metal layers 111 are different from the number of metal layers 111 in the non-cavity portion 11. Furthermore, the total thickness of the cavity dielectric layer 121 is different from the total thickness of the non-cavity dielectric layer 112, or the material of at least one cavity dielectric layer 121 is different from that of the non-cavity dielectric layer 112. The number of hollow portion 12 and metal layer 111 is different from the number of metal layer 111 in non-hollow portion 11, thereby reducing the total number of metal layers 111 and reducing manufacturing costs. Furthermore, by changing the material of hollow dielectric layer 121 or non-hollow dielectric layer 112, the thickness, arrangement and material selection of each dielectric layer in hollow portion 12 and non-hollow portion 11 can be set, thereby achieving stress balance between layers, thus avoiding stress concentration during high-temperature furnace reflow, and making the stress symmetrical in hollow portion 12 and non-hollow portion 11.

[0050] Therefore, the cavity plate 1 provided in this application can reduce manufacturing costs while avoiding stress concentration during high-temperature furnace treatment, thus ensuring stress symmetry and preventing the cavity plate 1 from warping when heated.

[0051] like Figure 1 As shown, in this embodiment of the application, the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11.

[0052] The total thickness of the cavity medium layer 121 is greater than the total thickness of the non-cavity medium layer 112.

[0053] In this embodiment, the number of metal layers 111 in the cavity portion 12 can be set to 4, and the number of metal layers 111 in the non-cavity portion 11 can be set to 8, so that the total number of copper sheets in the cavity plate 1 is 12.

[0054] In this embodiment, the number of copper foils in the cavity portion 12 and the number of copper foils in the non-cavity portion 11 can also be other numbers, as long as they are suitable for production and application.

[0055] In this embodiment, the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11, thereby reducing the total number of copper foils in the cavity plate 1. When the number of copper foils in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11, the total thickness of the cavity dielectric layer 121 is greater than the total thickness of the non-cavity dielectric layer 112. This allows for symmetrical stress distribution between the cavity portion 12 and the non-cavity portion 11, even when the number of copper foils is asymmetrical. Furthermore, the reduction in the number of copper foils lowers manufacturing costs and reduces the total thickness of the cavity plate 1, which is beneficial for device miniaturization.

[0056] like Figure 1 As shown in the embodiments of this application, at least one of the cavity dielectric layers 121 has a thickness greater than the thickness of the non-cavity dielectric layer 112; and / or

[0057] At least one of the cavity dielectric layers 121 is made of a different material than the non-cavity dielectric layer 112.

[0058] In one embodiment of this application, the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11. Correspondingly, the thickness of at least one cavity medium layer 121 in the cavity portion 12 can be set to be greater than the thickness of one cavity medium layer 121 in the non-cavity portion 11. Thus, by increasing the thickness of at least one cavity medium layer 121, the stress between the cavity portion 12 and the non-cavity portion 11 can be made symmetrical, and the stress between each layer in the cavity plate 1 can be balanced, avoiding stress concentration during high-temperature furnace reflow.

[0059] In another embodiment of this application, the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11. Correspondingly, the material of at least one cavity medium layer 121 in the cavity portion 12 can be different from the material of one cavity medium layer 121 in the non-cavity portion 11. Thus, by selecting different materials in each layer of the cavity portion 12 and the non-cavity portion 11, the stress between the cavity portion 12 and the non-cavity portion 11 can be symmetrical, and the stress between each layer in the cavity plate 1 can be balanced, avoiding stress concentration during high-temperature furnace reflow.

[0060] In another embodiment of this application, the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11. Correspondingly, the thickness of at least one cavity medium layer 121 in the cavity portion 12 can be set to be greater than the thickness of one cavity medium layer 121 in the non-cavity portion 11, and the material of at least one cavity medium layer 121 in the cavity portion 12 can be different from the material of one cavity medium layer 121 in the non-cavity portion 11. Thus, by increasing the thickness of at least one cavity medium layer 121 and selecting different materials in each layer of the cavity portion 12 and the non-cavity portion 11, the stress between the cavity portion 12 and the non-cavity portion 11 can be made symmetrical, and the stress between each layer in the cavity plate 1 can be balanced, avoiding stress concentration during high-temperature furnace reflow.

[0061] like Figure 1 As shown in the embodiments of this application, the plurality of non-cavity dielectric layers 112 include a plurality of first dielectric layers;

[0062] The plurality of cavity dielectric layers 121 include a second dielectric layer 122 and a plurality of third dielectric layers 123, wherein the thickness of the second dielectric layer 122 is greater than the thickness of the third dielectric layer 123, and the thickness of the third dielectric layer 123 is equal to the thickness of the first dielectric layer.

[0063] In this embodiment, a first dielectric layer is disposed between two adjacent metal layers 111 in the non-cavity portion 11.

[0064] In this embodiment, a second dielectric layer 122 or a third dielectric layer 123 is disposed between two adjacent metal layers 111 in the cavity portion 12.

[0065] In this embodiment, the thickness of the third dielectric layer 123 and the thickness of the first dielectric layer satisfy the same condition. It is understood that satisfying the same condition means absolutely identical and approximately identical, wherein the acceptable deviation range for approximately identical is, for example, the difference between the two satisfying the same condition is less than or equal to 5% of either one. That is, the difference between the thickness of the third dielectric layer 123 and the thickness of the first dielectric layer is less than or equal to 5% of either one.

[0066] In this embodiment, the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11. Correspondingly, the number of cavity dielectric layers 121 in the cavity portion 12 is less than the number of non-cavity dielectric layers 112 in the non-cavity portion 11. The thickness of the cavity dielectric layer 121 in the cavity portion 12 is the sum of the thicknesses of the second dielectric layer 122 and multiple third dielectric layers 123. The thickness of the non-cavity dielectric layer 112 in the non-cavity portion 11 is the sum of the thicknesses of multiple first dielectric layers. The thickness of the third dielectric layer 123 satisfies the condition of being equal to the thickness of the first dielectric layer. The thickness of the second dielectric layer 122 is greater than the thickness of the third dielectric layer 123. Thus, by increasing the thickness of the second dielectric layer 122, the stress between the cavity portion 12 and the non-cavity portion 11 can be made symmetrical, and the stress between each layer in the cavity plate 1 can be balanced, avoiding stress concentration during high-temperature furnace reflow.

[0067] In this embodiment of the application, the second dielectric layer 122 includes a plurality of dielectric sublayers 1221, and at least a portion of the dielectric sublayers 1221 are made of a different material than the first dielectric layer.

[0068] In this embodiment, the first dielectric layer of the non-cavity dielectric layer 112 may include EM-39B1027RC69%, and the third dielectric layer 123 of the cavity dielectric layer 121 may also include EM-39B1027RC69%. The multiple dielectric sublayers 1221 of the second dielectric layer 122 in the cavity dielectric layer 121 may include EM-39B 1027RC69%, EM-390 0.152mm H / H (RTF), EM-39B1080RC69%, and / or EM-390 0.305mmT / T (RTF), thereby forming a non-cavity dielectric layer 112 with different thicknesses and materials than the cavity dielectric layer 121. This allows for stress compensation of the cavity portion 12 through the addition of multiple dielectric sublayers 1221, and also allows for matching of the thermal expansion coefficients of the cavity portion 12 and the non-cavity portion 11, thereby achieving stress balance between the cavity portion 12 and the non-cavity portion 11.

[0069] In this embodiment, the multiple first dielectric layers included in the non-cavity portion 11 of the cavity plate 1 and the multiple third dielectric layers 123 included in the cavity portion 12 have the same material and thickness. The second dielectric layer 122 includes five dielectric sublayers 1221, which are EM-39B1027RC69%, EM-390 0.152mm H / H (RTF), EM-39B 1080RC69%, EM-390 0.305mmT / T (RTF), and EM-39B 1080RC69% stacked together.

[0070] In this embodiment of the application, at least a portion of the material of the first dielectric layer is different from the material of the third dielectric layer 123.

[0071] In this embodiment, the third dielectric layer 123 included in the cavity dielectric layer 121 may also include EM-39B1027RC69, and the first dielectric layer included in the non-cavity dielectric layer 112 may include EM-39B 1027RC69, and may also include EM-390 0.058mm T / T (RTF).

[0072] In this embodiment, the cavity portion 12 may include three third dielectric layers 123EM-39B1027RC69%, while the second dielectric layer 122 includes five dielectric sublayers 1221, which are respectively stacked EM-39B1027RC69%, EM-390 0.152mm H / H (RTF), EM-39B 1080RC69%, EM-390 0.305mmT / T (RTF), and EM-39B 1080RC69%. The non-cavity portion 11 may include seven layers of EM-39B 1027RC69%, and also includes one layer of EM-390 0.058mm T / T (RTF).

[0073] like Figure 1 As shown in the embodiment of this application, the total number of the plurality of dielectric sublayers 1221 and the plurality of third dielectric layers 123 is equal to the number of the plurality of first dielectric layers. In this embodiment, when the number of metal layers 111 in the cavity portion 12 is less than the number of metal layers 111 in the non-cavity portion 11, the total number of the plurality of dielectric sublayers 1221 and the plurality of third dielectric layers 123 is equal to the number of the plurality of first dielectric layers. This ensures that the number of dielectric layers in the cavity portion 12 and the non-cavity portion 11 is the same, thereby avoiding the problem of stress asymmetry between the cavity portion 12 and the non-cavity portion 11 due to high temperature during the furnace process.

[0074] In this embodiment, the cavity plate 1 includes multiple metal layers 111 and a dielectric layer between adjacent metal layers 111. The cavity plate 1 can be divided into a cavity portion 12 and a non-cavity portion 11. The cavity portion 12 includes multiple third dielectric layers 123 and a second dielectric layer 122. The non-cavity portion 11 includes a dielectric layer comprising multiple first dielectric layers. The second dielectric layer 122 is also located between the cavity portion 12 and the non-cavity portion 11. The second dielectric layer 122, through the stacking of multiple dielectric sub-layers 1221 of different materials, can achieve stress balance between the cavity portion 12 and the non-cavity portion 11, thereby solving the problem of warping of the cavity plate 1 when heated.

[0075] In this embodiment, the thickness of the cavity plate 1 can be 1.31 mm, the thickness of the cavity portion 12 can be 0.84 mm, and the thickness of the cavity portion 12 can also be 0.75 mm.

[0076] like Figure 1 As shown in the embodiments of this application, it also includes:

[0077] An insulating layer 13 is disposed between the non-cavity portion 11 and the cavity portion 12.

[0078] In this embodiment, an insulating layer 13 is coated on the surface of the non-cavity portion 11 facing the cavity portion 12. The insulating layer 13 is relatively thin, thereby providing electromagnetic shielding performance for the components disposed in the cavity portion 12 and reducing the impact of electromagnetic interference on the components in the cavity portion 12.

[0079] In this embodiment, the insulating layer 13 can be a green solder resist layer, also known as a solder mask layer, which is a protective layer on a printed circuit board (PCB). The main component of the green solder resist layer is a liquid photoresist, an acrylic oligomer. It forms a protective film by coating the unsoldered lines and substrate of the PCB, thus providing insulation. During the soldering process, the green solder resist layer can prevent solder overflow, avoid bridging and short circuits between different lines, and ensure soldering quality and circuit stability. It also prevents the metal layer 111 from being directly exposed to the air, avoiding physical breaks in the conductor circuit due to oxidation, corrosion, etc., and reduces the impact of external environmental factors such as dust and moisture on the circuit, preventing insulation deterioration.

[0080] Second aspect

[0081] This application also provides an electronic device, including: a motherboard; and a cavity board 1, the cavity board 1 being disposed on the motherboard; the cavity board 1 comprising:

[0082] The non-cavity portion 11 includes multiple metal layers 111 and a non-cavity dielectric layer 112 between two adjacent metal layers 111.

[0083] A cavity portion 12 is stacked on the non-cavity portion 11. The cavity portion 12 has a hollow area in the middle for placing components. The cavity portion 12 includes multiple metal layers 111 and a cavity dielectric layer 121 between two adjacent metal layers 111. The number of metal layers 111 in the cavity portion 12 is different from the number of metal layers 111 in the non-cavity portion 11. The total thickness of the cavity dielectric layer 121 is different from the total thickness of the non-cavity dielectric layer 112, or at least one of the materials of the cavity dielectric layer 121 is different from that of the non-cavity dielectric layer 112.

[0084] In this embodiment, the cavity portion 12 of the cavity plate 1 is disposed on the motherboard, and the non-cavity portion 11 is disposed away from the motherboard relative to the cavity portion 12.

[0085] In this embodiment, the cavity board 1 is a multilayer PCB board used in embedded circuit design, which can improve the integration and signal integrity of the circuit and is widely used in high-frequency signals and high-density electronic products. This design can effectively shorten the signal path, reduce resistance and parasitic inductance, thereby improving the signal integrity of the circuit and reducing noise.

[0086] In this embodiment, the cavity portion 12 has a structure with a hollowed-out area, which can be a hollowed-out area that extends through the cavity portion 12 along its thickness direction. The cavity portion 12 includes an edge region surrounding the hollowed-out area. Components are placed in the hollowed-out area.

[0087] In this embodiment, the cavity portion 12 includes multiple metal layers 111 and multiple cavity dielectric layers 121. A cavity dielectric layer 121 is disposed between two adjacent metal layers 111. The cavity dielectric layer 121 can be disposed between two metal layers 111 of the cavity portion 12, or it can be disposed between one metal layer 111 of the cavity portion 12 and one metal layer 111 of the non-cavity portion 11 near the cavity portion 12.

[0088] In this embodiment, the cavity dielectric layer 121 may include substrates with different thicknesses. The cavity dielectric layer 121 may include EM-39B 1027RC69% and EM-39B 1080RC69%, where EM-39B represents the substrate material type, 1027 and 1080 represent the thickness codes of the dielectric layer, and RC69% represents the resin content percentage, a parameter indicating that the resin content in the prepreg is 69% (mass fraction). The cavity dielectric layer 121 may also include EM-3900.152mm H / H (RTF), where EM-390 represents the substrate material type, 0.152mm represents the dielectric layer thickness, and H / H (RTF) represents the resin coating (RTF) on the double-sided modified (H / H) surface of the fiberglass cloth. This allows the cavity dielectric layer 121 to improve interlayer bonding and optimize processability. The cavity dielectric layer 121 may also include EM-390 0.305mm... T / T(RTF), where EM-390 represents the substrate material type, 0.305mm represents the dielectric layer thickness, and T / T(RTF) represents the double-sided resin treatment of the prepreg, thereby improving the interlayer bonding force with the upper and lower layers (same layer or substrate).

[0089] In this embodiment, the non-cavity portion 11 has a structure without any hollow areas. The non-cavity portion 11 includes multiple metal layers 111 and multiple non-cavity dielectric layers 112. A non-cavity dielectric layer 112 is disposed between two adjacent metal layers 111. The non-cavity dielectric layer 112 may include EM-39B 1027RC69% and EM-39B 1080RC69%, where EM-39B represents the substrate material type, 1027 and 1080 represent the thickness code of the dielectric layer, and RC69% represents the resin content percentage, which is a parameter of resin content in a prepreg, indicating that the resin accounts for 69% (mass fraction) of the material. The non-cavity dielectric layer 112 may also include EM-390 0.152mm. H / H(RTF), where EM-390 represents the substrate material type, 0.152mm represents the dielectric layer thickness, and H / H(RTF) represents double-sided modified (H / H) surface resin coating (RTF) of fiberglass cloth, thereby improving the interlayer bonding force of the cavity dielectric layer 121 and thus optimizing processability; the non-cavity dielectric layer 112 may also include EM-390 0.305mm T / T(RTF), where EM-390 represents the substrate material type, 0.305mm represents the dielectric layer thickness, and T / T(RTF) represents double-sided resin treatment of the prepreg, thereby improving the interlayer bonding force with the upper and lower layers (same layer or substrate).

[0090] In this embodiment, the number of metal layers in the non-cavity portion 11 is different from the number of copper sheets in the cavity portion 12, thereby reducing the total number of copper sheets in the cavity plate 1 as needed to lower manufacturing costs.

[0091] In this embodiment, while the number of metal layers in the non-cavity portion 11 is different from the number of copper foils in the cavity portion 12, the total thickness of the cavity dielectric layer 121 is different from the total thickness of the non-cavity dielectric layer 112, or at least the material of the cavity dielectric layer 121 is different from that of the non-cavity dielectric layer 112. Thus, the number of copper foils can be reduced by adjusting the thickness of the cavity dielectric layer 121 or the non-cavity dielectric layer 112, or by changing the material of the cavity dielectric layer 121 or the non-cavity dielectric layer 112. This allows for the setting of thickness, arrangement, and material selection of each dielectric layer in the cavity portion 12 and the non-cavity portion 11.

[0092] This application provides an electronic device including a cavity board 1 and a motherboard. The cavity board 1 includes a cavity portion 12 and a non-cavity portion 11. The cavity portion 12 includes multiple metal layers 111 and a cavity dielectric layer 121 disposed between two adjacent metal layers 111. The non-cavity portion 11 includes multiple metal layers 111 and a non-cavity dielectric layer 112 disposed between two adjacent metal layers 111. The number of the cavity portion 12 and the number of metal layers 111 are different from the number of metal layers 111 in the non-cavity portion 11. Furthermore, the total thickness of the cavity dielectric layer 121 is different from the total thickness of the non-cavity dielectric layer 112, or the material of at least one cavity dielectric layer 121 is different from that of the non-cavity dielectric layer 112. The number of hollow portion 12 and metal layer 111 is different from the number of metal layer 111 in non-hollow portion 11, thereby reducing the total number of metal layers 111 and reducing manufacturing costs. Furthermore, by changing the material of hollow dielectric layer 121 or non-hollow dielectric layer 112, the thickness, arrangement and material selection of each dielectric layer in hollow portion 12 and non-hollow portion 11 can be set, thereby achieving stress balance between layers, thus avoiding stress concentration during high-temperature furnace reflow, and making the stress symmetrical in hollow portion 12 and non-hollow portion 11.

[0093] Therefore, the electronic device provided in this application can reduce manufacturing costs while avoiding stress concentration during high-temperature reflow, thus achieving stress symmetry.

[0094] In this embodiment of the application, the cavity portion 12 is located on the motherboard, and the non-cavity portion 11 is disposed away from the motherboard;

[0095] The non-cavity portion 11 has a radio frequency device disposed on the side away from the motherboard.

[0096] In this embodiment, an insulating layer 13 is provided on the side of the non-cavity portion 11 facing the cavity portion 12, and a cavity dielectric layer 121 surrounding the hollow area is provided on the cavity portion 12 near the non-cavity portion 11. This can achieve an insulating effect on the components in the cavity portion 12, giving the electronic device good electromagnetic shielding performance, preventing the radio frequency signals of the radio frequency device from affecting the components, and ensuring the stability and low interference of the radio frequency signal during transmission.

[0097] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0098] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. In particular, as long as there is no structural conflict, the technical features mentioned in the various embodiments can be combined in any manner.

Claims

1. A cavity plate, characterized in that, include: The non-cavity portion includes multiple metal layers and a non-cavity dielectric layer between two adjacent metal layers; The cavity portion is stacked on the non-cavity portion and is used to be mounted on the motherboard. The cavity portion has a hollow area in the middle for placing components. The cavity portion includes multiple metal layers and a cavity dielectric layer between two adjacent metal layers. The number of metal layers in the cavity portion is different from the number of metal layers in the non-cavity portion. The total thickness of the cavity dielectric layer is different from the total thickness of the non-cavity dielectric layer, or at least one of the materials of the cavity dielectric layer is different from that of the non-cavity dielectric layer.

2. The cavity plate according to claim 1, characterized in that, The number of metal layers in the cavity portion is less than the number of metal layers in the non-cavity portion. The total thickness of the cavity medium layer is greater than the total thickness of the non-cavity medium layer.

3. The cavity plate according to claim 1, characterized in that, At least one of the cavity dielectric layers has a thickness greater than the thickness of the non-cavity dielectric layer; and / or At least one of the cavity media layers is made of a different material than the non-cavity media layer.

4. The cavity plate according to claim 3, characterized in that, The plurality of non-cavity dielectric layers include a plurality of first dielectric layers; The plurality of cavity dielectric layers include a second dielectric layer and a plurality of third dielectric layers, wherein the thickness of the second dielectric layer is greater than the thickness of the third dielectric layer, and the thickness of the third dielectric layer is equal to the thickness of the first dielectric layer.

5. The cavity plate according to claim 4, characterized in that, The second dielectric layer includes a plurality of dielectric sublayers, at least some of which are made of a different material than the first dielectric layer.

6. The cavity plate according to claim 4, characterized in that, At least part of the material of the first dielectric layer is different from the material of the third dielectric layer.

7. The cavity plate according to claim 5, characterized in that, The total number of the plurality of said dielectric sublayers and the plurality of said third dielectric layers is equal to the total number of the plurality of first dielectric layers.

8. The cavity plate according to claim 1, characterized in that, Also includes: An insulating layer is disposed between the non-cavity portion and the cavity portion.

9. An electronic device, characterized in that, include: Motherboard; and a cavity plate, wherein the cavity plate is disposed on the main board; The cavity plate includes: The non-cavity portion includes multiple metal layers and a non-cavity dielectric layer between two adjacent metal layers; The cavity portion is stacked on the non-cavity portion. The cavity portion has a hollow area in the middle for placing components. The cavity portion includes multiple metal layers and a cavity dielectric layer between two adjacent metal layers. The number of metal layers in the cavity portion is different from the number of metal layers in the non-cavity portion. The total thickness of the cavity dielectric layer is different from the total thickness of the non-cavity dielectric layer, or at least one of the materials of the cavity dielectric layer is different from that of the non-cavity dielectric layer.

10. The electronic device according to claim 9, characterized in that, The cavity portion is on the motherboard, and the non-cavity portion is located away from the motherboard; The non-cavity portion has radio frequency devices disposed on the side away from the motherboard.

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