Semiconductor device

Abstract

The utility model provides a kind of semiconductor device.The semiconductor device includes the gate line intersecting with active region, and the gate dielectric layer being configured to function as antifuse structure is formed between active region and gate line.The method for manufacturing semiconductor device includes forming active region and multiple gates intersecting with active region, and the gate dielectric material being configured to function as antifuse structure is formed between active region and gate.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor device manufacturing industry has experienced exponential growth. Over time, technological advancements in materials, design, and manufacturing have enabled the production of semiconductor devices with progressively smaller and more complex circuitry. In the evolution of semiconductor devices, the number of interconnects per unit chip area typically increases, while the size of circuit components typically decreases. This shrinking of semiconductor device architecture generally increases the complexity of handling and manufacturing semiconductor devices. Utility Model Content

[0003] This invention provides a semiconductor device. The semiconductor device includes: a substrate; an active region disposed above the substrate and extending along a first direction; an isolation region disposed above the substrate, the active region protruding above the isolation region; a plurality of gate lines extending along a second direction intersecting the first direction and intersecting with respective channel regions comprising a stack of semiconductor layers aligned with the active region; at least two of the plurality of gate lines include: a gate material and a dielectric material, the gate material being disposed above an upper semiconductor layer of the channel region where the at least two gate lines intersect, and the dielectric material being located between a semiconductor layer below the upper semiconductor layer and a semiconductor layer below the upper semiconductor layer of the channel region where the at least two gate lines intersect; at least one of the plurality of gate lines includes: the gate material, a semiconductor layer surrounding a channel region of the channel region where the at least two gate lines intersect; and a gate dielectric layer disposed between the gate material and the upper semiconductor layer of the at least two gate lines, the gate dielectric layer being configured to function as an antifuse structure.

[0004] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0005] Figure 1 A computing system according to an embodiment of the present invention is shown.

[0006] Figure 2A An antifuse array according to an embodiment of the present invention is shown.

[0007] Figure 2B An antifuse array according to an embodiment of the present invention is shown.

[0008] Figure 2C An antifuse array according to an embodiment of the present invention is shown.

[0009] Figure 3 , Figure 4A as well as Figure 4B Showing Figure 2B The operation of the antifuse array is shown.

[0010] Figure 5 A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0011] Figure 6 Showing Figure 5 A perspective view of a portion of the semiconductor device shown.

[0012] Figure 7A as well as Figure 7B Showing Figure 5 The cross-section of the semiconductor device shown.

[0013] Figure 7C as well as Figure 7D A cross-section of the antifuse structure portion according to an embodiment of the present invention is shown.

[0014] Figure 7E A cross-section of a semiconductor device according to an embodiment of the present invention is shown.

[0015] Figure 8 A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0016] Figure 9 Showing Figure 8 A perspective view of a portion of the semiconductor device shown.

[0017] Figure 10A Showing Figure 8 A cross-section of a portion of the semiconductor device shown.

[0018] Figure 10B A cross-section of a portion of a semiconductor device according to an embodiment of the present invention is shown.

[0019] Figure 11 A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0020] Figure 12 Showing Figure 11 A perspective view of a portion of the semiconductor device shown.

[0021] Figure 13A , Figure 13B , Figure 13C as well as Figure 13D Showing Figure 11 The semiconductor device shown is a partial cross-section.

[0022] Figure 13E A cross-section of a portion of a semiconductor device according to an embodiment of the present invention is shown.

[0023] Figure 14A An antifuse array according to an embodiment of the present invention is shown.

[0024] Figure 14B An antifuse array according to an embodiment of the present invention is shown.

[0025] Figure 14C An antifuse array according to an embodiment of the present invention is shown.

[0026] Figure 14D , Figure 14E as well as Figure 14F Showing Figure 14B The operation of the antifuse array is shown.

[0027] Figure 15 A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0028] Figure 16 Showing Figure 15 A three-dimensional view of a portion of the semiconductor device shown.

[0029] Figure 17 Showing Figure 15 A cross-section of a portion of the semiconductor device shown.

[0030] Figure 18A An antifuse array according to an embodiment of the present invention is shown.

[0031] Figure 18B An antifuse array according to an embodiment of the present invention is shown.

[0032] Figure 18C An antifuse array according to an embodiment of the present invention is shown.

[0033] Figure 18D , Figure 18E as well as Figure 18F Showing Figure 18B The operation of the antifuse array is shown.

[0034] Figure 19A A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0035] Figure 19B A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0036] Figure 19C A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0037] Figure 20 Showing Figure 19A , Figure 19B as well as Figure 19C A perspective view of a portion of the semiconductor device shown.

[0038] Figure 21A , Figure 21B , Figure 21C , Figure 22 as well as Figure 23 A cross-section of a semiconductor device portion according to an embodiment of the present invention is shown.

[0039] Figure 24 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0040] Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 25E , Figure 25F , Figure 25G , Figure 25H , Figure 25I , Figure 25J , Figure 25K , Figure 25L , Figure 25M , Figure 25N , Figure 25O A cross-sectional view showing the sequential process stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0041] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of this utility model. The specific embodiments or examples of elements and configurations described below are intended to simplify this utility model. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the required characteristics of the apparatus. Furthermore, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. For simplicity and clarity, various features may be drawn at any scale.

[0042] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," "upper," "top," "bottom," and "middle" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature, without excluding the presence of additional structures above, below, or between said features. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term "made of" may mean "comprising" or "constituting of."

[0043] Furthermore, in the following manufacturing processes, there may be one or more additional operations between the described operations, and the order of operations may change. In this invention, the term "one of A, B, and C" means "A, B, and / or C (A, B, C, A and B, A and C, B and C, or A, B, and C)," and unless otherwise stated, does not mean selecting one element from A, one element from B, and one element from C. Throughout the disclosure, source and drain are used interchangeably, and source / drain refers to one or both of the source and drain. In the following embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more figures) may be applied to other embodiments, and their detailed description may be omitted. A source / drain structure may refer to a source or a drain, individually or collectively depending on the context.

[0044] Reference Figure 1 According to some embodiments of the present invention, an example block diagram of a computing system 2 is shown. The computing system 2 includes a host device 4 associated with a memory device 6. The host device 4 is configured to receive input from one or more input devices 8 and provide output to one or more output devices 10. The host device 4 is configured to communicate with the memory device 6, the input devices 8, and the output devices 10 via suitable interfaces 12, 14, and 16, respectively. The computing system 2 can be implemented in various computing devices, such as computers (e.g., desktop computers, notebook computers, servers, data centers, etc.), tablet computers, personal digital assistants, mobile devices, other handheld or portable devices, or any other server suitable for using the host device 4.

[0045] Input device 8 may include any of a variety of input technologies, such as a keyboard, stylus, touchscreen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote control, input interface, one or more buttons, dial pad, joystick, and any other input peripheral device associated with host device 4 that allows an external source (e.g., a user) to input information (e.g., data) into the host device and send instructions to the host device. Similarly, output device 10 may include a variety of output technologies, such as external storage, printer, speaker, display, microphone, LED, headphones, video device, and any other output peripheral device configured to receive information (e.g., data) from host device 4. The “data” input to host device 4 and / or output from the host device may include any type of data suitable for performing operations or tasks, such as text data, signal data, graphic data, combinations thereof, or any one or more other types of analog and / or digital data suitable for processing using computing system 2.

[0046] The host device 4 includes or is associated with one or more processing units / processors, such as CPU cores 18 and 20. CPU cores 18 and 20 may be implemented as Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or any other type of processing unit. Each of the CPU cores 18 and 20 may be configured to execute instructions for running one or more applications of the host device 4. In some embodiments, the instructions and data required to run the one or more applications may be stored in the memory device 6. The host device 4 may also be configured to store the results of running the one or more applications in the memory device 6. Therefore, the host device 4 may be configured to request the memory device 6 to perform various operations. For example, the host device 4 may request the memory device 6 to read data, write data, update or delete data, and / or perform management or other operations.

[0047] The memory device 6 includes a memory controller 22 configured to read data from or write data to the memory array 24. In some embodiments, the memory array 24 may be a one-time programmable (OTP) memory array. An OTP memory array is a non-volatile memory type that retains the data stored therein after the memory device 6 is powered off. In some embodiments, the OTP memory array may include a plurality of anti-fuse cells configured to store at least one bit of data.

[0048] The memories within memory array 24 can be controlled individually and independently by memory controller 22. In other words, memory controller 22 can be configured to communicate individually and independently with each memory within memory array 24. Through communication with memory array 24, memory controller 22 can be configured to read data from or write data to the memory array in response to instructions received from host device 4. Although shown as part of memory device 6, in some embodiments, memory controller 22 can be part of host device 4 or another element of computing system 2 and associated with the memory device. Memory controller 22 can be implemented as software, hardware, firmware, or a combination thereof as logic circuitry to perform the functions described herein. For example, in some embodiments, memory controller 22 is configured to retrieve instructions associated with a desired operation stored in memory array 24 of memory device 6 upon receiving a request from host device 4.

[0049] It should be understood that, Figure 1 Only some components of computing system 2 are shown and described herein. However, computing system 2 may include other components such as various batteries and power supplies, network interfaces, routers, switches, external storage systems, controllers, etc. Computing system 2 may include any of the various hardware, software, and / or firmware components necessary or desirable for performing any desired function. Similarly, host device 4, input device 8, output device 10, and memory device 6 including memory controller 22 and memory array 24 may include other hardware, software, and / or firmware components deemed necessary or desirable for performing any desired function.

[0050] Figure 2A An antifuse unit array 25 according to some embodiments of the present invention is illustrated. The antifuse unit array 25 includes a first antifuse unit 27 and a second antifuse unit 29 (both are in...). Figure 2A(Shown in dashed boxes). In some embodiments, as shown, each of the first antifuse unit 27 and the second antifuse unit 29 includes two transistors. Therefore, the first antifuse unit 27 and the second antifuse unit 29 are configured as 2T units. Furthermore, in some embodiments, the first antifuse unit 27 and the second antifuse unit 29 may be configured to store one bit of metadata. Although the antifuse unit array 26 has a row including the first antifuse unit 27 and the second antifuse unit 29, additional unit rows and / or the same row along the X direction may include more or fewer antifuse units. Additionally, the first antifuse unit 27 and the second antifuse unit 29 may be in the form of n-type or p-type transistors. The first antifuse unit 27 and the second antifuse unit 29 respectively include word line transistors 35 and 37 and select line transistors 43 and 45. The first word line 51 (WLn) is connected to the gate terminal of the word line transistor 35 of the first antifuse unit 27, and the second word line 53 (WLn+1) is connected to the gate terminal of the word line transistor 37 of the second antifuse unit 29. The first select line 55 (SLn) is connected to the gate terminal of the select line transistor 43 of the first antifuse unit 27, and the second select line 57 (SLn+1) is connected to the gate terminal of the select line transistor 45 of the second antifuse unit 29. An isolation region 61 is located between the first antifuse unit 27 and the second antifuse unit 29. The source or drain terminals of the word line transistors 35 and 37 of the first antifuse unit 27 and the second antifuse unit 29 are connected to the bit line 59 (BLm). Therefore, the first antifuse unit 27 and the second antifuse unit 29 include select line transistors 43 and 45 and word line transistors 35 and 37 sharing the bit line 59.

[0051] Figure 2B An antifuse unit array 26 according to some embodiments of the present invention is illustrated. The antifuse unit array 26 includes a first antifuse unit 28, a second antifuse unit 30, a third antifuse unit 32, and a fourth antifuse unit 34 (each of which is in...). Figure 2B (Shown in dashed boxes). In some embodiments, as shown, each of the first antifuse unit 28, the second antifuse unit 30, the third antifuse unit 32, and the fourth antifuse unit 34 includes two transistors. Therefore, each of the first antifuse unit 28, the second antifuse unit 30, the third antifuse unit 32, and the fourth antifuse unit 34 is a 2T unit configuration. Furthermore, in some embodiments, each of the first antifuse unit 28, the second antifuse unit 30, the third antifuse unit 32, and the fourth antifuse unit 34 may be configured to store one bit of metadata.

[0052] Although the antifuse cell array 26 has a first row including a first antifuse cell 28 and a second antifuse cell 30, and a second row arranged along the Y direction relative to the first row including a third antifuse cell 32 and a fourth antifuse cell 34, more or fewer antifuse cells may be included in two or more cell rows, or in a single row along the X direction. Furthermore, the first antifuse cell 28, the second antifuse cell 30, the third antifuse cell 32, and the fourth antifuse cell 34 may be in the form of n-type or p-type transistors.

[0053] The first, second, third, and fourth antifuse units 28, 30, 32, and 34 each include word line transistors 36, 38, 40, and 42, and select line transistors 44, 46, 48, and 50, respectively. The first word line 52 (WLn) is connected to the gate terminals of the word line transistors 36 and 40 of the first and third antifuse units 28 and 32, and the second word line 54 (WLn) is connected to the gate terminals of the word line transistors 36 and 40 of the first and third antifuse units 28 and 32. n+1 The first select line 56 (SL) is connected to the gate terminals of the word line transistors 38 and 42 of the second and fourth antifuse units 30 and 34. m ) is connected to the gate terminals of the select line transistors 44 and 46 of the first and second fuse units 28 and 30, and the second select line 58 (SL) m+1 The select lines 56 and 58 are connected to the gate terminals of the select line transistors 48 and 50 of the third and fourth antifuse units 32 and 34, respectively. Select lines 56 and 58 bridge the isolation region 62 to the first and third antifuse units 28 and 32 and to the second and fourth antifuse units 30 and 34, respectively. The source or drain terminals of the word line transistors 36, 38, 40, and 42 of each of the first, second, third, and fourth antifuse units 28, 30, 32, and 34 are connected to the bit line 60 (BL). m Therefore, each of the first, second, third, and fourth antifuse units 28, 30, 32, and 34 includes select line transistors 44, 46, 48, and 50 sharing bit line 60, and word line transistors 36, 38, 40, and 42.

[0054] Figure 2C Draw Figure 2A The antifuse 26, wherein portions of the select line transistors 44, 46, 48, and 50 are in a resistive state.

[0055] Figure 3 Illustration based on one embodiment Figure 2B The array 26, wherein the first antifuse unit 28 is designated as selected and the fourth antifuse unit 34 is designated as unselected. Figure 4AThe illustration depicts a process for programming a single bit in a first antifuse cell 28, used for programming, according to one embodiment. In one embodiment, a programming voltage (e.g., 2.5V) is applied to a first select line 56 through a first select line transistor 44, a lower voltage (e.g., 0.75V) is applied to a first word line 52, and a reference voltage (e.g., 0V) is applied to a bit line 60. A fourth antifuse cell 34 is not selected due to a floating voltage on a second select line 58 and no voltage on a second word line 54. In some forms, a floating voltage indicates that a circuit node or pin is not connected to a defined voltage point, such as ground, power supply, or other fixed voltage. The difference between the voltage applied to the first select line 56 and the reference voltage creates an electric field on the gate dielectric layer of the first select line transistor 44. The electric field is large enough to continuously alter (e.g., break down or fuse 64) the gate dielectric layer of the first select line transistor 44, thereby reducing the resistance of the gate dielectric layer and programming a data bit in the first select line transistor.

[0056] Figure 4B This illustration depicts a process for reading a bit from a first antifuse cell 28 by selecting it for reading. A read voltage (e.g., 0.75V) is applied to a first select line 56 through a first select line transistor 44, a voltage (e.g., 0.75V) is applied to a first word line 52, and a reference voltage (e.g., 0V) is applied to a bit line 60. A fourth antifuse cell 34 is not selected due to a floating voltage on a second select line 58 and no voltage applied to a second word line 54. The difference between the read voltage and the reference voltage generates an electric field 66 on the dielectric semiconductor layer of the first select line transistor 44. The electric field is small enough to avoid continuously altering the gate dielectric layer of the first word line transistor 36, but large enough to generate a read current flowing through it. The read current flows through bit line 60 and is sensed by a sense amplifier (not shown) connected to the bit line to read the bit stored in the first select line transistor 44. Bits can be read from the second, third, and fourth select line transistors 46, 48, and 58 in a similar manner.

[0057] In another embodiment, a bit is programmed into the first antifuse cell 28 by applying a programming voltage (e.g., 3V) to the first select line transistor 44 on the first select line 56, a lower voltage (e.g., 1.2V) to the first word line 52, and a reference voltage (e.g., 0V) to the bit line 60. The fourth antifuse cell 34 is not selected due to the floating voltage of the second select line 58 and no voltage applied to the second word line 54. The process of reading a bit from the first antifuse cell 28 includes applying a read voltage (e.g., 0.8V) to the first select line transistor 44 on the first select line 56, applying a voltage (e.g., 0.8V) to the first word line 52, and applying a reference voltage (e.g., 0V) to the bit line 60. The fourth antifuse cell 34 is not selected due to the floating voltage of the second select line 58 and no voltage applied to the second word line 54.

[0058] To reduce the overall cell area of ​​the antifuse cell array 26, this invention provides a mechanism in various embodiments to enable the first and second antifuse cells 28, 30 and the third and fourth antifuse cells 32, 34 to be formed on a common active region. In various forms, the common active region can be a region of one or more three-dimensional field-effect transistors (e.g., fin field-effect transistors, nanosheets, gate-all-around (GAA) transistors), or an oxide-definition (OD) region of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs), allowing the active region to serve as a source or drain feature of its respective transistor. In various forms, the common active region can extend along the cell row direction. The common active region can include a source / drain structure formed by growing strained source / drain materials between the channel region or sacrificial gates using an epitaxial (epipedaxial) process. The lattice constant of the strained material may differ from that of the substrate forming the epitaxially grown common active region. Therefore, the epitaxially grown source / drain material can act as a stress source to improve carrier mobility. According to some embodiments, the epitaxially grown source / drain material includes silicon-germanium, silicon-carbon-doped silicon, or silicon. Depending on the type of transistor formed, such as a p-type or n-type transistor, p-type or n-type impurities can be in-situ doped during the process of forming the epitaxially grown source / drain material. For example, silicon-germanium-boron (SiGeB) can be grown when the resulting transistor is p-type. Conversely, silicon-phosphorus (SiP) or silicon-carbon-phosphorus (SiCP) can be grown when the resulting transistor is n-type. In some embodiments, p-type or n-type impurities can be implanted into the source / drain material as needed. Implantation can be omitted when p-type or n-type impurities are in-situ doped into the source / drain material during the epitaxial process. In some forms, the common active region includes a lower portion formed in a shallow trench isolation (STI) region and an upper portion formed above the top surface of the STI region.

[0059] Any embodiment of the semiconductor device in this invention may include one or more common active regions, including one of an n-type material or a p-type material formed on a substrate, the substrate including the other of an n-type or p-type material.

[0060] Figures 5 to 7B The illustration includes, according to the embodiment. Figure 2B Various views of the semiconductor device 68 in the circuit. Figure 5The plan view of the plotting device 68 includes a first common active region 70 and a second common active region 72, each extending along the X direction. A first gate line 74 extends along the Y direction and intersects with the first and second common active regions 70 and 72. The first gate line 74 corresponds to... Figure 2B The first character line 52 (WL) shown n The second gate line 76 extends along the Y direction and also intersects with the first and second shared active regions 70 and 72. The second gate line 76 corresponds to... Figure 2B The second character line 54 (WL) shown n+1 ).

[0061] The third gate line 78 extends along the Y direction and intersects the first common active region 70 between the first and second gate lines 74 and 76. The fourth gate line 80 extends along the Y direction and intersects the first common active region 70 between the second and third gate lines 76 and 78. The third and fourth gate lines 78 and 80 do not intersect the second common active region 72. The third and fourth gate lines 78 and 80 together correspond to... Figure 2B The first selection line 56 (SL) shown m This is achieved through an electrical connection between the third and fourth gate lines 78 and 80, which is not in Figure 5 The text is displayed in a simplified manner to simplify the illustration.

[0062] The fifth gate line 82 extends along the Y direction and is aligned with the third gate line 78, intersecting the second common active region 72 between the first and second gate lines 74 and 76. The sixth gate line 84 extends along the Y direction and is aligned with the fourth gate line 80, intersecting the second common active region 72 between the second and fifth gate lines 76 and 82. The fifth and sixth gate lines do not intersect the first common active region 70. The fifth and sixth gate lines 82 and 84 together correspond to... Figure 2B The second selection line 58 (SL) shown m+1 This is achieved through an electrical connection between the fifth and sixth gate lines 82 and 84, which is not in Figure 5 The text is displayed in a simplified manner to simplify the illustration.

[0063] In some embodiments, a virtual polysilicon (poly) segment, i.e., poly-on-OD-edge (PODE), is formed at the edge of the silicon dioxide defined (OD) region, such as the active region of a standard cell. In some embodiments, the PODE may be provided to minimize current leakage in the active region. In some embodiments, the PODE may be provided at the ends of one or more active regions to protect the active region. In some embodiments, the PODE is provided across an active region shared by the antifuse cell and can be considered a shared PODE or a continuous PODE (also referred to herein as CPODE (continuous polysilicon on oxide diffusion edge)). The CPODE may be provided in regions where gaps would otherwise be provided in a conventional standard cell. In some embodiments, the PODE or CPODE may be formed using STI technology. During the fabrication of the antifuse cell array, the PODE or CPODE may be created by forming trenches on the semiconductor wafer on which the antifuse cell array is fabricated, where a dielectric material may be deposited. Due to the use of a dielectric material, the PODE or CPODE does not provide an electrical or conductive path, preventing or at least reducing / minimizing current leakage between components where the PODE or CPODE is located.

[0064] exist Figure 5 In the middle, the first shared active area 70 is composed of Figure 2B The first and second antifuse units 28 and 30 shown are shared, and the second shared active region 72 is composed of... Figure 2B The third and fourth antifuse units 32 and 34 shown are shared. Device 68 includes a CPODE 86 as a first isolation structure. The CPODE 86 provides [something] corresponding to [something]. Figure 2B The region of the isolation region 62. The CPODE 86 extends along the Y direction and passes through the first common active region 70 between the third and fourth gate lines 78, 80, and through the second common active region 72 between the fifth and sixth gate lines 82, 84. The CPODE 86 includes trenches filled with dielectric material that extend into the substrate to a depth below the first and second common active regions 70, 72. Opposite sides of the CPODE along the X direction contact the first and second common active regions 70, 72. The CPODE separates the first common active region between the first and second antifuse units 28, 30, and separates the second common active region 72 between the third and fourth antifuse units 32, 34. Electrical connections exist between the third and fourth gate lines 78, 80 and between the fifth and sixth gate lines 82, 84 (not in... Figure 5 (Simplified illustration shown in the image) and across CPODE. By implementing CPODE in the isolation region of the antifuse array and bridging select lines on the isolation region, the overall cell area of ​​the semiconductor device can be reduced, and the total number of pins, such as compute word lines, select lines, and bit lines, can be reduced.

[0065] Device 68 includes PODE 88 and PODE 90 as isolation structures. PODE 88 extends along the Y direction and intersects with the first and second shared active regions 70 and 72 near the first gate line 74. PODE 90 extends along the Y direction and intersects with the first and second shared active regions 70 and 72 near the second gate line 78.

[0066] The device also includes a first metal diffusion line 92 extending in the Y direction and contacting the first common active region 70 and the second common active region 72, and a second metal diffusion line 94 extending in the Y direction and contacting the first common active region 70 and the second common active region 72. First and second gate lines 74 and 76 are located between the first metal diffusion line 92 and the second metal diffusion line 94. There is an electrical connection between the first metal diffusion line 92 and the second metal diffusion line 94, but not within... Figure 5 The diagram is shown for simplification. The first metal diffusion line 92 and the second metal diffusion line 94 are connected to... Figure 2B The bit line 60 (BL) shown m The device also includes a third metal diffusion line 96, a fourth metal diffusion line 97, a fifth metal diffusion line 98, and a sixth metal diffusion line 99, each extending in the Y direction and contacting the first common active region 70. The third, fourth, fifth, and sixth metal diffusion lines 96, 97, 98, and 99 do not contact the second common active region 72. The device also includes a seventh metal diffusion line 100, an eighth metal diffusion line 101, a ninth metal diffusion line 102, and a tenth metal diffusion line 103, each extending in the Y direction and contacting the second common active region 72. The seventh, eighth, ninth, and tenth metal diffusion lines 100, 101, 102, and 103 do not contact the first common active region 70.

[0067] Figure 6 Draw Figure 5 A partial perspective view of the device 68 shown. An isolation region 106 is disposed above the substrate 104. A first common active region 70 and a second common active region 72 are disposed above the substrate 104 and protrude from the isolation region 106 in the Z direction. Figure 6 Only the first common active region 70 is shown. First, second, third, and fourth gate lines 74, 76, 78, and 80 are shown intersecting the first common active region 70, and a first isolation structure 86 intersects the first common active region between the third and fourth gate lines 78 and 80. Gate line 80 is presented transparently to show region 110 and semiconductor layer 108. In region 110, the gate dielectric material of the gate line can change from an antifuse structure to a fuse structure when a sufficient voltage is applied. The first common active region 70 includes... Figure 2BThe source and drain terminals of the word line transistors 36 and 38 and the select line transistors 44 and 46 of the first antifuse unit 28 and the second antifuse unit 30 are shown. The first gate line 74 corresponds to... Figure 2B The first word line (WL) of transistor 36 shown is the first word line. n The second gate line 76 corresponds to Figure 2B The second word line (WL) of transistor 38 shown is the second word line. n+1 The third and fourth gate lines 78 and 80 correspond to... Figure 2B The first select line (SL) shown is connected between the first and second select line transistors 44 and 46. n The first common active region 70 is connected to the first metal diffusion line 92 and the second metal diffusion line 94. Figure 2B 60 bits (BL) m To simplify the explanation, Figure 6 The middle part is omitted Figure 5 The third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth metal diffusion lines shown are 96, 87, 98, 99, 100, 101, 102, and 103.

[0068] Region 110 illustrates the location where the gate dielectric material of the gate line can transform from an antifuse to a fuse structure when a sufficient voltage is applied. The stacking of semiconductor layers 108 is shown schematically. In the illustrated embodiment, semiconductor layer 108 is aligned with and extends along the length of a first common active region, passing through the channel regions of the first, second, third, and fourth gate lines 74, 76, 78, 80 and portions of the first common active region between the gate lines. In an alternative embodiment, the semiconductor layer is located within the channel regions of the gate lines, but there is no semiconductor layer in the portions of the common active region between the channel regions, and the common active region comprises a source / drain structure epitaxially formed between the channel regions of the gate lines without a semiconductor layer.

[0069] Figure 7A Drawing along Figure 5 A partial cross-section of device 68 in the X direction of AA. (For simplification...) Figure 7A The illustration has been omitted. Figure 6 The substrate and isolation area in the middle. Figure 7A The upper right corner is schematically illustrated, according to some embodiments, an enlarged region 110, in which the gate dielectric material 116 between the gate material 120 and the semiconductor layer 108 can be transformed from an antifuse structure to a fuse structure when a sufficient voltage is applied. Figure 7A The lower right corner schematically illustrates, according to certain embodiments, the formation of a conductive fuse structure 117 therein after a sufficient voltage is applied to the gate dielectric material 116. Figure 7A The situation in the area shown in the upper right corner.

[0070] Figure 7B The illustration is based on certain embodiments. Figure 7A A channel region is defined within the upper frame 112 of the second gate line 76. The channel region 112 includes a stack of semiconductor layers 108 and a gate structure 114 surrounding the semiconductor layers. The semiconductor layers function as the channel structure and extend along the X-direction through the gate line toward the source / drain structure of the first common active region 70. The gate structure 114 includes a gate dielectric layer 116, a work function layer 118, and a gate material 120. Internal spacers 122 are formed on opposite sides of the gate material 120. The gate material 120 is surrounded by the work function material 118, which in turn is surrounded by the gate dielectric layer 116. The gate dielectric layer 116 is located between the gate material 120 and the semiconductor layer 108, and between the gate material 120 and the source / drain structure of the first common active region 70. The gate dielectric layer 116 is configured to function as an antifuse structure, converting to a fuse structure by applying a sufficient voltage to the gate line. In some embodiments, each of the first, second, third, fourth, fifth, and sixth gate lines 74, 76, 78, 80, 82, 84 includes as follows Figure 7B The channel region shown.

[0071] Figure 7C An antifuse structure 93 formed on a substrate 95 according to an embodiment is illustrated schematically. In some embodiments, the substrate is a silicon substrate. The antifuse structure 93 includes an upper metal layer (or upper metal oxide layer) 97 disposed in contact with an insulating layer 99 (e.g., a gate dielectric layer), the insulating layer 99 being disposed above a lower metal layer (or lower metal oxide layer) 101. In some embodiments, the insulating layer is made of amorphous silicon. Figure 7C In this process, current 103 is applied through the upper metal layer 97, but the voltage is insufficient to cause substantial degradation or breakdown of the insulating layer 99. Therefore, the insulating layer 99 exhibits a higher resistance than the upper metal layer 97. Consequently, current 103 does not pass through the insulating layer 99. Figure 7D A fuse structure 105 is schematically illustrated, formed by applying a current 107 with a sufficient voltage to the upper metal layer 97, causing a portion of the insulating layer 99 to break down into a conductive material 109. Therefore, the conductive material has a resistance equal to or less than that of the upper metal layer 97. In some embodiments, the conductive material is polycrystalline silicon.

[0072] Figure 7E The illustration shows a partial cross-section of an array including two devices 113 and 115, each device having Figure 7AThe structure of device 68 is shown. Device 113 includes a selected region 119, and device 115 includes an unselected region 121. The selected region has an area 123 in which the gate dielectric material of the gate line can be transformed from an antifuse structure to a fuse structure when a sufficient voltage is applied. The isolation region 125 of device 113 results in a narrower spacing than the spacing 127 provided between the two devices 113, 115.

[0073] Figure 8 , Figure 9 , Figure 10A as well as Figure 10B The illustration includes, according to certain embodiments Figure 2B Various views of the semiconductor device 124 of the circuit shown. Figure 8 It's a floor plan. Figure 9 This is a 3D view of semiconductor device 124. Figures 8 to 10B The components of the device 124 shown are... Figures 5 to 7B The same structure provided in the device 68 shown is in Figures 8 to 10B The numbers are the same. Device 124 includes the corresponding Figure 2B A first sacrificial gate line 126 is located in the region of the central isolation region 62. The first sacrificial gate line 126 extends in the Y direction and passes through the first common active region 70 and the second common active region 72, situated between the third and fourth gate lines 78 and 80 and between the fifth and sixth gate lines 82 and 84. The device 124 also includes second and third sacrificial gate lines 128 and 130 extending in the Y direction. The second sacrificial gate line 128 intersects the first common active region 70 and the second common active region 72 near the first gate line 74, and the third sacrificial gate line 130 intersects the first common active region 70 and the second common active region 72 near the second gate line 76.

[0074] Figure 10A Drawing along Figure 8 The first sacrificial gate line 126 includes a stack of semiconductor layers 108 and a sacrificial dielectric 132 located between the semiconductor layers and on the upper semiconductor layer in the stack. Internal spacers 122 are formed on opposite sides of the sacrificial dielectric 132. The second and third sacrificial gate lines 128 and 130 may have the same or different structures as the first sacrificial gate line 126; for simplicity, the diagram is shown below. Figure 10A (The text is omitted.) By implementing sacrificial gate lines, the overall cell area of ​​the semiconductor device can be further reduced.

[0075] Figure 10B The illustration illustrates, according to certain embodiments, Figure 10AThe modified device shown features a longer common active region 70 and three sacrificial gate lines 126, 133, and 135. The selected cell 129 has an area 110 in which the gate dielectric material of the gate lines can be transformed from an antifuse to a fuse structure when a sufficient voltage is applied. The unselected region 131 does not have the transformed area 110. The insulated sacrificial gate line 133 reduces the spacing between the selected region 129 and the unselected region 135.

[0076] Figures 11 to 13D The illustration includes, according to the embodiments. Figure 2B Various views of the semiconductor device 134 of the circuit shown. Figures 11 to 13D The components of the device 134 shown are... Figures 5-7B The same structure provided in the device 68 shown is in Figures 11 to 13D The numbers are the same. Device 134 includes a region 136 surrounded by a dashed box, which contains a third gate line 138, a fourth gate line 140, a fifth gate line 142, and a sixth gate line 144. Each gate line extends in the Y direction and includes a focused antifuse structure as described below. The third and fourth gate lines 138 and 140 intersect with the first common active region 70, and the fifth and sixth gate lines 142 and 144 intersect with the second common active region 72. The third and fourth gate lines 138 and 140 do not intersect with the second common active region 72, and the fifth and sixth gate lines 142 and 144 do not intersect with the first common active region 70.

[0077] Device 134 includes a plurality of dielectric sacrificial gate lines 146 as a first isolation structure. The plurality of dielectric sacrificial gate lines 146 extend in the Y direction and intersect with a first common active region 70 between third and fourth gate lines 138, 140, and with a second common active region 72 between fifth and sixth gate lines 142, 144. The third and fourth gate lines 138, 140 together correspond to... Figure 2A The first selection line 56 (SL) shown m ), through the electrical connection of the sacrificial gate line 146 bridging the third and fourth gate lines 138, 140, this connection is simplified in the diagram Figure 11 Not shown in the image. In the same manner, the fifth and sixth gate lines 142 and 144 together correspond to... Figure 2B The second selection line 58 (SL) shown m+1 ).

[0078] Device 134 also includes isolation structures 148 and 150 extending in the Y direction and intersecting the first common active region 70 and the second common active region 72. First and second gate lines 74 and 76 are located between isolation structures 148 and 150. Isolation structures 148 and 150 may each have independent... Figure 10A The structure of the first sacrificial gate line 126 shown, PODE, Figure 13AThe structure shown can be a combination of dielectric sacrificial gate lines, or any other useful isolation structure.

[0079] Figure 12 Draw Figure 11 A perspective view of a portion of the illustrated device 134 includes a first common active region 70 and a portion of region 136, including third and fourth gate lines 138, 140 and a plurality of dielectric sacrificial gate lines 146. The first, second, third, and fourth gate lines 74, 76, 138, 140 and the plurality of dielectric sacrificial gate lines 146 intersect the first common active region 70. Gate lines 140 are presented transparently to show area 154 and semiconductor layer 152. Area 154 illustrates the location where the gate dielectric material of the gate line can transform from an antifuse to a fuse structure when a sufficient voltage is applied. A sufficient voltage can be applied when designated cell 30 is the selected cell. In some embodiments, the semiconductor layer 152 in the common active region between the second and fourth gate lines 76, 140 is aligned with and extends the length of the first common active region, passing through the channel regions of the first, second, third, and fourth gate lines 74, 76, 138, 140 and the cross-section of the first common active region between the gate lines. In an alternative embodiment, the semiconductor layer is located in the channel region of the gate line, but there is no semiconductor layer in the common active region cross section between the channel regions, and the common active region includes a source / drain structure epitaxially formed between the gate line channel regions without a semiconductor layer.

[0080] Figure 13A Drawing along Figure 11 The cross section of device 134 is intercepted in the X direction of CC. Figure 13A The upper right portion further illustrates, according to some embodiments, an enlarged area 154, wherein a gate dielectric material 116 formed around the gate material 120 can be transformed from an antifuse structure to a fuse structure when a sufficient voltage is applied. The gate dielectric material 116 is disposed between the gate material 120 and the semiconductor layer 152. Figure 13A The lower right of the diagram further illustrates, according to some embodiments, another enlarged area, in which a second dielectric material 164 is formed instead of Figure 13A The upper right corner shows the gate dielectric material 116 and the gate material 120. Figure 13A In the lower right corner, the second dielectric material 164 is formed as a multilayer. Alternatively, the second dielectric material may be formed as a single layer.

[0081] Figure 13B Draw Figure 13AA channel region is defined within a frame 156 on the second gate line 76. The channel region 156 includes a stack of semiconductor layers 152 and a gate structure 114 surrounding the semiconductor layers. The semiconductor layers function as a channel structure and extend along the X-direction through the gate line toward the source / drain structure of the first common active region 70. The gate structure 114 includes a gate dielectric layer 116, a work function layer 118, and a gate material 120. Internal spacers 122 are formed on opposite sides of the gate material 120. The gate material 120 is surrounded by the work function material 118, which in turn is surrounded by the gate dielectric layer 116. The gate dielectric layer 116 is located between the gate material 120 and the semiconductor layer 152, and between the gate material 120 and the source / drain structure of the first common active region 70.

[0082] Figure 13C Draw Figure 13A A channel region 158 is formed within a frame 158 of multiple dielectric sacrificial gate lines 146. The channel region 158 of the multiple dielectric sacrificial gate lines 146 includes a first dielectric material 162 and a second dielectric material 164. The first dielectric material 162 is disposed above an upper semiconductor layer 152U of the channel region and surrounded by a gate dielectric layer 116. The second dielectric material 164 is disposed below the upper semiconductor layer 152U and between a semiconductor layer 152L below the upper semiconductor layer. The second dielectric material 164 is surrounded by the gate dielectric layer 116. In some forms, the first and second dielectric materials are different. In some forms, the first dielectric material may include an insulator, such as silicon dioxide or silicon nitride, and the second dielectric material may include an insulator, such as aluminum oxide. In other forms, the first and second dielectric materials are the same. Internal spacers 122 are formed on opposite sides of the first and second dielectric materials 162, 164 in the channel region.

[0083] Figure 13D Draw Figure 13A A focused antifuse structure for the third and fourth gate lines 138 and 140 within the upper frames 160 and 161 of the middle channel region. A gate structure 114 is disposed above the upper semiconductor layer 152U. The gate structure 114 includes a gate dielectric layer 116, a work function layer 118, and a gate material 120. The gate dielectric layer 116 is located between the gate material 120 and the semiconductor layer 152U, and between the gate material 120 and the source / drain structure of the first common active region 70. The gate dielectric layer 116 is configured to function as an antifuse structure and can be converted into a fuse structure by applying a sufficient voltage to the third and fourth gate lines 138 and 140. A second dielectric material 164 is disposed below the upper semiconductor layer 152U and between the semiconductor layer 152L below the upper semiconductor layer 152U. The second dielectric material is surrounded by the gate dielectric layer 116. Internal spacers 122 are formed on opposite sides of the gate material 120 and the second dielectric material 164 at different levels in the channel region.

[0084] Given that the antifuse structures of the third and fourth gate lines 138, 140 are concentrated or focused on a single level, the conduction cell current through the antifuse structure can be more easily controlled compared to gate lines comprising multiple antifuse structures. In a channel region with a focused antifuse structure, the gate structure 114 can be provided at any level of the channel region, such as at the bottom, top, or any intermediate level between semiconductor layers, while the remaining layers between semiconductor layers may comprise dielectric material. By implementing sacrificial gate lines and gate lines including focused antifuse structures, the overall cell area of ​​the semiconductor device can be reduced, and the breakdown point of the antifuse structure can be controlled to improve the variation of conduction cell current and mitigate channel inversion. In some embodiments, the third and fourth gate lines 138, 140 may have the features discussed below. Figure 21C The structure shown.

[0085] Figure 13E One embodiment of the channel region of the plotting device includes layers 152U and 152L of semiconductor material. A second dielectric material 164 with a different dielectric constant is formed between layers 152U and 152L before a gate structure is applied over the upper semiconductor layer 152U.

[0086] Figure 14A An antifuse unit array 169 according to an embodiment of the present invention is illustrated. The antifuse unit array 169 includes a first antifuse unit 171 and a second antifuse unit 173 (both are located in...). Figure 14A (shown in dashed boxes). In some embodiments, as shown, the first and second antifuse units 171 and 173 each include three transistors. Therefore, the first and second antifuse units 171 and 173 are both 3T unit configurations. Although the antifuse unit array 169 has one row including the first antifuse unit 171 and the second antifuse unit 173, more or fewer antifuse units may be included in two or more unit columns and / or in the same row along the X direction. Furthermore, the first antifuse unit 171 and the second antifuse unit 173 may be in the form of n-type or p-type transistors. The first and second antifuse units 171 and 173 each include two word line transistors and one select line transistor. The first word line 179 (WL) n The second word line 181 (WL) is connected to the gate terminal of the word line transistor 187 of the first antifuse unit 171. n+1 The third word line 183 (WL) is connected to the gate terminal of the word line transistor 191 of the second antifuse unit 173. k The fourth word line 185 (WL) is connected to the gate terminal of the word line transistor 195 of the first antifuse unit 171. k+1 The character line transistor 199 is connected to the gate terminal of the second antifuse unit 173. Select line 203 (SL)m The select line 203 is connected to the gate terminals of the select line transistors 207 and 209 of the first and second antifuse units 171 and 173. The select line 203 bridges the isolation region 215 between the first and second antifuse units 171 and 173. The source or drain terminals of the word line transistors 195 and 199 of the first and second antifuse units are connected to the bit line 217 (BL). m Therefore, the first and second antifuse units include a select line transistor and two word line transistors sharing a bit line 217.

[0087] Figure 14B An antifuse unit array 170 according to an embodiment of the present invention is illustrated. The antifuse unit array 170 includes a first antifuse unit 172, a second antifuse unit 174, a third antifuse unit 176, and a fourth antifuse unit 178 (each in a...). Figure 14B (Shown in dashed boxes). In some embodiments, as shown, each of the first, second, third, and fourth antifuse units 172, 174, 176, and 178 includes three transistors. Therefore, each of the first, second, third, and fourth antifuse units 172, 174, 176, and 178 is a 3T unit configuration. Although the antifuse unit array 170 has a first row including the first antifuse unit 172 and the second antifuse unit 174, and a second row arranged along the Y direction relative to the first row and including the third antifuse unit 176 and the fourth antifuse unit 178, more or fewer antifuse units may be included in two or more unit rows, or in a single row along the X direction. Furthermore, the first antifuse unit 172, the second antifuse unit 174, the third antifuse unit 176, and the fourth antifuse unit 178 may be in the form of n-type or p-type transistors.

[0088] The first, second, third, and fourth antifuse units 172, 174, 176, and 178 each include two word line transistors and one select line transistor. The first word line 180 (WL) n The word line transistors 188 and 190 are connected to the gate terminals of the first and third antifuse units 172 and 176, respectively. The second word line 182 (WL) n+1 The third word line 184 (WL) is connected to the gate terminals of the word line transistors 192 and 194 of the second and fourth antifuse units 174 and 178. k The fourth word line 186 (WL) is connected to the gate terminals of the word line transistors 196 and 198 of the first and third antifuse units 172 and 176. k+1 () is connected to the gate terminals of the word line transistors 200 and 202 of the second and fourth antifuse units 174 and 178.

[0089] First choice line 204 (SL)m The gate terminals of the select line transistors 208 and 210 connected to the first and second antifuse units 172 and 174, and the second select line 206 (SL) m+1 The gate terminals of select line transistors 212 and 214 are connected to the third and fourth antifuse units 176 and 178. Select lines 204 and 206 bridge the isolation regions 216 between the first antifuse unit 172 and the second antifuse unit 174, and between the third antifuse unit 176 and the fourth antifuse unit 178, respectively. The source or drain terminals of the word line transistors 196, 200, 198, and 202 of each of the first, second, third, and fourth antifuse units are connected to the bit line 218 (BLm). Therefore, each of the first, second, third, and fourth antifuse units includes a select line transistor and a word line transistor sharing the bit line 218. Figure 14C Draw Figure 14B The antifuse array, in which portions of select line transistors 208, 210, 212 and 214 are in a resistive state.

[0090] Figure 14D The illustration is based on one embodiment. Figure 14B In the array, the first antifuse unit 172 is designated as selected and the fourth antifuse unit 178 is designated as unselected. Figure 14E The illustration depicts a process for programming bits in a first antifuse cell 172 according to one embodiment (selecting the first antifuse cell 172 for programming). A programming voltage (e.g., 3V) is applied to the first select line 204 to the first select line transistor 208, a lower voltage (e.g., 1.2V) is applied to the first and third word lines 180, 184, and a reference voltage (e.g., 0V) is applied to the bit line 218. The fourth antifuse cell 178 is not selected due to the floating voltage of the second select line 206 and no voltage is applied to the second and fourth word lines 182, 186. The difference between the voltage applied to the first select line 204 and the reference voltage generates an electric field on the gate dielectric layer of the first select line transistor 208. The electric field is large enough to continuously alter (e.g., break down or melt 211) the gate dielectric layer of the first select line transistor 208, thereby reducing the resistance of the gate dielectric layer and programming the data bits in the first select line transistor.

[0091] Figure 14FAn embodiment of the process for reading bits from the first antifuse cell 172 (selecting the first antifuse cell 172 for reading) is illustrated. A read voltage (e.g., 0.8V) is applied to the first select line 204 to the first select line transistor 208, a voltage (e.g., 0.8V) is applied to the first and third word lines 180, 184, and a reference voltage (e.g., 0V) is applied to the bit line 218. The fourth antifuse cell 178 is not selected because of the floating voltage of the second select line 206 and no voltage is applied to the second and fourth word lines 182, 186. The difference between the read voltage and the reference voltage generates an electric field 213 on the dielectric semiconductor layer of the first select line transistor 208. The electric field is small enough to avoid continuously altering the gate dielectric layer of the word line transistors 188, 196, but large enough to generate a read current flowing through it. The read current flows through bit line 218 and is sensed by a sense amplifier (not shown) connected to the bit line to read the bits stored in the first select line transistor 208.

[0092] Figures 15 to 17 The illustration is based on one embodiment, including Figure 14B Various views of the semiconductor device 220 of the circuit shown. Figure 15 The plan view of the plotting device 220 includes a first shared active area 222 and a second shared active area 224, both extending along the X direction. The first shared active area 222 consists of... Figure 14B The first and second antifuse units 172 and 174 shown are shared, and the second shared active region 224 is composed of Figure 14B The third and fourth antifuse units 176 and 178 shown are shared. The first and second gate lines 226 and 228 extend along the Y direction and intersect with the first and second shared active regions 222 and 224. The first gate line 226 corresponds to... Figure 14B The first character line shown is 180 (WL) n The second gate line 228 corresponds to Figure 14B The second character line 182 (WL) shown n+1 ).

[0093] The third and fourth gate lines 230 and 232 each extend along the Y direction and intersect with the first common active region 222. The third gate line 230 intersects with the first common active region 222 between the first and second gate lines 226 and 228, and the fourth gate line 232 intersects with the first common active region 222 between the second and third gate lines 228 and 230. The third and fourth gate lines 230 and 232 do not intersect with the second common active region 224. The third and fourth gate lines 230 and 232 together correspond to Figure 14B The first selection line 204 (SL) shown m ), through the electrical connection between the third and fourth gate lines 230, 232, this connection is not in Figure 15 The diagram is displayed in a simplified manner.

[0094] The fifth and sixth gate lines 234 and 236 extend along the Y direction and intersect with the second common active region 224. The fifth gate line 234 is located between the first and second gate lines 226 and 228 and is aligned with the third gate line 230. The sixth gate line 236 is located between the fifth and second gate lines 228 and 234 and is aligned with the fourth gate line 232. The fifth and sixth gate lines 234 and 236 do not intersect with the first common active region 222. Together, the fifth and sixth gate lines 234 and 236 correspond to... Figure 14B The second selection line 206 (SL) shown m+1 ), through the electrical connection between the fifth and sixth gate lines 234, 236, this connection is not in Figure 15 The diagram is displayed in a simplified manner.

[0095] Device 220 includes a seventh gate line 238 and an eighth gate line 240, which extend along the Y direction and intersect with the first and second shared active regions 222, 224. The first and second gate lines 226, 228 are located between the seventh and eighth gate lines 238, 240. The seventh gate line 238 corresponds to... Figure 14B The third word line 180 (WLk) shown corresponds to the eighth gate line 240. Figure 14B The fourth character line shown is 182 (WL) k+1 ).

[0096] Device 220 includes a region 242 defined by a dashed frame surrounding third, fourth, fifth, and sixth gate lines 230, 232, 234, and 236, wherein the third, fourth, fifth, and sixth gate lines 230, 232, 234, and 236 include channel regions having a focused antifuse structure as described below. Device 220 includes a plurality of dielectric sacrificial gate lines 244. The plurality of dielectric sacrificial gate lines 244 extend along the Y direction and intersect with a first common active region 222 between the third and fourth gate lines 230, 232, and with a second common active region 224 between the fifth and sixth gate lines 234, 236.

[0097] Device 220 also includes isolation structures 246 and 248 that extend along the Y direction and intersect with the first and second shared active regions 222 and 224. Seventh and eighth gate lines 238 and 240 are located between isolation structures 246 and 248. Isolation structures 246 and 248 may each have independent... Figure 10A The structure of the first sacrificial gate line 126 shown, PODE, polysilicon layer, multiple dielectric sacrificial gate lines 244, or any other useful isolation structure.

[0098] Device 220 further includes a first metal-covered diffusion line 253 and a second metal-covered diffusion line 261, which extend in the Y direction and contact the first common active region 222, and a third metal-covered diffusion line 250 and a fourth metal-covered diffusion line 252, which are aligned with the first and second metal-covered diffusion lines and contact the second common active region 224, respectively. First and second gate lines 226 and 228 are located between the third and fourth metal-covered diffusion lines 253 and 261, and between the third and fourth metal-covered diffusion lines 250 and 252. Device 220 also includes a fifth metal-covered diffusion line 254, a sixth metal-covered diffusion line 259, a seventh metal-covered diffusion line 255, and an eighth metal-covered diffusion line 258, each extending in the Y direction and contacting the first common active region 222. Device 220 also includes a ninth metal-covered diffusion line 251, a tenth metal-covered diffusion line 260, an eleventh metal-covered diffusion line 256, and a twelfth metal-covered diffusion line 257, each extending in the Y direction and contacting the second common active region 224. Device 220 also includes thirteenth and fourteenth metal-covered diffusion lines 262, 264, each extending along the Y direction and contacting the first and second common active regions 222, 224, and connected to Figure 14B The bit line 218 is shown.

[0099] Figure 16 Draw Figure 15 A partial perspective view of the device 220 shown. The device includes a substrate 266 and an isolation region 268 disposed on the substrate. First and second common active regions 222 and 224 are disposed on the substrate and protrude above the isolation region 268 in the Z direction. Figure 16 Only the first common active region 222 is shown. First gate line 226, second gate line 228, third gate line 230, fourth gate line 232, seventh gate line 238, and eighth gate line 240 are shown intersecting the first common active region 222. Multiple dielectric sacrificial gate lines 244 intersect the first common active region 222 between the third and fourth gate lines 230 and 232. The first common active region 222 includes... Figure 14B The source and drain terminals of the word line transistors 188, 196 and the select line transistor 208 of the first antifuse unit 172, and the source and drain terminals of the word line transistors 192, 200 and the select line transistor 210 of the second antifuse unit 174 are shown.

[0100] Region 242, including third and fourth gate lines 230, 232 and a plurality of dielectric sacrificial gate lines 244, is shown. The fourth gate line 232 is drawn transparently to show area 272 and semiconductor layer 152. In area 272, the gate dielectric material of the gate line can be converted from an antifuse to a fused structure when a sufficient voltage is applied. In some embodiments, semiconductor layer 152 extends the length of a first common active region, passing through the channel regions of the first, second, third, fourth, seventh, and eighth gate lines 226, 228, 230, 232, 238, 240 and portions of the first common active region 222 between the gate lines. In an alternative embodiment, the semiconductor layer is located within the channel regions of the gate lines, but there is no semiconductor layer in the portions of the common active region between the channel regions, and the common active region comprises a source / drain structure epitaxially formed between the gate line channel regions without a semiconductor layer.

[0101] Figure 17 Drawing along Figure 15 A partial cross-section of device 220 taken in the X direction of the middle DD. The dashed box 274 surrounds the channel region of the second gate line 228 and includes... Figure 13B The structure of the channel region is shown. The channel regions of the first, seventh, and eighth gate lines 226, 238, and 240 also have... Figure 13B The structure of the channel region is shown. The dashed box 276 surrounds the channel region containing the plurality of dielectric sacrificial gate lines 146 and includes... Figure 13C The structure of the channel region is shown. The dashed box 278 surrounds the channel region of the third and fourth gate lines 230, 232, and includes... Figure 13D The structure of the channel region shown. Figure 13D The gate dielectric layer 116 is configured as an antifuse structure, which can be converted into a fuse structure by applying sufficient voltage to the third and fourth gate lines 138, 140. Given that the antifuse structure is concentrated or focused on a single level of the third and fourth gate lines 230, 232, current control via the antifuse structure is easier to achieve compared to gate lines comprising multiple antifuse structures. By implementing sacrificial gate lines and gate lines including focused antifuse structures, circuits operating at high voltages can exhibit high bias immunity, and the breakdown point of the antifuse structure can be controlled to improve the variability of the conduction cell current. In other embodiments, the channel region in block 278 has the characteristics described below. Figure 21C The structure shown.

[0102] Figure 18A An antifuse unit array 279 according to some embodiments of the present invention is illustrated. The antifuse unit array 279 includes a first antifuse unit 281 and a second antifuse unit 283 (both are located in...). Figure 18A(As shown within the dashed box). In some embodiments, as shown, the first and second antifuse units 281 and 283 each include two transistors. Therefore, the first and second antifuse units 281 and 283 are both 2T unit configurations. Although the antifuse unit array 279 has rows including the first antifuse unit 281 and the second antifuse unit 283, more or fewer antifuse units may be included in two or more unit rows and / or in the same row along the X direction. Furthermore, the first antifuse unit 281 and the second antifuse unit 283 may be in the form of n-type or p-type transistors. The first and second antifuse units 281 and 283 each include a word line transistor and a select line transistor. The first word line 289 (WL) n The second word line 291 (WL) is connected to the gate terminal of the word line transistor 301 of the first antifuse unit 281. n+1 The first select line 293 (SL) is connected to the gate terminal of the word line transistor 305 of the second antifuse unit 283. m The gate terminal of the select line transistor 309 connected to the first antifuse unit 282, and the second select line 295 (SL) m ) is connected to the gate terminal of the select line transistor 311 of the second antifuse unit 283. Bit line 317 (BL m The source / drain structure is connected between the first and second word line transistors 301 and 305. Therefore, each of the first and second antifuse units includes a word line transistor sharing a bit line 317.

[0103] Figure 18B An antifuse unit array 280 according to some embodiments of the present invention is illustrated. The antifuse unit array 280 includes a first antifuse unit 282, a second antifuse unit 284, a third antifuse unit 286, and a fourth antifuse unit 288 (each in...). Figure 18B (As shown within the dashed box). In some embodiments, as shown, the first, second, third, and fourth antifuse units 282, 284, 286, and 288 each include two transistors. Therefore, the first, second, third, and fourth antifuse units 282, 284, 286, and 288 are each configured as 2T units.

[0104] Although the antifuse cell array 280 has a first row including a first antifuse cell 282 and a second antifuse cell 284, and a second row arranged along the Y direction relative to the first row and including a third antifuse cell 286 and a fourth antifuse cell 288, more or fewer antifuse cells may be included in two or more cell rows and / or in the same row along the X direction. Furthermore, the first antifuse cell 282, the second antifuse cell 284, the third antifuse cell 286, and the fourth antifuse cell 288 may be in the form of n-type or p-type transistors.

[0105] The first, second, third, and fourth antifuse units 282, 284, 286, and 288 each include a word line transistor and a select line transistor. The first word line 290 (WL) n The second word line 292 (WL) is connected to the gate terminals of the word line transistors 302 and 304 of the first and third antifuse units 282 and 286. n+1 The word line transistors 306 and 308 are connected to the gate terminals of the second and fourth antifuse units 284 and 288. The first select line 294 (SL) m The gate terminal of the select line transistor 310 connected to the first antifuse unit 282, and the second select line 296 (SL) m The third select line 298 (SL) is connected to the gate terminal of the select line transistor 312 of the second antifuse unit 284. m+1 The fourth select line 300 (SL) is connected to the gate terminal of the select line transistor 314 of the third antifuse unit 286. m+1 ) is connected to the gate terminal of the select line transistor 314 of the fourth antifuse unit 288. Bit line 318 (BL m The source / drain structure is connected between the first and second word line transistors 302 and 306 and between the third and fourth word line transistors 304 and 308. Therefore, the first, second, third, and fourth antifuse units 282, 284, 286, and 288 each include a word line transistor sharing a bit line 318.

[0106] Figure 18C The portions of select line transistors 310, 312, 314, and 316 are shown to illustrate their resistance states.

[0107] Figure 18D Draw Figure 18B An array in which a first antifuse unit 282 is designated as selected and a fourth antifuse unit 288 is designated as unselected, according to one embodiment. Figure 18EThe illustration depicts a process for programming bits in a first antifuse cell 282 (selecting the first antifuse cell 282 for programming) according to one embodiment. A programming voltage (e.g., 3V) is applied to a first select line 294 to a first select line transistor 310, a lower voltage (e.g., 1.2V) is applied to a first word line 290, and a reference voltage (e.g., 0V) is applied to a bit line 318. A fourth antifuse cell 288 is not selected by a floating voltage on a fourth select line 300 and by not applying a voltage to the second word line 292. The difference between the voltage applied to the first select line 294 and the reference voltage generates an electric field on the gate dielectric layer of the first select line transistor 310. This electric field is large enough to continuously alter (e.g., break down or melt 313) the gate dielectric layer of the first select line transistor 310, thereby reducing the resistance of the gate dielectric layer and programming data bits in the first select line transistor.

[0108] Figure 18F The illustration depicts a process for reading bits from a first antifuse cell 282 (selecting the first antifuse cell 282 for reading) in one embodiment. A read voltage (e.g., 0.8V) is applied to a first select line 294 through a first select line transistor 310, a voltage (e.g., 0.8V) is applied to a first word line 290, and a reference voltage (e.g., 0V) is applied to a bit line 318. A fourth antifuse cell 288 is not selected by a floating voltage on a fourth select line 300 and by not applying a voltage to the fourth word line 292. The difference between the read voltage and the reference voltage generates an electric field 315 on the dielectric semiconductor layer of the first select line transistor 310. This electric field is small enough to avoid continuously altering the gate dielectric layer of the first word line transistor 310, but large enough to generate a read current flowing through it. The read current flows through bit line 318 and is sensed by a sense amplifier (not shown) connected to the bit line to read the bits stored in the first select line transistor 310.

[0109] Figure 19A The illustration includes, according to one embodiment, Figure 18B Semiconductor device 320 with the circuit wiring shown. Figure 19A The plan view of the plotting device 320 includes a first shared active area 322 and a second shared active area 324, each extending along the X direction. The first shared active area 322 consists of... Figure 18B The first and second antifuse units 282 and 284 shown are shared, and the second shared active area 324 is composed of Figure 18B The third and fourth antifuse units 286 and 288 shown are shared. The first and second gate lines 326 and 328 extend along the Y direction and intersect with the first shared active region 322, but do not intersect with the second shared active region 324. The first gate line 326 corresponds to... Figure 18B The first selection line 294 (SL) shown mThe second gate line 328 corresponds to Figure 18B The second selection line 296 (SL) shown m The third and fourth gate lines 330 and 332 extend along the Y direction and intersect the second shared active region 324, but do not intersect the first shared active region 322. The third gate line 330 is aligned with the first gate line 326, and the fourth gate line 332 is aligned with the second gate line 328. The third gate line 330 corresponds to... Figure 18B The third selection line 298 (SL) shown m+1 ), the fourth gate line 332 corresponds to Figure 18B The fourth selection line 300 (SL) shown m+1 ).

[0110] The fifth and sixth gate lines 334 and 336 extend along the Y direction and intersect with both the first and second shared active regions. The fifth gate line 334 intersects with the first shared active region 322 between the first and second gate lines 326 and 328, and with the second shared active region 324 between the third and fourth gate lines 330 and 332. The sixth gate line 336 intersects with the first shared active region 322 between the second and fifth lines 328 and 334, and with the second shared active region 324 between the fourth and fifth lines 332 and 334. The fifth gate line 334 corresponds to... Figure 18B The first character line shown is 290 (WL) n The sixth gate line 336 corresponds to Figure 18B The second character line 292 (WL) shown n+1 ).

[0111] The device 320 further includes a first metal diffusion layer 338 and a second metal diffusion layer 340, which extend along the Y direction and contact the first and second common active regions 322 and 324. First, second, third, fourth, fifth, and sixth gate lines 326, 328, 330, 332, 334, and 336 are located between the first and second metal diffusion layers 338 and 340. Third and fourth metal diffusion layers 342 and 344 extend along the Y direction and contact the first and second common active regions 322 and 324. The third metal diffusion layer 342 intersects the first common active region 322 between the first and fifth gate lines 326 and 334, and intersects the second common active region between the third and fifth gate lines 330 and 334. The fourth metal diffusion layer 344 intersects the first common active region 322 between the second and sixth gate lines 328 and 336, and intersects the second common active region between the fourth and sixth gate lines 332 and 336. The fifth metal diffusion layer 346 intersects with the first and second common active regions 322 and 324 between the fifth and sixth gate lines 334 and 336. The fifth metal diffusion layer 346 corresponds to... Figure 18B The bit line shown (BL)m ).

[0112] Device 320 also includes isolation structures 348 and 350 extending along the Y direction and intersecting with the first and second shared active regions 322 and 324. Isolation structures 348 and 350 may each have independent... Figure 10A The structure of the first sacrificial gate line 126 shown, PODE, Figure 13A The structure shown includes multiple dielectric sacrificial gate lines, or any other useful isolation structure.

[0113] Device 220 includes a region 352 defined by a dashed frame surrounding the first and third gate lines 326, 330, and a region 354 defined by a dashed frame surrounding the second and fourth gate lines 328, 332, wherein the first, second, third, and fourth gate lines include channel regions having a focused antifuse structure as described below.

[0114] Figure 19B A plan view of another embodiment of semiconductor device 321 is shown, having a first common active region 322 and a second common active region 324 extending along the X direction. The first common active region 322 consists of... Figure 18B The first and second antifuse units 282 and 284 shown are shared, and the second shared active area 324 is composed of Figure 18B The third and fourth antifuse units 286 and 288 shown are shared. The first and second gate lines 326 and 328 extend along the Y direction and intersect with the first shared active region 322, but do not intersect with the second shared active region 324. The first gate line 326 corresponds to... Figure 18B The first selection line 294 (SL) shown m The second gate line 328 corresponds to Figure 18B The second selection line 296 (SL) shown m The third and fourth gate lines 330 and 332 extend along the Y direction and intersect the second common active region 324, but do not intersect the first common active region 322. The third gate line 330 is aligned with the first gate line 326, and the fourth gate line 332 is aligned with the second gate line 328. The third gate line 330 corresponds to... Figure 18B The third selection line 298 (SL) shown m+1 ), the fourth gate line 332 corresponds to Figure 18B The fourth selection line 300 (SL) shown m+1The fifth and sixth gate lines 334 and 336 extend along the Y direction and intersect with both the first and second shared active regions. The fifth gate line 334 intersects with the first shared active region 322 between the first and second gate lines 326 and 328, and with the second shared active region 324 between the third and fourth gate lines 330 and 332. The sixth gate line 336 intersects with the first shared active region 322 between the second and fifth gate lines 328 and 334, and with the second shared active region 324 between the fourth and fifth gate lines 332 and 334. The fifth gate line 334 corresponds to... Figure 18B The first character line shown is 290 (WL) n The sixth gate line 336 corresponds to Figure 18B The second character line 292 (WL) shown n+1 The device 321 further includes first and second metal-coated diffusion lines 341 and 343 extending in the Y direction and contacting the first common active region 322 but not the second common active region 324. The device 321 also includes third and fourth metal-coated diffusion lines 345 and 347 extending in the Y direction and contacting the second common active region 324 but not the second common active region 322. A fifth metal-coated diffusion layer 346 corresponds to... Figure 18B The bit line shown (BL) m ).

[0115] Figure 19C A plan view of a semiconductor device 323 according to some embodiments is shown. The semiconductor device 323 includes a first common active region 322 and a second common active region 324 extending along the X direction. First and second gate lines 334, 336 extend along the Y direction and intersect both the first and second common active regions 322, 324. Third and fourth gate lines 327, 329 extend along the Y direction and intersect the first common active region 322 and the second common active region 324. The third and fourth gate lines 327, 329 can function as a PODE structure. The device 321 also includes first and second metal-covered diffusion lines 341, 343 extending along the Y direction and contacting the first common active region 322 but not the second common active region 324. The device 321 also includes third and fourth metal-covered diffusion lines 345, 347 extending along the Y direction and contacting the second common active region 324 but not the second common active region 322. Fifth and sixth metal-covered diffusion layers 349, 351 are located between the first and second gate lines 334, 336.

[0116] Figure 20 Draw Figures 19A to 19C Partial perspective views of devices 320 and 321 are shown in the figures. The devices include a substrate 356 and an isolation region 358 disposed on the substrate. First and second common active regions 322 and 324 are disposed on the substrate and protrude beyond the isolation region 358 in the Z direction. Figure 20Only the first common active region 322 is shown. First gate line 326, second gate line 328, fifth gate line 334, and sixth gate line 336 are shown intersecting the first common active region 322. Second gate line 328 is transparently shown to display area 360 and semiconductor layer 152. The first common active region 322 includes... Figure 18B The source and drain terminals of the word line transistors 302 and 306 and the select line transistors 310 and 312 of the first and second antifuse units 282 and 284 are shown.

[0117] An area of ​​360 is shown, wherein the gate dielectric material of the gate lines can transform from an antifuse structure to a fuse structure when a sufficient voltage is applied. A semiconductor layer 152 is schematically illustrated. In some embodiments, the semiconductor layer 152 extends through a cross-section between the gate lines in a first common active region. In an alternative embodiment, the semiconductor layer is located in the channel regions of the gate lines, but there is no semiconductor layer in the cross-section of the common active region between the channel regions, and the common active region comprises a source / drain structure epitaxially formed between the gate line channel regions without a semiconductor layer.

[0118] Figure 21A Illustrations of the edges according to some embodiments Figure 19A E'-E' and Figure 19B A partial cross-section of devices 320 and 321 in the X direction, E''-E''. Dashed box 362 surrounds and includes the channel region of the first gate line 326. Figure 13D The structure of the channel region is shown. The channel region of the second gate 328 also has... Figure 13D The structure of the channel region shown. Figure 13D The gate dielectric layer 116 is configured to function as an antifuse structure, which can be converted into a fuse structure by applying a sufficient voltage to the first and second gate lines 326, 328. Given that the antifuse structure can be concentrated or focused on a single layer of the first and second gate lines 326, 328, the current through the antifuse structure is easier to control compared to gate lines comprising multiple antifuse structures. The selected cell 329 has an area 327 in which the gate dielectric material of the gate line can be converted from an antifuse to a fuse structure when a sufficient voltage is applied. The unselected region 331 does not have a conversion region 327. The dashed box 364 surrounds and includes the channel region of the fifth gate line 334. Figure 13B The structure of the channel region is shown. The channel region of the sixth gate line 336 also has... Figure 13B The structure of the channel region shown. Figure 21A The array shown does not have an isolation structure.

[0119] The first, second, third, and fourth gate lines 326, 328, 330, and 332 can function as a PODE structure. By implementing PODE in the antifuse region, the overall cell area of ​​the semiconductor device can be reduced, and the total number of pins, such as compute word lines, select lines, and bit lines, can be reduced. By implementing gate lines including a focused antifuse structure, the breakdown point of the antifuse structure can be controlled to improve the variation of conduction cell current and reduce the occurrence of channel inversion.

[0120] Figure 21B The illustration shows, according to some embodiments, along the X direction in Figure 19A E'-E' and Figure 19B A partial cross-section of device 321 taken at E''-E''. The dashed box 364 surrounds the channel region of the fifth gate line 334 and includes... Figure 13B The channel region structure is shown. The sixth gate line also has... Figure 13B The channel region structure is shown. The dashed box 363 surrounds the channel region of the first gate line 326 and includes... Figure 21C The channel region structure is shown. The second gate line 328 also includes... Figure 21C The channel region structure is shown. Figure 21C The diagram illustrates the focused antifuse structure of the first and second gate lines 326, 328. A gate structure 114 is disposed around the upper semiconductor layer 152U. The gate structure 114 includes a gate dielectric layer 116, a work function layer 118, and a gate material 120. The gate dielectric layer 116 is located between the gate material 120 and the semiconductor layer 152U, and between the gate material 120 and the source / drain structure of the first common active region 322. The gate dielectric layer 116 is configured to function as an antifuse structure, converting to a fuse structure by applying a sufficient voltage to the first and second gate lines 326, 328. A second dielectric material 164 is disposed below the upper semiconductor layer 152U and between the semiconductor layer 152L below the upper semiconductor layer 152U. The second dielectric material is surrounded by the gate dielectric layer 116. Internal spacers 122 are formed on opposite sides of the gate material 120 and the second dielectric material 164 at different heights in the channel region. Given that the antifuse structure can be concentrated or focused at two heights of the first and second gate lines 326, 328, current control via the antifuse structure is easier to achieve compared to gate lines comprising more than two antifuse structures. Figure 21B In the selected cell 329, there is a region 327 in which the gate dielectric material of the gate line can be transformed from an antifuse to a fuse structure when a sufficient voltage is applied. The unselected region 331 does not have a transformation region 327. A dashed box 364 surrounds the channel region of the fifth gate line 334 and includes... Figure 13B The channel region structure is shown. The channel region of the sixth gate line 336 also has... Figure 13BThe channel region structure is shown.

[0121] The first, second, third, and fourth gate lines 326, 328, 330, and 332 can function as a PODE structure. By implementing the PODE structure in the antifuse region, the overall cell area of ​​the semiconductor device can be reduced, and the total number of pins, such as compute word lines, select lines, and bit lines, can be reduced. By implementing gate lines including a focused antifuse structure, the breakdown point of the antifuse structure can be controlled to improve the variation of conduction cell current and mitigate channel inversion.

[0122] Figure 22 and Figure 23 Drawing and Figure 21A The same structure, except for the number of semiconductor layers. Figure 21A different. Figure 22 The semiconductor layer 152 extending through the channel region and the first common active region has a stacking ratio of Figure 21A The semiconductor layer stack shown has one less semiconductor layer. Figure 23 The semiconductor layer 152 extending through the channel region and the first common active region has a stacking ratio of Figure 21A The semiconductor layer stack shown has one more semiconductor layer. Any embodiment of this invention may include a semiconductor layer stack having any useful number of semiconductor layers, such as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 layers, or any other useful number of semiconductor layers.

[0123] Figure 24 A flowchart illustrating a method for forming transistors and embedded insulating structures according to some embodiments is shown. Figures 25A to 25O A schematic cross-sectional view showing the structure of each stage of the semiconductor device manufacturing process. Figure 25M It is along Figure 25L The cross-sectional view of the C-C' line is shown. Transistor (e.g., Figure 25M-Figure 25O The transistors 440 and 442 shown can be word-line transistors or select-line transistors.

[0124] Reference Figure 24 and Figure 25AProcess P100 is performed to form a semiconductor layer 402, a sacrificial layer 404, and a hard mask structure 406 on a substrate 400. Isolation regions, such as those formed by an STI process and comprising one or more insulating materials, may be provided on the substrate surface. For simplicity, the isolation regions are omitted. The substrate 400 may be a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. The semiconductor layer 402 and the sacrificial layer 404 are alternately formed on the substrate 400 to form a stacked structure on the substrate 400. In some embodiments, the semiconductor layer 402 and the sacrificial layer 404 are made of different semiconductor materials, such that the semiconductor layer 402 has sufficient etch selectivity relative to the sacrificial layer 404. For example, the semiconductor layer 402 is made of silicon, while the sacrificial layer 404 is made of silicon-germanium. Furthermore, the method of forming the semiconductor layer 402 and the sacrificial layer 404 may include one or more deposition processes, such as epitaxial processes. On the other hand, the hard mask structure 406 is formed on the stacked structure. In some embodiments, the hard mask structure 406 is aligned along the Y direction and extends along the X direction. Furthermore, in some embodiments, each rigid mask structure 406 includes a rigid mask layer 406a and a rigid mask layer 406b formed on the rigid mask layer 406a. The rigid mask layers 406a and 406b may be made of different insulating materials. For example, the materials of the rigid mask layers 406a and 406b may be selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, etc. The method of forming the rigid mask structure 406 may include one or more deposition processes (e.g., chemical vapor deposition (CVD) processes) and self-aligned multiple patterning processes (e.g., self-aligned double patterning (SADP) processes or self-aligned quadruple patterning (SAQP) processes).

[0125] Reference Figure 24 and Figure 25B In some embodiments, process P102 is performed, using a hard mask structure 406 as a mask to pattern the semiconductor layer 402 and the sacrificial layer 404 into a stacked structure 408 to form a stacked structure of semiconductor layer 402 and sacrificial layer 404. In those embodiments where the hard mask structure 406 is aligned in the Y direction and extends in the X direction, the formed stacked structure 408 is also aligned in the Y direction and extends in the X direction. The method of patterning the stacked structure to form the stacked structure 408 may include an etching process, such as anisotropic etching. The etching process may be stopped when the top surface of the substrate 400 is exposed, or the top of the substrate may be removed during the etching process. In some forms, depositing the stacked structure includes depositing layers and etching the layers into a stacked structure. In some embodiments, the hard mask layer 406b of the hard mask structure 406 is removed during the etching process.

[0126] Reference Figure 24 and Figure 25CIn some embodiments, process P104 is performed to form a sacrificial gate structure 410 on substrate 400. The extension direction of the sacrificial gate structure 410 intersects the extension direction of the stacked structure 408, and the sacrificial gate structure 410 covers a portion of the stacked structure 408 that overlaps with the sacrificial gate structure 410. In those embodiments where the stacked structure 408 is aligned in the Y direction and extends in the X direction, the sacrificial gate structure 410 is aligned in the X direction and extends in the Y direction. In some embodiments, each sacrificial gate structure 410 includes a sacrificial gate dielectric layer 412 and a sacrificial gate electrode 414. The sacrificial gate dielectric layer 412 is conformally formed on substrate 400 and stacked structure 408, while the sacrificial gate electrode 414 covers the sacrificial gate dielectric layer 412 and is formed with a height greater than the height of the stacked structure 408. In some embodiments, each sacrificial gate structure 410 also includes a housing structure 416 located on the sacrificial gate electrode 414. The housing structure 416 may include a capping layer 416a and a capping layer 416b located above the capping layer 416a. In some embodiments, the capping layer 416b has rounded apex corners. The materials of the sacrificial gate dielectric layer 412, capping layer 416a, and capping layer 416b may respectively include silicon dioxide, silicon nitride, silicon oxynitride, the like, or combinations thereof, while the material of the sacrificial gate electrode 414 may include polysilicon. Furthermore, the methods for forming the sacrificial gate dielectric layer 412, capping layers 416a, 416b, and sacrificial gate electrode 414 may each include deposition processes, such as CVD or atomic layer deposition.

[0127] Reference Figure 24 and Figure 25D In some embodiments, process P106 is performed to form a gate spacer layer 418. In some embodiments, the gate spacer layer 418 is globally formed on, for example, Figure 25D In the structure shown, substrate 400, stacked structure 408, and sacrificial gate structure 410 may be conformally covered by gate spacer layer 418. The material of gate spacer layer 418 may include silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide oxycarbide, SiOCN, the like, or combinations thereof, and the method of forming gate spacer layer 418 may include a deposition process, such as a CVD process or an atomic layer deposition process.

[0128] Reference Figure 24 and Figure 25EIn some embodiments, process P108 is initiated to replace portions of the stacked structure between the sacrificial gates with a common active region. Portions of the stacked structure 408 and the gate spacer layer 418 are removed. In some embodiments, the portion of the gate spacer layer 418 covering the sidewalls of the sacrificial gate structure 410 becomes the gate spacer 420. Alternatively, other portions of the gate spacer layer 418 are removed, accordingly exposing portions of the stacked structure 408 not covered by the sacrificial gate structure 410 and the gate spacer 420. Subsequently, the exposed portions of the stacked structure 408 are removed, while the portions of the stacked structure 408 covered by the gate spacer 420 and the sacrificial gate structure 410 are retained. Figure 25F In another embodiment shown, portions of the stacked structure 408 not covered by the sacrificial gate structure 410 are selectively etched to remove the sacrificial layer 404, while the semiconductor layer 402 outside and beneath the sacrificial gate structure 410 is retained. In some embodiments, the method of removing selected portions or all of the stacked structure 408 not covered by the sacrificial gate structure 410 and removing the gate spacer layer 418 may include one or more etching processes, such as one or more anisotropic etching processes. Furthermore, the etching process may selectively remove the sacrificial layer 404 while retaining the semiconductor layer 402. The etching process may be stopped when the top surface of the substrate 400 is exposed, or the top portion of the substrate 400 may be removed during the etching process.

[0129] Reference Figure 24 and Figure 25G The sacrificial layer 404 is laterally etched from the semiconductor layer 402 and the gate spacer 420. Therefore, a recess 424 is formed on the sidewalls of the remaining portion of the stacked structure 408. In some embodiments, the distance by which the sacrificial layer 404 is laterally etched from the semiconductor layer 402 and the gate spacer 420 ranges from 0.5 nm to 1 nm. Methods for laterally etching the sacrificial layer 404 may include etching processes, such as isotropic etching processes. By appropriately selecting the etchant for the etching process and / or appropriately selecting the materials of the sacrificial layer 404 and the semiconductor layer 402, the sacrificial layer 404 can be etched without consuming the semiconductor layer 402 and other components in the current structure. Similarly, Figure 25F The structure shown can be processed to, for example Figure 25G The method shown involves laterally etching the sacrificial layer 404 beneath the sacrificial gate structure 410 without removing the semiconductor layers 402 covered and uncovered by the sacrificial gate structure 410.

[0130] Reference Figure 24 and Figure 25HAn insulating material is filled in the recesses 424 of the sidewalls of the stacked structure 408. The portion of the insulating material filled in the recesses 424 forms an internal spacer 428. In some embodiments, the exposed surface of the internal spacer 428 is substantially coplanar with the exposed surface of the semiconductor layer 402 and the sidewalls of the gate spacer 420. In an alternative embodiment, the exposed surface of the internal spacer 428 is recessed from the exposed surface of the semiconductor layer 402 and the sidewalls of the gate spacer 420. The insulating material used to form the internal spacer 428 may include silicon dioxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbon oxynitride, or other suitable dielectric materials or combinations thereof. A method of forming the internal spacer 428 may include first forming a full coverage layer. Figure 25G The material layer of the structure shown is then removed, and the portion of the cover layer outside the recess 424 is removed. The remaining portion of the insulating material layer forms the internal spacers 428. In some embodiments, the material layer is formed using a deposition process (e.g., a CVD process or an ALD process), and portions of the material layer are removed using an etching process (e.g., an anisotropic etching process).

[0131] Reference Figure 24 and Figure 25I Process P108 continues, and source / drain structures 430 are formed on substrate 400 to form a common active region extending between sacrificial gate structures 410. The sacrificial gate structures 410 are located between the source / drain structures 430 and separated from them by gate spacers 418. Furthermore, the semiconductor layer 402 and internal spacers 428 covering each sacrificial gate structure 410 are in lateral contact with a pair of source / drain structures 430. Similarly, Figure 25F The illustrated structure can be further processed to form a source / drain structure 430 around the semiconductor layer not covered by the sacrificial gate structure 410. The material of the source / drain structure 430 may include silicon, silicon germanium, silicon carbide, or similar materials. In some embodiments, the source / drain structure 430 is formed by an epitaxial process. In these embodiments, the source / drain structure 430 may be grown from exposed portions of the semiconductor layer 402 and the substrate 400. Although the source / drain structure 430 is depicted as a rectangular cuboid, it can be formed in other shapes, and the present invention is not limited to the illustrated shape of the source / drain structure 430.

[0132] Reference Figure 24 and Figure 25J In some embodiments, process P110 begins by removing the sacrificial gate structure 410. A dielectric layer 432 is formed on the source / drain structure 430. In some embodiments, the dielectric layer 432 initially covers... Figure 25IThe entire structure shown can then undergo a planarization process to remove the top portion of dielectric layer 432 and expose sacrificial gate structure 410. In some cases, the top portion of sacrificial gate structure 410 may also be removed during the planarization process. For example, the planarization process may include a chemical mechanical polishing process, an etching process, or a combination thereof. After the sacrificial gate structure 410 is exposed, the remaining portion of the sacrificial gate structure 410 is removed, forming cavities defined between adjacent gate spacers 420, respectively. The semiconductor layer 402 and sacrificial layer 404, previously covered by the sacrificial gate structure 410, are now exposed in the cavities. The material of dielectric layer 432 may include tetraethyl orthosilicate oxide, undoped silicate glass or silicon-doped oxide (e.g., borosilicate glass, fused silica glass, phosphosilicate glass, borosilicate glass), other suitable dielectric materials, or combinations thereof. The method of forming dielectric layer 432 may include a deposition process, such as a CVD process. Alternatively, the sacrificial gate structure 410 may be removed by an etching process (e.g., an isotropic etching process).

[0133] In some embodiments, prior to the formation of dielectric layer 432, Figure 25I A contact etch stop layer (CESL) (not shown) is formed on the structure shown. Initially, the CESL layer conformally covers the source / drain structure 430 and the sacrificial gate structure 410. Subsequently, the top portion of the CESL layer covering the sacrificial gate structure 410 may be removed along with the top portion of the dielectric layer 432 during a planarization process. The material of the CESL layer may include silicon nitride, silicon oxynitride, silicon nitride containing oxygen or carbon, the like, or combinations thereof, and the method of forming the CESL layer may include a deposition process, such as a CVD process or an ALD process.

[0134] Reference Figure 24 and Figure 25K Process P110 continues to remove the sacrificial layer 404. Therefore, the semiconductor layer 402 is released in the cavities defined between adjacent gate spacers 420. The released semiconductor layer 402 can function as a channel structure. Furthermore, the inner sidewalls of the internal spacers 428 previously covered by the sacrificial layer 404 are now exposed in the cavities. In some embodiments, the method of removing the sacrificial layer 404 includes an etching process, such as an isotropic etching process. By appropriately selecting the etchant for the etching process and / or appropriately selecting the materials of the sacrificial layer 404 and the semiconductor layer 402, the sacrificial layer 404 can be etched without removing the semiconductor layer 402 and other components in the current structure.

[0135] Reference Figure 24 , Figure 25L and Figure 25MIn some embodiments, process P112 for forming the gate dielectric layer and process P114 for forming the gate line of transistor 440 are performed. The gate dielectric gate layer 424 and the gate line including gate material 436 are formed in cavities defined between adjacent gate spacers 420. The previously shown sacrificial gate structure 410 can be considered as being replaced by gate structure 438. Figure 25L and Figure 25M As shown, the gate dielectric layer 434 covers the semiconductor layer 402, the substrate 400, the internal spacer 428, and the exposed surfaces of the gate spacer 420 within cavities defined between adjacent gate spacers 420. The gate material 436 of the gate electrode fills the spaces in these cavities. The material of the gate dielectric layer 434 may include a high-k dielectric material. Examples of high-k dielectric materials may include HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate material 436 may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. Furthermore, the method for forming the gate dielectric layer 434 may include a deposition process, such as a CVD process or an ALD process. The method for forming the gate material 436 of the gate electrode may include a deposition process (e.g., a CVD process or an ALD process), an electroplating process (e.g., an electroplating process or an electroless process), or a combination thereof.

[0136] In some embodiments, one or more work function layers are formed between each gate dielectric layer 432 and the gate electrode 436 (e.g., see reference). Figure 13B The work function layer 118 is described. Furthermore, in some embodiments, an interface layer (not shown) is formed on the exposed surface of the semiconductor layer 402 prior to the formation of the gate dielectric layer 434. The transistor 440 includes a gate structure 438, a semiconductor layer 402 within this gate structure 438, and a pair of source / drain structures 430 on either side of this gate structure 438.

[0137] Reference Figure 24 and Figure 25NThe process P112, which forms the gate dielectric layer, and P114, which forms the focused antifuse gate line of the focused antifuse transistor 442, are performed. A gate dielectric layer 434 is formed in the cavities corresponding to transistors 440 and 442. A sacrificial material (not shown) is deposited into the cavity corresponding to transistor 440, and then a second dielectric material 444 is deposited into the cavity corresponding to focused antifuse transistor 442. In one embodiment, the second dielectric material 444 is deposited to a specific height in the cavity, exposing one or more upper semiconductor layers 402U. In another embodiment, the second dielectric material fills the cavity, the structure is then masked, and photolithography and etching processes are performed to form openings and remove excess second dielectric material to expose one or more upper semiconductor layers 402. The sacrificial material is removed from the cavity corresponding to transistor 440, and then gate material 436 and optional work function material are deposited in the cavity corresponding to transistor 440 and on the upper semiconductor layer 402U deposited in the cavity corresponding to focused antifuse transistor 442.

[0138] Reference Figure 24 and Figure 25O In some embodiments, process P116 for forming an isolation structure is performed. A gate dielectric layer 434 is formed in a cavity corresponding to transistor 440 and which will become a plurality of dielectric sacrificial gate lines 444. A sacrificial material (not shown) is deposited into the cavity corresponding to transistor 440, and then a second dielectric material 444 is deposited into the cavity corresponding to the plurality of dielectric sacrificial gate lines 444. The second dielectric material may be deposited to a specific height in the cavity while keeping one or more upper semiconductor layers 402U exposed, or excess dielectric material may be selectively removed to expose one or more upper semiconductor layers 402. A first dielectric material 446 is then deposited on the upper semiconductor layer 402U in the cavity corresponding to the plurality of dielectric sacrificial gate lines 444. The sacrificial material is removed from the cavity corresponding to transistor 440, and then gate material 436 and optional work function material are deposited in the cavity corresponding to transistor 440.

[0139] The first and second dielectric materials 446 and 444 may independently comprise one or more selected from hafnium oxide, zirconium oxide, aluminum oxide, aluminum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like. The first and second dielectric materials 446 and 444 may be the same or different. Furthermore, the methods for depositing the first and second dielectric materials 446 and 444 may be the same or different and may include deposition processes such as CVD or ALD processes.

[0140] By implementing an isolation region that includes any CPODE and a sacrificial gate, the overall cell area of ​​the semiconductor device can be reduced, and the total number of pins, such as those including word lines, select lines, and bit lines, can be reduced. By implementing sacrificial gate lines and gate lines that include focused antifuse structures, the breakdown point of the antifuse structure can be controlled to improve the variability of the on-cell current.

[0141] According to one embodiment, a method of manufacturing a semiconductor device includes depositing a first stacked structure and a second stacked structure on a substrate. The first and second stacked structures extend in a first direction and include semiconductor layers and sacrificial layers alternately stacked on the substrate. The method further includes depositing a plurality of sacrificial gates on the substrate. The sacrificial gates extend in a second direction intersecting the first direction and cover the first and second stacked structures. The method further includes replacing portions of the first stacked structure between the sacrificial gates with a first active region. The method further includes replacing portions of the second stacked structure between the sacrificial gates with a second active region. The method further includes etching the plurality of sacrificial gates and a sacrificial layer located beneath the sacrificial gates to expose channel regions of the first and second stacked structures. The method further includes depositing a gate dielectric material around the semiconductor layers exposed in the channel regions of the first and second stacked structures. The method further includes forming a first gate line extending in a second direction, the first gate line intersecting with a channel region of the first stacked structure channel region and intersecting with a channel region of the second stacked structure channel region. The method further includes forming a second gate line extending in a second direction, the second gate line intersecting with a channel region of the first stacked structure channel region and intersecting with a channel region of the second stacked structure channel region. The method further includes forming a third gate line extending in a second direction between the first and second gate lines, the third gate line intersecting a channel region of the first stacked structure channel region but not intersecting any channel region of the second stacked structure. The method further includes forming a fourth gate line extending in a second direction between the third and second gate lines, the fourth gate line intersecting a channel region of the first stacked structure channel region but not intersecting any channel region of the second stacked structure. The method further includes forming a fifth gate line between the first and second gate lines, aligned with the third gate line in a second direction, the fifth gate line intersecting a channel region of the second stacked structure channel region but not intersecting any channel region of the first stacked structure. The method further includes forming a sixth gate line between the second and fifth gate lines, aligned with the fourth gate line in a second direction, the sixth gate line intersecting a channel region of the second stacked structure channel region but not intersecting any channel region of the first stacked structure. The method further includes forming a first isolation structure extending in a second direction between the third and fourth gate lines and between the fifth and sixth gate lines. In one embodiment, forming the first isolation structure includes forming a groove in a substrate and filling the groove with a dielectric material. In one embodiment, forming the first isolation structure includes forming a first dielectric material around a semiconductor layer in a channel region of a first stacked structure channel region, with a gate dielectric material located between the first dielectric material and the semiconductor layer.In one embodiment, forming the first, second, third, and fourth gate lines includes depositing gate material around a semiconductor layer in a channel region that intersects the first, second, third, and fourth gate lines, respectively, wherein the gate material and the gate dielectric material between the semiconductor layer are configured to function as an antifuse structure. In one embodiment, forming a first isolation structure includes forming a first dielectric material around a semiconductor layer below an upper semiconductor layer in a channel region of a first stacked structure channel region where the first isolation structures intersect, and forming a second dielectric layer on the upper semiconductor layer of the channel region where the first isolation structures intersect. Forming a third gate line includes forming a first dielectric material around a semiconductor layer below an upper semiconductor layer in a channel region of a first stacked structure where the third gate line intersects, and forming a gate material on the upper semiconductor layer of the channel region of the first stacked structure where the third gate line intersects. Forming a fourth gate line includes forming a first dielectric material around a semiconductor layer below an upper semiconductor layer in a channel region of a first stacked structure where the fourth gate line intersects, and forming a gate material on the upper semiconductor layer of the channel region of the first stacked structure where the fourth gate line intersects. The gate dielectric material between the upper semiconductor layer and the gate material in the channel region of the first stacked structure where the third and fourth gate lines intersect functions as an antifuse structure. In one embodiment, the method further includes forming a seventh gate line extending in a second direction and intersecting with a channel region of the first stacked structure channel region and a channel region of the second stacked structure channel region, and forming an eighth gate line extending in a second direction and intersecting with a channel region of the first stacked structure channel region and a channel region of the second stacked structure channel region, wherein the first and second gate lines are located between the seventh and eighth gate lines. In one embodiment, the method further includes forming a second isolation structure extending in a second direction and intersecting with the first and second active regions near the first gate line; and forming a third isolation structure extending in a second direction and intersecting with the first and second active regions near the second gate line. In one embodiment, the method further includes forming a second isolation structure extending in a second direction and intersecting with the first and second active regions near the seventh gate line; and forming a third isolation structure extending in a second direction and intersecting with the first and second active regions near the eighth gate line. In one embodiment, replacing the first and second stacked structure portions between the sacrificial gates with the first and second active regions respectively includes removing the sacrificial layer between the sacrificial gates and forming a source / drain structure around the semiconductor layer between the sacrificial gates.

[0142] According to another embodiment, a method of manufacturing a semiconductor device includes depositing a first stacked structure and a second stacked structure on a substrate, the first and second stacked structures extending in a first direction and including semiconductor layers and sacrificial layers alternately stacked on the substrate. The method further includes depositing a plurality of sacrificial gates on the substrate, the sacrificial gates extending in a second direction intersecting the first direction and covering the first and second stacked structures. The method further includes replacing portions of the first stacked structure between the sacrificial gates with a first active region. The method further includes replacing portions of the second stacked structure between the sacrificial gates with a second active region. The method further includes etching a plurality of sacrificial gates and a sacrificial layer located beneath selected sacrificial gates to expose channel regions of the first and second stacked structures. The method further includes depositing a gate dielectric material around the semiconductor layers exposed in the channel regions of the first and second stacked structures. The method further includes forming a first gate line extending in the second direction, the first gate line intersecting with one channel region of the channel region of the first stacked structure but not intersecting with any channel region of the second stacked structure. The method further includes forming a second gate line extending in the second direction, the second gate line intersecting with one channel region of the channel region of the first stacked structure but not intersecting with any channel region of the second stacked structure. The method further includes forming a third gate line extending in a second direction aligned with and intersecting the first gate line, the third gate line intersecting a channel region of the second stacked structure channel region but not intersecting any channel region of the first stacked structure. The method further includes forming a fourth gate line extending in a second direction aligned with and intersecting the fourth gate line, the fourth gate line intersecting a channel region of the second stacked structure channel region but not intersecting any channel region of the first stacked structure. The method further includes forming a fifth gate line extending in the second direction, the fifth gate line intersecting a channel region of the first stacked structure channel region between the first and second gate lines, and intersecting a channel region of the second stacked structure channel region between the third and fourth gate lines. The method further includes forming a sixth gate line extending in the second direction, the sixth gate line intersecting a channel region of the first stacked structure channel region between the fifth and second gate lines, and intersecting a channel region of the second stacked structure channel region between the fifth and fourth gate lines.In one embodiment, forming a first gate line includes forming a first dielectric material around a semiconductor layer below an upper semiconductor layer in a first stacked structure channel region where the first gate lines intersect, and forming a gate material on the upper semiconductor layer in the first stacked structure channel region where the first gate lines intersect. Forming a second gate line includes forming a first dielectric material around a semiconductor layer below an upper semiconductor layer in a first stacked structure channel region where the second gate lines intersect, and forming a gate material on the upper semiconductor layer in the first stacked structure channel region where the second gate lines intersect. Forming third and fourth gate lines includes forming gate materials around semiconductor layers in the first stacked structure channel regions where the third and fourth gate lines intersect, wherein the gate dielectric material is configured to function as an antifuse structure between the upper semiconductor layers of the first and second gate line intersecting channel regions and the gate material formed on the upper semiconductor layers of these channel regions. In one embodiment, the first stacked structure channel region where the first, second, third, and fourth gate structures intersect has two semiconductor layers. In one embodiment, the first stacked structure channel region where the first, second, third, and fourth gate structures intersect has three semiconductor layers. In one embodiment, the first stacked structure channel region where the first, second, third, and fourth gate structures intersect has four semiconductor layers.

[0143] According to another embodiment, the semiconductor device includes a substrate; an active region disposed above the substrate and extending in a first direction. The device also includes an isolation region disposed above the substrate, with the active region protruding above the isolation region. The device further includes a plurality of gate lines extending in a second direction intersecting the first direction and intersecting with respective channel regions comprising a stack of semiconductor layers aligned with the active region. At least two of the plurality of gate lines include a gate material and a dielectric material, the gate material being disposed above an upper semiconductor layer in the channel region where the at least two gate lines intersect, and the dielectric material being disposed below the upper semiconductor layer and between semiconductor layers below the upper semiconductor layer in the channel region where the at least two gate lines intersect. At least one of the plurality of gate lines includes a gate material surrounding a semiconductor layer in the channel region where the at least two gate lines intersect. The device also includes a gate dielectric layer disposed between the gate material and the upper semiconductor layers of the at least two gate lines, the gate dielectric layer being configured to function as an antifuse structure. In one embodiment, a semiconductor layer extends from the channel region through the active region in the first direction, and a source / drain structure surrounds the semiconductor layer in the active region. In one embodiment, the active region comprises either an n-type material or a p-type material, and the substrate comprises either an n-type material or a p-type material. In one embodiment, the device further includes a plurality of metal-covered diffusion lines extending in a second direction and contacting the active region between the gate lines. In one embodiment, the semiconductor layer stack comprises four semiconductor layers. In one embodiment, the active region comprises either an n-type material or a p-type material, and the substrate comprises either an n-type material or a p-type material.

[0144] The foregoing has outlined the features of several embodiments or examples to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that this invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this invention, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this invention.

Claims

1. A semiconductor device, characterized in that, include: substrate; An active region disposed above the substrate and extending along a first direction; An isolation region is disposed above the substrate, and the active region protrudes above the isolation region; Multiple gate lines extend along a second direction intersecting the first direction and intersect with respective channel regions comprising semiconductor layer stacks aligned with the active region; At least two of the plurality of gate lines include: a gate material and a dielectric material, wherein the gate material is disposed above an upper semiconductor layer in the channel region where the at least two gate lines intersect, and the dielectric material is located below the upper semiconductor layer and between a semiconductor layer below the upper semiconductor layer in the channel region where the at least two gate lines intersect; At least one of the plurality of gate lines includes: the gate material; a semiconductor layer surrounding a channel region of the channel region where the at least one gate line intersects; and A gate dielectric layer disposed between the gate material and the upper semiconductor layer of the at least two gate lines, the gate dielectric layer being configured to function as an antifuse structure.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor layer extends from the channel region through the active region along the first direction, and the source / drain structure surrounds the semiconductor layer in the active region.

3. The semiconductor device according to claim 1, characterized in that, The active region includes either an n-type material or a p-type material, and the substrate includes either the n-type material or the p-type material.

4. The semiconductor device according to claim 1, characterized in that, It also includes a plurality of metal-covered diffusion lines that extend along the second direction and contact the active region between the gate lines.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor layer stack includes four semiconductor layers.

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