Integrated circuit device

Abstract

The utility model provides a kind of integrated circuit device, it includes: substrate;Multiple dielectric layers are set on substrate;And capacitor structure, including multiple first capacitor parts, each of first capacitor part includes: first conductive component, extends through dielectric layer;Dielectric component, extends through dielectric layer and is aligned along first conductive component;And second conductive component, extends through dielectric layer and is aligned along dielectric component;Wherein at least one of dielectric layer includes first dielectric layer, first dielectric layer extends laterally between multiple first adjacent pairs of first capacitor part, wherein multiple first capacitor parts in each of first adjacent pair of first capacitor part are spaced apart from each other with less than first length, wherein first dielectric layer includes the side wall of gap defined between each pair of multiple second adjacent pairs of first capacitor part, wherein the length of gap is greater than or equal to first length.

Description

Technical Field

[0001] This utility model relates to an integrated circuit device. Background Technology

[0002] One area of ​​interest in integrated circuit (IC) technology is the improvement of capacitors used within IC devices (e.g., in terms of density, footprint, etc.). One advancement in this area is the three-dimensional (3D) metal-insulator-metal (MIM) capacitor, which achieves a capacitor with a high conductor surface area relative to the volume consumed within the IC device. Utility Model Content

[0003] This invention provides an integrated circuit device comprising: a substrate; a plurality of dielectric layers disposed on the substrate; and a capacitor structure including a plurality of first capacitor portions, each of the plurality of first capacitor portions including: a first conductive component extending through the plurality of dielectric layers; a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component; and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component; wherein at least one of the plurality of dielectric layers includes a first dielectric layer extending laterally between a plurality of first adjacent pairs of the plurality of first capacitor portions, wherein the plurality of first capacitor portions in each of the plurality of first adjacent pairs of the plurality of first capacitor portions are spaced apart from each other by a length less than a first length, wherein the first dielectric layer includes a sidewall defining a gap between each of a plurality of second adjacent pairs of the plurality of first capacitor portions, wherein the length of the gap is greater than or equal to the first length.

[0004] This invention provides an integrated circuit device comprising: a substrate; a plurality of dielectric layers disposed on the substrate; and a capacitor structure including a plurality of first capacitor portions, each of the plurality of first capacitor portions comprising: a first conductive component extending through the plurality of dielectric layers; a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component; and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component; wherein, in a plan view of the integrated circuit device, the plurality of first capacitor portions are arranged in a two-dimensional array; wherein at least one of the plurality of dielectric layers bridges each adjacent pair of the plurality of first capacitor portions aligned along rows or columns of the two-dimensional array; and wherein the at least one of the plurality of dielectric layers includes a gap between each adjacent pair of the plurality of first capacitor portions.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] The various aspects of the embodiments of this utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A A schematic side view is shown during the manufacture of a single-side MIM capacitor structure according to some embodiments of the present invention.

[0008] Figure 1B A schematic side view is shown during the manufacture of a double-side MIM capacitor structure according to some embodiments of the present invention.

[0009] Figure 2A A schematic plan view of the manufacturing process of a mechanically stable double-sided three-dimensional (3D) MIM capacitor structure according to some embodiments of the present invention is shown.

[0010] Figure 2B , Figure 2C and Figure 2D Plan view, orthogonal side view and diagonal side view of a mechanically stable double-sided 3DMIM capacitor structure according to some embodiments of the present invention are shown respectively.

[0011] Figures 3 to 9 , Figure 10A and Figure 10B , Figure 11A and Figure 11B , Figure 12A , Figure 12B and Figure 12C , Figure 13A and Figure 13B , Figure 14A and Figure 14B as well as Figure 15A and Figure 15B Various side views are shown at various manufacturing stages of an IC device including a mechanically stable double-sided 3D MIM capacitor structure, according to some embodiments of the present invention.

[0012] Figure 16 , Figure 17A and Figure 17B as well as Figure 18A and Figure 18BVarious side views are shown at different stages of the manufacturing process of an IC device including a mechanically stable double-sided 3D MIM capacitor structure, according to an additional embodiment of the present invention.

[0013] Figure 19 A method for forming an IC device including a mechanically stable double-sided 3D MIM capacitor structure according to some embodiments of the present invention is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components, values, operations, materials, arrangements, or similar elements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or similar elements are contemplated. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, the present invention may reuse reference numerals and / or letters in various instances. Such reuse is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0016] Figure 1AA schematic side view is shown during the fabrication of a single-sided MIM capacitor structure 100A according to some embodiments of the present invention. As shown, multiple trenches 106 may be disposed in a base substrate 101 (e.g., a dielectric layer, substrate, or the like). Along the upper surface of a layer or structure within an IC device, the trenches 106 may carry a first conductive component 102A, a dielectric component (e.g., an insulating component) 104, and a second conductive component 102B, which may respectively serve as a metal layer, an insulating layer, and a metal layer of the IC device. Furthermore, the MIM capacitor structure 100A using the first conductive component 102A, the insulating component 104, and the second conductive component 102B may include a horizontal body 107 and multiple columns 108 extending downward from the horizontal body 107. In this arrangement, from a mechanical point of view, all portions of the MIM capacitor structure 100A tend to be stable because each portion of the MIM capacitor structure 100A is fully supported during IC fabrication.

[0017] Figure 1B A schematic side view is shown during the manufacture of a dual-sided MIM capacitor structure 100B according to some embodiments of the present invention. In this configuration, the first conductive component 102A may be formed as a plurality of upward-directed segments, and the insulating component 104 and the second conductive component 102B may be disposed above these segments to form the MIM capacitor structure 100B. In this arrangement, the upward-directed segments may be narrower and positioned closer than the trench 106 of the MIM capacitor structure 100A, thus potentially providing a larger area for the first conductive component 102A, the dielectric component 104, and the second conductive component 102B, thereby generating a higher potential capacitance value.

[0018] However, in this particular configuration, providing mechanical support for the upward-pointing segment (e.g., a portion of the first conductive component 102A) during the manufacture of the IC device may not be optimal, potentially leading to reduced device yield and increased device manufacturing costs.

[0019] To address these issues, this invention provides embodiments of an IC device and related manufacturing methods relating to a mechanically stable double-sided MIM capacitor structure. In some embodiments, the IC device may include a plurality of dielectric layers disposed above a substrate and a capacitor structure comprising a plurality of capacitor portions. Each capacitor portion may include a first conductive component extending through the plurality of dielectric layers, a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component, and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component. At least one dielectric layer may laterally span or bridge the linear distance between each pair of adjacent capacitor portions, wherein each pair of adjacent capacitor portions is separated by an interval less than a certain length. Conversely, at least one dielectric layer may not laterally span or bridge the linear distance between each pair of adjacent capacitor portions, wherein each pair of adjacent capacitor portions is separated by an interval greater than or equal to the certain length.

[0020] Therefore, the use of some embodiments of the method can provide a physical feature (e.g., at least one of the dielectric layers described above) that provides mechanical stability to the capacitor structure by bridging the linear distance between each adjacent pair, particularly during the manufacture of the IC device. Furthermore, in some embodiments, since at least one of the dielectric layers does not span between other adjacent pairs of capacitor portions, it is possible to contact the lower layer of the IC device beneath at least one of the dielectric layers to provide material for one or more additional capacitor portions in addition to the plurality of first capacitor portions, thereby creating a double-sided MIM capacitor structure.

[0021] Figure 2A A plan view is shown illustrating the manufacturing process of the mechanically stable double-sided three-dimensional (3D) MIM capacitor structure according to the present invention. In some embodiments, as described above... Figure 1B The first conductive component 102A discussed, combined with the first (bottom) electrode 202 (also referred to as the first electrode), can be configured as a plurality of first capacitor portions 220 that may include multiple vertically oriented portions (e.g., cylinders). Also as Figure 2A As shown, a portion of the first conductive component 102A can form part of a protective ring 222, which can provide structural and / or electrical isolation for the resulting 3D MIM capacitor structure.

[0022] To provide stability for the first conductive component 102A in subsequent processing, such as the addition of the insulating component 104 and the second conductive component 102B, multiple structural elements 242 may be laterally connected or span adjacent first capacitor portions 220 and / or laterally connected or span one or more first capacitor portions 220 to a portion of the guard ring 222. In some embodiments, the structural element 242 may be formed of a structural dielectric layer 206 (or dielectric layer, first (structural) dielectric layer, first dielectric layer) (e.g., an etch stop layer). More specifically, in some embodiments, the structural dielectric layer 206 may be laterally connected or span adjacent first capacitor portions 220 separated by a gap of less than a certain length (e.g., a first length 252 less than the certain length). Furthermore, in some embodiments, the structural dielectric layer 206 may include sidewalls defining gaps between some adjacent first capacitor portions 220, wherein the length of the gap is greater than or equal to the certain length (e.g., a second length 254 greater than or equal to the certain length). Figure 2A In some embodiments related to the plan view, the first capacitor portions 220 are arranged as a two-dimensional array, the structural dielectric layer 206 may join or span the first capacitor portions 220 along the rows and pillars of the array, and the structural dielectric layer 206 may define the gaps between the first capacitor portions 220 along the diagonal of the array.

[0023] Figure 2B , Figure 2C and Figure 2D The figures show a plan view, an orthogonal side view, and a diagonal side view of the mechanically stable double-sided 3D MIM capacitor structure 200 according to the present invention. As shown in the figures, Figure 2A This is a plan view of the capacitor structure 200 at a specific structural dielectric layer 206, which selectively spans the distance between pairs of first capacitor portions 220. In some embodiments, each first capacitor portion 220 may include a cylindrical structure in a circular shape, such as... Figure 2B As shown in the plan view. Further, each first capacitor portion 220 may include a cylindrical first conductive component 102A; a dielectric (e.g., insulating) component 104, which is cylindrical and coaxially aligned and in contact with the first conductive component 102A; and a second conductive component 102B, which is cylindrical, coaxially aligned and in contact with the dielectric component 104.

[0024] In some embodiments, such as Figure 2B As shown, the structural dielectric layer 206 laterally spans a linear distance (e.g., along) between adjacent first capacitor portions 220 spaced apart by a predetermined length. Figure 2C(orthogonal cross-sectional view), but does not laterally cross the linear distance between adjacent first capacitor portions 220 spaced apart by a predetermined length greater than or equal to a certain length (e.g., along) Figure 2D (Diagonal cross-section diagram).

[0025] Furthermore, in some embodiments, such as Figure 2B As depicted in the plan view, the first capacitor section 220 can be arranged as a two-dimensional rectangular array with rows and columns. Figure 2B In a specific case, the first capacitor portion 220 is arranged in a 3×3 array. However, arrays of other sizes and configurations can be used in other embodiments (e.g., 1×2, 2×1, 2×2, 2×3, 3×2, 4×4, etc.). Therefore, in the rows or columns of the two-dimensional array (e.g., along...), Figure 2C In the cross-sectional view, adjacent first capacitor portions 220 are separated by a relatively short distance (e.g., less than a predetermined length), and therefore said distance is traversed by the structural dielectric layer 206. Otherwise, they are not separated along one of the rows or pillars of the two-dimensional array (e.g., along the diagonal of the two-dimensional array, such as...). Figure 2D (Cross-sectional view) Adjacent first capacitor portions 220 aligned are separated by a relatively long distance (e.g., greater than or equal to a predetermined length).

[0026] The first capacitor section 220 is also shown. Figure 2C and Figure 2D A cross-sectional view. In some embodiments, the first capacitor portion 220 may be laterally separated by one or more second capacitor portions 221 comprising the first conductive component 102A, the dielectric component 104, and the second conductive component 102B to facilitate a dual-sided 3D MIM capacitor structure. As discussed in more detail below, the volumes between the first capacitor portions 220 used to form one or more second capacitor portions 221 may be contacted during manufacturing via one or more openings 224 in the structural dielectric layer 206 (e.g., as shown below). Figure 2B (As shown).

[0027] Furthermore, in some embodiments, such as Figure 2BAs shown in the optimal plan view, the first capacitor portion 220 and the second capacitor portion 221 can be laterally surrounded by a protective ring 222. In some embodiments, the protective ring 222 may include a core of a second conductive component 102B, which can be laterally surrounded by a dielectric component 104, which in turn can be laterally surrounded by a first conductive component 102A (e.g., in a manner similar to that of each first capacitor portion 220). In some embodiments, the protective ring 222 provides an electrical barrier between the capacitor structure 200 and surrounding electrical components that may be disposed in an IC device including the capacitor structure 200. Furthermore, in some embodiments, during manufacturing, the protective ring 222 may protect other circuitry surrounding the 3D MIM capacitor structure, for example, by confining solvents within the area of ​​the 3D MIM capacitor structure.

[0028] In some embodiments, such as Figure 2C and Figure 2D As shown in the cross-sectional view, a first (bottom) electrode 202 (e.g., comprising a metal or metal alloy (e.g., copper (Cu), another conductive metal or alloy, or another conductive material)) can be disposed above a dielectric layer 204, which in turn can be disposed above a substrate 201 (e.g., a semiconductor substrate comprising silicon (Si), another semiconductor material, or combinations thereof). In some embodiments, the first electrode 202 can be directly or indirectly connected to one or more first capacitor portions 220, second capacitor portions 221, and / or guard rings 222 to another electronic circuit or voltage reference of the IC device.

[0029] Furthermore, in some embodiments, the first capacitor portion 220, the second capacitor portion 221, and / or the guard ring 222 may be located within one or more dielectric layers 204, 206, and 208. In some embodiments, each of the dielectric layers 204, 206, and 208 may include one or more dielectric materials, including but not limited to silicon oxide (SiO2). x (e.g., silicon oxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, and the like. For example, in some embodiments, dielectric layer 204 may include silicon oxide, dielectric layer 206 may include silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC) (e.g., used as an etch stop layer), and dielectric layer 208 may include silicon nitride (e.g., used as an interlayer dielectric). Moreover, although Figure 2C and Figure 2DThe specific arrangement and thickness of dielectric layers 204, 206, and 208 are described herein, but other arrangements and thicknesses are possible in other embodiments. As described in more detail herein, dielectric layer 206 can provide mechanical stability to capacitor structure 200 during manufacturing. Alternatively or additionally, in some embodiments, one or more other dielectric layers 204, 206, and 208 may provide such stability.

[0030] Regarding the first capacitor portion 220 and the second capacitor portion 221, the first conductive component 102A (e.g., also referred to as capacitor bottom metal (CBM)) and the second conductive component 102B (e.g., also referred to as capacitor top metal (CTM)) may each comprise a metal (e.g., copper (Cu), other metals or metal alloys) or another conductive material (e.g., polycrystalline silicon, silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), etc.). In some embodiments, the first conductive component 102A and the second conductive component 102B may comprise the same or different materials. Furthermore, in some embodiments, the dielectric component 104 may comprise an insulator and / or other insulating or dielectric materials.

[0031] like Figure 2C and Figure 2D As shown in the cross-sectional view, a dielectric cover layer 210 may be disposed above the second conductive component 102B and the dielectric layer 204. Additionally, a dielectric spacer 211 may be disposed above the dielectric component 104 and laterally surround a portion of the dielectric cover layer 210, the dielectric layer 204, and the second conductive component 102B. In some embodiments, the dielectric cover layer 210 and the dielectric spacer 211 may be made of the same dielectric material, such as silicon nitride, but other dielectric materials may be used in other embodiments.

[0032] In some embodiments, the second electrode 212 may contact the second conductive component 102B. The second electrode 212 may include a conductive material, such as copper (Cu), a copper alloy, another metal, or another conductive material. Moreover, in some embodiments, the second electrode 212 may have a wider upper portion and a narrower lower portion. The narrower lower portion may extend through the dielectric cap layer 210 and the dielectric layer 204 to contact the second conductive component 102B.

[0033] The first electrode 202 and the second electrode 212 can be used as two electrical connections of the MIM capacitor structure 200 employed in the IC device. In some embodiments, the MIM capacitor structure 200 can be used as a component in digital or analog circuits, such as a bypass capacitor or a decoupling capacitor (e.g., for DC voltage, such as power supply voltage).

[0034] like Figure 2C As shown in the cross-sectional view, in some embodiments, one or more conductive interconnect structures 244 may be disposed in the dielectric layers 204, 206, and 208 near the first conductive component 102A and the second conductive component 102B. One or more conductive interconnect structures 244 may include a plurality of conductive metal lines 246 stacked perpendicularly to the plurality of vias 240. The conductive materials of the conductive metal lines 246 and the vias 240 may include, for example, copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), some other conductive materials, or any combination of the foregoing materials.

[0035] Figures 3 to 9 , Figure 10A and Figure 10B , Figure 11A and Figure 11B , Figure 12A , Figure 12B and Figure 12C , Figure 13A and Figure 13B , Figure 14A and Figure 14B as well as Figure 15A and Figure 15B Various side views are shown illustrating different stages of the manufacturing process of an IC device including a mechanically stabilized double-sided 3DMIM capacitor structure (e.g., capacitor structure 200) according to some embodiments of the present invention. More specifically, Figures 3 to 9 as well as Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A Is with Figure 2C Orthogonal cross-sectional views at the same cross-section line. Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B They are respectively with Figure 2D The diagonal section view at the same section line, and is the same as Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A Views at the same manufacturing stage. Although Figures 3 to 9 , Figure 10A and Figure 10B , Figure 11A and Figure 11B , Figure 12A , Figure 12B and Figure 12C , Figure 13A and Figure 13B , Figure 14A and Figure 14B as well as Figure 15A and Figure 15B The actions are described as a series of actions; however, it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0036] Figure 3 A first electrode 202 is shown, on which a plurality of dielectric layers 204, 206, and 208 are disposed. In some embodiments, a substrate 201 (e.g., a silicon (Si) substrate) may support the first dielectric layer 204, and the first electrode 202 may be formed thereon, followed by the formation of successive additional dielectric layers 204, 206, and 208. Figure 3 As shown, the relatively thin dielectric layers 206 and 208 can be formed alternately between the thicker dielectric layer 204, although many other structures and formation sequences can be used with dielectric layers 204, 206, and / or 208. As described above, in some embodiments, each of dielectric layers 204, 206, and 208 may include one or more dielectric materials, including but not limited to silicon oxide (SiO2). x (e.g., silicon oxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC). For example, dielectric layer 204 may include silicon oxide (SiO2). x Dielectric layer 206 may include silicon carbide (SiC), and dielectric layer 208 may include silicon nitride (SiN), but other materials and combinations are also possible. Furthermore, in some embodiments, Figure 3 The upper dielectric layer 206 shown can be used as Figure 2B , Figure 2C and Figure 2D The structure dielectric layer 206.

[0037] Additionally, in some embodiments, one or more vias 240 and associated metal layers may be disposed in dielectric layers 204, 206, and 208 in the vicinity (e.g., around) the 3D MIM capacitor structure to be manufactured, as depicted in the following figures.

[0038] Figure 4 The removal of multiple trenches 402 (e.g., by photolithography and etching) is shown, which will determine the location of each first capacitor portion 220 and guard ring 222. In some embodiments, each trench 402 extends from the upper surface of the uppermost dielectric layer 204 to the upper surface of the first electrode 202.

[0039] Figure 5The diagram illustrates the formation (e.g., conformal deposition) of the first conductive component 102A inside and outside (e.g., between) trenches 402. As described above, the first conductive component 102A may include a metal (e.g., copper (Cu)), a metal alloy, and / or another conductive material (e.g., polycrystalline silicon, tantalum nitride (TaN), etc.).

[0040] Figure 6 The diagram illustrates the formation (e.g., deposition) of a plurality of protective plugs 502 filling trench 402, and the formation of a photoresist material 504 that can protect multiple portions of the first conductive component 102A not located between adjacent trenches 402. In some embodiments, the protective plugs 502 may be formed of a fluid organic-type material. The protective plugs 502 and the photoresist material 504 together can facilitate the selective removal (e.g., etching) of portions of the first conductive component 102A located between adjacent trenches 402, such as... Figure 7 As shown, this forms a plurality of individual first conductive components 102A. Thereafter, Figure 8 The removal (e.g., dissolution) of the protective plug 502 and the photoresist material 504 is shown.

[0041] Figure 9 The upper dielectric layer 204 (e.g., silicon oxide (SiO2) is shown) x The removal of (such as silicon dioxide (SiO2) or another soluble dielectric material) (e.g., wet removal or dissolution using a solvent such as hydrofluoric acid) extends down to the upper instance of structural dielectric layer 206. In some embodiments, structural dielectric layer 206 may include silicon carbide (SiC) or another dielectric material that is more resistant to dissolving in a particular solvent than dielectric layer 204.

[0042] Figure 10A and Figure 10B Orthogonal and diagonal cross-sectional views are shown of a dielectric spacer structure 1002 formed (e.g., deposited) over an exposed conductive surface (e.g., the surface of the first conductive component 102A). In some embodiments, the deposited dielectric spacer structure 1002 may form a dielectric layer 204 having a non-uniform upper surface, which may generally follow the contours of at least some of the multiple portions of the first conductive component 102A and the structural dielectric layer 206 located therebelow.

[0043] Figure 11A and Figure 11BOrthogonal and diagonal cross-sectional views are shown, respectively, of dielectric material removed (e.g., extensive or “comprehensive” etching) from the dielectric spacer wall structure 1002. In some embodiments, sufficient amount of dielectric material may be removed from the dielectric spacer wall structure 1002 to remove portions of a first (structural) dielectric layer 206 (also referred to as the first dielectric layer) between adjacent trenches 402 (e.g., associated with the first capacitor portion 220) of a plurality of trenches 402 spaced at least a first linear distance (e.g., the length 254 between adjacent trenches 402 along the diagonal of an associated two-dimensional array in a plan view), such as Figure 11B As shown. In some embodiments, the dielectric spacer wall structure 1002 may be thinner than the trench 402 positioned diagonally. Furthermore, in such embodiments, such removal may leave an intact remainder of the first dielectric layer 206 (e.g., between adjacent portions of the plurality of trenches 402 along orthogonal lines of an associated two-dimensional array in a plan view), as... Figure 11A As shown. Maintaining the integrity of these remaining portions of the first dielectric layer 206 can provide mechanical stability for further manufacturing stages.

[0044] For example, Figure 12A , Figure 12B and Figure 12C The removal of other dielectric layers (e.g., through a removed portion of at least one of the first dielectric layers 206) is illustrated separately (e.g., wet dip removal or dissolution). For example, all exposed dielectric layers other than the first dielectric layer 206 (e.g., dielectric layers 204 and 208) can be removed, including... Figure 12A The dielectric layers shown, because Figure 12B The multiple openings in the first dielectric layer 206 depicted facilitate contact.

[0045] During this manufacturing stage, additional material layers can be formed to complete the fabrication of the first capacitor portion 220, the second capacitor portion 221, and / or the protective ring 222. For example, Figure 13A and Figure 13BOrthogonal and diagonal cross-sectional views are shown, respectively, of a first conductive material (e.g., to complete the first conductive component 102A of the first capacitor portion 220 and the second capacitor portion 221) formed (e.g., conformally deposited) inside and outside the plurality of trenches 402. In some embodiments, such deposition can facilitate the application of a conductive material (e.g., a metal (copper (Cu)), a metal alloy, or another conductive material (e.g., polycrystalline silicon, tantalum nitride (TaN), etc.) to the exposed upper and lower portions of the dielectric layer 206 and to the previously present portions of the first conductive component 102A. For example, in some embodiments, the conductive material can be deposited by atomic layer deposition (ALD). This deposition can allow all exposed upper, lower, and side surfaces of the dielectric material of the dielectric layer 206, and possibly the first conductive component 102A, to be covered by the first conductive material.

[0046] Figure 14A and Figure 14B Orthogonal and diagonal cross-sectional views are shown of a dielectric material (e.g., dielectric assembly 104 for forming first capacitor portion 220 and second capacitor portion 221) formed (e.g., conformally deposited) over a first conductive material. In some embodiments, the dielectric material may include an insulator and / or other dielectric materials.

[0047] Figure 15A and Figure 15B Orthogonal and diagonal cross-sectional views are shown, respectively, of a second conductive material (e.g., a second conductive assembly 102B for forming a first capacitor portion 220 and a second capacitor portion 221) formed (e.g., deposited or filled) on a dielectric material. In some embodiments, a sufficient amount of the second conductive material may cover the entire dielectric assembly 104. Also as... Figure 15A and Figure 15B As shown, in some embodiments, one or more pores 230 may be formed within the second conductive material 102B in one or more second capacitor portions 221 between the first capacitor portion 220 or the guard ring 222.

[0048] Subsequently, dielectric capping layer 210 and dielectric spacer wall 211 can be formed above dielectric assembly 104 to laterally surround dielectric capping layer 210, dielectric layer 204, and a portion of second conductive assembly 102B, as described above. Figure 2C and Figure 2D As discussed. Furthermore, in some embodiments, the second electrode 212 may be formed to extend through the dielectric cap layer 210 and the dielectric layer 204 to contact the second conductive component 102B.

[0049] In some embodiments, Figure 16 , Figure 17A and Figure 17B ,as well as Figure 18A and Figure 18A The text describes the above-mentioned... Figures 6 to 9 as well as Figure 10A , Figure 10B , Figure 11A and Figure 11B The discussion focuses on alternative processes for the manufacturing stage. These processes are specifically designed for... Figure 5 The stage used to create an opening in the structural dielectric layer 206 after the formation (e.g., conformal deposition) of the first conductive component 102A shown.

[0050] For example, Figure 16 The diagram illustrates the formation (e.g., deposition) of protective plugs 502 filling trench 402, and the formation of photoresist material 504, which can protect multiple portions of the first conductive component 102A not located between adjacent trenches 402 and multiple protective plugs 502 located in the trenches 402 associated with the first capacitor portion 220. The protective plugs 502 and photoresist material 504 together can facilitate the selective removal (e.g., etching) of portions of the first conductive component 102A located between adjacent trenches 402, as well as some dielectric layers 204, along rows or columns of the two-dimensional array, such as... Figure 17A The cross-sectional view is shown. Additionally, in some embodiments, along the diagonal of the array, such as... Figure 17B As shown in the cross-sectional view, the structural dielectric layer 206 below the trenches 402 (that is, a portion of the structural dielectric layer 206) can be removed (e.g., due to the greater distance between the trenches 402 along the diagonal cross-sectional view). Figure 18A and Figure 18B The cross-sectional view shows the subsequent removal (e.g., dissolution) of the protective plug 502 and the photoresist material 504.

[0051] At this stage, the process can be as follows: Figure 12A , Figure 12B and Figure 12C As shown in the diagram. Figure 12A , Figure 12B and Figure 12C Orthogonal cross-sectional views, diagonal cross-sectional views, and planar views are shown, respectively, of the removal (e.g., wet removal or dissolution) of some of the additional dielectric layers (e.g., removed portions through at least one of the first dielectric layers 206). As described above, all exposed dielectric layers other than the first dielectric layer 206 (e.g., dielectric layers 204 and 208) can be removed, including... Figure 12A The dielectric layers shown, because Figure 12B The multiple openings in the first dielectric layer 206 depicted facilitate contact. Then, it can be bonded as described above. Figure 13A and Figure 13B , Figure 14A and Figure 14B as well as Figure 15A and Figure 15B Continue manufacturing as discussed.

[0052] Figure 19 The diagram illustrates a mechanically stable double-sided MIM capacitor structure according to some embodiments (e.g., Figure 2B , Figure 2C and Figure 2D Method 1900 of an IC device (MIM capacitor structure 200). Although the methods and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present invention is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0053] At action 1902, for example, the first electrode (e.g., Figure 2B , Figure 2C and Figure 3 The first electrode 202 can be formed on the substrate (e.g., Figure 2C , Figure 2D and Figure 3 On the substrate 201). At operation 1904, multiple dielectric layers (e.g., ...) can be formed above the first electrode. Figure 3 Dielectric layers 204, 206 and 208). Figure 3 Cross-sectional views corresponding to some embodiments of actions 1902 and 1904 are shown.

[0054] At action 1906, multiple grooves can be formed (e.g., Figure 4 The trench 402 passes through multiple dielectric layers. As described above, each trench can define the location of the corresponding first capacitor portion 220. Figure 4 Cross-sectional views corresponding to some embodiments of action 1906 are shown.

[0055] At action 1908, the first conductive structure (e.g., Figure 5 The first conductive component 102A can be conformally deposited on multiple dielectric layers and deposited into multiple trenches. Figure 5 Cross-sectional views corresponding to some embodiments of action 1908 are shown.

[0056] At action 1910, the portion of the first conductive structure outside the plurality of trenches can be removed. At action 1912, the first dielectric layer (e.g., in the plurality of dielectric layers) can be removed. Figure 2B , Figure 2C and Figure 2D Before the structural dielectric layer 206, a portion of at least one of the plurality of dielectric layers located outside the plurality of trenches is removed. Furthermore, at action 1914, less than all of the first dielectric layer may be removed. Figures 6 to 9 , Figure 10A and Figure 10B as well as Figure 11A and Figure 11B Cross-sectional views corresponding to some embodiments of actions 1910, 1912, and 1914 are shown. Alternatively, Figure 16 , Figure 17A and Figure 17B as well as Figure 18A and Figure 18B Cross-sectional views corresponding to some embodiments of actions 1910, 1912 and 1914 are shown.

[0057] At action 1916, some other dielectric layers (e.g., Figure 11A and Figure 11B The dielectric layers 204 and 208 can be removed by at least one removed portion of the first dielectric layer. Figure 12A and Figure 12B Cross-sectional views corresponding to some embodiments of action 1916 are shown.

[0058] At action 1918, the first conductive material (e.g., used for...) Figure 13A and Figure 13B The first conductive component 102A can be conformally deposited inside and outside multiple trenches. Figure 13A and Figure 13B Cross-sectional views corresponding to some embodiments of action 1918 are shown.

[0059] At action 1920, the dielectric material (e.g., Figure 14A and Figure 14B The dielectric component 104 can be conformally deposited on the first conductive material. Figure 14A and Figure 14B Cross-sectional views corresponding to some embodiments of action 1920 are shown.

[0060] At action 1922, a second conductive material can be formed on the dielectric material (e.g., Figure 15A and Figure 15B The second conductive component 102B). Figure 15A and Figure 15B Cross-sectional views corresponding to some embodiments of action 1922 are shown.

[0061] At action 1924, a second electrode can be formed (e.g., Figure 2C and Figure 2D The second electrode 212 is used to contact the second conductive material. Therefore, in some embodiments, the first electrode and the second electrode can be used as access MIM capacitor structures (e.g., Figure 2B , Figure 2C and Figure 2D The contact points of the MIM capacitor structure (200). Figure 2C and Figure 2D Cross-sectional views corresponding to some embodiments of action 1924 are shown.

[0062] Some embodiments relate to an IC device. The IC device includes a plurality of dielectric layers disposed above a substrate and a capacitor structure comprising a plurality of capacitor portions. Each of the plurality of capacitor portions includes a first conductive component extending through the plurality of dielectric layers, a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component, and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component. The plurality of dielectric layers include a first dielectric layer extending laterally between a plurality of first adjacent pairs of the plurality of capacitor portions, wherein the plurality of capacitor portions in the plurality of first adjacent pairs of the plurality of capacitor portions are spaced apart from each other by a length less than a first length. The first dielectric layer includes a sidewall defining a gap between each of a plurality of second adjacent pairs of the plurality of capacitor portions, wherein the length of the gap is greater than or equal to the first length.

[0063] Some embodiments relate to another type of IC device. The IC device includes a plurality of dielectric layers disposed above a substrate and a capacitor structure comprising a plurality of capacitor portions. Each of the plurality of capacitor portions includes a first conductive component extending through the plurality of dielectric layers, a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component, and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component. In a top view of the IC device, the plurality of capacitor portions are arranged in a two-dimensional array. At least one of the plurality of dielectric layers bridges each adjacent pair of the plurality of capacitor portions aligned along rows or columns of the two-dimensional array. The at least one of the plurality of dielectric layers includes a gap between each adjacent pair of the plurality of capacitor portions.

[0064] Some embodiments relate to a method. The method includes forming a first electrode on a substrate; forming a plurality of dielectric layers over the first electrode; forming a plurality of trenches through the plurality of dielectric layers; conformally depositing a first conductive structure over the plurality of dielectric layers and in the plurality of trenches; removing portions of the plurality of first conductive structures located outside the trenches; removing portions of at least one of the plurality of dielectric layers outside the plurality of trenches before (or above) the first dielectric layer of the plurality of dielectric layers; removing less than the entire first dielectric layer; removing other portions of the plurality of dielectric layers through at least one removed portion of the first dielectric layer; conformally depositing a first conductive material inside and outside the plurality of trenches; conformally depositing a dielectric material on the first conductive material; forming a second conductive material on the dielectric material; and forming a second electrode on the second conductive material.

[0065] This utility model provides an integrated circuit device, comprising: a substrate; a plurality of dielectric layers disposed on the substrate; and a capacitor structure including a plurality of first capacitor portions, each of the plurality of first capacitor portions including: a first conductive component extending through the plurality of dielectric layers; a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component; and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component; wherein at least one of the plurality of dielectric layers includes a first dielectric layer, the first dielectric layer extending laterally between a plurality of first adjacent pairs of the plurality of first capacitor portions, wherein the plurality of first capacitor portions in each of the plurality of first adjacent pairs of the plurality of first capacitor portions are spaced apart from each other by a length less than a first length, wherein the first dielectric layer includes a sidewall defining a gap between each of a plurality of second adjacent pairs of the plurality of first capacitor portions, wherein the length of the gap is greater than or equal to the first length.

[0066] In one embodiment, in the integrated circuit device, wherein: in a plan view of the integrated circuit device, the plurality of first capacitor portions are arranged in a two-dimensional array; each of the plurality of first adjacent pairs of the plurality of first capacitor portions is aligned along a row or column of the two-dimensional array; and each of the plurality of second adjacent pairs of the plurality of first capacitor portions is aligned along a diagonal of the two-dimensional array. In one embodiment, in the integrated circuit device, wherein the first dielectric layer is an etch stop layer. In one embodiment, in the integrated circuit device, wherein the plurality of dielectric layers further includes a second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials. In one embodiment, in the integrated circuit device, wherein, for each of the plurality of first capacitor portions: the first conductive component includes a first structure vertically oriented in a side view of the integrated circuit device; the dielectric component includes a second structure coaxial with and located within the first conductive component; and the second conductive component includes a third structure coaxial with and located within the dielectric component. In one embodiment, the integrated circuit device further includes: a first electrode electrically connected to a first conductive component of each of the plurality of first capacitor portions; and a second electrode electrically connected to a second conductive component of each of the plurality of first capacitor portions. In one embodiment, in the integrated circuit device, the capacitor structure further includes: one or more second capacitor portions, each of the one or more second capacitor portions comprising: a first conductive component extending through the plurality of dielectric layers, wherein a portion of the first conductive component is shared with a portion of the first conductive component of at least one of the plurality of first capacitor portions; a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component; and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component.

[0067] This utility model provides an integrated circuit device, comprising: a substrate; a plurality of dielectric layers disposed on the substrate; and a capacitor structure including a plurality of first capacitor portions, each of the plurality of first capacitor portions including: a first conductive component extending through the plurality of dielectric layers; a dielectric component extending through the plurality of dielectric layers and aligned along the first conductive component; and a second conductive component extending through the plurality of dielectric layers and aligned along the dielectric component; wherein, in a plan view of the integrated circuit device, the plurality of first capacitor portions are arranged in a two-dimensional array; wherein at least one of the plurality of dielectric layers bridges each adjacent pair of the plurality of first capacitor portions aligned along rows or columns of the two-dimensional array; and wherein the at least one of the plurality of dielectric layers includes a gap between each adjacent pair of the plurality of first capacitor portions.

[0068] In one embodiment, in the integrated circuit device, at least one of the plurality of dielectric layers includes an etch stop layer. In one embodiment, in the integrated circuit device, each of the plurality of first capacitor portions is vertically oriented through the plurality of dielectric layers. In one embodiment, in the integrated circuit device, each of the plurality of first capacitor portions is cylindrical in the plan view of the integrated circuit device.

[0069] This utility model provides a method for manufacturing an integrated circuit device, comprising: forming a first electrode on a substrate; forming a plurality of dielectric layers on the first electrode; forming a plurality of trenches through the plurality of dielectric layers; conformally depositing a first conductive structure on the plurality of dielectric layers and depositing it into the plurality of trenches; removing a portion of the first conductive structure outside the plurality of trenches; removing a portion of at least one of the plurality of dielectric layers outside the plurality of trenches, before the first dielectric layer of the plurality of dielectric layers; deleting less than the entire first dielectric layer; removing some of the other dielectric layers through at least one removed portion of the first dielectric layer; conformally depositing a first conductive material inside and outside the plurality of trenches; conformally depositing a dielectric material on the first conductive material; forming a second conductive material on the dielectric material; and forming a second electrode on the second conductive material.

[0070] In one embodiment, in the method, each of the plurality of trenches extends to the first electrode. In one embodiment, in the method, the first dielectric layer includes an etch stop layer. In one embodiment, in the method, some of the other dielectric layers include at least one of silicon oxide or silicon nitride. In one embodiment, in the method, the plurality of trenches are arranged as a two-dimensional array in a plan view. In one embodiment, in the method, after removing less than the entire first dielectric layer, multiple portions of the first dielectric layer extend between adjacent trenches in each pillar and each row of the two-dimensional array. In one embodiment, in the method, wherein: removing a portion of each of at least one of the plurality of dielectric layers outside the plurality of trenches, before the first dielectric layer of the plurality of dielectric layers, comprises removing exposed portions of the plurality of dielectric layers outside the plurality of trenches to the first dielectric layer; and removing less than the entire first dielectric layer comprises: forming a plurality of dielectric spacer structures on conductive surfaces inside and outside the plurality of trenches; and removing a sufficient amount of dielectric material from the dielectric spacer structures to remove a plurality of portions of the first dielectric layer between adjacent plurality of trenches spaced at least a first linear distance, while leaving the complete remaining portion of the first dielectric layer. In one embodiment, in the method, wherein a single etching operation is used to remove the portion of the first conductive structure not located in the plurality of trenches, to remove a portion of each of at least one of the plurality of dielectric layers outside the plurality of trenches, before the first dielectric layer of the plurality of dielectric layers, and to remove less than the entire first dielectric layer. In one embodiment, in the method, a wet immersion removal operation is used to remove some of the other dielectric layers through the at least one removed portion of the first dielectric layer.

[0071] It should be understood that in the written description and the appended claims, the terms "first," "second," "third," etc., are merely generic identifiers used for ease of description and to distinguish different terms. A figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the components and are not intended to describe corresponding components in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An integrated circuit device, characterized in that, include: Substrate; Multiple dielectric layers are disposed on the substrate; as well as A capacitor structure includes a plurality of first capacitor portions, each of the plurality of first capacitor portions comprising: A first conductive component extends through the plurality of dielectric layers; Dielectric components, extending through the plurality of dielectric layers and aligned along the first conductive component; and A second conductive component extends through the plurality of dielectric layers and is aligned along the dielectric component; At least one of the plurality of dielectric layers includes a first dielectric layer that extends laterally between a plurality of first adjacent pairs of the plurality of first capacitor portions, wherein the plurality of first capacitor portions in each of the plurality of first adjacent pairs of the plurality of first capacitor portions are spaced apart from each other by a length less than a first length, wherein the first dielectric layer includes a sidewall defining a gap between each of the plurality of second adjacent pairs of the plurality of first capacitor portions, wherein the length of the gap is greater than or equal to the first length.

2. The integrated circuit device according to claim 1, characterized in that: In the plan view of the integrated circuit device, the plurality of first capacitor portions are arranged in a two-dimensional array; Each of the plurality of first adjacent pairs of the plurality of first capacitor portions is aligned along the rows or columns of the two-dimensional array; as well as Each of the plurality of second adjacent pairs of the plurality of first capacitor portions is aligned along the diagonal of the two-dimensional array.

3. The integrated circuit device according to claim 1, characterized in that, The first dielectric layer is an etch stop layer.

4. The integrated circuit device according to claim 1, characterized in that, The plurality of dielectric layers further include a second dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different materials.

5. The integrated circuit device according to claim 1, characterized in that, For each of the plurality of first capacitor portions: The first conductive component includes a first structure vertically oriented in a side view of the integrated circuit device; The dielectric component includes a second structure coaxial with and located inside the first conductive component; and The second conductive component includes a third structure that is coaxial with the dielectric component and located inside the dielectric component.

6. The integrated circuit device according to claim 1, characterized in that, Also includes: The first electrode is electrically connected to the first conductive component of each of the plurality of first capacitor portions; as well as The second electrode is electrically connected to the second conductive component of each of the plurality of first capacitor portions.

7. The integrated circuit device according to claim 1, characterized in that, The capacitor structure also includes: One or more second capacitor portions, each of the one or more second capacitor portions comprising: A first conductive component extends through the plurality of dielectric layers, wherein a portion of the first conductive component is shared with a portion of the first conductive component of at least one of the plurality of first capacitor portions; Dielectric components, extending through the plurality of dielectric layers and aligned along the first conductive component; and A second conductive component extends through the plurality of dielectric layers and is aligned along the dielectric component.

8. An integrated circuit device, characterized in that, include: Substrate; Multiple dielectric layers are disposed on the substrate; as well as A capacitor structure includes a plurality of first capacitor portions, each of the plurality of first capacitor portions comprising: A first conductive component extends through the plurality of dielectric layers; Dielectric components, extending through the plurality of dielectric layers and aligned along the first conductive component; and A second conductive component extends through the plurality of dielectric layers and is aligned along the dielectric component; In the plan view of the integrated circuit device, the plurality of first capacitor portions are arranged in a two-dimensional array; At least one of the plurality of dielectric layers bridges each adjacent pair of the plurality of first capacitor portions aligned along the rows or pillars of the two-dimensional array; and At least one of the plurality of dielectric layers includes a gap between each adjacent pair of the plurality of first capacitor portions.

9. The integrated circuit device according to claim 8, characterized in that, Each of the plurality of first capacitor portions is oriented vertically through the plurality of dielectric layers.

10. The integrated circuit device according to claim 8, characterized in that, In the plan view of the integrated circuit device, each of the plurality of first capacitor portions is cylindrical.

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