Semiconductor device

Abstract

A semiconductor device includes a substrate, a first interlayer dielectric disposed on the substrate, and a metal-insulator-metal (MIM) capacitor disposed in the first interlayer dielectric. The MIM capacitor includes a first metal layer disposed on the substrate, a first insulator layer including a horizontal portion and a sidewall portion, a second metal layer, wherein the horizontal portion of the first insulator layer is disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulator layer horizontally surrounds the second metal layer, a second insulator layer that surrounds the sidewall portion of the first insulator layer, at least one metal contact that extends vertically through the second insulator layer, wherein a lower end of the at least one metal contact is in contact with the first metal layer, and at least one air spacer that horizontally surrounds the at least one metal contact.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to semiconductor devices having metal-insulator-metal (MIM) capacitors, and more specifically, to semiconductor devices having front-end process (FEOL) MIM capacitors having air spacers. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. However, this shrinkage also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor integrated circuits and devices require similar progress in semiconductor manufacturing processes and technologies. Utility Model Content

[0003] Some embodiments of this disclosure provide a semiconductor device comprising: a substrate, a first interlayer dielectric, and a metal-insulator-metal capacitor. The first interlayer dielectric is disposed on the substrate. The metal-insulator-metal capacitor is disposed in the first interlayer dielectric and includes: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, at least one metal contact, and at least one air spacer. The first metal layer is disposed on the substrate. The first insulating layer includes a horizontal portion and a sidewall portion. The second metal layer includes the horizontal portion of the first insulating layer disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer. The second insulating layer surrounds the sidewall portion of the first insulating layer. At least one metal contact extends vertically through the second insulating layer, wherein a lower end of the at least one metal contact contacts a top surface of the first metal layer. At least one air spacer horizontally surrounds the at least one metal contact.

[0004] Further embodiments of this disclosure provide a semiconductor device comprising: a substrate, a first interlayer dielectric, and a metal-insulator-metal capacitor. The first interlayer dielectric is disposed on the substrate. The metal-insulator-metal capacitor is disposed in the first interlayer dielectric and includes: a third metal layer, a third insulating layer, a first metal layer, a second metal layer, at least one metal contact, and an air spacer. The third metal layer is disposed on the substrate. The third insulating layer is disposed on the third metal layer. The first metal layer is disposed on the third insulating layer and includes a horizontal portion and a sidewall portion. The first insulating layer includes a horizontal portion and a sidewall portion, the sidewall portion of the first metal layer horizontally surrounding the sidewall portion of the first insulating layer. The second metal layer includes a horizontal portion of the first insulating layer disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounding the second metal layer. At least one metal contact extends vertically through the first interlayer dielectric, wherein a lower end of the at least one metal contact contacts a top surface of the third metal layer. An air spacer horizontally surrounds this sidewall portion of the first metal layer.

[0005] Further embodiments of this disclosure provide a semiconductor device comprising: a substrate, a first interlayer dielectric, a metal-insulator-metal capacitor, and a second interlayer dielectric. The first interlayer dielectric is disposed on the substrate. The metal-insulator-metal capacitor is disposed in the first interlayer dielectric and includes: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, at least one metal contact, and at least one air spacer. The first metal layer is disposed on the substrate. The first insulating layer includes a horizontal portion and a sidewall portion. The second metal layer includes the horizontal portion of the first insulating layer disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer. The second insulating layer surrounds the sidewall portion of the first insulating layer. At least one metal contact extends vertically through the second insulating layer, wherein a lower end of the at least one metal contact contacts a top surface of the first metal layer. At least one air spacer horizontally surrounds the at least one metal contact. The second interlayer dielectric is disposed on the first interlayer dielectric. Attached Figure Description

[0006] Several aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A It is a cross-sectional schematic diagram illustrating a cross-sectional view of a wafer according to some embodiments;

[0008] Figure 1B This is a schematic diagram illustrating some implementation methods. Figure 1A A top view of a portion of the chip;

[0009] Figure 2 This is a schematic top view illustrating a portion of another chip according to some embodiments;

[0010] Figure 3 It is a flowchart illustrating an embodiment of a method according to some implementation methods;

[0011] Figures 4A to 4D It is a cross-sectional view illustrating the cross-sections of multiple structures at various manufacturing stages according to some implementation methods;

[0012] Figure 5A This is a cross-sectional view of a wafer according to some implementation methods;

[0013] Figure 5B This is a schematic diagram illustrating some implementation methods. Figure 5A A top view of a portion of the chip;

[0014] Figure 6A This is a cross-sectional schematic diagram of a wafer according to some implementation methods;

[0015] Figure 6B This is a schematic diagram illustrating some implementation methods. Figure 6A A top view of a portion of the chip;

[0016] Figure 7 It is a flowchart illustrating an embodiment of a method according to some implementation methods;

[0017] Figures 8A to 8D It is a cross-sectional schematic diagram illustrating the cross-sections of multiple structures at different manufacturing stages according to some implementation methods.

[0018] [Symbol Explanation]

[0019] 100: Chip

[0020] 102: Field-Effect Transistor Region (Field-Effect Transistor)

[0021] 103: Field-Effect Transistor

[0022] 104: Front-end process MIM capacitor area (MIM capacitor)

[0023] 105: Front-end process MIM capacitor (MIM capacitor)

[0024] 105': MIM capacitor

[0025] 105”: MIM capacitor

[0026] 105a: MIM capacitor

[0027] 105b: MIM capacitor

[0028] 105c: MIM capacitor

[0029] 105d:MIM capacitor

[0030] 105e: MIM capacitor

[0031] 105F: MIM capacitor

[0032] 122: Oxide diffusion region (OD)

[0033] 124: Source / Drain Region (S / D)

[0034] 126: Metal gate (metal gate structure, MG)

[0035] 128: Spacer structure (spacer)

[0036] 130: First interlayer dielectric (interlayer dielectric, ILD 0)

[0037] 131: Third metal layer

[0038] 132: First metal layer (MIM metal 1)

[0039] 133: Third Insulating Layer

[0040] 134: First Insulating Layer (MIM Insulator 1)

[0041] 136: Second metal layer (MIM metal 2)

[0042] 138: Second Insulating Layer (MIM Insulator 2)

[0043] 140: Second interlayer dielectric (interlayer dielectric, ILD 1)

[0044] 142: Metal Contact (CT)

[0045] 142a: First metal contact (metal contact)

[0046] 142b: Second metal contact (metal contact layer, metal contact)

[0047] 142c: Metal contact

[0048] 142d: Metal contact

[0049] 142e: Metal contact

[0050] 144: Intermetallic Dielectric (IMD)

[0051] 146: M1 layer metal guide rail (M1 metal guide rail)

[0052] 150a: First air gap (air gap)

[0053] 150b: Second air gap (air gap)

[0054] 150e: Air spacer

[0055] 150f: Air spacer

[0056] 300: Method

[0057] 302: Operation

[0058] 304: Operation

[0059] 306: Operation

[0060] 308: Operation

[0061] 310: Operation

[0062] 312: Operation

[0063] 314: Operation

[0064] 316: Operation

[0065] 402: Trench

[0066] 404: Dummy silicon spacers

[0067] 410: Pinch-off section

[0068] 700: Method

[0069] 702: Operation

[0070] 704: Operation

[0071] 706: Operation

[0072] 708: Operation

[0073] 710: Operation

[0074] 800: Five-layer structure

[0075] 802: Trench

[0076] A-A': line

[0077] X: Direction

[0078] Y: direction

[0079] Z: Direction Detailed Implementation

[0080] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and not limiting. For example, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not imply a relationship between the various implementations and / or configurations discussed.

[0081] Furthermore, the source / drain region may refer to either the source or the drain, individually or collectively, depending on the context. For example, between other components, a device may include a first source / drain region and a second source / drain region. The first source / drain region may be a source region, and the second source / drain region may be a drain region, or vice versa. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0082] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms such as "below," "below," "lower," "higher," "upper," or similar terms may be used herein. In addition to the directions illustrated in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0083] Some embodiments of this disclosure are described. Additional operations may be provided before, during, and / or after the multiple stages described in these embodiments. For different embodiments, some stages may be replaced or omitted. For different embodiments, some features described below may be replaced or omitted, and additional features may be added. Although some embodiments discuss multiple operations performed in a particular order, these operations may be performed in another logical order.

[0084] Overview

[0085] Metal-insulator-metal (MIM) capacitors are a type of electronic component that stores electrical energy. They are characterized by their simple structure, consisting of two metal electrodes separated by a thin insulating layer. This configuration allows for high capacitance values ​​in a relatively small footprint. MIM capacitors typically consist of a top electrode, a bottom electrode, and an insulating layer. The top and bottom electrodes are usually made of conductive metals such as aluminum, tantalum, or titanium. The insulating layer is typically made of a dielectric material such as silicon nitride, tantalum oxide, or aluminum oxide. Its thickness determines the capacitor's capacitance.

[0086] The advantages of MIM capacitors include high capacitance, low leakage current, high reliability, and a wide operating voltage range. Accordingly, MIM capacitors are widely used in applications such as integrated circuits (for providing coupling, filtering, and storage functions), radio frequency (RF) devices (e.g., filters, oscillators, and mixers), storage devices (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), and the like), and power electronics (for decoupling, filtering, and energy storage).

[0087] Back-end-of-line (BEOL) MIM capacitors have been developed. BEOL MIM capacitors are integrated within the wiring layers of a semiconductor device. They provide a compact and efficient way to provide capacitance within the die's structure, thereby enhancing performance and functionality. BEOL MIM capacitors are seamlessly integrated into the existing wiring layers of the die, eliminating the need for separate components and reducing overall package size. They can achieve high capacitance values ​​in a small area, enabling high-density integration of multiple components and improving circuit performance. Their integration within the die's wiring layers minimizes parasitic effects such as inductance and resistance, thereby improving signal integrity and accelerating circuit operation.

[0088] On the other hand, front-end process (FEOL) MIM capacitors offer several advantages over back-end process capacitors. FEOL MIM capacitors can be manufactured early in the manufacturing process, allowing for smaller and denser integration of multiple components. Due to their proximity to the active device, FEOL MIM capacitors can provide lower parasitic effects and faster switching speeds. Early integration of FEOL MIM capacitors improves long-term reliability and reduces the risk of defects. FEOL MIM capacitors can be customized for specific capacitance values, enabling more precise circuit design and optimization.

[0089] Therefore, front-end process MIM capacitors have great potential for a wide range of applications. They are ideal for applications requiring high speed, low power consumption, and small component size. Low parasitic effects and customizable capacitance make front-end process MIM capacitors ideal for analog circuits such as filters, amplifiers, and oscillators. They can also be used in storage cells to improve performance and reduce power consumption.

[0090] Front-end MIM capacitors can also be used in CMOS image sensor (CIS) chips due to their unique properties and advantages. These capacitors play a crucial role in capturing and processing light signals, ensuring high-quality image and video output. Front-end MIM capacitors are ideal for applications requiring high-resolution imaging, such as smartphone cameras, surveillance cameras, and medical imaging systems. They help reduce noise in CIS chips, making them suitable for applications where low noise is critical, such as scientific imaging and night vision. The reduced parasitic effects of front-end MIM capacitors enable faster image capture and processing, making them suitable for applications requiring high frame rates, such as action cameras and video surveillance.

[0091] However, there is always room for improvement. Specifically, front-end process MIM capacitors manufactured via methods such as dummy replacement are affected by edge capacitance from nearby conductors (e.g., contacts, connectors, and the like). Edge capacitance is an unintended capacitance resulting from the overlap of electric fields between multiple nearby conductors. In the case of front-end process MIM capacitors, edge capacitance may occur between the top and bottom electrodes, and between the electrodes and other nearby structures such as interconnects or vias. Edge capacitance increases the total capacitance of the front-end process MIM capacitor, exceeding its expected value. This can lead to unexpected circuit behavior and affect the performance of the front-end process MIM capacitor. Edge capacitance introduces parasitic effects, such as increased coupling between multiple signals and reduced bandwidth. This degrades the overall performance of the circuit. Accurate modeling and control of edge capacitance can be challenging, especially in complex chip designs with dense interconnects. Therefore, there is a need to further reduce edge capacitance in front-end process MIM capacitors.

[0092] According to some aspects of this disclosure, a front-end process MIM capacitor is provided. In some embodiments, metal contacts (e.g., vias) are surrounded by air spacers. In one embodiment, the air spacers are formed by removing a dummy silicon layer around the metal contacts and sealed by performing an ion-implantation process on the interlayer dielectric (ILD) to cause volume expansion of the interlayer dielectric. By surrounding the metal contacts with air spacers, the edge capacitance between the metal contacts and the metal layers of the front-end process MIM capacitor can be significantly reduced. In other embodiments, a MIM stack structure (sometimes referred to as an "MG equivalent structure") is surrounded by air spacers instead of metal contacts. Details of these features will be discussed below.

[0093] Example front-end process for MIM capacitors and example manufacturing process flow

[0094] Figure 1A This is a cross-sectional schematic diagram illustrating an embodiment of a wafer according to some implementation methods. Figure 1B This is a schematic diagram illustrating some implementation methods. Figure 1A A top view of a portion of the chip. It should be understood that... Figure 1A and Figure 1B It was not drawn to scale.

[0095] exist Figure 1A In the illustrated embodiment, wafer 100 includes a front-end process MIM capacitor (or simply "MIM capacitor") 105 and a field-effect transistor (FET) 103 disposed in a substrate not shown. The MIM capacitor region is disposed in a front-end process MIM capacitor region 104, and the FET 103 is disposed in a field-effect transistor (FET) region 102. In this embodiment, the MIM capacitor 105 and the FET 103 are isolated by a spacer structure 128. In some embodiments, the spacer structure 128 comprises silicon nitride (SiNx), silicon oxide (SiO2), or other suitable materials.

[0096] Both the MIM capacitor 105 and the field-effect transistor 102 are disposed on the oxide diffusion (“OD”) region 122 of the substrate. Furthermore, both the MIM capacitor 105 and the field-effect transistor 102 are disposed on the first interlayer dielectric (in... Figure 1A In the 130 marked "ILD 0" in the middle. Therefore, like the field-effect transistor 103, the MIM capacitor 105 is manufactured using front-end process technology. The MIM capacitor 105 is not the back-end process MIM capacitor described above. The second interlayer dielectric (in Figure 1A The winning designation is "ILD 1") 140, which is set above the first interlayer dielectric 130. Intermetallic dielectric (in... Figure 1AThe intermetallic dielectric 144 (marked "IMD") is disposed on the second intermetallic dielectric 140. Since the metal rails 146 of the first metal layer (i.e., the "M1 layer") are disposed within the intermetallic dielectric 144, the layer containing the intermetallic dielectric 144 and the M1 layer metal rails 146 is also referred to as the "M1 layer". Although in Figure 1A Although not shown, those skilled in the art will understand that there are typically multiple layers, such as M2, M3, M4, etc., disposed on the M1 layer. Thus, a multi-layer interconnect (MLI) structure is disposed above the MIM capacitor 104 and the field-effect transistor 103 for wiring. The multi-layer interconnect structure is manufactured using back-end processing techniques.

[0097] exist Figure 1A The field-effect transistor 103 in the illustrated embodiment is a planar metal-oxide-semiconductor field-effect transistor (MOSFET) including a metal gate 126 and two source / drain regions 124. In some embodiments, the metal gate 126 comprises titanium nitride (TiN) or tungsten (W), molybdenum (Mo), or other suitable materials. It should be understood that this is exemplary, and other types of field-effect transistors may be employed as needed. Some embodiments include fin field-effect transistors (FinFETs), gate all-ring field-effect transistors (GAAFETs), and complementary field-effect transistors (CFETs). Although only one MIM capacitor 105 and one field-effect transistor 103 are shown, it should be understood that multiple (e.g., tens, hundreds, or even thousands) MIM capacitors and field-effect transistors can be fabricated and integrated into a single circuit to achieve various desired functions. Other passive and active devices may also be employed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0098] Among other components, the MIM capacitor 105 includes a first metal layer (in Figure 1A (marked as "MIM metal 1") 132, second metal layer (in Figure 1A The middle marked "MIM metal 2") 136 and the first insulating layer (in Figure 1A The first metal layer 134 (labeled "MIM Insulator 1") is a U-shaped insulator layer 134. A first metal layer 132 serves as the bottom electrode, and a second metal layer 136 serves as the top electrode. The first insulator layer 134 includes a horizontal portion and two sidewall portions. The horizontal portion of the first insulator layer 134 is disposed between the first metal layer 132 and the second metal layer 136. In other words, the horizontal portion of the first insulator layer 134 is sandwiched between the first metal layer 132 and the second metal layer 136. The sidewall portions of the first insulator layer 134 surround the second metal layer 136 (in...). Figure 1AIn the cross-section shown, on both sides of the second metal layer 136 in the X direction. The top surface of the sidewall portion is coplanar with the top surface of the second metal layer 136 in the Z direction. Thus, the first metal layer 132, the first insulating layer 134, and the second metal layer 136 form a capacitor, namely a MIM capacitor 105.

[0099] Second insulating layer (in) Figure 1A The middle label is “MIM Insulator 2”) 138 surrounding the first insulating layer 134 (in Figure 1A In the cross-section shown, on both sides of the first insulating layer 134 in the X direction. A second insulating layer 138 is perpendicularly disposed on the first metal layer 132. The second insulating layer 138 is characterized by two trenches, one for receiving a first metal contact (e.g., a via) 142a, and the other for receiving a second metal contact (e.g., a via) 142b. The first metal contact 142a extends perpendicularly in the Z direction and penetrates the second insulating layer 138. The bottom end of the first metal contact 142a contacts the first metal layer 132. Similarly, the second metal contact 142b extends perpendicularly in the Z direction and penetrates the second insulating layer 138. The bottom end of the second metal contact 142b contacts the first metal layer 132. The first metal contact 142a and the second metal contact 142b (i.e., metal contact (CT) 142) may comprise tungsten, copper, or other suitable materials.

[0100] Unlike the conventional structure in which the first metal contact 142a and the second metal contact 142b contact the second insulating layer 138, in Figure 1A The MIM capacitor 105 shown is characterized by a first air spacer 150a surrounding a first metal contact 142a and a second air spacer 150b surrounding a second metal contact 142b. In other words, the first metal contact 142a does not directly contact the second insulating layer 138. Instead, the first air spacer 150a is disposed between them. Similarly, the second metal contact 142b does not directly contact the second insulating layer 138. Instead, the second air spacer 150b is disposed between them.

[0101] Air has a low dielectric constant (approximately 1.00059 at room temperature) compared to insulators and most semiconductor materials. The dielectric constant is a measure of a material's ability to store electrical energy. For a given area, a lower dielectric constant means a smaller capacitance. As a result, the first air spacer 150a can significantly reduce the edge capacitance between the first metal contact 142a and the second metal layer 136, while the second air spacer 150b can significantly reduce the edge capacitance between the second metal contact 142b and the second metal layer 136.

[0102] Despite Figure 1A In the illustrated embodiment, the height of the first air spacer 150a is the same as the height of the second insulating layer 138, but it should be understood that this is not mandatory. In some embodiments, during manufacturing, the top portion of the first air spacer 150a may be occupied by the second interlayer dielectric 140. However, even in this case, the first air spacer 150a still functions to reduce edge capacitance. In one embodiment, the height of the first air spacer 150a is greater than 30% of the height of the second insulating layer 138. In another embodiment, the height of the first air spacer 150a is greater than 50% of the height of the second insulating layer 138. In another embodiment, the height of the first air spacer 150a is greater than 70% of the height of the second insulating layer 138. In yet another embodiment, the height of the first air spacer 150a is greater than 90% of the height of the second insulating layer 138.

[0103] Similarly, although in Figure 1A In the illustrated embodiment, the height of the second air spacer 150b is the same as the height of the second insulating layer 138, but it should be understood that this is not mandatory. In some embodiments, during manufacturing, the top portion of the second air spacer 150b may be occupied by the second interlayer dielectric 140. However, even in this case, the second air spacer 150b still functions to reduce edge capacitance. In one embodiment, the height of the second air spacer 150b is greater than 30% of the height of the second insulating layer 138. In another embodiment, the height of the second air spacer 150b is greater than 50% of the height of the second insulating layer 138. In another embodiment, the height of the second air spacer 150b is greater than 70% of the height of the second insulating layer 138. In yet another embodiment, the height of the second air spacer 150b is greater than 90% of the height of the second insulating layer 138.

[0104] As in Figure 1B As shown, a first air spacer 150a surrounds a first metal contact 142a, while a second air spacer 150b surrounds a second metal contact 142b. Although the horizontal cross-sections of the first air spacer 150a and the second air spacer 150b are rectangular, it should be understood that other shapes (e.g., circular, elliptical, or similar) may be used. Many variations, modifications, and substitutions will be recognized by those skilled in the art. Furthermore, although in Figure 1A and Figure 1B In the embodiment shown, two metal contacts are used for electrical connection to the first metal layer 132; however, it should be understood that only one of them may be used in other embodiments. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0105] Refer again Figure 1AMetal contact 142c is disposed in the second interlayer dielectric 140 for electrical connection to the second metal layer 136. Furthermore, metal contact 142d is disposed in the second interlayer dielectric 140 for electrical connection to the metal gate structure 126 of the field-effect transistor 103. First metal contact 142a, second metal contact 142b, metal contact 142c, and metal contact 142d are electrically connected to the M1 layer metal rail 146 for further wiring in subsequent stages. In some embodiments, the M1 layer metal rail 146 comprises copper or other suitable material.

[0106] Figure 2 This is a schematic diagram, illustrating a top view of a portion of another chip according to some embodiments. (Compared to...) Figure 1B The MIM capacitors shown are aligned differently in the Y direction; MIM capacitors 105a, 105b, 105c, 105d, 105e, and 105f are arranged in a diamond configuration. Multiple metal contacts (e.g., 142a and 142b) and multiple corresponding air spacers (e.g., 150a and 150b) are arranged accordingly. This allows for a high degree of design flexibility depending on the specific circumstances. Those skilled in the art will recognize many variations, modifications, and substitutions.

[0107] Figure 3 It is a flowchart illustrating an embodiment of method 300 according to some implementation methods. Figures 4A to 4D This is a cross-sectional schematic diagram, illustrating the cross-sections of multiple structures at various manufacturing stages according to some implementation methods. Figure 3 In the illustrated embodiment, method 300 includes operations 302, 304, 306, 308, 310, 312, 314, and 316. Additional operations may be performed. Furthermore, it should be understood that the above references... Figure 3 The order of operations discussed is provided for illustrative purposes, and similarly, other embodiments may utilize different orders. These different sequences of operations will be included within the scope of multiple embodiments.

[0108] In operation 302, a first metal layer 132, a first insulating layer 134, and a second metal layer 136 are fabricated on a substrate. In some embodiments, the first metal layer 132 and the second metal layer 136 may comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), aluminum (Al), or other suitable materials. In some embodiments, the first insulating layer 134 may comprise silicon dioxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), or other suitable materials. The first insulating layer 134 and the second metal layer 136 are horizontally surrounded by a second insulating layer 138. An interlayer dielectric (i.e., a second interlayer dielectric 140) is disposed on the second metal layer 136 and the second insulating layer 138. Details of these layers have been described above in reference. Figures 1A to 1B It has been described.

[0109] When dealing with a 304 error, such as in Figure 4A As shown, the second interlayer dielectric 140 and the second insulating layer 138 are etched to form a trench 402. The trench 402 extends perpendicularly in the Z direction from the top surface of the second interlayer dielectric 140 to the top surface of the first metal layer 132. Therefore, the trench 402 exposes the top surface of the first metal layer 132, enabling the fabrication of metal contacts electrically connected to the first metal layer 132 in a later stage. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0110] When operating 306, such as in Figure 4B As shown, dummy silicon spacers 404 are formed in trench 402. The dummy silicon spacers 404 are conformally formed in trench 402, covering the bottom and sidewalls of trench 402. The dummy silicon spacers 404 can be formed using techniques such as chemical vapor deposition (CVD), such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or similar methods. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0111] When operating 308, such as in Figure 4B As shown, the bottom portion of the dummy silicon spacer 404 is etched to expose the top surface of the first metal layer 132. Thus, metal contacts electrically connected to the first metal layer 132 can be established in a subsequent stage. The bottom portion of the dummy silicon spacer 404 can be etched using techniques such as dry etching (e.g., plasma etching, reactive ion etching (RIE), deep RIE, etc.) or wet etching (e.g., anisotropic wet etching). Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0112] In operation 310, such as in Figure 4BAs shown, a deposited metal contact layer 142b is formed. The metal contact layer 142b fills trench 402. The metal contact layer 142b can be formed using techniques such as chemical vapor deposition (e.g., metal-organic chemical vapor deposition (MOCVD)), electroplating, atomic layer deposition, physical vapor deposition (PVD), or similar methods. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0113] When operating 312, such as in Figure 4B As shown, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed. After the planarization process, excess portions of the dummy silicon spacers 404 and the metal contact layer 142b outside the trench 402 are removed, and this structure becomes... Figure 4B The structure is shown in the figure. Specifically, the metal contact layer 142b becomes a metal contact (e.g., a via) 142b. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0114] When operating 314, such as in Figure 4C As shown, dummy silicon spacer 404 is removed. After removing dummy silicon spacer 404, air spacer 150b is formed. (Refer to the above...) Figure 1A and Figure 1B As described, the air spacer 150b horizontally surrounds the metal contact 142b, thereby reducing edge capacitance. The dummy silicon spacer 404 can be removed using techniques such as wet etching (e.g., isotropic wet etching). Various types of etchants can be used depending on factors such as selectivity, uniformity, and contamination. Examples of etchants may include ammonia solution (NH3OH), KOH (potassium hydroxide), TMAH (tetramethylammonium hydroxide), and HF (hydrofluoric acid). Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0115] When operating 316, such as in Figure 4DAs shown, an ion implantation process is performed on the interlayer dielectric 140 to seal the air spacer 150b. In some embodiments, dopants such as xenon (Xe) and germanium (Ge) are implanted into the interlayer dielectric 140. When dopants are implanted into the interlayer dielectric 140, which comprises, for example, silicon dioxide, local stresses are generated due to the large atomic radii of such dopants (e.g., Xe and Ge). The local stresses in the interlayer dielectric 140 cause volume expansion of the interlayer dielectric 140 through mechanisms such as lattice distortion and expansion. As a result, pinch-off portions 410 are formed due to the volume expansion, and the air spacer 150b is sealed on top of them. It should be understood that the volume expansion during this "sealing" process can be horizontal or vertical. Therefore, the height of the air spacer 150b may be reduced due to vertical volume expansion. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0116] It should be understood that, despite Figures 4A to 4D The embodiment shown depicts only one metal contact, but two or more metal contacts can be similarly manufactured. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0117] It should also be noted that other steps can be followed to achieve more complex structural features. For example, an M1 layer can be subsequently fabricated for wiring. Those skilled in the art will recognize many variations, modifications, and substitutions.

[0118] Figure 5A This is a cross-sectional schematic diagram, illustrating a cross-sectional view of a wafer according to some embodiments. Figure 5B This is a schematic diagram illustrating some implementation methods. Figure 5A A top view of a portion of the chip. It should be understood that... Figure 5A and Figure 5B It is not drawn to scale.

[0119] With Figure 1A and Figure 1B The embodiment shown is similar, with the wafer including a front-end process MIM capacitor (or simply "MIM capacitor") 105'. Therefore, in reference... Figure 5A and Figure 5B for Figure 5A and Figure 5B The same features are no longer repeated in the description.

[0120] The main difference lies in the fact that the MIM capacitor 105' features a five-layer structure instead of a three-layer structure. Specifically, in addition to the first metal layer 132, the second metal layer 136, and the first insulating layer 134, the MIM capacitor 105' also includes a third metal layer 131 and a third insulating layer 133, as shown in... Figure 5AAs shown in the diagram, metal contacts (e.g., vias) 142c, 142b, and 142e are electrically connected to the second metal layer 136, the first metal layer 132, and the third metal layer 131, respectively. The third metal layer 131 is embedded in an oxide diffusion (“OD”) region 122 of the substrate. The top surface of the third metal layer 131 is coplanar with the top surface of the oxide diffusion region 122. A third insulating layer 133 is disposed between the first metal layer 132 and the third metal layer 131. Unlike in... Figure 1A In the embodiment shown, the first metal layer 132 is used in Figure 5A The configuration shown has sidewall sections for easy wiring.

[0121] Similarly, the metal contact 142e contacts the top surface of the third metal layer 131. Unlike conventional structures, the MIM capacitor 105' is characterized by an air spacer 150e surrounding the metal contact 142e. In other words, the metal contact 142e does not directly contact the interlayer dielectric 130. Air has a low dielectric constant (approximately 1.00059 at room temperature) compared to insulators and most semiconductor materials. As a result, the air spacer 150e can significantly reduce the edge capacitance between the metal contact 142e, the second insulating layer 138, and the first metal layer 132.

[0122] Despite Figure 5A In the illustrated embodiment, the height of the air spacer 150e is the same as the sum of the heights of the first interlayer dielectric 130 and the spacer 128, but it should be understood that this is not mandatory. In some embodiments, the top portion of the air spacer 150e may be occupied by the second interlayer dielectric 140 during manufacturing. However, even in this case, the air spacer 150e still functions to reduce edge capacitance. In one embodiment, the height of the air spacer 150e is greater than 30%, 50%, 70%, or 90% of the sum of the heights of the first interlayer dielectric 130 and the spacer 128.

[0123] As in Figure 5B As shown, a first air spacer 150e surrounds the metal contact 142e. Although the horizontal cross-section of the air spacer 150e is rectangular, it should be understood that other shapes are also possible (e.g., circular, elliptical, or similar). Many variations, modifications, and substitutions will be recognized by those skilled in the art. Furthermore, although in Figure 5A and Figure 5B In the embodiment shown, only one metal contact is used for electrical connection to the third metal layer 131; however, it should be understood that more than one (e.g., two) metal contacts may be used in other embodiments. Many variations, modifications, and substitutions will be recognized by those skilled in the art. Those skilled in the art will also understand that the manufacturing process is similar to... Figure 3 and Figures 4A to 4D The process is shown. It should also be noted that similar MIM capacitors with more than five layers (e.g., a seven-layer structure) can be manufactured similarly.

[0124] Figure 6A This is a cross-sectional schematic diagram illustrating an embodiment of a wafer according to some implementation methods. Figure 6B This is a schematic diagram illustrating some implementation methods. Figure 6A A top view of a portion of the chip. It should be understood that... Figure 6A and Figure 6B It is not drawn to scale.

[0125] With Figure 1A and Figure 1B The embodiment shown is similar, with the wafer including a front-end process MIM capacitor (or simply "MIM capacitor") 105". Therefore, in reference to... Figure 6A and Figure 6B for Figure 6A and Figure 6B The same features are no longer repeated in the description.

[0126] One of the main differences is that the MIM capacitor 105" features a five-layer structure instead of a three-layer structure. Specifically, in addition to the first metal layer 132, the second metal layer 136, and the first insulating layer 134, the MIM capacitor 105" also includes a third metal layer 131 and a third insulating layer 133, as shown in... Figure 6A As shown in the diagram, metal contacts (e.g., vias) 142c, 142b, and 142e are electrically connected to the second metal layer 136, the first metal layer 132, and the third metal layer 131, respectively. The third metal layer 131 is embedded in an oxide diffusion (“OD”) region 122 of the substrate. The top surface of the third metal layer 131 is coplanar with the top surface of the oxide diffusion region 122. A third insulating layer 133 is disposed between the first metal layer 132 and the third metal layer 131. Unlike in... Figure 1A In the embodiment shown, the first metal layer 132 is used in Figure 5A The configuration shown has sidewall sections for easy wiring.

[0127] Another key difference is the position of the air gap at 150°F. Unlike in... Figure 5A and Figure 5B In the embodiment shown, the spacer 128 includes a sidewall portion, in Figure 6AIn the illustrated embodiment, the spacer 128 does not include a sidewall portion. Instead, the air spacer 150f horizontally surrounds the first metal layer 132. The sidewall portion of the first metal layer 132 contacts the air spacer 150f and therefore does not contact the first interlayer dielectric 130. On the other hand, the air spacer 150f does not horizontally surround the metal contact 142e.

[0128] Because air has a low dielectric constant (approximately 1.00059 at room temperature) compared to insulators and most semiconductor materials, the air spacer 150f can significantly reduce the edge capacitance between the metal contact 142e and the first metal layer 132. Thus, although the air spacer 150f is placed in different locations, it still functions to reduce edge capacitance because the basic principle of the air spacer 150f remains unchanged.

[0129] Despite Figure 6A In the illustrated embodiment, the height of the air spacer 150f is the same as the sum of the heights of the first interlayer dielectric 130 and the spacer 128, but it should be understood that this is not mandatory. In some embodiments, the top portion of the air spacer 150f may be occupied by the second interlayer dielectric 140 during manufacturing. However, even in this case, the air spacer 150f still functions to reduce edge capacitance. In one embodiment, the height of the air spacer 150f is greater than 30%, 50%, 70%, or 90% of the sum of the heights of the first interlayer dielectric 130 and the spacer 128.

[0130] As in Figure 6B As shown, the air spacer 150f surrounds the first metal layer 132, rather than the non-metallic contact 142e. Although the horizontal cross-section of the air spacer 150f is rectangular, it should be understood that other shapes (e.g., circular, elliptical, or similar) may be used. Many variations, modifications, and substitutions will be recognized by those skilled in the art. Furthermore, although in Figure 6A and Figure 6B In the embodiment shown, only one metal contact is used for electrical connection to the third metal layer 131; however, it should be understood that more than one (e.g., two) metal contacts may be used in other embodiments. Many variations, modifications, and substitutions will be recognized by those skilled in the art. It should also be noted that similar MIM capacitors with more than five layers (e.g., a seven-layer structure) can be similarly manufactured.

[0131] Figure 7 It is a flowchart illustrating an embodiment of method 700 according to some implementation methods. Figures 8A to 8D This is a cross-sectional schematic diagram, illustrating the cross-sections of multiple structures at various manufacturing stages according to some implementation methods. Figure 7In the illustrated embodiment, method 700 includes operations 702, 704, 706, 708, and 710. Additional operations may be performed. Furthermore, it should be understood that the above references... Figure 7 The order of operations discussed is provided for illustrative purposes, and similarly, other embodiments may utilize different orders. These different sequences of operations will be included within the scope of multiple embodiments.

[0132] When operating 702, such as in Figure 8A As shown, a five-layer structure 800 is fabricated in a first interlayer dielectric 130 disposed on a substrate. The five-layer structure includes a first metal layer 132, a first insulating layer 134, a second metal layer 136, a third metal layer 131, and a third insulating layer 133. Spacers 128 are conformally disposed on the five-layer structure 800. Details of these layers have been described in the above references. Figures 6A to 6B It has been described.

[0133] When dealing with a 704 error, such as in Figure 8A As shown, a planarization process (e.g., CMP) is performed. After the planarization process, the top portion of the spacer 128 on the five-layer structure 800 is removed. The sidewall portions of the spacer 128 are then... Figure 8A The first metal layer 132, the first insulating layer 134, the second metal layer 136, and the third insulating layer 133 are arranged horizontally as shown. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0134] When operating 706, such as in Figure 8B As shown, a portion of the sidewall of spacer 128 is removed. After the sidewall of spacer 128 is removed, trench 802 is formed. Trench 802 exposes a portion of the top surface of the third metal layer 131 and surrounds the first metal layer 132 and the third insulating layer 133. As will be described below, trench 802 will be sealed on top in a later stage to form in Figure 6A The air spacer 150f is shown. In some embodiments, spacer 128 comprises silicon nitride (SiN), silicon oxynitride (SiNON), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or dummy silicon. In some embodiments, techniques such as wet etching (e.g., anisotropic wet etching) are used to remove sidewall portions of spacer 128. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0135] When operating 708, such as in Figure 8CAs shown, a second interlayer dielectric 140 is deposited on top of this structure. Because trench 802 is characterized by a high aspect ratio, the second interlayer dielectric 140 seals trench 802 from the top to form air spacers 150f. In some embodiments, the second interlayer dielectric 140 is deposited using techniques such as CVD, PECVD, sputtering, ALD, or similar methods. Many variations, modifications, and substitutions will be recognized by those skilled in the art. It should be understood that the second interlayer dielectric 140 may partially fill trench 802, and the height of the air spacers 150f may be less than the height of trench 802. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0136] When operating 710, such as in Figure 8D As shown, metal contact 142e is formed. Metal contact 142e extends vertically from the top surface of the second interlayer dielectric 140 to the top surface of the third metal layer 131, thereby providing an electrical connection to the third metal layer 131. In some embodiments, metal contact 142e is formed via photolithography, followed by etching of the bottom portions of the second interlayer dielectric 140, the first interlayer dielectric 130, and the spacer 128. Metal contact 142e is then formed using techniques such as chemical vapor deposition (e.g., metal-organic chemical vapor deposition (MOCVD)), electroplating, atomic layer deposition, physical vapor deposition (PVD), or similar methods. Many variations, modifications, and substitutions will be recognized by those skilled in the art. It should be understood that metal contacts 142b and 142c can be formed in a similar manner.

[0137] Overview

[0138] According to some aspects of this disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate; a first interlayer dielectric (ILD) disposed on the substrate; and a metal-insulator-metal (MIM) capacitor disposed in the first interlayer dielectric. The metal-insulator-metal capacitor includes: a first metal layer disposed on the substrate; a first insulating layer including a horizontal portion and a sidewall portion; a second metal layer, wherein the horizontal portion of the first insulating layer is disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer; a second insulating layer surrounding the sidewall portion of the first insulating layer; at least one metal contact extending vertically through the second insulating layer, wherein the lower end of the at least one metal contact contacts the top surface of the first metal layer; and at least one air spacer horizontally surrounding the at least one metal contact.

[0139] In some embodiments, in a semiconductor device, the height of the air spacer is greater than 30% of the height of the second insulating layer.

[0140] In some embodiments, in a semiconductor device, the height of the air spacer is greater than 90% of the height of the second insulating layer.

[0141] In some embodiments, the semiconductor device further includes a second interlayer dielectric disposed on the first interlayer dielectric.

[0142] In some embodiments, in a semiconductor device, the second interlayer dielectric seals the at least one air spacer at a top portion of the at least one air spacer.

[0143] In some embodiments, in a semiconductor device, the second interlayer dielectric is characterized by at least one dopant.

[0144] In some embodiments, in a semiconductor device, the at least one dopant comprises xenon (Xe).

[0145] In some embodiments, in a semiconductor device, the at least one dopant comprises germanium (Ge).

[0146] In some embodiments, in a semiconductor device, a top surface of the second metal layer is coplanar with a top surface of the sidewall portion of the first insulating layer.

[0147] In some embodiments, in a semiconductor device, the width of the first metal layer is greater than the width of the horizontal portion of the first insulating layer.

[0148] Based on some aspects of this disclosure, a method is provided. The method includes: fabricating a metal-insulator-metal (MIM) capacitor in a first interlayer dielectric (ILD) disposed on a substrate, wherein the MIM capacitor includes: a first metal layer disposed on the substrate; a first insulating layer including a horizontal portion and a sidewall portion; a second metal layer, wherein the horizontal portion of the first insulating layer is disposed between the first metal layer and a second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer; and a second insulating layer surrounding the sidewall portion of the first insulating layer; depositing the second interlayer dielectric on the first interlayer dielectric; etching the second interlayer dielectric and the second insulating layer to form a trench, exposing a portion of the top surface of the first metal layer; forming dummy silicon spacers in the trench; etching the bottom portion of the dummy silicon spacers to expose this portion of the top surface of the first metal layer; depositing a metal contact layer to fill the trench; performing a planarization process; removing the dummy silicon spacers to form air spacers horizontally surrounding the metal contact layer in the trench; and performing an ion implantation process on the second interlayer dielectric to seal the air spacers.

[0149] In some embodiments, forming the dummy silicon spacer in a method of manufacturing a semiconductor device includes conformally forming the dummy silicon spacer on the trench.

[0150] In some embodiments, in a method of manufacturing a semiconductor device, a lower end of the metal contact layer in the trench contacts a portion of the top surface of the first metal layer.

[0151] In some embodiments, in a method of manufacturing a semiconductor device, the planarization process removes an excess portion of the dummy silicon spacer and the metal contact layer outside the trench.

[0152] In some embodiments, removing the dummy silicon spacer in a method of manufacturing a semiconductor device includes etching the dummy silicon spacer using a wet etching process.

[0153] In some embodiments, in a method of manufacturing a semiconductor device, the ion implantation process introduces at least one dopant into the second interlayer dielectric.

[0154] In some embodiments, the at least one dopant in the method of manufacturing a semiconductor device comprises xenon (Xe).

[0155] In some embodiments, the at least one dopant in the method of manufacturing a semiconductor device comprises germanium (Ge).

[0156] According to some aspects of this disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate; a first interlayer dielectric (ILD) disposed on the substrate; and a metal-insulator-metal (MIM) capacitor disposed in the first interlayer dielectric. The MIM capacitor includes: a third metal layer disposed on the substrate; a third insulating layer disposed on the third metal layer; a first metal layer disposed on the third insulating layer and including a horizontal portion and a sidewall portion; the first insulating layer including a horizontal portion and a sidewall portion, the sidewall portion of the first metal layer horizontally surrounding the sidewall portion of the first insulating layer; a second metal layer, wherein the horizontal portion of the first insulating layer is disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer; at least one metal contact extending vertically through the first interlayer dielectric, wherein the lower end of the at least one metal contact contacts the top surface of the third metal layer; and an air spacer horizontally surrounding the sidewall portion of the first metal layer.

[0157] In some embodiments, the semiconductor device further includes a second interlayer dielectric. The second interlayer dielectric is disposed on the first interlayer dielectric, and wherein the second interlayer dielectric seals the air spacer at a top portion of the air spacer.

[0158] Further embodiments of this disclosure provide a semiconductor device comprising: a substrate, a first interlayer dielectric, a metal-insulator-metal (MIM) capacitor, and a second interlayer dielectric. The first interlayer dielectric is disposed on the substrate. The metal-insulator-metal MIM capacitor is disposed in the first interlayer dielectric and includes: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, at least one metal contact, and at least one air spacer. The first metal layer is disposed on the substrate. The first insulating layer includes a horizontal portion and a sidewall portion. The second metal layer includes the horizontal portion of the first insulating layer disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer. The second insulating layer surrounds the sidewall portion of the first insulating layer. At least one metal contact extends vertically through the second insulating layer, wherein a lower end of the at least one metal contact contacts a top surface of the first metal layer. At least one air spacer horizontally surrounds the at least one metal contact. The second interlayer dielectric is disposed on the first interlayer dielectric.

[0159] In some embodiments, the second interlayer dielectric seals the at least one air spacer at a top portion of the at least one air spacer.

[0160] In some embodiments, a top surface of the second metal layer is coplanar with a top surface of the sidewall portion of the first insulating layer.

[0161] The foregoing has outlined several features of various embodiments, enabling those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art should understand that they may readily use this disclosure as the basis for the design or modification of other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: One substrate; A first interlayer dielectric is disposed on the substrate; and A metal-insulator-metal capacitor is disposed in the first interlayer dielectric, the metal-insulator-metal capacitor comprising: A first metal layer is disposed on the substrate; A first insulating layer comprising a horizontal portion and a sidewall portion; A second metal layer, wherein the horizontal portion of the first insulating layer is disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer; A second insulating layer surrounds the sidewall portion of the first insulating layer; At least one metal contact extends vertically through the second insulating layer, wherein a lower end of the at least one metal contact contacts a top surface of the first metal layer; and At least one air spacer is horizontally surrounding the at least one metal contact.

2. The semiconductor device as claimed in claim 1, characterized in that, The height of the air spacer is greater than 30% of the height of the second insulating layer.

3. The semiconductor device as claimed in claim 1, characterized in that, The height of the air gap is greater than 90% of the height of the second insulating layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the second metal layer is coplanar with the top surface of the sidewall portion of the first insulating layer.

5. The semiconductor device as claimed in claim 1, characterized in that, The width of the first metal layer is greater than the width of the horizontal portion of the first insulating layer.

6. A semiconductor device, characterized in that, Include: One substrate; A first interlayer dielectric is disposed on the substrate; and A metal-insulator-metal capacitor is disposed in the first interlayer dielectric, the metal-insulator-metal capacitor comprising: A third metal layer is disposed on the substrate; A third insulating layer is disposed on the third metal layer; A first metal layer is disposed on the third insulating layer and includes a horizontal portion and a sidewall portion; A first insulating layer includes a horizontal portion and a sidewall portion, the sidewall portion of the first metal layer horizontally surrounding the sidewall portion of the first insulating layer; A second metal layer, wherein the horizontal portion of the first insulating layer is disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer; At least one metal contact extends vertically through the first interlayer dielectric, wherein a lower end of the at least one metal contact contacts a top surface of the third metal layer; and An air gap is horizontally surrounding the sidewall portion of the first metal layer.

7. The semiconductor device as claimed in claim 6, characterized in that, Also includes: A second interlayer dielectric is disposed on the first interlayer dielectric, wherein the second interlayer dielectric seals the air spacer at a top portion of the air spacer.

8. A semiconductor device, characterized in that, Include: One substrate; A first interlayer dielectric is disposed on the substrate; A metal-insulator-metal capacitor is disposed in the first interlayer dielectric, the metal-insulator-metal capacitor comprising: A first metal layer is disposed on the substrate; A first insulating layer comprising a horizontal portion and a sidewall portion; A second metal layer, wherein the horizontal portion of the first insulating layer is disposed between the first metal layer and the second metal layer, and the sidewall portion of the first insulating layer horizontally surrounds the second metal layer; A second insulating layer surrounds the sidewall portion of the first insulating layer; At least one metal contact extends vertically through the second insulating layer, wherein a lower end of the at least one metal contact contacts a top surface of the first metal layer; and At least one air spacer, horizontally surrounding the at least one metal contact; as well as A second interlayer dielectric is disposed on the first interlayer dielectric.

9. The semiconductor device as claimed in claim 8, characterized in that, The second interlayer dielectric seals the at least one air spacer at one top portion.

10. The semiconductor device as claimed in claim 8, characterized in that, The top surface of the second metal layer is coplanar with the top surface of the sidewall portion of the first insulating layer.

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