Semiconductor device

Abstract

The utility model provides a kind of semiconductor device, comprising: substrate, including substrate and first interlayer dielectric layer on substrate;Capacitor structure is located first interlayer dielectric layer, capacitor structure includes at least two layers of electrode plate and the dielectric layer between adjacent electrode plate;Second interlayer dielectric layer is located first interlayer dielectric layer, and second interlayer dielectric layer covers capacitor structure;First conductive structure and second conductive structure, from first interlayer dielectric layer below capacitor structure upwards and extend to the second interlayer dielectric layer of partial thickness in capacitor structure, first conductive structure is electrically connected with the even layer electrode plate in capacitor structure, and second conductive structure is electrically connected with the odd layer electrode plate in capacitor structure.The technical scheme of the utility model makes the conductive structure above capacitor structure clearance while connecting capacitor structure into circuit.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device. Background Technology

[0002] When using hybrid bonding technology to fabricate CIS (CMOS Image Sensor) products, the top metal layer in the interconnect structure is required to achieve hybrid bonding. CIS products generally have a capacitor structure. A metal layer is formed above the electrode plate in the capacitor structure to connect the electrode plate to the bonding interface. The metal layer above the electrode plate also needs to be electrically connected to the top metal layer in the interconnect structure to connect the electrode plate into the circuit.

[0003] However, connecting the electrode plates into the circuit by forming a metal layer above the electrode plates in the capacitor structure will prevent the formation of structures required for CIS products such as antennas in the area above the capacitor structure.

[0004] Therefore, how to connect the capacitor structure into the circuit while keeping the metal layer above the capacitor structure clear is an urgent problem to be solved. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor device that allows the conductive structure above the capacitor structure to be cleared while connecting the capacitor structure into the circuit.

[0006] To achieve the above objectives, this utility model provides a semiconductor device, comprising:

[0007] The substrate includes a substrate and a first interlayer dielectric layer located on the substrate;

[0008] A capacitor structure is located on the first interlayer dielectric layer, the capacitor structure including at least two electrode plates and a dielectric layer located between adjacent electrode plates;

[0009] The second interlayer dielectric layer is located on the first interlayer dielectric layer and covers the capacitor structure;

[0010] A first conductive structure and a second conductive structure extend upward from the first interlayer dielectric layer below the capacitor structure through the capacitor structure and into the second interlayer dielectric layer of a certain thickness. The first conductive structure is electrically connected to the even-numbered electrode plate in the capacitor structure, and the second conductive structure is electrically connected to the odd-numbered electrode plate in the capacitor structure.

[0011] Optionally, the top surface of the first conductive structure is flush with the top surface of the second conductive structure.

[0012] Optionally, the semiconductor device further includes:

[0013] A first interconnect structure and a second interconnect structure extend from the first interlayer dielectric layer surrounding the capacitor structure to the top surface of the second interlayer dielectric layer. The first interconnect structure is electrically connected to the first conductive structure below the capacitor structure, and the second interconnect structure is electrically connected to the second conductive structure below the capacitor structure.

[0014] Optionally, a first opening is formed in the odd-numbered electrode plates, and at least one odd-numbered dielectric layer extends to the inner wall of at least one first opening. The first conductive structure penetrates the even-numbered electrode plates and the dielectric layer in the first opening region. A second opening is formed in the even-numbered electrode plates, and the capacitor structure includes at least three electrode plates. At least one even-numbered dielectric layer extends to the inner wall of at least one second opening, and the second conductive structure penetrates the odd-numbered electrode plates and the dielectric layer in the second opening region.

[0015] Optionally, the first interlayer dielectric layer includes a first insulating layer and a second insulating layer stacked from bottom to top, the second interlayer dielectric layer includes a third insulating layer and a fourth insulating layer stacked from bottom to top, the first conductive structure includes a first conductive layer and a first conductive plug electrically connected, the second conductive structure includes a second conductive layer and a second conductive plug electrically connected, the first conductive layer and the second conductive layer extend from the top surface of the first insulating layer into the first insulating layer, and the first conductive plug and the second conductive plug respectively extend upward from the top surface of the first conductive layer and the second conductive layer through the second insulating layer and the capacitor structure and extend to the top surface of the third insulating layer.

[0016] Optionally, the first interconnect structure includes multiple layers of third conductive layers and third conductive plugs connecting adjacent third conductive layers, the second interconnect structure includes multiple layers of fourth conductive layers and fourth conductive plugs connecting adjacent fourth conductive layers, the first conductive structure below the capacitor structure is electrically connected to any third conductive layer other than the top third conductive layer, and the second conductive structure below the capacitor structure is electrically connected to any fourth conductive layer other than the top fourth conductive layer.

[0017] Optionally, the dielectric layer between adjacent electrode plates extends at least to cover the sidewall of the electrode plate below the dielectric layer.

[0018] Optionally, the semiconductor device further includes:

[0019] The device structure is located in the substrate, and the first interconnect structure and the second interconnect structure are electrically connected to the device structure, respectively.

[0020] Optionally, the number of both the first conductive structure and the second conductive structure is at least two.

[0021] Optionally, the area of ​​the capacitor structure is greater than 35 μm. 35μm.

[0022] Optionally, the capacitor structure is a MIM capacitor.

[0023] Compared with the prior art, in the semiconductor device provided by this utility model, since the first conductive structure and the second conductive structure penetrate upward through the first interlayer dielectric layer below the capacitor structure and extend into the second interlayer dielectric layer of a certain thickness, the first conductive structure is electrically connected to the even-numbered electrode plate in the capacitor structure, and the second conductive structure is electrically connected to the odd-numbered electrode plate in the capacitor structure. This allows the capacitor structure to be connected into the circuit through the first conductive structure and the second conductive structure below the capacitor structure. Consequently, the remaining thickness of the second interlayer dielectric layer above the capacitor structure can be cleared of conductive structures, allowing the area above the capacitor structure with clear conductive structures to be used to fabricate other structures required for the semiconductor device. Furthermore, the capacitor structure can contain multiple layers of the electrode plates, and an effective capacitance can be formed between all adjacent electrode plates. All capacitors are connected in parallel, which greatly increases the total capacitance value and realizes a large capacitor structural design. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the semiconductor device according to Embodiment 1 of this utility model;

[0025] Figure 2 This is a schematic diagram of the structure of the semiconductor device according to Embodiment 2 of this utility model;

[0026] Figures 3a-3h This is a schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention.

[0027] Among them, the appendix Figures 1-3h The annotations in the attached figures are explained as follows:

[0028] 11-Substrate; 12-First interlayer dielectric layer; 121-First insulating layer; 122-Second insulating layer; 131-First electrode plate; 132-First dielectric layer; 133-Second electrode plate; 134-Second dielectric layer; 135-Third electrode plate; 136-First opening; 137-Second opening; 14-Second interlayer dielectric layer; 141-Third insulating layer; 142-Fourth insulating layer; 15-First conductive structure; 151-First conductive layer; 152-First conductive plug; 16-Second conductive structure; 161-Second conductive layer; 162-Second conductive plug; 17-First interconnect structure; 171-Third conductive layer; 172-Third conductive plug; 18-Second interconnect structure; 181-Fourth conductive layer; 182-Fourth conductive plug. Detailed Implementation

[0029] To make the objectives, advantages, and features of this utility model clearer, the semiconductor device proposed by this utility model will be described in further detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the explanation of the embodiments of this utility model.

[0030] One embodiment of this utility model provides a semiconductor device, comprising: a substrate, including a base and a first interlayer dielectric layer located on the substrate; a capacitor structure located on the first interlayer dielectric layer, the capacitor structure including at least two electrode plates and a dielectric layer located between adjacent electrode plates; a second interlayer dielectric layer located on the first interlayer dielectric layer and covering the capacitor structure; a first conductive structure and a second conductive structure extending upward through the first interlayer dielectric layer below the capacitor structure and into a portion of the thickness of the second interlayer dielectric layer, the first conductive structure being electrically connected to an even-numbered electrode plate in the capacitor structure, and the second conductive structure being electrically connected to an odd-numbered electrode plate in the capacitor structure.

[0031] See below. Figures 1-3h The semiconductor device provided in this embodiment will be described in detail. Figures 1-3h It is also a longitudinal cross-sectional diagram.

[0032] The substrate includes a substrate 11 and a first interlayer dielectric layer 12 located on the substrate 11.

[0033] The substrate 11 can be made of any suitable substrate known to those skilled in the art, such as at least one of the following materials: silicon, germanium, silicon germanium, silicon carbon, silicon carbon germanium, indium arsenide, gallium arsenide, indium phosphide, or silicon on insulator.

[0034] The first interlayer dielectric layer 12 can be a multilayer stacked structure. In one embodiment, the first interlayer dielectric layer 12 includes a first insulating layer 121 and a second insulating layer 122 stacked from bottom to top. The materials of the first insulating layer 121 and the second insulating layer 122 may include at least one insulating material selected from silicon oxide, silicon oxynitride, and nitrogen-doped silicon carbide.

[0035] In one embodiment, the first insulating layer 121 may include a multilayer stacked structure, and the second insulating layer 122 may also include a multilayer stacked structure. For example, the second insulating layer 122 may include a nitrogen-doped silicon carbide layer and a silicon oxide layer stacked from bottom to top, wherein the nitrogen-doped silicon carbide layer is used as a diffusion barrier layer and an etch stop layer.

[0036] The capacitor structure is located on the first interlayer dielectric layer 12, and the capacitor structure includes at least two electrode plates and a dielectric layer located between adjacent electrode plates.

[0037] In one embodiment, in two adjacent electrode plates, the projection of the upper electrode plate onto the substrate is located within the projection range of the lower electrode plate onto the substrate.

[0038] In one embodiment, a first opening is formed in the odd-numbered layer of electrode plates, the first opening penetrating the odd-numbered layer of electrode plates in which it is located. The capacitor structure includes at least two layers of electrode plates, and at least one odd-numbered dielectric layer on the odd-numbered layer of electrode plates extends to the inner wall of at least one first opening. A second opening is formed in the even-numbered layer of electrode plates, the second opening penetrating the even-numbered layer of electrode plates in which it is located. The capacitor structure includes at least three layers of electrode plates, and at least one even-numbered dielectric layer on the even-numbered layer of electrode plates extends to the inner wall of at least one second opening. Here, "odd-numbered layer" refers to the odd-numbered layer from bottom to top, and "even-numbered layer" refers to the even-numbered layer from bottom to top.

[0039] For example, when the capacitor structure includes two electrode plates, the inner wall of the first opening in the first electrode plate is covered by the first dielectric layer, and the inner wall of the second opening in the second electrode plate is not covered by the dielectric layer; when the capacitor structure includes three electrode plates, the inner wall of the first opening in the first electrode plate is covered by the first dielectric layer, the inner wall of the second opening in the second electrode plate is covered by the second dielectric layer, and the inner wall of the first opening in the third electrode plate is not covered by the dielectric layer; when the capacitor structure includes four electrode plates, the inner wall of the first opening in the first electrode plate is covered by the first dielectric layer, the inner wall of the second opening in the second electrode plate is covered by the second dielectric layer, the inner wall of the first opening in the third electrode plate is covered by the third dielectric layer, and the inner wall of the second opening in the fourth electrode plate is not covered by the dielectric layer.

[0040] In one embodiment, the first openings in all odd-numbered electrode plates are aligned in a direction perpendicular to the substrate, and the second openings in all even-numbered electrode plates are aligned in a direction perpendicular to the substrate.

[0041] Among them, Figure 1 In the embodiment shown, the capacitor structure includes a first electrode plate 131, a second electrode plate 133, and a first dielectric layer 132 located between the first electrode plate 131 and the second electrode plate 133. A first opening is formed in the first electrode plate 131, the first opening penetrates the first electrode plate 131, and the first dielectric layer 132 extends to the inner wall of the first opening. The inner wall of the second opening in the second electrode plate 133 is not covered by the dielectric layer.

[0042] exist Figure 2 In the illustrated embodiment, the capacitor structure includes a first electrode plate 131, a second electrode plate 133, a third electrode plate 135, a first dielectric layer 132 located between the first electrode plate 131 and the second electrode plate 133, and a second dielectric layer 134 located between the second electrode plate 133 and the third electrode plate 135. Both the first electrode plate 131 and the third electrode plate 135 have a first opening. The first opening in the first electrode plate 131 penetrates the first electrode plate 131, and the first opening in the third electrode plate 135 penetrates the third electrode plate 135. The first openings in the first electrode plate 131 and the third electrode plate 135 are aligned in a direction perpendicular to the substrate. The first dielectric layer 132 also extends to the inner wall of the first opening in the first electrode plate 131, and the inner wall of the first opening in the third electrode plate 135 is not covered by the dielectric layer. A second opening is formed in the second electrode plate 133, penetrating the second electrode plate 133. The second dielectric layer 134 also extends to the inner wall of the second opening.

[0043] Preferably, the dielectric layer between adjacent electrode plates extends at least to cover the sidewall of the electrode plate below the dielectric layer, so that the dielectric layer can cover and enclose the electrode plate below it, achieving complete isolation between the electrode plates above and below the dielectric layer, and preventing electrical breakdown between adjacent electrode plates due to defects or excessive proximity.

[0044] In one embodiment, the dielectric layer between adjacent electrode plates extends to cover the sidewall of the electrode plate below the dielectric layer; or, the dielectric layer between adjacent electrode plates extends to cover the sidewall of the electrode plate below the dielectric layer and the first interlayer dielectric layer 12 surrounding the bottommost electrode plate.

[0045] Among them, Figure 2 In the illustrated embodiment, the first dielectric layer 132 extends from between the first electrode plate 131 and the second electrode plate 133 to cover the sidewall of the first electrode plate 131 below the first dielectric layer 132 and the first interlayer dielectric layer 12 around the first electrode plate 131. The second dielectric layer 134 extends from between the second electrode plate 133 and the third electrode plate 135 to cover the sidewall of the second electrode plate 133 below the second dielectric layer 134 and the first dielectric layer 132 around the first electrode plate 131.

[0046] Preferably, the area of ​​the capacitor structure is greater than 35 μm. 35μm.

[0047] The electrode plate can be made of metal (e.g., aluminum, copper, or titanium), metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), or polycrystalline silicon. When the electrode plate is made of metal or metal nitride, the capacitor structure is a MIM (Metal Insulator Metal) capacitor.

[0048] The dielectric layer can be made of various insulating materials known to those skilled in the art. Preferably, the dielectric layer is made of a high-k (relative permittivity) material with a relative permittivity greater than 7.9 (7.9 is the relative permittivity of silicon nitride), such as a metal oxide, to achieve a higher capacitance density in the capacitor structure. It should be noted that the dielectric layer can also be made of other materials such as silicon oxide or silicon oxynitride.

[0049] The thicknesses of the electrode plate and the dielectric layer can be defined according to the capacitance value required by the capacitor structure. In one embodiment, the thickness of the electrode plate is 100 Å to 600 Å, and the thickness of the dielectric layer is 50 Å to 150 Å.

[0050] In one embodiment, the dielectric layer comprises a first zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer, and a second zirconium oxide (ZrO2) layer stacked from bottom to top. In one embodiment, the thickness of the first zirconium oxide layer is 20 Å to 30 Å (inclusive), the thickness of the aluminum oxide layer is 0 Å to 45 Å (exclusive of 0 Å but inclusive of 45 Å), and the thickness of the second zirconium oxide layer is 20 Å to 30 Å (inclusive of 20 Å and 30 Å).

[0051] The second interlayer dielectric layer 14 is located on the first interlayer dielectric layer 12, and the second interlayer dielectric layer 14 covers the capacitor structure.

[0052] The second interlayer dielectric layer 14 can be a multilayer stacked structure. In one embodiment, the second interlayer dielectric layer 14 includes a third insulating layer 141 and a fourth insulating layer 142 stacked from bottom to top. The material of the third insulating layer 141 and the fourth insulating layer 142 may include at least one insulating material such as silicon oxide, silicon oxynitride, and nitrogen-doped silicon carbide.

[0053] In one embodiment, the third insulating layer 141 can be a single-layer structure or a multi-layer stacked structure, and the fourth insulating layer 142 can be a single-layer structure or a multi-layer stacked structure. For example, the third insulating layer 141 may include a silicon oxide layer; the fourth insulating layer 142 may include a silicon nitride layer and a silicon oxide layer stacked from bottom to top, wherein the silicon nitride layer is used as an etch stop layer.

[0054] A first conductive structure 15 and a second conductive structure 16 extend upward through the first interlayer dielectric layer 12 below the capacitor structure and into a portion of the thickness of the second interlayer dielectric layer 14. The first conductive structure 15 is electrically connected to the even-numbered electrode plate in the capacitor structure and is insulated from the odd-numbered electrode plate in the capacitor structure. The second conductive structure 16 is electrically connected to the odd-numbered electrode plate in the capacitor structure and is insulated from the even-numbered electrode plate in the capacitor structure.

[0055] In one embodiment, the capacitor structure comprises at least three electrode plates. Since the first conductive structure 15 is electrically connected to the even-numbered electrode plates and the second conductive structure 16 is electrically connected to the odd-numbered electrode plates, each electrode plate in the capacitor structure is electrically connected to the first conductive structure 15 and the second conductive structure 16 via an interlocking structure. This allows effective capacitance to be formed between all adjacent electrode plates, and all capacitors are connected in parallel, greatly increasing the total capacitance value. This significantly improves the capacitance density in the multi-layer electrode plate structure, resulting in lower noise, higher signal integrity, higher accuracy, stronger energy storage and voltage regulation capabilities, and the ability to meet specific circuit requirements. The more electrode plates there are, the larger the capacitance value of the capacitor structure.

[0056] For example, in Figure 2 In the illustrated embodiment, the capacitor structure includes three electrode plates: a first electrode plate 131, a second electrode plate 133, and a third electrode plate 135. The first conductive structure 15 is electrically connected to the second electrode plate 133, and the second conductive structure 16 is electrically connected to the first electrode plate 131 and the third electrode plate 135. A first capacitor is formed between the first electrode plate 131 and the second electrode plate 133, and a second capacitor is formed between the second electrode plate 133 and the third electrode plate 135. The first capacitor and the second capacitor are connected in parallel, and the total capacitance of the capacitor structure is the sum of the capacitance values ​​of the first capacitor and the second capacitor.

[0057] The top surfaces of the first conductive structure 15 and the second conductive structure 16 are flush.

[0058] Since a first opening is formed in the odd-numbered electrode plate, the first conductive structure 15 penetrates the even-numbered electrode plate and the dielectric layer of the first opening region, thereby electrically connecting the first conductive structure 15 to the even-numbered electrode plate of the first opening region. Since a second opening is formed in the even-numbered electrode plate, the second conductive structure 16 penetrates the odd-numbered electrode plate and the dielectric layer of the second opening region, thereby electrically connecting the second conductive structure 16 to the odd-numbered electrode plate of the second opening region. The structure of the first opening region refers to the portion of the corresponding structure whose projection on the odd-numbered electrode plate is located within the first opening, and the structure of the second opening region refers to the portion of the corresponding structure whose projection on the even-numbered electrode plate is located within the second opening.

[0059] For example, in Figure 2In the illustrated embodiment, the first conductive structure 15 penetrates the second electrode plate 133, the first dielectric layer 132, and the second dielectric layer 134 of the first opening region, such that the first conductive structure 15 is electrically connected to the second electrode plate 133 of the first opening region, and the first conductive structure 15 is insulated from the first electrode plate 131 and the third electrode plate 135; the second conductive structure 16 penetrates the first electrode plate 131, the third electrode plate 135, the first dielectric layer 132, and the second dielectric layer 134 of the second opening region, such that the second conductive structure 16 is electrically connected to the first electrode plate 131 and the third electrode plate 135 of the second opening region, and the second conductive structure 16 is insulated from the second electrode plate 133.

[0060] Preferably, the number of the first conductive structure 15 and the second conductive structure 16 is at least two, which enables the reduction of resistance, the improvement of current distribution uniformity, and the optimization of high-frequency performance. In other embodiments, the number of the first conductive structure 15 and the second conductive structure 16 may be one.

[0061] In one embodiment, the first conductive structure 15 includes a first conductive layer 151 and a first conductive plug 152 electrically connected, and the second conductive structure 16 includes a second conductive layer 161 and a second conductive plug 162 electrically connected. The first conductive layer 151 and the second conductive layer 161 extend from the top surface of the first insulating layer 121 into the first insulating layer 121. The first conductive plug 152 and the second conductive plug 162 respectively extend upward from the top surfaces of the first conductive layer 151 and the second conductive layer 161, penetrating the second insulating layer 122 and the capacitor structure, and extending to the top surface of the third insulating layer 141 (i.e., penetrating the third insulating layer 141). The fourth insulating layer 142 covers the first conductive plug 152 and the second conductive plug 162. It should be noted that the first conductive structure 15 may only include, as shown in the example below. Figure 1 and Figure 2 As shown, there is a first conductive layer 151 and a first conductive plug 152. The second conductive structure 16 may only include, as shown, a first conductive layer 151 and a first conductive plug 152. Figure 1 and Figure 2 The first conductive structure 15 may comprise multiple layers of the first conductive layer 151 and multiple layers of the first conductive plug 152, and the second conductive structure 16 may comprise multiple layers of the second conductive layer 161 and multiple layers of the second conductive plug 162. Figure 1 and Figure 2The diagram shows the top first conductive layer 151, the top first conductive plug 152, the top second conductive layer 161, and the top second conductive plug 162. The other layers, the first conductive layer 151 and the first conductive plug 152, are below the top first conductive layer 151, and the other layers, the second conductive layer 161 and the second conductive plug 162, are below the top second conductive layer 161.

[0062] The area of ​​the capacitor structure is greater than 35 μm. At 35μm, the area of ​​the capacitor structure allows the distance between the first conductive structure 15 and the second conductive structure 16 to be large enough, avoiding the high-frequency performance being affected by the distance between the first conductive structure 15 and the second conductive structure 16 being too small.

[0063] The materials of the first conductive structure 15 and the second conductive structure 16 may include metallic materials such as copper.

[0064] The semiconductor device further includes: a first interconnect structure 17 and a second interconnect structure 18, extending from the first interlayer dielectric layer 12 surrounding the capacitor structure to the top surface of the second interlayer dielectric layer 14. The first interconnect structure 17 is electrically connected to the first conductive structure 15 below the capacitor structure, and the second interconnect structure 18 is electrically connected to the second conductive structure 16 below the capacitor structure. This allows voltage to be applied to the even-numbered electrode plates through the first interconnect structure 17 and the first conductive structure 15, and voltage to be applied to the odd-numbered electrode plates through the second interconnect structure 18 and the second conductive structure 16. In other words, the capacitor structure is connected into the circuit through the first conductive structure 15 and the second conductive structure 16 below the capacitor structure.

[0065] In one embodiment, the first interconnect structure 17 includes multiple layers of third conductive layers 171 and third conductive plugs 172 connecting adjacent third conductive layers 171, and the second interconnect structure 18 includes multiple layers of fourth conductive layers 181 and fourth conductive plugs 182 connecting adjacent fourth conductive layers 181. The first conductive structure 15 below the capacitor structure is electrically connected to any third conductive layer 171 other than the top third conductive layer 171, and the second conductive structure 16 below the capacitor structure is electrically connected to any fourth conductive layer 181 other than the top fourth conductive layer 181.

[0066] In one embodiment, the first conductive layer 151 is electrically connected to any third conductive layer 171 other than the top third conductive layer 171, and the first conductive layer 151 and any third conductive layer 171 other than the top third conductive layer 171 are located in the same layer; the second conductive layer 161 is electrically connected to any fourth conductive layer 181 other than the top fourth conductive layer 181, and the second conductive layer 161 and any fourth conductive layer 181 other than the top fourth conductive layer 181 are located in the same layer. In this configuration, the first conductive layer 151 and the third conductive layer 171 located further down in the first interconnect structure 17 are located on the same layer, and the second conductive layer 161 and the fourth conductive layer 181 located further down in the second interconnect structure 18 are located on the same layer. That is, the lower the position of the capacitor structure in the semiconductor device, the more layers of the third conductive layer 171 and the third conductive plug 172 that are higher than the first conductive structure 15 in the first interconnect structure 17, and the more layers of the fourth conductive layer 181 and the fourth conductive plug 182 that are higher than the second conductive structure 16 in the second interconnect structure 18. In other words, the portion of the first interconnect structure 17 that is higher than the first conductive structure 15 is longer, and the portion of the second interconnect structure 18 that is higher than the second conductive structure 16 is longer, resulting in a larger area of ​​clear conductive structure above the capacitor structure.

[0067] exist Figure 1 and Figure 2In the illustrated embodiment, the first conductive layer 151 is electrically connected to the second-to-top third conductive layer 171, and the first conductive layer 151 and the second-to-top third conductive layer 171 are located in the same layer. The first conductive plug 152 and the top third conductive plug 172 are located in the same layer. The second-to-top third conductive layer 171 extends from the top of the first insulating layer 121 into the first insulating layer 121. The third conductive layers 171 and the third conductive plugs 172 below the second-to-top third conductive layer 171 are located in the first insulating layer 121. The top third conductive plug 172 extends upward from the top of the second-to-top third conductive layer 171 through the second insulating layer 122 and the third insulating layer 141. The top third conductive layer 171 extends upward from the top of the top third conductive plug 172 through the fourth insulating layer. 142; The second conductive layer 161 is electrically connected to the fourth conductive layer 181 of the next-top layer. The second conductive layer 161 and the fourth conductive layer 181 of the next-top layer are located in the same layer. The second conductive plug 162 and the fourth conductive plug 182 of the top layer are located in the same layer. The fourth conductive layer 181 of the next-top layer extends from the top of the first insulating layer 121 into the first insulating layer 121. The fourth conductive layers 181 and the fourth conductive plugs 182 below the fourth conductive layer 181 are located in the first insulating layer 121. The fourth conductive plug 182 of the top layer penetrates the second insulating layer 122 and the third insulating layer 141 from the top of the fourth conductive layer 181 of the next-top layer. The fourth conductive layer 181 of the top layer penetrates the fourth insulating layer 142 from the top of the fourth conductive plug 182 of the top layer. The fourth insulating layer 142 above the capacitor structure (i.e., the area within the dashed box) has no conductive structure.

[0068] The materials of the first interconnect structure 17 and the second interconnect structure 18 may include metal materials such as copper.

[0069] The semiconductor device further includes a device structure (not shown) located in the substrate, wherein the first interconnect structure 17 and the second interconnect structure 18 are electrically connected to the device structure.

[0070] The device structure can be an active device structure (such as a transistor or diode) or a passive device structure (such as a resistor or inductor).

[0071] The first interconnect structure 17 and the second interconnect structure 18 may be electrically connected to different structures in the same device structure, or the first interconnect structure 17 and the second interconnect structure 18 may be electrically connected to different device structures respectively.

[0072] In one embodiment, the top third conductive layer 171 of the first interconnect structure 17 is connected to the positive terminal of the power supply, and the top fourth conductive layer 181 of the second interconnect structure 18 is connected to the negative terminal of the power supply; or, the top third conductive layer 171 of the first interconnect structure 17 is connected to the negative terminal of the power supply, and the top fourth conductive layer 181 of the second interconnect structure 18 is connected to the positive terminal of the power supply.

[0073] In one embodiment, the semiconductor device further includes a semiconductor structure bonded to the side of the second dielectric layer 14 away from the substrate; wherein the top third conductive layer 171 of the first interconnect structure 17 and the top fourth conductive layer 181 of the second interconnect structure 18 are respectively bonded to a metal layer on the surface of the semiconductor structure, and the second dielectric layer 14 is bonded to a dielectric layer on the surface of the semiconductor structure. The semiconductor structure may have through-silicon via (TSV) conductive structures and redistribution structures formed therein. The metal layer on the surface of the semiconductor structure is electrically connected to the redistribution structures through the TSV conductive structures, such that the first interconnect structure 17 and the second interconnect structure 18 can be electrically connected to the positive and negative terminals of a power supply respectively through the TSV conductive structures and the redistribution structures.

[0074] In one embodiment, to manufacture Figure 1 For example, refer to the semiconductor device shown. Figures 3a-3h The method for manufacturing the semiconductor device may include:

[0075] like Figure 3a As shown, a substrate 11 is provided, a first insulating layer 121 is formed on the substrate 11, a first conductive layer 151 and a second conductive layer 161 are formed extending from the top surface of the first insulating layer 121 into the first insulating layer 121, a multilayer third conductive layer 171 is formed extending from the top surface of the first insulating layer 121 into the first insulating layer 121 and a third conductive plug 172 electrically connected to adjacent third conductive layers 171 is formed, and a multilayer fourth conductive layer 181 is formed extending from the top surface of the first insulating layer 121 into the first insulating layer 121 and a fourth conductive plug 182 electrically connected to adjacent fourth conductive layers 181 is formed.

[0076] like Figure 3b As shown, a second insulating layer 122 is formed on the first insulating layer 121, and the second insulating layer 122 covers the first conductive layer 151, the second conductive layer 161, the third conductive layer 171 and the fourth conductive layer 181;

[0077] like Figure 3cAs shown, a first electrode plate material layer is formed on the second insulating layer 122, and photolithography and etching processes are performed to remove the first electrode plate material layer in the non-capacitive region and open the first electrode plate material layer in the capacitive region to form a first electrode plate 131. A first opening 136 is formed in the first electrode plate 131 to expose the second insulating layer 122.

[0078] like Figure 3d As shown, a first dielectric layer 132 is formed on the first electrode plate 131, the inner wall of the first opening 136, and the second insulating layer 122 on the periphery of the first electrode plate 131.

[0079] like Figure 3e As shown, a second electrode material layer is formed on the first dielectric layer 132, and photolithography and etching processes are performed to remove the second electrode material layer in the non-capacitive region and open the second electrode material layer in the capacitive region to form a second electrode plate 133. A second opening 137 is formed in the second electrode plate 133 to expose the first dielectric layer 132. By adjusting the etching selectivity ratio of the second electrode material layer to the first dielectric layer 132, the first dielectric layer 132 with a partial thickness around the second electrode plate 133 can be retained while etching the second electrode material layer to form the second electrode plate 133. In one embodiment, the etching selectivity ratio of the second electrode material layer to the first dielectric layer 132 is greater than or equal to 20:1.

[0080] like Figure 3f As shown, a third insulating layer 141 is formed on the first dielectric layer 132, the third insulating layer 141 covers the second electrode plate 133, the third insulating layer 141 fills the second opening 137, and a planarization process (e.g., chemical mechanical polishing) is performed on the third insulating layer 141.

[0081] like Figure 3gAs shown, the third insulating layer 141, the second electrode plate 133, the first dielectric layer 132, and the second insulating layer 122 in the region of the first opening 136 are etched to form a first through-hole exposing the first conductive layer 151. The third insulating layer 141, the first dielectric layer 132, the first electrode plate 131, and the second insulating layer 122 in the region of the second opening 137 are etched to form a second through-hole exposing the second conductive layer 161. The third insulating layer 141, the first dielectric layer 132, and the second insulating layer 122 around the first electrode plate 131 are etched to form a third through-hole exposing the third conductive layer 171 of the sub-top layer and a fourth through-hole exposing the fourth conductive layer 181 of the sub-top layer. Metal material is filled into the first through-hole, the second through-hole, the third through-hole, and the fourth through-hole to form a first conductive plug 152, a second conductive plug 162, a top third conductive plug 172, and a top fourth conductive plug 182, respectively.

[0082] like Figure 3h As shown, a fourth insulating layer 142 is formed on the third insulating layer 141, and the fourth insulating layer 142 covers the first conductive plug 152, the second conductive plug 162, the top third conductive plug 172 and the top fourth conductive plug 182.

[0083] like Figure 3h As shown, the fourth insulating layer 142 on the top third conductive plug 172 and the top fourth conductive plug 182 is etched to form a first trench exposing a portion of the third insulating layer 141 around the top third conductive plug 172 and the periphery of the top third conductive plug 172, and a second trench exposing a portion of the third insulating layer 141 around the top fourth conductive plug 182; and a metal material is filled in the first trench and the second trench to form the top third conductive layer 171 and the top fourth conductive layer 181 respectively.

[0084] As can be seen from the above, in the semiconductor device provided by this utility model, since the first conductive structure 15 and the second conductive structure 16 penetrate upward through the first interlayer dielectric layer 12 below the capacitor structure and extend into the second interlayer dielectric layer 14 of a certain thickness, the first conductive structure 15 is electrically connected to the even-numbered electrode plate in the capacitor structure, and the second conductive structure 16 is electrically connected to the odd-numbered electrode plate in the capacitor structure. This allows the capacitor structure to be connected into the circuit through the first conductive structure 15 and the second conductive structure 16 below the capacitor structure, thereby allowing the remaining thickness of the second interlayer dielectric layer 14 above the capacitor structure (such as...) Figure 1 and Figure 2 The area within the dashed box in the figure can be cleared of conductive structures, so that the area above the capacitor structure with clear conductive structures can be used to fabricate other structures required for the semiconductor device (such as antennas, conductive layers for bonding, etc.); and the capacitor structure can contain multiple layers of the electrode plates, with effective capacitance formed between all adjacent electrode plates, and all capacitors connected in parallel, which greatly increases the total capacitance value and realizes a large capacitor structure design.

[0085] It should be noted that the above-described embodiments in this specification can be combined independently or as needed.

[0086] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a substrate and a first interlayer dielectric layer located on the substrate; A capacitor structure is located on the first interlayer dielectric layer, the capacitor structure including at least two electrode plates and a dielectric layer located between adjacent electrode plates; The second interlayer dielectric layer is located on the first interlayer dielectric layer and covers the capacitor structure; A first conductive structure and a second conductive structure extend upward from the first interlayer dielectric layer below the capacitor structure through the capacitor structure and into the second interlayer dielectric layer of a certain thickness. The first conductive structure is electrically connected to the even-numbered electrode plate in the capacitor structure, and the second conductive structure is electrically connected to the odd-numbered electrode plate in the capacitor structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The top surfaces of the first conductive structure and the second conductive structure are flush.

3. The semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes: A first interconnect structure and a second interconnect structure extend from the first interlayer dielectric layer surrounding the capacitor structure to the top surface of the second interlayer dielectric layer. The first interconnect structure is electrically connected to the first conductive structure below the capacitor structure, and the second interconnect structure is electrically connected to the second conductive structure below the capacitor structure.

4. The semiconductor device as claimed in claim 1, characterized in that, A first opening is formed in the odd-numbered electrode plates, and at least one odd-numbered dielectric layer extends to the inner wall of at least one first opening. The first conductive structure penetrates the even-numbered electrode plates and the dielectric layer in the first opening region. A second opening is formed in the even-numbered electrode plates, and the capacitor structure includes at least three electrode plates. At least one even-numbered dielectric layer extends to the inner wall of at least one second opening. The second conductive structure penetrates the odd-numbered electrode plates and the dielectric layer in the second opening region.

5. The semiconductor device as claimed in claim 1, characterized in that, The first interlayer dielectric layer includes a first insulating layer and a second insulating layer stacked from bottom to top. The second interlayer dielectric layer includes a third insulating layer and a fourth insulating layer stacked from bottom to top. The first conductive structure includes a first conductive layer and a first conductive plug that are electrically connected. The second conductive structure includes a second conductive layer and a second conductive plug that are electrically connected. The first conductive layer and the second conductive layer extend from the top surface of the first insulating layer into the first insulating layer. The first conductive plug and the second conductive plug respectively extend upward from the top surface of the first conductive layer and the second conductive layer, penetrating the second insulating layer and the capacitor structure, and extending to the top surface of the third insulating layer.

6. The semiconductor device as claimed in claim 3, characterized in that, The first interconnect structure includes multiple third conductive layers and third conductive plugs connecting adjacent third conductive layers. The second interconnect structure includes multiple fourth conductive layers and fourth conductive plugs connecting adjacent fourth conductive layers. The first conductive structure below the capacitor structure is electrically connected to any third conductive layer other than the top third conductive layer. The second conductive structure below the capacitor structure is electrically connected to any fourth conductive layer other than the top fourth conductive layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The dielectric layer between adjacent electrode plates extends at least to the sidewall of the electrode plate covering the area beneath the dielectric layer.

8. The semiconductor device as claimed in claim 3, characterized in that, The semiconductor device further includes: The device structure is located in the substrate, and the first interconnect structure and the second interconnect structure are electrically connected to the device structure, respectively.

9. The semiconductor device as claimed in claim 1, characterized in that, The number of the first conductive structure and the second conductive structure is at least two.

10. The semiconductor device as claimed in claim 1, characterized in that, The area of ​​the capacitor structure is greater than 35 μm. 35μm.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The capacitor structure is a MIM capacitor.

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