A semiconductor device and an electronic apparatus

Abstract

The application provides a semiconductor device and an electronic device, wherein the semiconductor device comprises a plurality of cell structures, each of which comprises an epitaxial layer, a doped region and a first metal layer. The first surface of the epitaxial layer has a groove, and the epitaxial layer has a first conductivity type; the doped region is arranged in the epitaxial layer and is connected with the groove wall, wherein the doped region comprises a first part at the bottom of the groove and a second part at one side of the groove; the width of the first part along a first direction is smaller than the width of the bottom wall of the groove along the first direction; the doped region has a second conductivity type; the first direction is the arrangement direction of the plurality of cell structures; and the first metal layer is arranged on the first surface of the epitaxial layer and the groove wall. Through the above arrangement, the Schottky contact area is increased, the electric field distribution is in a "three-dimensional uniform distribution", the voltage resistance of the device is improved, the forward conduction characteristics are significantly optimized, and the miniaturization design of the device is facilitated.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and an electronic device. Background Technology

[0002] Among common semiconductor devices, the Schottky Barrier Diode (SBD) is a semiconductor device based on the formation of a Schottky barrier through a metal-semiconductor contact. It has unique electrical characteristics and is widely used in high-frequency, low-voltage, and high-current applications.

[0003] Schottky diodes are mainly classified into planar and trench types. In a planar Schottky diode, the metal electrode (anode) makes planar contact with the N-type semiconductor surface, creating a two-dimensional contact surface. In a trench Schottky diode, periodic vertical trenches are formed on the N-type semiconductor surface through etching, with the metal electrode covering the inner walls of the trenches and the chip surface, forming a "three-dimensional contact." This three-dimensional structure design overcomes the performance bottlenecks of planar structures, resulting in superior performance in terms of voltage withstand, conduction loss, and current density.

[0004] However, with the trend of device miniaturization, how to further reduce the size of Schottky diodes and improve their performance is an urgent problem to be solved. Utility Model Content

[0005] To address the aforementioned problems, this application provides a semiconductor device and an electronic device that can reduce device size and improve device performance.

[0006] To address the aforementioned problems, the first technical solution provided in this application is: to provide a semiconductor device, the semiconductor device comprising a plurality of cell structures, each of the cell structures comprising:

[0007] An epitaxial layer, wherein a first surface of the epitaxial layer has trenches, and the epitaxial layer has a first conductivity type;

[0008] A doped region is disposed within the epitaxial layer and in contact with the trench wall, wherein the doped region includes a first portion located at the bottom of the trench and a second portion located on one side of the trench; the width of the first portion along a first direction is smaller than the width of the bottom wall of the trench along the first direction; the doped region has a second conductivity type; the first direction is the arrangement direction of the plurality of cell structures;

[0009] A first metal layer is disposed on the first surface of the epitaxial layer and the trench wall.

[0010] To address the aforementioned problems, the second technical solution provided in this application is: to provide an electronic device, wherein the electronic device includes any of the semiconductor devices described above.

[0011] The beneficial effects of this application are that, unlike the prior art, the semiconductor device provided in this application includes multiple cell structures, each cell structure including an epitaxial layer, a doped region, and a first metal layer. The first surface of the epitaxial layer has a trench, and the epitaxial layer has a first conductivity type. The doped region is disposed within the epitaxial layer and is in contact with the trench wall. The doped region includes a first portion located at the bottom of the trench and a second portion located on one side of the trench. The width of the first portion along a first direction is smaller than the width of the bottom wall of the trench along the first direction. The doped region has a second conductivity type. The first direction is the arrangement direction of the multiple cell structures. The first metal layer is disposed on the first surface of the epitaxial layer and the trench wall. Through the above configuration, the Schottky contact area is increased, and the electric field distribution is made "three-dimensionally uniformly distributed," improving the device's withstand voltage, significantly optimizing the forward conduction characteristics, and facilitating the miniaturization design of the device. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0013] Figure 1 A partial structural cross-sectional view of an embodiment of the semiconductor device provided in this application;

[0014] Figure 2 A partial structural cross-sectional view of another embodiment of the semiconductor device provided in this application;

[0015] Figure 3 A partial structural cross-sectional view of yet another embodiment of the semiconductor device provided in this application;

[0016] Figure 4 A schematic diagram of a module of an embodiment of the electronic device provided in this application.

[0017] Label Explanation:

[0018] Cell structure - 100; Substrate - 10; Epitaxial layer - 20; Intrinsic epitaxial region - 201; Doped region - 30; First part - 301; Second part - 302; First doped region - 31; Second doped region - 32; First metal layer - 40; Second metal layer - 50; Dielectric layer - 60;

[0019] First direction - X; Second direction - Y. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0024] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0025] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0026] Among common semiconductor devices, Schottky diodes are mainly classified into planar and trench diode structures.

[0027] However, planar Schottky diodes are prone to electric field accumulation at the edge, resulting in limited reverse blocking voltage and a lower actual breakdown voltage than the theoretical value. If the breakdown voltage is increased by thickening the drift region, the forward voltage drop (VF) will increase significantly. VF is a key parameter of the Schottky diode, primarily affected by the Schottky barrier height (ΦB) and series resistance (especially the drift region resistance Rd), and it increases with increasing current and temperature.

[0028] Trench Schottky diodes, through their vertical trench design, transform the electric field distribution from "planar edge concentration" to "three-dimensional uniform distribution," breaking the bottleneck of electric field concentration at the edges of planar structures. Furthermore, if a higher withstand voltage is required, the trench structure does not need to excessively thicken the drift region (to avoid a surge in series resistance Rd). Instead, by optimizing the trench's geometric parameters (such as aspect ratio), a higher reverse blocking voltage can be achieved with the same drift region thickness.

[0029] Although trench Schottky diodes have improved many of the shortcomings of planar diodes through their three-dimensional structure, they still have inherent limitations:

[0030] From a performance perspective, its reverse withstand voltage is still limited by the traditional semiconductor "voltage-on-resistance trade-off". For example, when the withstand voltage requirement exceeds 600V, the doping concentration of the drift region needs to be further reduced and the thickness increased, which leads to a sharp increase in on-resistance (Rd), an increase in forward voltage drop, and an increase in losses.

[0031] From a size perspective, in order to balance the withstand voltage and on-resistance, the trench structure requires increasing the chip area or deepening the trench, which limits the miniaturization of the device.

[0032] See Figure 1 , Figure 1 This is a partial structural cross-sectional view of an embodiment of the semiconductor device provided in this application.

[0033] To further reduce device size while ensuring device performance, this application provides a semiconductor device 200, taking a Schottky diode as an example. Specifically, the semiconductor device 200 includes multiple cell structures 100, each cell structure 100 including a substrate 10, an epitaxial layer 20, a doped region 30, a first metal layer 40, and a second metal layer 50.

[0034] The epitaxial layer 20 is epitaxially grown on a surface of the substrate 10, and the epitaxial layer 20 has a first conductivity type, forming the drift region of the device.

[0035] The material of the epitaxial layer 20 may be the same as or different from that of the substrate 10. The materials of the substrate 10 and the epitaxial layer 20 include, but are not limited to, silicon (Si) and silicon carbide (SiC).

[0036] In this embodiment, the first surface of the epitaxial layer 20 facing away from the substrate 10 has a trench T.

[0037] The doped region 30 has a second conductivity type and is disposed within the epitaxial layer 20 and in contact with the trench wall of the trench T. Specifically, the doped region 30 includes a first portion 301 located at the bottom of the trench T and a second portion 302 located on one side of the trench T; and in the arrangement direction of the plurality of cell structures 100 (defined as the first direction X), the width W1 of the first portion 301 along the first direction X is smaller than the width W2 of the bottom wall of the trench T along the first direction X.

[0038] The region of epitaxial layer 20 that is not doped by doped region 30 is defined as intrinsic epitaxial region 201, and intrinsic epitaxial region 201 is connected to doped region 30.

[0039] In this application, one of the first conductivity type and the second conductivity type is N-type and the other is P-type. The first conductivity type is N-type and the second conductivity type is P-type.

[0040] The first metal layer 40 is disposed on the first surface of the epitaxial layer 20 and the trench wall of the trench T; the second metal layer 50 is disposed on the surface of the substrate 10 opposite to the epitaxial layer 20. The first metal layer 40 and the second metal layer 50 serve as the two electrodes of the Schottky diode.

[0041] Specifically, in the semiconductor device 200 provided in this application, by setting the epitaxial layer 20 to have a trench T, and the first metal layer 40 being disposed on the first surface of the epitaxial layer 20 and the trench wall of the trench T, the first metal layer 40 forms a Schottky contact with the first surface of the epitaxial layer 20 and the trench wall of the trench T (excluding the area in contact with the doped region 30), which increases the Schottky contact area and makes the electric field distribution "three-dimensionally uniformly distributed", improving the withstand voltage of the device; and the three-dimensional contact of the trench T expands the current path to "three-dimensional vertical + horizontal", which can carry higher current under the same chip area; or the on-resistance (especially the drift region resistance) is greatly reduced under the same current, significantly optimizing the forward conduction characteristics.

[0042] Furthermore, a doped region 30 with a different conductivity type than the epitaxial layer 20 is formed in the epitaxial layer 20. When the device is reverse biased, the charge compensation between the doped region 30 and the intrinsic epitaxial region 201 achieves a uniform distribution of the longitudinal electric field, breaking through the traditional semiconductor "voltage withstand-on resistance" trade-off relationship. It can withstand higher voltages under the same epitaxial thickness, or significantly reduce on resistance under the same voltage withstand, which is beneficial to the miniaturization design of the device.

[0043] Furthermore, the first portion 301 of the doped region 30 is located at the bottom of the trench T, and the second portion 302 of the doped region 30 is located on one side of the trench T. The first portion 301 can suppress the electric field concentration at the bottom of the trench T, improving the overall breakdown voltage of the device. Since the current mainly flows longitudinally through the Schottky contacts on the sidewall of the trench T, the first portion 301 has minimal obstruction to the current path and a low on-resistance, which helps reduce the forward voltage drop. The second portion 302 forms lateral charge compensation with the intrinsic epitaxial region 201 on the side of the trench T, which can directly disperse the electric field concentration on the side of the trench T, significantly improving the reliability of the reverse breakdown voltage.

[0044] Please continue reading Figure 1 In this embodiment of the application, the depth H1 of the trench T along the second direction Y is greater than the width W2 of the trench T along the first direction X; wherein, the second direction Y is the direction from the first surface of the epitaxial layer 20 to the inside of the epitaxial layer 20.

[0045] Specifically, when the trench depth H1 is greater than the width W2, the trench T sidewall area (main conductive area) per unit chip area increases significantly, thereby reducing current density, on-resistance and forward voltage drop.

[0046] In addition, deep and narrow trenches T can achieve the same contact area and current carrying capacity as shallow and wide trenches T in a smaller planar size, which is beneficial for device miniaturization.

[0047] In some embodiments, the depth H1 of the trench T along the second direction Y is 1-3 micrometers. For example, the depth H1 of the trench T along the second direction Y is 1 micrometer; or the depth H1 of the trench T along the second direction Y is 2 micrometers; or the depth H1 of the trench T along the second direction Y is 3 micrometers. No limitation is made here.

[0048] The width W2 of the trench T along the first direction X is 0.5-2 micrometers. For example, the width W2 of the trench T along the first direction X is 0.5 micrometers; or, the width of the trench T along the first direction X is 1 micrometer; or, the width W2 of the trench T along the first direction X is 1.5 micrometers; or, the width W2 of the trench T along the first direction X is 2 micrometers; no limitation is made here.

[0049] Specifically, the aspect ratio of the trench T is designed according to actual needs. Its value needs to be comprehensively weighed in combination with the device's withstand voltage level, current requirements, material characteristics and process capabilities to meet the balance of "performance-process-cost".

[0050] See Figure 2 , Figure 2 A partial structural cross-sectional view of another embodiment of the semiconductor device provided in this application.

[0051] In one embodiment, the semiconductor device 200 further includes a dielectric layer 60 disposed on the trench wall of the trench T and in contact with the first metal layer 40.

[0052] The dielectric layer 60 is made of materials including, but not limited to, silicon dioxide and silicon nitride.

[0053] Specifically, the dielectric layer 60 on the trench T wall can alter the direction of the electric field lines, reducing electric field concentration at the corners of the trench T, thereby improving the reverse blocking capability of the device. Furthermore, the dielectric layer 60 can reduce thermionic emission (the main mechanism of reverse leakage in Schottky junctions) at the interface between the first metal layer 40 and the semiconductor, especially suppressing leakage current caused by surface states (such as defects introduced by trench T etching). Simultaneously, the barrier effect of the dielectric layer 60 on water vapor and ions can reduce the disturbance of the Schottky barrier by environmental factors, improving leakage current stability at high temperatures.

[0054] In other embodiments, the dielectric layer 60 may also be disposed only on the trench wall of the trench T between the first metal layer 40 and the intrinsic epitaxial region 201; and / or, the dielectric layer 60 may extend to the first surface of the epitaxial layer 20, which is not limited here.

[0055] See Figure 1 or Figure 2 In one embodiment, the doped region 30 is spaced apart from the substrate 10.

[0056] Specifically, when the device is reverse biased, since a certain thickness of intrinsic epitaxial region 201 is retained between the doped region 30 and the substrate 10, it can ensure that the depletion layer extends longitudinally from the doped region 30 to the intrinsic epitaxial region 201 under reverse voltage, while avoiding direct conduction between the doped region 30 and the substrate 10, and ensuring that the epitaxial layer 20 can fully withstand the reverse electric field.

[0057] When the device is forward-biased, electrons flow from the second metal layer 50 to the first metal layer 40, with the main path being the intrinsic epitaxial region 201. This reduces current congestion and on-resistance, thereby lowering the forward voltage drop.

[0058] Furthermore, it is understandable that the core advantage of a Schottky diode is its "majority carrier conduction" (no minority carrier storage, resulting in fast switching speed). If the doped region 30 is connected to the substrate 10, reverse bias may induce minority carrier (hole) injection from the substrate 10 into the doped region 30, leading to a minority carrier storage effect and disrupting the high-frequency switching characteristics. In this embodiment, the doped region 30 and the substrate 10 are designed to be spaced apart. The intrinsic epitaxial region 201 between the doped region 30 and the substrate 10 can block minority carrier injection, maintaining the majority carrier conduction mechanism of the Schottky diode and ensuring fast switching performance.

[0059] In addition, the doped region 30 is spaced apart from the substrate 10, so the doped region 30 does not need to penetrate the entire thickness of the epitaxial layer 20, which reduces the precision requirements for depth control and lowers the manufacturing cost.

[0060] Of course, in other embodiments, the doped region 30 may also be disposed in contact with the substrate 10, which is not limited here.

[0061] In one embodiment, the second portion 302 of the doped region 30 is connected to another cell structure 100 located on the same side of the trench T and adjacent to it, while the first portion 301 of the doped region 30 is spaced apart from the adjacent cell structure 100. For example... Figure 1 or Figure 2 As shown, the second part 302 of the doped region 30 is connected to the intrinsic epitaxial region 201 of another cell structure 100 located on the same side of the trench T and adjacent to it, and the first part 301 of the doped region 30 is separated from the adjacent cell structure 100 by the intrinsic epitaxial region 201.

[0062] Specifically, the second portion 302 of the doped region 30 forms a lateral PN junction with the intrinsic epitaxial region 201 of the adjacent cell structure 100. Under reverse bias, the depletion layer extends laterally from the second portion 302 of the doped region 30 to the intrinsic epitaxial region 201. Because the second portion 302 of the doped region 30 is continuous and uniform, the lateral electric field distribution is smoother, effectively eliminating electric field concentration on the sidewalls of the trench T. Due to geometric constraints, a field strength peak is easily formed at the bottom of the trench T. The first portion 301 of the doped region 30 reduces the field strength at the bottom of the trench T by balancing the charge with the intrinsic epitaxial region 201 at the bottom of the trench T, thus avoiding local breakdown. This results in a more uniform electric field distribution throughout the drift region.

[0063] In addition, the doped region 30 is located only on one side of the trench T, while the other side of the trench T retains a complete N-type conductive channel. When electrons flow from the second metal layer 50 through the intrinsic epitaxial region 201 to the Schottky contact on the sidewall of the trench T, they can avoid the obstruction of the doped region 30 and reduce the on-resistance.

[0064] See Figure 3 , Figure 3 A partial structural cross-sectional view of another embodiment of the semiconductor device provided in this application.

[0065] In one embodiment, the doped region 30 includes a first doped region 31 and a second doped region 32, and the ion doping concentration of the first doped region 31 is greater than the ion doping concentration of the second doped region 32; wherein at least a portion of the first doped region 31 is located at the bottom of the trench T.

[0066] Specifically, the first doped region 31 (high concentration P+) is at least partially located at the bottom of the trench T. Through a higher fixed negative charge density, it forms stronger local compensation with the positive charge of the intrinsic epitaxial region 201 at the bottom of the trench T, rapidly depleting the charge in the intrinsic epitaxial region 201 at the bottom of the trench T, reducing the peak electric field at the bottom of the trench T, and preventing premature breakdown at the bottom of the trench T. The second doped region 32 (low concentration P-) serves as the main body, achieving global charge balance with the intrinsic epitaxial region 201 (total negative charge in the P region ≈ total positive charge in the N region), ensuring uniform expansion of the depletion layer under reverse bias, and maintaining the "high breakdown voltage - low resistance" advantage of the superjunction structure.

[0067] like Figure 3 As shown, part of the first doped region 31 is located at the bottom of the trench T, and the other part is located on the side wall of the trench T. The second doped region 32 is located at the bottom of the first doped region 31 and is connected to the first doped region 31.

[0068] The first doped region 31 and the second doped region 32 can be formed through a secondary epitaxial process. For example, a first epitaxial layer is first grown on the substrate 10, and then ion implantation is performed on the first epitaxial layer to form the second doped region 32 in the first epitaxial layer. Then, a second epitaxial layer is formed by secondary epitaxial growth on the surface of the first epitaxial layer, and then ion implantation is performed on the second epitaxial layer to form the first doped region 31 in the second epitaxial layer, which is connected to the second doped region 32. The first epitaxial layer and the second epitaxial layer together form the epitaxial layer 20.

[0069] Optionally, the ion implantation element in the second doped region 32 is aluminum, with a dose of 1e12 (cm). -2 ) to 1e14 (cm -2 The second doped region 32 contains aluminum as the ion implantation element, with a dose of 1e14 (cm). -2 ) to 1e15 (cm) -2 ).

[0070] Specifically, the semiconductor device 200 provided in this application incorporates a trench T and a doped region 30 into a Schottky diode. This increases the Schottky contact area using vertical surfaces within the same cell size, thereby increasing the effective conduction area and reducing on-resistance and on-voltage. Furthermore, the trench T-structure ensures a uniform electric field distribution in the drift region, preventing surface electric field accumulation. The superjunction structure formed by the doped region 30 and the intrinsic epitaxial region 201 reduces epitaxial thickness, decreases series resistance and device size, and enhances the device's forward conduction capability, thereby increasing current density. Additionally, the first doped region 31 enhances the depletion region pinch-off effect.

[0071] See Figure 4 , Figure 4 A schematic diagram of a module of an embodiment of the electronic device provided in this application.

[0072] This application also provides an electronic device 1000, which includes the semiconductor device 200 provided in any of the above embodiments. The electronic device 1000 includes, but is not limited to, home appliances, power supply devices, automotive electronic modules, photovoltaic devices, and energy storage devices.

[0073] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes multiple cell structures, each of the cell structures comprising: An epitaxial layer, wherein a first surface of the epitaxial layer has trenches, and the epitaxial layer has a first conductivity type; A doped region is disposed within the epitaxial layer and in contact with the trench wall, wherein the doped region includes a first portion located at the bottom of the trench and a second portion located on one side of the trench; the width of the first portion along a first direction is smaller than the width of the bottom wall of the trench along the first direction; the doped region has a second conductivity type; the first direction is the arrangement direction of the plurality of cell structures; A first metal layer is disposed on the first surface of the epitaxial layer and the trench wall.

2. The semiconductor device according to claim 1, characterized in that, The depth of the trench along the second direction is greater than the width of the trench along the first direction; The second direction is the direction from the first surface of the epitaxial layer to the inside of the epitaxial layer.

3. The semiconductor device according to claim 2, characterized in that, The trench has a depth of 1-3 micrometers along the second direction; and / or The width of the groove along the first direction is 0.5-2 micrometers.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A medium layer is disposed on the wall of the trench.

5. The semiconductor device according to claim 1, characterized in that, The second portion of the doped region is connected to another cell structure located on the same side of the trench and adjacent to it, while the first portion of the doped region is spaced apart from the other adjacent cell structure.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The doped region includes a first doped region and a second doped region, and the ion doping concentration of the first doped region is greater than the ion doping concentration of the second doped region; At least a portion of the first doped region is located at the bottom of the trench.

7. The semiconductor device according to claim 6, characterized in that, A portion of the first doped region is located at the bottom of the trench, and another portion is located on the sidewall of the trench. The second doped region is located at the bottom of the first doped region and is connected to the first doped region.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A substrate is disposed on the surface of the epitaxial layer opposite to the first metal layer; A second metal layer is disposed on the surface of the substrate opposite to the epitaxial layer.

9. The semiconductor device according to claim 8, characterized in that, The doped region is spaced apart from the substrate.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-9.

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