Trench bottom field dispersion igbt device
Patent Information
- Application Number
- CN202522098056.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-29
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2035-09-29
AI Technical Summary
然而，这种结构优化方式却带来了一系列技术瓶颈，成为制约沟槽型IGBT向纳米级（<1μm）沟槽间距发展的关键问题：从结构加工与成型角度来看，当沟槽间距缩减至1μm以下时，对沟槽结构的尺寸精度要求大幅提升
[0013]本实用新型栅极区上窄下宽的结构在保证垂直导电通道有效性的同时，减少电流导通路径上的电阻，结合高单元密度的沟槽结构优势，进一步降低器件的导通电压，提升导电效率。P+区与N+区的合理布局、栅极区电场分布的优化，协同改善器件的整体电场分布，避免局部电场过高导致的击穿电压下降问题，在降低导通电压的同时，保障器件具有较高的击穿电压，实现低导通损耗与高耐压性能的兼顾，满足大、中功率应用场景对器件性能的严苛需求。
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Figure CN224910007U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a trench bottom electric field distributed IGBT device. Background Technology
[0002] An Insulated Gate Bipolar Transistor (IGBT) is a device composed of a MOS transistor and a bipolar transistor. Its input electrode is a MOS transistor, and its output electrode is a PNP transistor. It combines the advantages of both devices, possessing the low drive power and fast switching speed of MOS transistors, and the low saturation voltage and large capacitance of bipolar transistors. It has been increasingly widely used in modern power electronics technology, especially in high-frequency, high-power transistor applications.
[0003] In the development of IGBT structures, trench IGBTs, by embedding the gate structure inside the silicon wafer to form a vertical conductive channel, have replaced the traditional planar gate structure and become the mainstream IGBT structure type. From a structural perspective, trench IGBTs have three main advantages: First, the vertical channel structure allows current to flow vertically after the gate is embedded inside the silicon wafer, shortening the conduction path compared to a planar structure; second, high cell density allows for the integration of more device cells per unit area of the silicon wafer, effectively reducing the on-resistance; and third, optimized electric field distribution disperses the electric field intensity within the silicon wafer, reducing localized electric field concentration and thus improving the device's breakdown voltage.
[0004] To further reduce the on-state voltage of trench IGBTs and adapt to higher-efficiency power electronics applications, existing technologies typically optimize trench structure parameters, specifically by employing deeper trench designs and reducing the spacing between adjacent trenches. However, this structural optimization approach introduces a series of technical bottlenecks, becoming a key issue restricting the development of trench IGBTs towards nanometer-level (<1μm) trench spacing: From a structural processing and forming perspective, when the trench spacing is reduced to below 1μm, the dimensional accuracy requirements of the trench structure increase significantly. On the one hand, the extremely small trench spacing significantly increases the difficulty of forming trenches on the silicon wafer, and adjacent trenches are prone to dimensional deviations and irregular edges, directly affecting the consistency of device units; on the other hand, after the gate is embedded in the trench, a uniform oxide layer needs to be formed on the trench sidewalls to achieve insulation and gate protection. However, in narrow-pitch trench structures, it is difficult to ensure the uniformity of the sidewall oxide layer thickness, and some areas are prone to having oxide layers that are too thin or too thick, affecting the gate insulation performance and device stability. In summary, existing trench IGBTs face the dual bottlenecks of difficult structural fabrication and degradation of key performance in the process of reducing trench spacing to the nanometer level (<1μm) in pursuit of low on-state voltage. How to optimize the structural design of trench IGBTs to solve the process fabrication and reliability problems caused by narrow spacing while ensuring low on-state voltage has become the core requirement for the current improvement of trench IGBT structures. Utility Model Content
[0005] To address the above problems, this invention provides a trench-bottom electric field-dispersed IGBT device that reduces the on-state voltage drop Vce(sat) while enhancing the device's short-circuit withstand capability (SCSOA).
[0006] The technical solution of this utility model is: The trench bottom electric field distributed IGBT device includes, from bottom to top, a collector metal layer, a P-region one, an N-type buffer zone, an N-type drift region, a P-region two, multiple N+ regions, and multiple dielectric layers; The plurality of N+ regions are located on the side of the silicon dioxide layer, and their bottoms are connected to the corresponding P+ regions. The dielectric layer extends downwards from the top of the N+ region into the N-type drift region; the bottom width of the dielectric layer is greater than the width of the dielectric layer in region P. The dielectric layer contains: An insulating region is located within the dielectric layer of the N-type drift region, and a first gap is provided between the insulating region and the dielectric layer; The gate region extends downward from the top region of the dielectric layer into the insulating region, and has a second spacing between it and the inner sidewall of the dielectric layer at two locations of the P region; the first spacing is greater than the second spacing. The top of the P-area 2 is provided with multiple downward-extending P+ areas; the top corner of the P+ area is connected to the corresponding N+ area; The dielectric layer is topped with an emitter metal layer connected to the P+ region.
[0007] Specifically, the dielectric layer includes a first dielectric layer located at the top of the N+ region and a silicon dioxide layer extending downward from the side of the N+ region to the N-type drift region; The silicon dioxide layer has a narrow top and wide bottom structure.
[0008] Specifically, the emitter metal layer has a thickness of 4-5 μm ALCu metal layer.
[0009] Specifically, the current collector metal layer includes Ti / TiN, Al / AlSiCu, or Ni / Ag / Au.
[0010] Specifically, a first gap is provided between the insulating region and the dielectric layer.
[0011] Specifically, a second spacing is provided on the inner sidewalls of the dielectric layer at the two locations: the gate region and the P region.
[0012] Specifically, the first spacing is greater than the second spacing.
[0013] This invention features a gate region that is narrow at the top and wide at the bottom. While ensuring the effectiveness of the vertical conductive channel, it reduces the resistance along the current conduction path. Combined with the advantages of a high-density trench structure, it further reduces the device's on-state voltage and improves conductivity. The rational layout of the P+ and N+ regions and the optimized electric field distribution in the gate region synergistically improve the overall electric field distribution of the device, avoiding the breakdown voltage drop caused by excessively high local electric fields. While reducing the on-state voltage, it ensures the device has a high breakdown voltage, achieving a balance between low conduction loss and high withstand voltage performance, meeting the stringent performance requirements of high- and medium-power applications.
[0014] The layered structure, consisting of a collector metal layer, P-region 1, N-type buffer zone, N-type drift region, and P-region 2 arranged sequentially from bottom to top, ensures the structural integrity of the device and the synergy of the functions of each region. Simultaneously, the design of embedding the gate region within the dielectric layer and placing an emitter metal layer at the top connecting to the P+ region achieves reliable connection between the electrodes and functional regions, reducing contact resistance and avoiding problems such as localized heating and current fluctuations caused by poor contact. Furthermore, the distribution of multiple N+ regions, P+ regions, and gate regions ensures uniform current conduction and output within the device, improving current output consistency, reducing localized stress concentration caused by uneven current distribution, and further enhancing the structural stability and long-term operational reliability of the device. This makes it suitable for power electronics applications with high requirements for current stability. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the cross-sectional structure of the N-type silicon substrate of this utility model. Figure 2 This is a schematic diagram of the cross-sectional structure in step two; Figure 3 This is a schematic diagram of the cross-sectional structure of polycrystalline silicon with trench and surface-implanted n-type doped silicon. Figure 4 This is a schematic diagram of the cross-sectional structure of the polysilicon section after etching within the trench; Figure 5 This is a schematic diagram of the cross-sectional structure of the gate oxide layer grown on the sidewall of the trench; Figure 6 This is a schematic diagram of the cross-sectional structure of the remaining polysilicon after etching within the trench; Figure 7 This is a schematic diagram of the cross-sectional structure after etching the bottom of the trench; Figure 8 This is a schematic diagram of the cross-sectional structure of the second silica growth. Figure 9This is a schematic diagram of the cross-sectional structure of deposited insulating material (TEOS); Figure 10 This is a schematic diagram of the cross-sectional structure of the second polycrystalline silicon deposition. Figure 11 This is a schematic diagram of the cross-sectional structure after the formation of region P; Figure 12 This is a schematic diagram of the cross-sectional structure after the formation of the N+ region; Figure 13 This is a schematic diagram of the cross-sectional structure after the formation of the P+ region; Figure 14 This is a schematic diagram of the cross-sectional structure after the emitter metal is fabricated; Figure 15 This is a schematic diagram of the cross-sectional structure after the bottom fabrication process; Figure 16 This is a graph showing the relationship between different mesa spacings and IGBT conduction losses; In the diagram, 1 represents the collector metal layer, 200 represents P-region 1, 300 represents the N-type buffer zone, 400 represents the N-type drift region, 500 represents P-region 2, 600 represents the N+ region, 700 represents the dielectric layer, 710 represents the silicon dioxide layer, 800 represents the gate region, 900 represents the P+ region, A00 represents the emitter metal layer, and B00 represents the insulating region. Detailed Implementation
[0016] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.
[0017] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0018] The following is for reference. Figure 1-16 The present invention provides a cross-sectional structural schematic diagram of an embodiment of the IGBT device. The IGBT device includes a gate trench that is narrow at the top and wide at the bottom located within an n-drift semiconductor layer; the mesa region between the trenches has the opposite structure, i.e., a design that is wide at the top and narrow at the bottom. The trench etching and gate oxidation utilize existing process flows to achieve nanometer-level ultra-fine mesa region process precision.
[0019] The fabrication method of a trench-bottom electric field-dispersed IGBT device includes the following steps: Step 1: As Figure 1 As shown, an N-type drift region is provided; select an appropriate resistivity. Step Two: As Figure 2 As shown, through an etching process, trenches of the IGBT are etched on the top of the N-type drift region, with a trench depth of 2-5 micrometers; Step 3: As Figure 3 As shown, polysilicon, photoresist, or organic materials are injected into the trenches and surfaces at high temperatures through a deposition process; in this case, polysilicon is preferred.
[0020] Step Four: As Figure 4 As shown, polysilicon is first CMP polished, and then the polysilicon, photoresist or organic matter on the trench is etched by an etching process. The depth of polysilicon in the trench is 2-3 micrometers. Organic materials include polymer-type fillers, specifically as follows: 1. Spin-on materials (SOG / SOD for short); 2. SOG (Spin-On Glass); 3. SOD (Spin-On Dielectric); 4. Polyimide; 5. BCB (Benzocyclobutene); Step 5: As Figure 5 As shown, a gate oxide layer (or first silicon dioxide) with a thickness of 10-50 nanometers is grown on the trench. Step Six: As Figure 6 As shown, the polysilicon, photoresist, or organic matter in the trench is completely etched through an etching process; Step Seven: As Figure 7 As shown, the sidewalls and bottom of the trench without an oxide layer are etched using an etching process, resulting in a narrow-at-the-top and wide-at-the-bottom structure, i.e., an upper trench and a lower trench. The lateral cross-sectional width of the lower trench is greater than that of the upper trench. The bottom of the lower trench adopts an arc-shaped structure design to alleviate the problem of excessive electric field concentration at the bottom (right angles are more prone to breakdown), thereby improving device reliability and reducing gate oxide stress. The mesa region between adjacent trenches is designed to be wider at the top and narrower at the bottom. By reducing the mesa region (the area between trenches), the trench density is increased, carrier control is strengthened, thereby reducing the on-state voltage drop and increasing the current density.
[0021] Specifically, the cross-sectional width of the upper trench is typically 1 micrometer, while the cross-sectional width of the lower trench is between 1.2 and 1.5 micrometers. Widening the lower trench can reduce the mesa region, increase carrier control, and lower the IGBT's on-state voltage.
[0022] The height of the upper trench needs to meet the design length of the trench, and is generally not less than 1 micrometer; the total height of the trench is 4-6 micrometers, and the height of the lower trench is = total height - upper trench height.
[0023] During the etching process, SF6, O2 and / or Ar gases are introduced.
[0024] Step 8: As Figure 8 As shown, a second silicon dioxide layer with a thickness adapted to the threshold voltage is grown using the SACVD process. Step Nine: Figure 9 As shown, a deposited insulating region (TEOS) is then etched deeply. Step 10: As Figure 10 As shown, the second polysilicon deposition involves high-temperature implantation of n-type doped polysilicon into the trench and on the surface of the N-type drift region, followed by CMP polishing of the polysilicon to remove excess polysilicon and planarize the surface; the high temperature is 520-560 degrees Celsius. Step 11: As Figure 11 As shown, a P-region (Pbase) is formed by implantation on the N-type drift region, and multiple N+ regions are formed by implantation on the side of the second silica in the P-region; Step Twelve: As Figure 12 As shown, a dielectric layer is deposited on the wafer surface (the material of the ILD can be an insulating material such as TEOS or BPSG), and then the surface is planarized by chemical mechanical polishing (CMP) or BPSG reflow. Step 13: Photolithography defines the location of the vias. After dry etching through the ILD, silicon is etched (0.2µm to 0.5µm), and P+ ion implantation is performed at the openings. Figure 13 As shown; A Ti / TiN layer is deposited and tungsten metal is etched back to form an ohmic contact hole; a 4~5um AlCu metal layer is deposited on the front side; Step Fourteen: Deposit fill and etch back to form ohmic contact holes; deposit an ALCu metal layer on the front side, such as... Figure 14 As shown; Step 15: Backside thinning, N-type buffer doping, P-region formation, and collector metal fabrication processes are performed, such as... Figure 15 As shown.
[0025] Specifically, the P-region (P-collector) is formed by back-side implantation; after laser annealing, the back-side collector metal of the IGBT is formed. The metal material (Ti / TiN, Al / AlSiCu, Ni / Ag / Au can be a combination of various types, where " / " indicates a relationship between them) is used.
[0026] Based on the existing mature 1.6-micron process platform, this invention optimizes several key process steps to achieve a device structure with submicron (<1 μm) trench spacing without adding new layout design or relying on more precise photolithography and etching equipment.
[0027] Figure 16 This diagram illustrates the relationship between different mesa spacings and IGBT conduction losses. The horizontal axis represents the mesa spacing, and the vertical axis represents the IGBT on-state voltage drop. Figure 16 It can be seen that reducing the mesa spacing can reduce the on-state voltage drop. They are linearly related.
[0028] The trench-bottom electric field distributed IGBT device includes, from bottom to top, a collector metal layer 100, a P-region 200, an N-type buffer zone 300, an N-type drift region 400, a P-region 500, multiple N+ regions 600, and multiple dielectric layers 700; the multiple N+ regions 600 are respectively located on the side of the silicon dioxide layer 710, and their bottoms are respectively connected to the corresponding P+ regions 900; The dielectric layer 700 extends downward from the top of the N+ region 600 into the N-type drift region 400; the bottom lateral width of the dielectric layer 700 is greater than the lateral width of the dielectric layer 700 in the P region 500, that is, after extending downward from the side of the N+ region 600, the lateral width has a shape that is narrow at the top and wide at the bottom. The dielectric layer 700 contains: The insulating region B00 is located within the dielectric layer 700 of the N-type drift region 400. A first gap is provided between the insulating region B00 and the dielectric layer 700, and the first gap ranges from 200 to 400 nm. The insulating region 800 is made of silicon dioxide, low-K or SiN. The gate region 800 extends downward from the dielectric layer 700 near the top region into the insulating region B00, and is provided with a second distance from the inner sidewall of the dielectric layer 700 at P region 500, the second distance ranging from 80-120mm; the gate region 800 in this case has a rectangular cross-section. The top of P-region 2 500 has multiple downward-extending P+ regions 900; there is a gap between the bottom surface of the P+ region 900 and the bottom surface of P-region 2 500, and the top corners are connected to the corresponding N+ regions 600; the structural design of the P+ region 900 optimizes the current distribution and carrier transport path inside the device. On the one hand, the connection method between the P+ region and the N+ region can quickly conduct the large current generated during short circuit faults, and avoid the device overheating and damage caused by excessive current concentration in local areas; On the other hand, the design of extending the P+ region downwards and maintaining a distance from the P+ region can adjust the balance between the on-state voltage drop and the short-circuit current of the device. While ensuring a low on-state voltage drop, it can improve the device's tolerance to short-circuit current, reduce the risk of device failure due to short-circuit faults, and enable the device to operate safely and stably under complex operating conditions.
[0029] The dielectric layer 700 has an emitter metal layer A00 on top, which is connected to the P+ region 900.
[0030] The dielectric layer 700 includes a first dielectric layer located on top of the N+ region 600 and a silicon dioxide layer 710 extending downward from the side of the N+ region 600 to the N-type drift region 400. The silicon dioxide layer 710 has a narrow top and wide bottom structure.
[0031] The silicon dioxide layer 710 is connected to the N+ region 600, the P-region 500, and the N-type drift region 400, respectively, and includes an upper silicon dioxide region and a lower silicon dioxide region from top to bottom (the lower silicon dioxide region is an arc-shaped structure with upper and lower corners); in this case, the cross-section of the silicon dioxide layer 710 has a narrow upper and wide lower structure, and the aforementioned lower silicon dioxide region is the widened region. The cross-sectional thickness of the upper silicon dioxide region is smaller than that of the lower silicon dioxide region.
[0032] The insulating region B00 is located at the bottom of the silicon dioxide layer 710, i.e., in the lower wide region.
[0033] This design employs a post-oxide layer technology at the bottom of the trench, commonly known as Bottom Oxide, Thick Oxide, or Pad Oxide. The lower wide region at the bottom uses a 200-400nm thick oxide layer, while the upper narrow region (gate side) uses an 80-120nm thin gate oxide layer. This not only effectively reduces the electric field concentration at the bottom of the trench, addressing a major weakness of trench-type IGBTs: excessively high electric fields at the bottom corners, which easily lead to gate oxide breakdown. The thick oxide layer at the bottom "padded" the dielectric thickness, reducing the electric field strength on the gate oxide and improving reliability. Furthermore, it avoids parasitic channels. In ordinary trenches, if the bottom gate oxide is as thin as the sidewalls, a parasitic channel may form at the bottom when a positive gate voltage is applied, leading to leakage and parasitic conduction. The thick oxide layer increases the threshold voltage of the trench-bottom MOS, allowing channels only to form on the sidewalls. Simultaneously, it improves Cgd (Miller capacitance). The thick oxide at the bottom of the trench reduces the coupling capacitance (Cgc / Cgd) between the gate and collector, helping to reduce the gate charge Qg and improve switching speed and dv / dt controllability.
[0034] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A trench-bottom-distributed IGBT device, characterized in that, It includes, from bottom to top, a collector metal layer (100), a P-region one (200), an N-type buffer zone (300), an N-type drift region (400), a P-region two (500), multiple N+ regions (600), and multiple dielectric layers (700). The dielectric layer (700) extends downward from the top of the N+ region (600) into the N-type drift region (400); the bottom width of the dielectric layer (700) is greater than the width of the dielectric layer (700) in the second P region (500); The dielectric layer (700) contains: The insulating region (B00) is located within the dielectric layer (700) of the N-type drift region (400); The gate region (800) extends downward from the dielectric layer (700) near the top region into the insulating region (B00), and is provided with a second spacing from the inner sidewall of the dielectric layer (700) at the second P region (500); the first spacing is greater than the second spacing; The top of the second P area (500) is provided with a plurality of downwardly extending P+ areas (900); the top corner of the P+ area (900) is connected to the corresponding N+ area (600); The dielectric layer (700) has an emitter metal layer (A00) on top that is connected to the P+ region (900).
2. The trench-bottom electric field distributed IGBT device according to claim 1, characterized in that, The dielectric layer (700) includes a first dielectric layer located on top of the N+ region (600) and a silicon dioxide layer (710) extending downward from the side of the N+ region (600) to the N-type drift region (400). The silicon dioxide layer (710) has a narrow top and wide bottom structure.
3. The trench-bottom electric field distributed IGBT device according to claim 1, characterized in that, The emitter metal layer (A00) has a thickness of 4-5 μm ALCu metal layer.
4. The trench-bottom electric field distributed IGBT device according to claim 1, characterized in that, The current collector metal layer (100) includes Ti / TiN, Al / AlSiCu or Ni / Ag / Au.
5. The trench-bottom electric field distributed IGBT device according to claim 1, characterized in that, A first gap is provided between the insulating region (B00) and the dielectric layer (700).
6. The trench-bottom electric field distributed IGBT device according to claim 1, characterized in that, The gate region (800) and the inner sidewall of the dielectric layer (700) at the second P region (500) are provided with a second spacing.
7. The trench-bottom electric field distributed IGBT device according to claim 1, characterized in that, The first spacing is greater than the second spacing.