A semiconductor device and an electronic apparatus

Abstract

The utility model relates to a kind of semiconductor device and electronic equipment.Semiconductor device includes substrate, semiconductor stack, multiple source electrodes, multiple drain electrodes, multiple gate electrodes, via hole and metal layer;Semiconductor stack has active region, multiple drain electrodes, multiple gate electrodes, interval configuration in active region;Multiple drain electrodes are electrically connected by drain bus between multiple drain electrodes, and multiple gate electrodes are electrically connected by gate bus between multiple gate electrodes;Multiple source electrodes interval configuration in active region between drain bus and gate bus;Via hole extends from substrate, semiconductor stack direction to expose the source electrode by penetrating semiconductor stack;Metal layer covers second surface and extends to the sidewall of via hole, and is in contact with source electrode;The thickness d3 of metal layer in contact with source electrode in via hole is greater than the thickness d2 of semiconductor stack.By the above setting, while reducing parasitic inductance, it can effectively achieve to shorten carrier transverse conduction path, increase heat conduction area, reduce current loss, improve device heat dissipation effect and other beneficial effects.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and electronic device. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) offer advantages such as high frequency, high voltage, and high temperature, representing the future direction of solid-state microwave power devices and power electronics. They are widely used in 5G communications, radar, and power electronics. In traditional silicon carbide (SiC)-based GaN HEMT RF devices, the source needs to be connected to the package or ground via long bonding wires. These bonding wires introduce significant parasitic inductance, which in turn introduces severe negative feedback, reducing the device's effective transconductance and gain. This results in more energy being dissipated in parasitic parameters rather than being output to the load, thus reducing the device's power-added efficiency. Furthermore, during high-power operation, the high local thermal current density between the gate and the channel layer near the drain generates significant heat, raising the junction temperature and leading to performance degradation and reliability issues. Existing technologies typically achieve the shortest path grounding for the source by connecting the active region to the back-side ground metal layer via a back via, thereby reducing inductance and providing a vertical low thermal resistance heat dissipation path, optimizing heat dissipation. As the frequency and power of radio frequency applications continue to increase, the requirements for reducing parasitic inductance become stronger, while heat dissipation also needs to be taken into account. However, existing back vias still have problems with large parasitic inductance and poor heat dissipation.

[0003] Therefore, how to reduce source parasitic inductance while optimizing heat dissipation and ensuring the RF characteristics and reliability of the device is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] This invention provides a semiconductor device that, through design, can solve at least one problem in the prior art, thereby reducing parasitic inductance, effectively shortening the lateral conduction path of charge carriers, increasing the thermal conductivity area, reducing current loss, and improving the heat dissipation effect of the device, especially improving the overall performance and reliability of SiC-based GaN HEMTs.

[0005] This invention provides a semiconductor device, comprising: a substrate having a first surface and a second surface opposite to each other; a semiconductor stack located on the first surface, having one side and another side opposite to each other, one side of the semiconductor stack being in contact with the first surface; the semiconductor stack having an active region; the semiconductor stack including a heterojunction structure; a plurality of drains and a plurality of gates, spaced apart within the active region; the plurality of drains being electrically connected to each other via a drain bus, and the plurality of gates being electrically connected to each other via a gate bus; a plurality of sources, spaced apart within the active region between the drain bus and the gate bus; a via extending along the thickness direction of the substrate from the second surface sequentially toward the substrate and the semiconductor stack to penetrate the semiconductor stack and expose the sources; a metal layer covering the second surface and extending to cover the sidewall of the via, and in contact with the sources; the thickness d3 of the metal layer in the via in contact with the sources is greater than the thickness d2 of the semiconductor stack.

[0006] Furthermore, the thickness of the metal layer covering the sidewall of the via decreases from the second surface toward the semiconductor stack.

[0007] Furthermore, viewed in cross-section along the substrate thickness direction, the via includes a first segment located within the substrate and connected to the second surface, and a second segment spanning the substrate and the semiconductor stack. The second segment extends from the end of the first segment away from the second surface toward the semiconductor stack and penetrates the entire semiconductor stack. The first angle α formed by the extension line of the sidewall of the first segment and the other side of the semiconductor stack is greater than the second angle β formed by the sidewall of the second segment and the other side of the semiconductor stack.

[0008] Furthermore, the depth h1 of the first hole segment is greater than the depth h2 of the second hole segment.

[0009] Furthermore, the number of vias provided below a single source electrode is multiple, and the minimum distance W4 between adjacent vias satisfies: W4≥6μm.

[0010] Furthermore, W4 ≥ 30 μm.

[0011] Furthermore, viewed from above, the via on the other side of the semiconductor stack is a rounded rectangle.

[0012] Furthermore, the maximum length W3 of a single through-hole along the gate width direction is within the range of: 15μm≤W3≤80μm.

[0013] Furthermore, at least one source electrode is provided with the via, and the top-view projected area of ​​a single source electrode on the other side of the semiconductor stack is defined as S; the sum of the end-face areas formed by all vias located below the single source electrode on the other side of the semiconductor stack is defined as S0. TVThen 1.3 < S / S TV <20; the length of a single source electrode is between 100μm and 600μm, and the width of a single source electrode is between 20μm and 120μm.

[0014] This invention also provides an electronic device, including the semiconductor device of any of the above embodiments.

[0015] The semiconductor device provided by this invention, through the structural design of the vias and metal layers, can effectively improve the lateral conduction path of charge carriers, enhance the heat dissipation effect of the device, and improve the overall performance and reliability of HEMT.

[0016] Other features and beneficial effects of this invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this invention. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a top view of a semiconductor device provided in another embodiment of the present invention; Figure 3 yes Figure 1 A partial sectional view at point AA in the middle; Figure 4 yes Figure 2 A partial sectional view at point BB; Figure 5 This is a schematic cross-sectional view of the through hole in Embodiment 1; Figure 6 This is a partial cross-sectional schematic diagram of a semiconductor device; Figure 7 A schematic diagram of the top view of the through hole shape; Figure 8 This is a comparison chart of linear gain characteristic curves of semiconductor devices with different back hole sizes; Figure 9 This is a comparison chart of thermal simulation curves of channel temperature for semiconductor devices with different back via sizes. Figure 10 This is a schematic cross-sectional view of the first hole segment in Embodiment 2, which is a curve or arc. Figure 11 This is a cross-sectional view of the first hole segment as a curve or arc, provided in another example of Embodiment 2; Figure 12 This is a cross-sectional view of the first and second hole segments in Embodiment 2, both of which are curves or arcs. Figure 13 This is a cross-sectional view of the first and second hole segments, which are both curves or arcs, provided in another example of Embodiment 2.

[0019] Figure label: 10. Substrate; S1. First surface; S2. Second surface; 20. Semiconductor stack; 31. Source; 32. Drain; 321. Drain busbar; 33. Gate; 331. Gate busbar; 40. Via; 401. Maximum size of via; 402. Minimum size of via; 41. First segment; 42. Second segment; 50. Metal layer; 60. Groove; 100. Active region; α. First included angle; β. Second included angle; L1. Minimum horizontal dimension of groove; L2. Maximum horizontal dimension of groove. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings; the technical features designed in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0021] To address the heat accumulation effect in the active region of semiconductor devices during high-power operation and effectively maximize device performance, the conventional design currently uses a back via to connect the source of the active region to the back ground metal layer, shortening the heat conduction path and achieving better heat dissipation. However, this design reduces the channel carrier mobility of HEMT devices to some extent, affecting device performance.

[0022] To further investigate the impact of the back via size on semiconductor device performance, the following tests were conducted. The semiconductor device was a GaN HEMT device with SiC as the substrate. Under the same input power conditions, the changes in device gain with varying input power and different back via sizes were studied. Figure 8 As shown, Figure 8The graph shows a comparison of the linear gain characteristic curves of semiconductor devices with different back via sizes. The X-axis represents the device input power P(au), where P(au) is the relative intensity of the device input power; the Y-axis represents the device gain G(au), where G(au) is the relative intensity of the device gain. au is an abbreviation for arbitrary unit, representing relative intensity. A first direction X and a second direction Y are defined, and they are perpendicular to each other. Specifically, the first direction X is defined as the gate length direction, i.e., the direction in which the gate 33 extends between the source 31 and the drain 32; the second direction Y is defined as the direction perpendicular to the gate length direction, also known as the gate width direction. The back via is a rounded rectangle, with the longer side called the long side and the shorter side called the short side. The short side is the dimension of the first direction X, and the long side is the dimension of the second direction Y. The dashed line represents the linear gain characteristic curve of the small-sized back via, and the solid line represents the linear gain characteristic curve of the large-sized back via. The long side of the small-sized back via is the same as that of the large-sized back via, both being 70μm. The short side of the small-sized back via is 20μm, and that of the large-sized back via is 35μm. In this comparison graph, when the input power is 0~40dBm, the gain of the large-sized back via is >0.08dB higher than that of the small-sized back via. The study found that the large-sized back via is equivalent to providing a large number of parallel paths for the source current. After parallel connection, the total inductance value is reduced, which is beneficial to improving the gain of the device.

[0023] However, further research into heat dissipation revealed that simply increasing the size of the back vents actually worsened the heat dissipation effect. For example... Figure 9 The thermal simulation curves of the device channel temperature for different back via sizes are shown, with the X-axis representing the back via size and the Y-axis representing the channel temperature. Taking a back via with a rounded rectangle, a fixed long side of 70 μm, and the short side representing the X-axis as an example, the channel temperature increases with increasing back via size. When the back via size exceeds 20 μm, the channel temperature rises sharply. This is because the thermal conductivity of air inside the back via is lower than that of SiC (SiC has a thermal conductivity of 490 W / mK), making its thermal conductivity far inferior to SiC. A larger back via size means a larger back via volume, resulting in the removal of more SiC material. Since SiC itself has excellent thermal conductivity and heat dissipation properties, increased material removal hinders heat dissipation, leading to higher channel temperatures. Similarly, because SiC has a higher thermal conductivity than metals, retaining more SiC material and reducing metal usage facilitates faster heat conduction, but the need to reduce parasitic inductance must also be considered.

[0024] Furthermore, due to the significant difference in the coefficient of thermal expansion (CTE) between the back-side ground metal layer and SiC / GaN, changes in device temperature can lead to thermal stress. This thermal stress disrupts the periodicity of the GaN lattice, causing lattice distortion or defects, introducing additional scattering centers, and ultimately resulting in enhanced carrier scattering and reduced channel carrier mobility. The polarization charge is mainly distributed at the heterojunction interface (such as the AlGaN / GaN interface), and stress can also alter the polarization charge distribution, leading to a decrease in polarization difference and a reduction in carrier concentration.

[0025] In view of this, and in response to the problems of semiconductor HEMT devices with the introduction of back vias mentioned above, the following embodiments disclose a metal layer and via design for semiconductor devices and electronic devices, which can reduce source parasitic inductance and optimize heat dissipation, while reducing thermal stress caused by differences in thermal expansion coefficients, and improving the RF characteristics and reliability of the device.

[0026] In a first aspect, the following embodiments disclose a semiconductor device comprising at least a substrate 10, a semiconductor stack 20, a plurality of drains 32, a plurality of gates 33, a plurality of sources 31, a via 40, and a metal layer 50.

[0027] Substrate 10 has a first surface S1 and a second surface S2 opposite to each other; a semiconductor stack 20 is located on the first surface S1, having one side and another side opposite to each other; the semiconductor stack 20 has an active region 100; the semiconductor stack 20 includes a heterojunction structure; a plurality of drains 32 and a plurality of gates 33 are spaced apart within the active region 100; the plurality of drains 32 are electrically connected to each other through a drain bus 321, and the plurality of gates 33 are electrically connected through a gate bus 331; a plurality of sources 31 are spaced apart. The via 40 is disposed in the active region 100 between the drain bus 321 and the gate bus 331; the via 40 extends along the thickness direction of the substrate 10 from the second surface S2 toward the substrate 10 and the semiconductor stack 20 to penetrate the semiconductor stack 20 and expose the source 31; the metal layer 50 covers the second surface S2 and extends to cover the sidewall of the via 40 and contacts the source 31; the thickness d3 of the metal layer 50 in the via 40 that contacts the source 31 is greater than the thickness d2 of the semiconductor stack 20.

[0028] By setting the via 40 and the metal layer 50, the back electrode metal can be guaranteed to have a sufficient cross-sectional area for lateral conduction, ensuring that the semiconductor stack 20 has the shortest current conduction path in the lateral direction to the back electrode.

[0029] Secondly, the following embodiments also provide an electronic device that includes a semiconductor device as provided in any of the embodiments of the first aspect above, so as to effectively optimize the performance of the electronic device.

[0030] The technical solution of this utility model will now be described and explained in detail through various specific embodiments and accompanying drawings.

[0031] Example 1 Please see Figures 1-4 , Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of the present invention. The semiconductor device includes at least a substrate 10, a semiconductor stack 20, a plurality of drains 32, a plurality of gates 33, a plurality of sources 31, a via 40, and a metal layer 50.

[0032] The substrate 10 can be a substrate known to those skilled in the art for supporting semiconductor integrated circuit components, typically silicon carbide (SiC). In one embodiment, the thickness d1 of the substrate 10 ranges from 40 μm ≤ d1 ≤ 120 μm.

[0033] The substrate 10 has a first surface S1 and a second surface S2 opposite to each other. A semiconductor stack 20 is disposed on the first surface S1 of the substrate 10. The semiconductor stack 20 can be fabricated on the substrate 10 by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). This embodiment does not limit the specific process, and the appropriate process can be selected according to actual needs. In this embodiment, the semiconductor device is preferably a HEMT device, wherein the semiconductor stack 20 includes a heterojunction. Specifically, the semiconductor stack 20 includes at least a GaN layer and a barrier layer; the GaN layer and the barrier layer form a heterojunction to form a two-dimensional electron gas. The barrier layer can be a single layer or a stack of AlGaN, aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride, or aluminum indium gallium nitride. In one embodiment, the thickness d2 of the semiconductor stack 20 is in the range of 100nm ≤ d2 ≤ 2500nm.

[0034] It should be noted that, depending on the actual needs of the semiconductor device, the semiconductor stack 20 may also be provided with at least one of the functional layers (not shown in the figure), such as a nucleation layer, a transition layer, a buffer layer, and an insertion layer. No further restrictions are imposed here.

[0035] For example, an AlN insertion layer can be placed between the GaN layer and the barrier layer. The thickness of the AlN insertion layer can range from 0.5 nm to 2 nm. The AlN insertion layer can improve the channel electron density and electron mobility, and enhance the role of the heterointerface.

[0036] For example, a nucleation layer and a buffer layer are sequentially disposed between the substrate 10 and the GaN layer. The nucleation layer is made of AlN and has a thickness of 10nm to 50nm. The nucleation layer can release the mismatch stress caused by the lattice mismatch between the buffer layer and the substrate 10, as well as the thermal stress caused by the coefficient of thermal expansion, and optimize the flatness of the nucleation layer surface, resulting in lower defects in the growth of the semiconductor stack 20. The buffer layer includes one or more combinations of AlN, AlGaN, and GaN to alleviate the problems of lattice mismatch and coefficient of thermal expansion mismatch between the substrate 10 and the GaN layer. Preferably, the buffer layer is a GaN buffer layer.

[0037] This embodiment also includes a source 31, a drain 32, and a gate 33 located on the side of the semiconductor stack 20 away from the substrate 10 (i.e., the other side of the semiconductor stack 20) ​​and isolated from each other. The gate 33 is disposed between the source 31 and the drain 32. The source 31, drain 32, and gate 33 can be a single layer of metal, a single layer of alloy, or multiple layers of metal or multiple layers of alloy. For example, the materials of the source 31 and the drain 32 can be metals such as nickel, gold, titanium, aluminum, platinum, and chromium, or their alloys or stacks, such as a Ti / Au metal stack, to facilitate the formation of an ohmic contact with the semiconductor stack 20. The gate 33 can be designed as a T-gate or a recessed gate, etc., to effectively reduce the short-channel effect of the device, and the specific structure is not limited here. The material of the gate 33 can be metals such as Ni, Ag, Cu, Co, Pu, Ni, Pt, and Au, or their alloys or stacks, to facilitate the formation of a Schottky contact with the semiconductor stack 20.

[0038] In some embodiments, the source 31, drain 32, and gate 33 can be formed by using electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., to form electrode materials, and then patterning the electrode materials.

[0039] An insulating layer (not shown in the figure) is also provided on the side of the semiconductor stack 20 away from the substrate 10; the material of the insulating layer can be one or a combination of SiO2, SiN, Al2O3, and SiON, and this embodiment does not limit this. By designing the insulating layer, external charged particles or impurities can be effectively prevented from affecting the normal operation of the HEMT.

[0040] Define a first direction X and a second direction Y, which are perpendicular to each other. The first direction X is defined as the gate length direction, that is, the direction in which the gate 33 extends between the source 31 and the drain 32; the second direction Y is defined as the direction perpendicular to the gate length direction, also known as the gate width direction.

[0041] Please continue reading. Figure 1To increase output power, the semiconductor device provided in this embodiment adopts a multi-finger gate structure. Specifically, the semiconductor stack 20 has an active region 100, and a single semiconductor device includes multiple sources 31, multiple drains 32, and multiple gates 33 spaced apart within the active region 100. The multiple drains 32 are electrically connected via a drain bus 321, and the multiple gates 33 are electrically connected via a gate bus 331. The multiple sources 31 are spaced apart within the active region 100 between the drain bus 321 and the gate bus 331. The drain bus 321 and the gate bus 331 extend parallel to each other along a first direction X, and the multiple gates 33, multiple sources 31, and multiple drains 32 are arranged along a second direction Y between the drain bus 321 and the gate bus 331.

[0042] The semiconductor device includes a via 40, which extends along the thickness direction of the substrate 10 from the second surface S2 sequentially toward the substrate 10 and the semiconductor stack 20, penetrating the semiconductor stack 20 and exposing the source electrode 31. The sidewalls of the via 40 are covered with a metal layer 50 to electrically connect the source electrode 31 located on one side of the semiconductor stack 20 to the metal layer 50, achieving grounding and making metal wiring more flexible. This effectively reduces the parasitic capacitance and inductance of the semiconductor device and improves its thermal conductivity. In one embodiment, the depth of the via 40 is between 40 μm and 120 μm, and the depth of the via 40 is the sum of the thickness d2 of the semiconductor stack 20 and the thickness d1 of the substrate 10.

[0043] In this embodiment, the metal layer 50 covers the second surface S2 of the substrate 10 and extends to cover the sidewall of the via 40, and contacts the source electrode 31. That is, the metal layer 50 further extends to cover the lower surface of the source electrode 31 to achieve contact with the source electrode 31. The material of the metal layer 50 can be a metal with high thermal conductivity and high electrical conductivity, such as gold, silver, titanium, aluminum, platinum, tungsten, palladium or a combination thereof, but this embodiment is not limited to this.

[0044] Please see Figure 3 , Figure 4 The thickness d3 of the metal layer 50 in the via 40 that contacts the source electrode 31 is greater than the thickness d2 of the semiconductor stack 20. Compared to a thickness d3 being smaller than d2, this design ensures that the back electrode metal has sufficient lateral conductive cross-sectional area, guaranteeing the shortest lateral current conduction path from the semiconductor stack 20 to the back electrode. Furthermore, it can better accommodate the heat dissipation path between the substrate 10 and the metal layer 50 in contact with the source electrode 31, thereby increasing the heat conduction area and improving the device's heat dissipation performance.

[0045] from Figure 1From a top view, the shape of the via 40 is the shape of the horizontal cross-section of the via 40 on the surface of the semiconductor stack 20 away from the substrate 10. A single source 31 of the semiconductor device can be provided with multiple vias 40, and the multiple vias 40 are arranged regularly along the second direction Y within the single source 31. The specific number can be reasonably set according to actual needs, such as 2, 3, 4, 5, etc., and this embodiment does not limit this. As an example, such as... Figure 1 In this embodiment, two vias 40 are symmetrically distributed along the second direction Y in a single source electrode 31 region. Specifically, a portion of the metal layer 50 within the via 40 contacts the bottom of the source electrode 31. In one embodiment, the via 40 is located below the source electrode 31, and the top view projection between the via 40 and the source electrode 31 at least partially overlaps. Preferably, in this embodiment, the via 40 is located within the top view projection range of the source electrode 31.

[0046] Preferably, the number of vias 40 disposed below a single source electrode 31 is multiple. When there are multiple vias 40, in this embodiment, the minimum distance W4 between adjacent vias 40 preferably satisfies: W4 ≥ 6 μm; in a preferred embodiment, W4 ≥ 30 μm. This setting can effectively tolerate fluctuations in CD (Critical Dimension) and overlay error (OVL) during the process, avoiding the risk of short circuits or performance abnormalities in adjacent vias 40 due to excessively small spacing, thereby improving product yield. It should be noted that, please refer to... Figure 2 In other embodiments, a single source electrode 31 may be provided with a via 40. In this case, the via 40 is located at the center of the source electrode 31 region and is arranged in a single row along the second direction Y. The distance between the edge of the via 40 and the edge of the source electrode 31 is not less than the minimum spacing allowed by the process, which is usually 1~3μm, to avoid the risk of short circuit caused by process deviation and the impact on manufacturing yield.

[0047] Viewed from above, the via on the other side of the semiconductor stack is a rounded rectangle. Although, Figure 1 The via 40 shown is a rounded rectangle in top view, wherein the rounded rectangle includes a long side, which is parallel to the gate 33. It can also be other shapes, such as a standard rounded rectangle (e.g.,...). Figure 7 As shown in (a), the four right angles of the rectangle are replaced with rounded transitions, or a stadium-shaped rounded rectangle (such as...). Figure 7 As shown in (b) above, the shape resembles a stadium, formed by connecting the two ends of the two long sides of a rectangle to semicircles with diameters equal to the length of the short side of the rectangle. However, this embodiment is not limited to this. In other embodiments, the top view shape of the through hole 40 can also be elliptical or circular (e.g., Figure 7(c) and combinations of rectangles or other circles. Taking a rounded rectangle as an example, the shape of the cross-section of the via 40 on the surface of the semiconductor stack 20 is a rounded rectangle. The maximum length W3 of a single via 40 along the gate width direction (i.e., the second direction Y) is 15μm≤W3≤80μm, and the minimum width W2 along the gate length direction (i.e., the first direction X) is 10μm≤W2≤45μm. This limitation can effectively prevent the via 40 from being too small, which would lead to an excessively large parasitic inductance of the source 31, and prevent the via from being too large, which would lead to poor heat dissipation and affect device performance.

[0048] In one embodiment, the top-view projected area of ​​a single source electrode 31 on the other side of the semiconductor stack 20 is defined as S; the sum of the end-face areas formed by all vias 40 located below the single source electrode 31 on the other side of the semiconductor stack 20 is defined as S0. TV Then 1.3 < S / S TV <20. If the number of vias 40 provided at a single source 31 is 1, then S TV The area of ​​the end face of the via 40 formed on the other side of the semiconductor stack 20. The length of a single source 31 is between 100 μm and 600 μm, and the width of a single source 31 is between 20 μm and 120 μm. The via 40 has an end face formed on the other side of the semiconductor stack 20. All vias 40 located below a single source 31 refer to vias 40 whose end face falls within the top-view projection range of the single source 31, and / or vias 40 whose end face overlaps with the top-view projection range of the single source 31 in the top-view projection.

[0049] On the one hand, due to the area of ​​the back hole (S) TV The larger the area of ​​the via (S), the smaller the source parasitic inductance. This means the via effectively provides numerous parallel paths for the source current, reducing the total inductance. On the other hand, the area of ​​the via (S)... TV The larger the value, the worse the heat dissipation effect. Therefore, when limiting S / S... TV >1.3, avoid excessively large back via area, which can lead to excessive removal of SiC material, resulting in poor heat dissipation during device operation, causing performance degradation and reliability issues. When limiting S / S TV <20 can avoid the increase of source parasitic inductance caused by an excessively small back via area, which would cause more energy to be lost in parasitic parameters during device operation rather than output to the load, resulting in a decrease in the device's power-added efficiency. This is achieved by considering the sum of the top-view projection area S of a single source 31 and the end-face area S formed by the via 40 on the other side of the semiconductor stack 20. TV The ratio is limited to reduce source parasitic inductance while optimizing heat dissipation, thus ensuring the RF characteristics and reliability of the device.

[0050] Preferably, the thickness of the metal layer 50 covering the sidewalls of the via 40 decreases from the second surface S2 toward the semiconductor stack 20. The degree of reduction in the thickness of the metal layer 50 covering the sidewalls of the first via segment 41 and the sidewalls of the second via segment 42 can be the same or different, and can be reasonably set according to actual needs. Because the coefficients of thermal expansion (CTE) of the metal layer 50, the substrate 10, and the semiconductor stack 20 differ significantly, changes in device temperature can lead to thermal stress due to this difference in CTE. This thermal stress causes lattice distortion in the GaN channel, introducing additional scattering centers, ultimately resulting in enhanced carrier scattering and reduced channel carrier mobility. Furthermore, stress can also alter the polarization charge distribution, affecting carrier concentration. Furthermore, the operating temperature of the metal layer 50 is higher near the semiconductor stack 20 and lower near the substrate 10. If the thickness of the metal layer 50 covering the sidewalls of the via 40 is uniform, the area near the semiconductor stack 20 with higher temperature is prone to severe thermal expansion, resulting in greater thermal stress. This can lead to mismatch between the metal layer 50, the semiconductor stack 20, and the substrate 10, affecting the performance of the semiconductor device during high-power operation. This embodiment effectively alleviates the above problem by designing the thickness of the metal layer 50 to decrease from below the substrate 10 towards the semiconductor stack 20. The reduction in the thickness of the metal layer 50 reduces thermal stress at areas with lower thickness, thereby mitigating CTE mismatch caused by temperature differences in the metal layer 50 at different locations and improving the performance degradation and reliability issues caused by heat during high-power operation of the semiconductor device.

[0051] Further, please refer to Figure 5 The semiconductor device also includes a third direction Z, defined as a thickness direction that is perpendicular to both the first direction X and the second direction Y. Viewed in cross-section along the thickness direction of the substrate 10 (i.e., the third direction Z), the via 40 includes a first segment 41 located within the substrate 10 and connected to the second surface S2, and a second segment 42 spanning the substrate 10 and the semiconductor stack 20. The second segment 42 extends from the end of the first segment 41 away from the second surface S2 towards the semiconductor stack 20 and penetrates the entire semiconductor stack 20. In this embodiment, the minimum horizontal aperture of the first segment 41 is greater than or equal to the maximum horizontal aperture of the second segment 42, and the horizontal aperture of the first segment 41 decreases along the depth direction of the via 40 (i.e., the third direction Z from the substrate 10 to the semiconductor stack 20), while the horizontal aperture of the second segment 42 decreases along the depth direction of the via 40. The reduction can be linear or non-linear. When the horizontal diameter of both the first hole segment 41 and the second hole segment 42 decreases linearly along the depth direction of the through hole 40, in the cross-section of the through hole 40 along its central axis in the third direction Z, the contour lines on both sides of the first hole segment 41 and the second hole segment 42 are straight lines, and the slope of the straight line of the first hole segment 41 is greater than the slope of the straight line of the second hole segment 42. Figure 5As shown, in the actual etching process, the side contours of the first hole segment 41 and the second hole segment 42 can be approximated as straight lines. When the horizontal diameters of both the first hole segment 41 and the second hole segment 42 decrease non-linearly along the depth direction of the through hole 40, in the cross-section of the through hole 40 along its central axis in the third direction Z, the side contours of the first hole segment 41 and the second hole segment 42 are both arcs, and the slope of the arcs of the first hole segment 41 and the second hole segment 42 can increase or decrease along the depth direction of the through hole 40 to form an arc bending towards the inside of the through hole 40 or an arc bending towards the outside of the through hole 40, such as... Figures 10-13 As shown. Of course, the contour lines on both sides of the first hole segment 41 can also be set to straight lines and the contour lines on both sides of the second hole segment 42 to be curved lines, or the contour lines on both sides of the first hole segment 41 can be curved lines and the contour lines on both sides of the second hole segment 42 can be curved lines. The specific values ​​of the slope of the straight line and the curvature of the curve should be reasonably set according to actual needs, and this example does not limit them.

[0052] Preferably, the first angle α formed by the extension line of the sidewall of the first hole segment 41 and the first surface S1 (i.e., the other side of the semiconductor stack 20) ​​is greater than the second angle β formed by the sidewall of the second hole segment 42 and the first surface S1, and the depth h1 of the first hole segment 41 is greater than the depth h2 of the second hole segment 42. Here, the first angle α refers to the acute angle formed by the extension line of the sidewall of the first hole segment 41 and the first surface S1, and the second angle β refers to the acute angle formed by the sidewall of the second hole segment 42 and the first surface S1.

[0053] With the above configuration, in this embodiment, the substrate 10 is a SiC substrate 10, the back electrode metal is a metal with high thermal conductivity and high electrical conductivity (e.g., gold, copper), and the holes are filled with a high thermal conductivity material. When the GaN HEMT device operates at high power, the local thermal current density between the lower right side of the gate 33 and the channel layer is high, generating a large amount of heat, causing the device junction temperature to rise, leading to performance degradation and reliability issues. Figure 3 X-axis analysis shows that the high heat near the gate needs to pass through SiC, and then through the back electrode metal to conduct heat through the high thermal conductivity material filled by the back hole. SiC has a thermal conductivity of 490 W / mK, gold has a thermal conductivity of 317 W / mK, and copper has a thermal conductivity of 400 W / (mK). Since SiC has a higher thermal conductivity than metal, heat is transferred faster in SiC. Therefore, for the same heat transfer distance, this design, which uses more SiC substrate material and less metal, is conducive to faster heat conduction and further improves the heat dissipation capability of semiconductor devices.

[0054] It should be understood that the structures of the first hole segment 41 and the second hole segment 42 are not limited to the forms shown in the sectional view of the attached figure: in the attached figure, both are single-segment structures, and the contour lines on both sides of their through holes in the cross-section are composed of inclined straight lines or inclined arcs (i.e., the slope is constant or gradually changes). In fact, the first hole segment 41 and the second hole segment 42 can also adopt a multi-segment structure, and the contour lines on both sides of their through holes in the cross-section are composed of at least one combination of inclined straight lines, inclined arcs, and horizontal straight lines (i.e., the slope of the contour lines on both sides of adjacent segments changes abruptly), such as stepped holes, multi-segment straight holes with different slopes, or composite holes connecting straight lines and arcs, etc.

[0055] In this embodiment, the through-hole 40 is preferably formed by an etching process. The value range of the first included angle α formed by the extended line of the sidewall of the first hole segment 41 and the first surface S1 is: 84°≤α≤90°. The value range of the second included angle β formed by the sidewall of the second hole segment 42 and the first surface S1 is: 78°≤β≤88°. By limiting the specific values ​​of the first included angle α and the second included angle β, the area near the semiconductor stack 20, i.e., near the heat center (such as... Figure 3 More substrate 10 material is retained in the SiC substrate 10 region (near the red dashed box below the gate 33) to utilize the high thermal conductivity of the SiC substrate 10 and quickly conduct heat away from the heat center. Simultaneously, the increased back via size, resulting in greater SiC material removal, helps reduce the parasitic inductance of the device source 31. Therefore, SiC material is removed on the side furthest from the heat center to ensure lower parasitic inductance and improve device gain. Furthermore, this avoids issues such as poor coverage during back electrode metal fabrication due to excessively large or mismatched first and second angles α and β, which could lead to voids, metal detachment, and impaired current conduction, causing device performance degradation and reliability problems.

[0056] In a more preferred embodiment, 87°≤α≤89°, 80°≤β≤85°. In some alternative embodiments, α=89.5°, β=85.5°; α=88°, β=83°; α=88°, β=81°; α=84°, β=79°; α=85°, β=78°; α=85°, β=81°.

[0057] In this configuration, the first surface S1 and the second surface S2 of the substrate 10 are relatively parallel. Similarly, the semiconductor stack 20 is stacked on the substrate 10, with one side of the semiconductor stack 20 being relatively parallel to the other side. Alternatively, it can be understood that the angle formed between the extension line of the sidewall of the first aperture segment 41 and the first surface S1 is equal to a first included angle α, and the angle formed between the sidewall of the second aperture segment 42 and the first surface S1 is equal to a second included angle β.

[0058] In addition, such as Figure 5As shown, the second via 42, spanning the substrate 10 and the semiconductor stack 20, includes a via located in the substrate 10 (with a depth of h3 = h2 - d2) and a via located in the semiconductor stack 20 (with a depth equal to the thickness d2 of the semiconductor stack 20). The second via 42 near the semiconductor stack 20, at a depth h3 in the substrate 10 portion, is formed by matching the thickness (d2) of the semiconductor stack 20 and using low-power, low-damage, slow etching (compared to the etching rate of the via 40 formed by the first via 41). This effectively reduces etching damage to the semiconductor stack 20, thereby minimizing the decrease in channel carrier mobility caused by damage to the semiconductor stack 20. Since the depth h1 of the first via 41 is greater than the depth h3 of the second via 42 in the substrate 10 portion, the deeper first via 41, combined with high-power, fast etching, achieves rapid material removal and ensures efficient etching. In this embodiment, the preferred ratio of the depth h1 of the first via 41 to the depth h3 of the second via 42 located on the substrate 10 is 1 / 5 ≤ h3 / h1 ≤ 3 / 4. This avoids damage to the semiconductor stack 20 caused by excessively shallow h3 depth when h3 / h1 is less than 1 / 5, due to fluctuations in the etching rate stability during the etching process. Specifically, the first via 41 uses high-power plasma etching to ensure etching efficiency. If the h3 depth is too shallow, high-energy plasma bombardment may penetrate the portion of the second via 42 on the substrate 10 corresponding to h3, resulting in lattice defects or disordered doping distribution in the portion of the semiconductor stack 20 where the second via 42 is located, ultimately leading to a decrease in channel carrier mobility. When h3 / h1 is greater than 3 / 4, the overall etching rate of the via 40 is slow, affecting the device fabrication efficiency. By controlling the upper limit of the depth h3 of the second via 42 on the substrate 10, the etching time can be controlled within a reasonable range, effectively balancing etching efficiency and the quality of the semiconductor stack 20.

[0059] In a preferred embodiment, 0.3 ≤ h3 / h1 ≤ 0.6. In some alternative embodiments, h3 / h1 can be selected as 0.25, 0.35, 0.45, 0.5, 0.55, or 0.65.

[0060] Based on the above, this embodiment, through the design of the depth of the first hole segment 41 and the depth of the second hole segment 42, as well as the first included angle α and the second included angle β, can reduce the parasitic inductance of the source 31 and optimize the heat dissipation effect, while also ensuring etching efficiency (reducing process time) and damage control (improving the integrity of the semiconductor stack 20).

[0061] As an example, the range of the first angle α formed by the extension line of the sidewall of the first aperture segment 41 and the other side of the semiconductor stack 20 is: 84°≤α≤90°, and the range of the second angle β formed by the sidewall of the second aperture segment 42 and the other side of the semiconductor stack 20 is: 78°≤β≤88°. By limiting the specific values ​​of the first angle α and the second angle β, on the one hand, the mechanical strength of the substrate 10 is reduced due to the first angle α being too small; on the other hand, the contact area between the source electrode 31 and the metal layer 50 is reduced due to the second angle β being too small, which would cause heat to accumulate at the center of the heat source and affect the lateral heat dissipation efficiency. At the same time, the second angle β is prevented from being too large, which would prevent more substrate 10 material from being retained in the area of ​​substrate 10 near the heat center. Because the substrate 10 material has a low coefficient of thermal expansion and high thermal conductivity, by designing a specific value for the second included angle β, the contact area between the source 31 and the metal layer 50 is sufficient to ensure lateral conduction, while retaining more substrate 10 material in the region near the heat source. This allows the high thermal conductivity of the substrate 10 to rapidly conduct heat laterally to the metal layer 50, effectively improving heat dissipation performance. Simultaneously, since the coefficient of thermal expansion of the substrate 10 is significantly lower than that of the metal layer 50 material, the larger tilt angle between the first included angle α and the second included angle β reduces stress concentration at the interface. That is, when the device operating temperature rises, the expansion difference between the SiC substrate 10 and the metal layer 50 generates thermal stress, and the tilted sidewalls of the vias can disperse this stress through structural buffering, preventing interface cracking or contact failure due to expansion mismatch. This ensures efficient lateral heat conduction while reducing interface damage during thermal cycling through angle matching, ultimately achieving a synergistic improvement in heat dissipation performance and structural reliability.

[0062] In one embodiment, the thickness d2 of the semiconductor stack 20 and the depth h3 of the second aperture segment 42 located in the substrate 10 are related by the following: Where h3 = h2 - d2. That is, as shown in the figure. Figure 5 As shown, the second aperture segment 42, which spans the substrate 10 and the semiconductor stack 20, includes an aperture segment (with a depth of h3) located in the substrate 10 and an aperture segment (with a depth equal to the thickness d2 of the semiconductor stack 20) ​​located in the semiconductor stack 20. In this embodiment, the depth h3 of the second aperture segment 42 in the substrate 10 is defined as greater than or equal to... To avoid the situation where the depth h3 is too shallow, which could cause damage to the semiconductor stack 20 due to fluctuations in the etching rate during the etching process, specifically, the plasma etching energy might penetrate the preset stop layer and directly bombard the surface of the semiconductor stack 20, causing lattice defects or disordered doping distribution, thereby leading to a decrease in channel carrier mobility. By controlling the lower limit of the depth h3 of the second via segment 42 located in the substrate 10, sufficient etching buffer space can be reserved, which, combined with a low-damage etching process, ensures the integrity of the semiconductor stack 20. Simultaneously, the depth h3 of the second via segment 42 located in the substrate 10 is limited to less than or equal to... To avoid an exponential increase in etching time due to excessive depth h3, which not only reduces production efficiency but also increases the roughness of the hole sidewalls due to continuous plasma bombardment, affecting the uniformity of metal layer 50 filling, the etching time can be controlled within a reasonable range by controlling the upper limit of the depth h3 of the second hole segment 42 located in the substrate 10, effectively balancing etching efficiency and semiconductor stack 20 quality. In a more preferred embodiment, In some alternative embodiments, h3 can take the value of , , , , , .

[0063] For further information, please refer to [link / reference]. Figure 6The relationship between the thickness d3 of the metal layer 50 in contact with the source 31 in the via 40 and the thickness d4 of the metal layer 50 covering the sidewall of the second via 42 satisfies: d3 ≥ d4. Since the thickness d4 of the metal layer 50 covering the sidewall of the second via 42 is gradually changing, in this embodiment, "d3 ≥ d4" means that the thickness d3 of the metal layer 50 in contact with the source 31 in the via 40 is greater than or equal to the minimum thickness value of the thickness d4 of the metal layer 50 covering the sidewall of the second via 42. By limiting the thickness of the metal layer 50 as described above, sufficient lateral conductive cross-sectional area is ensured between the thicker metal layer 50 at the bottom of the source 31 and the source 31, effectively allowing the charge carriers to contact the metal layer 50 at the bottom of the source 31 laterally, shortening the charge carrier conduction path, increasing the conduction area, thereby reducing the on-resistance and effectively reducing current loss. When d3 ≥ d4, if the thickness d4 of the metal layer 50 on the sidewall of the second hole segment 42 is too thick, metal accumulation at the bottom of the second hole segment 42 is likely to occur during metal deposition due to gravity or surface tension, potentially causing mechanical stress on the semiconductor stack 20 at the second hole segment 42. Furthermore, when the thickness d4 of the metal layer 50 on the sidewall of the second hole segment 42 is thinner, the interface stress between the metal layer 50 and the sidewall of the second hole segment 42 is smaller, which can accommodate the difference in thermal expansion coefficients between the SiC substrate 10 and the metal layer 50 (e.g., gold / copper), reducing the risk of cracking of the metal layer 50 on the sidewall of the second hole segment 42.

[0064] Preferably, the thickness d3 of the metal layer 50 located in the via 40 and in contact with the source electrode 31 is greater than or equal to 2 μm, so as to effectively ensure low on-resistance at the bottom of the source electrode 31 and improve current flow capability. The thickness d4 of the metal layer 50 covering the sidewall of the second hole segment 42 is greater than or equal to 2 μm, so as to ensure reduced contact resistance.

[0065] Optionally, viewed along a cross-section parallel to the gate length and passing through the center of the through-hole 40, the difference between the maximum size W1 and the minimum size W2 of the through-hole 40 is greater than 3 μm. That is, as shown... Figure 5 As shown, in a cross-sectional view along a direction parallel to the first direction X and passing through the center of the via 40, the maximum size W1 of the via 40 is located on the second surface S2 of the substrate 10, and the minimum size W2 of the via 40 is located on the side of the semiconductor stack 20 away from the substrate 10. Specifically, the maximum size 401 of the via (close to the second surface S2 of the substrate 10) is formed with a higher lateral etching rate, resulting in the maximum size W1, while the minimum size 402 of the via (close to the source 31) is formed with a lower etching rate, resulting in the minimum size W2. By controlling the etching time difference and etching rate, a size difference of W1-W2 > 3 μm is achieved. This size difference helps retain substrate 10 material near the source 31, resulting in better lateral heat conduction.

[0066] Please see Figure 6 In this embodiment, the thickness d5 of the metal layer 50 covering the sidewall of the first hole segment 41 and the thickness d6 of the metal layer 50 covering the second surface S2 of the substrate 10 preferably satisfy the following relationship: Since the thickness d5 of the metal layer 50 covering the side of the first hole segment 41 is gradually changing, in this embodiment, "d5≤d6" means that the minimum thickness of the metal layer 50 d5 covering the sidewall of the first hole segment 41 is less than or equal to the thickness d6 of the metal layer 50 covering the second surface S2 of the substrate 10. This means that the thickness d6 of the metal layer 50 covering the second surface S2 of the substrate 10 is less than the maximum thickness d5 of the metal layer 50 covering the sidewall of the first hole segment 41, and the thickness d5 of the metal layer 50 covering the sidewall of the first hole segment 41 is less than 8 μm. By limiting the thickness ratio of d5 and d6 as described above, the low resistance characteristic of the metal layer 50 as the main current path is ensured, while avoiding the risk of substrate 10 warping or cracking of the metal layer 50 covering the first hole segment 41 due to excessive thickness of the metal layer 50 covering the second surface S2 of the substrate 10.

[0067] Please see Figure 3 , Figure 4 ,in, Figure 3 for Figure 1 A partial sectional view at point AA in the middle; Figure 4 for Figure 2 A partial sectional view at point BB; the cutting line AA is located at... Figure 1 The section line BB is located at the position where the through hole 40 passes between two adjacent source electrodes 31 and is parallel to the first direction X. Figure 2 The via 40 passes through the two adjacent source electrodes 31 and is positioned parallel to the first direction X. Further, please refer to... Figure 6A groove 60 is formed within the through-hole 40 between the metal layer 50 covering the sidewall of the through-hole 40 and the metal layer 50 in contact with the source electrode 31 within the through-hole 40. The difference between the minimum horizontal dimension L1 and the maximum horizontal dimension L2 of the groove 60 is less than or equal to 5 μm. The XY plane, formed by the first direction X and the second direction Y, is defined as the horizontal plane. A series of horizontal cross-sections (i.e., cross-sections parallel to the XY plane) are taken from the groove 60 along the third direction Z (perpendicular to the XY plane). For each horizontal cross-section, the dimensions of its cross-sectional profile in the XY plane are measured. Among all horizontal cross-sections, the minimum cross-sectional profile dimension is defined as the minimum horizontal dimension L1, and the maximum cross-sectional profile dimension is defined as the maximum horizontal dimension L2. Preferably, the minimum horizontal dimension L1 of the groove 60 is located near the first hole segment 41, and the maximum horizontal dimension L2 of the groove 60 is located at the bottom of the groove 60 near the semiconductor stack 20, with L2-L1 ≤ 5μm. The design of the groove 60 effectively releases stress, preventing poor coverage and voids when filling with high thermal conductivity materials, which would affect heat dissipation. The stress caused by the difference in thermal expansion coefficients between the metal layer 50 and the substrate 10 can be partially offset by the space of the groove 60, rather than being concentrated at the interface. This also further optimizes heat conduction efficiency and avoids the "heat island effect" caused by excessive thickness of the central metal. Furthermore, by limiting the minimum horizontal width L1 and the maximum horizontal width L2 of the groove 60, and in conjunction with the aperture design of the via 40, the thickness of the metal layer 50 is further ensured to have a gradual design, thereby effectively mitigating the CTE mismatch caused by temperature differences and reducing thermal stress. Moreover, its positional limitation effectively guides heat from the semiconductor stack 20 (high-temperature region) to the substrate 10 (heat dissipation region) through a wider horizontal width. The L2>L1 design creates a "wide cross-section current-conducting region" at the bottom of the groove 60 (near the semiconductor stack 20). Combined with the synergistic control of the thickness of the metal layer 50, it can suppress current accumulation, reduce metal atom accumulation caused by electromigration, and lower contact resistance.

[0068] It should be noted that in other implementations, at least one source is provided with a via 40. For example, in a single semiconductor device with multiple sources 31, one source 31 is provided with a via 40. The number of vias 40 can be one or more, while the other sources 31 are not provided with vias 40.

[0069] It should be noted that in other implementations, the number of vias 40 provided at different locations of the multiple sources 31 of a single semiconductor device can be the same or different.

[0070] It should be noted that in other implementations, the sum of the back hole areas of the vias 40 provided on the multiple sources 31 of a single semiconductor device can be the same or different.

[0071] It should be noted that in other implementations, the number of vias 40 provided on the multiple sources 31 of a single semiconductor device may be different, but the sum of the back via areas may be the same. Alternatively, the number of vias 40 provided on the different sources 31 may be different, and the sum of the back via areas may be different.

[0072] Example 2 The semiconductor device provided in this second embodiment differs from that in the first embodiment in that the contour lines of the first segment 41 and / or the second segment 42 of the through-hole 40 in the cross-sectional plane are not straight lines, but can be curves or arcs, such as... Figures 10-13 As shown.

[0073] Figure 10 As shown, the first hole segment 41 is a curve or arc, the second hole segment 42 is a straight line, and the first included angle α is the junction of the first hole segment 41 and the second hole segment 42 (i.e., Figure 10 The angle between the tangent of the first hole segment (at the junction of the first hole segment 41 and the second hole segment 42, located at the dashed line position in the horizontal direction) and the other side of the semiconductor stack 20. The first hole segment 41 is concave outward from the dashed line position between the junction of the first hole segment 41 and the second hole segment 42 and the second surface S2.

[0074] Figure 11 As shown, the first hole segment 41 is a curve or arc, and the second hole segment 42 is a straight line. The first included angle α is the angle between the tangent at the junction of the first hole segment 41 and the second hole segment 42 and the other side of the semiconductor stack 20. The first hole segment 41 bulges inward relative to the dashed line at the junction of the first hole segment 41 and the second hole segment 42 and the second surface S2.

[0075] Figure 12 As shown, the first hole segment 41 is a curve or arc, the second hole segment 42 is a curve or arc, and the first included angle α is the angle between the tangent at the junction of the first hole segment 41 and the second hole segment 42 and the other side of the semiconductor stack 20. The second included angle β is the angle between the tangent at the junction of the second hole segment 42 and the other side of the semiconductor stack 20 and the other side of the semiconductor stack 20.

[0076] The first hole segment 41 bulges inward from the junction of the first hole segment 41 and the second hole segment 42 to the dashed line at the junction of the first hole segment 41 and the second surface S2. The second hole segment 42 bulges outward from the junction of the first hole segment 41 and the second hole segment 42 to the dashed line at the junction of the second hole segment 41 and the other side of the semiconductor stack 20.

[0077] Figure 13As shown, the first hole segment 41 is a curve or arc, and the second hole segment 42 is a curve or arc. The first included angle α is the angle between the tangent at the junction of the first hole segment 41 and the second hole segment 42 and the other side of the semiconductor stack 20. The second included angle β is the angle between the tangent at the junction of the second hole segment 42 and the other side of the semiconductor stack 20 and the other side of the semiconductor stack 20. The first hole segment 41 is concave outward from the point where the junction of the first hole segment 41 and the second hole segment 42 extends to the point where the first hole segment 41 meets the second surface S2 (dashed line). The second hole segment 42 is concave outward from the point where the junction of the first hole segment 41 and the second hole segment 42 extends to the point where the second hole segment 41 meets the other side of the semiconductor stack 20 (dashed line).

[0078] Example 3 This utility model embodiment also provides an electronic device, including a semiconductor device. The electronic device may be a radio frequency device, and the semiconductor device is a gallium nitride semiconductor device. The specific structure, function, and role of the semiconductor device can be referred to the foregoing embodiments one and two, and will not be repeated here.

[0079] It should be noted that in other implementations, vias 40 can also be provided outside the active region of the semiconductor device, and vias 40 are provided in the pad area of ​​the passive region of the device.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first surface and a second surface opposite to each other; A semiconductor stack is located on the first surface, having one side and another side facing each other, with one side of the semiconductor stack in contact with the first surface; The semiconductor stack has an active region; the semiconductor stack includes a heterojunction structure; Multiple drains and multiple gates are spaced apart within the active region; the multiple drains are electrically connected to each other via a drain bus, and the multiple gates are electrically connected to each other via a gate bus. Multiple sources are spaced apart and arranged within the active region between the drain bus and the gate bus; The via extends along the thickness direction of the substrate from the second surface toward the substrate and the semiconductor stack to penetrate the semiconductor stack and expose the source electrode; A metal layer covers the second surface and extends to cover the sidewall of the via, and contacts the source electrode; The thickness d3 of the metal layer in the via that is in contact with the source electrode is greater than the thickness d2 of the semiconductor stack.

2. The semiconductor device according to claim 1, characterized in that: The thickness of the metal layer covering the sidewall of the via decreases from the second surface toward the semiconductor stack.

3. The semiconductor device according to claim 1, characterized in that: Viewed in cross section along the thickness direction of the substrate, the via includes a first segment located within the substrate and connected to the second surface, and a second segment spanning the substrate and the semiconductor stack. The second segment extends from the end of the first segment away from the second surface toward the semiconductor stack and penetrates the entire semiconductor stack. The first angle α formed between the extension line of the sidewall of the first segment and the other side of the semiconductor stack is greater than the second angle β formed between the sidewall of the second segment and the other side of the semiconductor stack.

4. The semiconductor device according to claim 3, characterized in that: The depth h1 of the first hole segment is greater than the depth h2 of the second hole segment.

5. The semiconductor device according to claim 1, characterized in that: The number of vias provided below a single source electrode is multiple, and the minimum distance W4 between adjacent vias satisfies: W4≥6μm.

6. The semiconductor device according to claim 5, characterized in that: W4≥30μm.

7. The semiconductor device according to claim 1, characterized in that: Viewed from above, the via on the other side of the semiconductor stack is a rounded rectangle.

8. The semiconductor device according to claim 1, characterized in that: The maximum length W3 of a single via along the width direction of the gate satisfies the following range: 15μm≤W3≤80μm.

9. The semiconductor device according to claim 1, characterized in that: At least one source electrode is provided with the via, and the top-view projected area of ​​a single source electrode on the other side of the semiconductor stack is defined as S; the sum of the end-face areas formed by all vias located below the single source electrode on the other side of the semiconductor stack is defined as Si. TV Then 1.3 < S / S TV <20; the length of a single source electrode is between 100μm and 600μm, and the width of a single source electrode is between 20μm and 120μm.

10. An electronic device, characterized in that: Includes the semiconductor device described in any one of claims 1 to 9.

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