Semiconductor device

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a channel layer, a barrier layer, a first ohmic electrode and a gate, an auxiliary semiconductor layer, a field plate and a first passivation layer. The channel layer is located on one side of the substrate; the barrier layer is located on a side of the channel layer away from the substrate; the first ohmic electrode and the gate are located on a side of the barrier layer away from the channel layer; the auxiliary semiconductor layer is located on a side of the barrier layer away from the channel layer, the auxiliary semiconductor layer is located between the first ohmic electrode and the gate, the auxiliary semiconductor layer is in contact with the barrier layer, and the auxiliary semiconductor layer is provided with a first opening; the field plate is located on a side of the auxiliary semiconductor layer away from the barrier layer, and a side surface of a side of the field plate facing the first ohmic electrode is located in a normal projection of the first opening on the substrate; the first passivation layer is located between the field plate and the auxiliary semiconductor layer, and the first passivation layer covers the first ohmic electrode and the gate, and the first passivation layer fills the first opening. The electric field can be optimized.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and specifically to a semiconductor device. Background Technology

[0002] Semiconductor devices can include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), high electron mobility transistors (HEMTs), and modulation-doped FETs (MODFETs). Among them, the high electron mobility transistor (HEMT) is a field-effect transistor that operates based on a two-dimensional electron gas (2DEG) at the heterojunction interface. Due to its excellent characteristics such as high electron mobility, high saturation velocity, high operating frequency, and high power density, it has become a core device in radio frequency communication, power electronics, and millimeter-wave devices. Utility Model Content

[0003] This application provides a semiconductor device, including: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate; The first ohmic electrode and the gate are located on the side of the barrier layer away from the channel layer; An auxiliary semiconductor layer is located on the side of the barrier layer away from the channel layer. The auxiliary semiconductor layer is located between the first ohmic electrode and the gate. The auxiliary semiconductor layer is in contact with the barrier layer. The auxiliary semiconductor layer has a first opening. The field plate is located on the side of the auxiliary semiconductor layer away from the barrier layer, and the orthographic projection of the side of the field plate facing the first ohmic electrode on the substrate is located within the orthographic projection of the first opening on the substrate. A first passivation layer is located between the field plate and the auxiliary semiconductor layer, and the first passivation layer covers the first ohmic electrode and the gate, and the first passivation layer fills the first opening.

[0004] In some embodiments, the semiconductor device further includes an insertion layer located on the side of the auxiliary semiconductor layer near the barrier layer, and the insertion layer is in contact with the auxiliary semiconductor layer.

[0005] In some embodiments, the semiconductor device further includes a protective layer located on the side of the auxiliary semiconductor layer away from the barrier layer, and the protective layer is in contact with the auxiliary semiconductor layer.

[0006] In some embodiments, in the direction of the gate pointing towards the first ohmic electrode, the distance between the side of the field plate near the first ohmic electrode and the side of the first opening near the gate is one-third to two-thirds of the width of the opening.

[0007] In some embodiments, the first opening extends through the surface of the auxiliary semiconductor layer near the substrate and the surface away from the substrate.

[0008] In some embodiments, the number of field plates is at least two, the number of first openings is at least two, and the orthographic projection of the side of each field plate near the first ohmic electrode onto the substrate lies within the orthographic projection of one of the first openings onto the substrate.

[0009] In some embodiments, the auxiliary semiconductor layer further comprises a second opening, wherein... The semiconductor layer further includes a p-type cap layer, which is located between the barrier layer and the gate. The p-type cap layer is located within the second opening, and there is a gap between the side of the second opening and the side of the p-type cap layer. Alternatively, the gate is in contact with the barrier layer, the gate is located within the second opening, and there is a gap between the second opening and the gate.

[0010] In some embodiments, the auxiliary semiconductor layer is made of the same material as the barrier layer.

[0011] In some embodiments, the semiconductor device further includes a second ohmic electrode located on the side of the gate away from the first ohmic electrode, and the auxiliary semiconductor layer is located between the second ohmic electrode and the gate.

[0012] In some embodiments, the semiconductor device further includes a second ohmic electrode located on the side of the gate away from the first ohmic electrode, and the field plate is electrically connected to the second ohmic electrode or the gate.

[0013] In some embodiments, the first ohmic electrode is a drain or a source.

[0014] In some embodiments, the semiconductor layer further includes a p-type cap layer located between the barrier layer and the gate, wherein the orthogonal projection of the field plate on the substrate overlaps with the orthogonal projection of the p-type cap layer on the substrate.

[0015] In some embodiments, the orthographic projection of the field plate on the substrate overlaps with the orthographic projection of the gate on the substrate.

[0016] In some embodiments, the semiconductor device further includes a shielding structure located between the auxiliary semiconductor layer and the field plate. The shielding structure is made of a semiconductor material. The shielding structure is spaced apart from the field plate and the first opening. The orthographic projection of the side of the field plate facing the first ohmic electrode onto the substrate is located within the orthographic projection of the shielding structure onto the substrate.

[0017] The beneficial effects of this application include: In this embodiment, the auxiliary semiconductor layer has a first opening, which overlaps longitudinally with the side of the field plate near the first ohmic electrode (the end of the field plate). Therefore, the thickness of the barrier layer below the end of the field plate can be set to be thinner. The thinner the barrier layer, the lower the 2DEG concentration, thus reducing the 2DEG concentration below the end of the field plate. Simultaneously, the total thickness of the auxiliary semiconductor layer (excluding the first opening) and the barrier layer is greater than the original barrier layer thickness. By changing the polarization distribution or band structure, the auxiliary semiconductor layer increases the effective positive charge at the heterojunction interface (the interface between the barrier layer and the channel layer), thereby increasing the DEG areal density. Therefore, the area of ​​the auxiliary semiconductor layer and the barrier layer (excluding the first opening) can have a higher 2DEG concentration than the original barrier layer, further reducing the on-resistance of the semiconductor device. Thus, in this embodiment, the region containing the electric field spike and the high-concentration 2DEG region avoid each other, preventing their superposition from weakening the field plate's control effect on the electric field.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 The diagram shown is a schematic cross-sectional view of a semiconductor device. Figures 2-11 The diagram shown is a cross-sectional view of several semiconductor devices provided in an exemplary embodiment of this application; Figures 12a-12dThe diagram shown is a partial structural schematic of each step of a method for fabricating a semiconductor device provided in an exemplary embodiment of this application.

[0021] In the figure: 1-substrate; 2-buffer layer; 3-channel layer; 4-barrier layer; 5-auxiliary semiconductor layer; 5a-first opening; 5b-second opening; 61-first ohmic electrode (drain); 62-second ohmic electrode (source); 63-gate; 7-p-type cap layer; 8-field plate; 81-side (field plate); 91-first passivation layer; 92-second passivation layer; 93-interconnect metal; 94-insertion layer; 95-protective layer; 96-shielding structure; 97-mask structure. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0024] It should be noted that when element A, such as a layer, film, or region, is referred to as "on the side of element B away from element C," it means that element A can be directly on the surface of element B on the side away from element C, or that an intermediate layer, intermediate region, or intermediate element may exist between element B and element A. When element A, such as a layer, film, or region, is referred to as "between element B and element C," it means that only element A exists between element B and element C, or that an intermediate layer, intermediate region, or intermediate element may exist between element A and element B, or between element A and element C.

[0025] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0026] While terms such as "first," "second," etc., can be used to describe various components, such components are not limited by these terms. These terms are only used to distinguish one component from another and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Where there is no conflict, the features in the embodiments described below in this application may complement or combine with each other.

[0027] The semiconductor devices and their fabrication methods in the embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments may complement or combine with each other.

[0028] Figure 1 The diagram shows a cross-sectional view of a semiconductor device. The semiconductor device includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a source 62, a drain 61, a p-type cap layer 7, and a gate 63, all stacked sequentially on the side of the barrier layer 4 away from the channel layer 3. The region between the gate 63 and the drain 61 is the drift region. In this semiconductor device, the barrier layer 4 below the p-type cap layer 7 is thinner than the barrier layer 4 located in the drift region. Specifically, designing the barrier layer 4 in the drift region to be relatively thicker ensures a higher saturation current, while designing the barrier layer 4 below the p-type cap layer 7 to be relatively thinner ensures a higher threshold voltage. However, the greater thickness of the barrier layer 4 in the drift region leads to a higher 2DEG concentration in the 2DEG (Two-Dimensional Electron Gas) region between the barrier layer 4 and the channel layer 3, enhancing the channel charge density. This results in a narrower depletion region in the off-state, increasing the electric field strength at the same voltage and causing a significant increase in the electric field peak near the drain 61 (i.e., "electric field concentration"), thus leading to electric field deterioration. Related technologies typically use a field plate 8 in the drift region to control the electric field; however, this introduces a new electric field peak at the end of the field plate 8 near the drain 61. This new electric field peak, combined with the high concentration of 2DEG, weakens the control effect of the field plate 8.

[0029] Therefore, the semiconductor device and its fabrication method provided in this application are intended to solve or improve the above-mentioned technical problems.

[0030] This application provides a semiconductor device, such as Figure 2As shown, it includes a substrate 1, a channel layer 3, a barrier layer 4, a first ohmic electrode 61 and a gate 63, an auxiliary semiconductor layer 5, a field plate 8, and a first passivation layer 91. The structure includes a channel layer 3 located on one side of the substrate 1; a barrier layer 4 located on the side of the channel layer 3 away from the substrate 1; a first ohmic electrode 61 and a gate 63 located on the side of the barrier layer 4 away from the channel layer 3; an auxiliary semiconductor layer 5 located on the side of the barrier layer 4 away from the channel layer 3, situated between the first ohmic electrode 61 and the gate 63, in contact with the barrier layer 4, and having a first opening 5a; a field plate 8 located on the side of the auxiliary semiconductor layer 5 away from the barrier layer 4, with the orthographic projection of the side 81 of the field plate 8 facing the first ohmic electrode 61 onto the substrate 1 located within the orthographic projection of the first opening 5a onto the substrate 1; a first passivation layer 91 located between the field plate 8 and the auxiliary semiconductor layer 5, covering the first ohmic electrode 61 and the gate 63, and filling the first opening 5a.

[0031] In this embodiment, the auxiliary semiconductor layer 5 has a first opening 5a, which overlaps longitudinally with the side 81 (end of the field plate 8) of the field plate 8 near the first ohmic electrode 61. Therefore, the thickness of the barrier layer 4 below the end of the field plate 8 can be set thinner. The thinner the barrier layer 4, the lower the 2DEG concentration, thus reducing the 2DEG concentration below the end of the field plate 8. Simultaneously, the total thickness of the auxiliary semiconductor layer 5 (excluding the first opening 5a) and the barrier layer 4 is greater than the original barrier layer 4 thickness. By changing the polarization distribution or band structure, the auxiliary semiconductor layer 5 increases the effective positive charge at the heterojunction interface (the interface between the barrier layer 4 and the channel layer 3), thereby increasing the 2DEG areal density. Therefore, the auxiliary semiconductor layer 5 and the barrier layer 4 (excluding the first opening 5a) can have a higher 2DEG concentration than the original barrier layer 4, further reducing the on-resistance of the semiconductor device. Therefore, in this embodiment, the region where the electric field peak is located and the region with high concentration of 2DEG avoid each other, thus preventing the superposition of the two from weakening the field plate's control effect on the electric field.

[0032] In some embodiments, the first ohmic electrode 61 can be a drain 61, the field plate 8 can be located between the gate 63 and the drain 61, and the first opening 5a of the auxiliary semiconductor layer 5 can also be located between the gate 63 and the drain 61. Further, the semiconductor device also includes a second ohmic electrode 62, which can be a source 62. The second ohmic electrode 62 is located on the side of the gate 63 away from the first ohmic electrode 61, and the auxiliary semiconductor layer 5 is located between the second ohmic electrode 62 and the gate 63. With this configuration, the auxiliary semiconductor layer 5 can also avoid the superposition of a strong electric field region and a high-concentration 2DEG region located between the second ohmic electrode 62 and the gate 63.

[0033] In some embodiments, the second ohmic electrode 62 is a source electrode 62, such as Figure 3 As shown, a portion of the field plate 8 can be located between the gate 63 and the second ohmic electrode 62, and the first opening 5a of the auxiliary semiconductor layer 5 can also be located between the gate 63 and the second ohmic electrode 62. In this case, the semiconductor device can be a transistor structure with bidirectional conduction and bidirectional turn-off.

[0034] In some embodiments, the first ohmic electrode 61 may also be a source electrode (not shown in the figure). A portion of the field plate 8 may be located between the gate 63 and the first ohmic electrode 61, and the first opening 5a of the auxiliary semiconductor layer 5 may also be located between the gate 63 and the first ohmic electrode 61.

[0035] In some embodiments, the first ohmic electrode 61 may include a conductive material, which may include a metal, alloy, doped semiconductor material (e.g., doped crystalline silicon) or other suitable conductive material, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials.

[0036] In some embodiments, the second ohmic electrode 62 may include a conductive material, which may include a metal, alloy, doped semiconductor material (e.g., doped crystalline silicon) or other suitable conductive material, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials.

[0037] In some embodiments, the material of the gate 63 may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and its compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)) or other suitable materials.

[0038] In some embodiments, substrate 1 may comprise silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs) or other semiconductor materials, and may also comprise sapphire, silicon-on-insulator (SOI) or other suitable materials.

[0039] In some embodiments, the channel layer 3 can be a material with high electron mobility, such as gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP), or indium gallium arsenide (In). x Ga 1-x As, where 0 < x < 1, aluminum gallium nitride (Al x Ga 1- xN, where 0 < x < 1, etc. Preferably, the channel layer 3 can be gallium nitride (GaN), and the bandgap of GaN is about 3.4 eV.

[0040] In some embodiments, a buffer layer 2 is further provided between the channel layer 3 and the substrate 1. The buffer layer 2 is used to reduce the lattice mismatch between the substrate 1 and the channel layer 3. The material of the buffer layer 2 can be the same as that of the channel layer 3.

[0041] In some embodiments, the barrier layer 4 can be a wide-bandgap semiconductor material, which may include group III-V compounds, such as aluminum gallium nitride (Al₂O₃). x Ga 1-x N, where x≤1), AlGaAs, InAlGaNi (In a Al b Ga 1-a-b N, where a+b≤1), aluminum indium phosphide (AlInP), aluminum gallium nitride (Al x Ga 1-x N, where x≤1), indium aluminum nitrogen (In x Al 1-x N, where x < 1). The bandgap of the barrier layer 4 can be larger than the bandgap of the channel layer 3. Preferably, the barrier layer 4 can be aluminum gallium nitride (Al₂O₃). x Ga 1-x N, where x≤1), Al x Ga 1-x The band gap of N is approximately 3.4 to 6.2 eV.

[0042] It should be noted that due to the band difference between the channel layer 3 and the barrier layer 4, the barrier layer 4 can form a potential well for electrons, which restricts the movement of electrons in the direction perpendicular to the barrier layer 4, while allowing them to move freely in the plane of the barrier layer 4, thus forming a two-dimensional electron gas (2DEG) region.

[0043] In some embodiments, the auxiliary semiconductor layer 5 can be made of a material with high electron mobility, such as gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP), or indium gallium arsenide (In). x Ga 1-x As, where 0 < x < 1, aluminum gallium nitride (Al x Ga 1-x N, where 0 < x < 1, indium aluminum nitrogen (In x Al 1-x N, where x < 1), etc. Preferably, the barrier layer 4 can be aluminum gallium nitride (Al₂O₃), where x < 1, etc. x Ga 1-x N, where x≤1).

[0044] In some embodiments, the auxiliary semiconductor layer 5 can be made of the same material as the barrier layer 4. This effectively increases the thickness of the barrier layer 4, thereby directly increasing the density of 2DEGs and significantly improving the 2DEG concentration outside the region of the first opening 5a. In some examples, both the barrier layer 4 and the auxiliary semiconductor layer 5 are made of AlGaN.

[0045] In other embodiments, the material of the auxiliary semiconductor layer 5 may differ from that of the barrier layer 4. In some examples, the barrier layer 4 is made of AlGaN, and the auxiliary semiconductor layer 5 is made of AlN, which can increase the 2DEG concentration by enhancing the total polarization charge and increasing the conduction band step. The auxiliary semiconductor layer 5 may also be made of InAlN, which matches the GaN lattice, has strong spontaneous polarization, and is not piezoelectrically polarized, thus also increasing the 2DEG concentration.

[0046] In some embodiments, the thickness of the auxiliary semiconductor layer 5 is greater than the thickness of the barrier layer 4. This configuration maximizes the 2DEG concentration in the region excluding the first opening 5a. In some embodiments, the thickness of the barrier layer 4 ranges from 10 nm to 15 nm. Furthermore, considering the relatively small thickness of the barrier layer 4 and the difficulty in directly etching openings onto it from a fabrication process perspective, in this embodiment, the auxiliary semiconductor layer 5 is disposed on the side of the barrier layer 4 away from the channel layer 3 to ensure that the electric field spike at the end of the field plate 8 and the high-concentration 2DEG region avoid each other. That is, the orthogonal projections of the end of the field plate 8 and the region excluding the first opening 5a (the high-concentration 2DEG region) onto the substrate 1 do not overlap, thereby mitigating the problem that the superposition of the field plate 8's end spike and the high-concentration 2DEG region weakens the field control effect of the field plate 8.

[0047] In some embodiments, the field plate 8 can be made of metal, multilayer metal, or inorganic metal compound. For example, the field plate 8 can be made of Al, Cu, Ni / Au, Ti / Al / Ti / Au, Ti / Al / Ni / Au, TiN, etc.

[0048] In some embodiments, the material of the first passivation layer 91 may be phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y ), aluminum oxide (Al2O3), etc.

[0049] In some embodiments, such as Figure 2As shown, the semiconductor device also includes a second passivation layer 92 located on the side of the field plate 8 away from the first passivation layer 91. An interconnect metal 93 is disposed on the side of the second passivation layer 92 away from the field plate 8, and both ends of the interconnect metal 93 are electrically connected to the field plate 8 and the second ohmic electrode 62, respectively. Exemplarily, the second ohmic electrode 62 can be a source electrode 62. This configuration increases the input capacitance C of the semiconductor device. ds This further improves the efficiency of input signal injection. That is, the field plate 8 can be electrically connected to the second ohmic electrode 62. In other embodiments, such as... Figure 4 As shown, the field plate 8 can also be electrically connected to the gate 63.

[0050] In some embodiments, such as Figure 2 As shown, the distance d2 between the end of the field plate 8 near the first ohmic electrode 61 and the barrier layer 4 is smaller than the distance d1 between the area of ​​the field plate 8 other than the end and the barrier layer 4. The orthographic projection of the end of the field plate 8 near the first ohmic electrode 61 onto the substrate 1 lies within the orthographic projection of the first opening 5a onto the substrate 1. This arrangement results in a smaller distance between the end of the field plate 8 and the barrier layer 4, allowing for better adjustment of the electric field at the first opening 5a.

[0051] In some embodiments, the semiconductor device further includes a p-type cap layer 7 located between the barrier layer 4 and the gate 63 to enable the semiconductor device to form an enhancement-mode HEMT. In some embodiments, the p-type cap layer 7 may be made of p-type GaN.

[0052] In some embodiments, such as Figure 2 As shown, the width w1 of the first opening 5a can range from 0.4 to 0.6 µm.

[0053] In some embodiments, in the direction from the gate 63 to the first ohmic electrode 61, the distance x1 between the side 81 of the field plate 8 near the first ohmic electrode 61 and the side of the first opening 5a near the gate 63 is one-third to two-thirds of the width w1 of the opening. This arrangement ensures that a large area at the end of the field plate 8 falls within the opening, thereby reducing the risk of electric field spikes.

[0054] In some embodiments, such as Figure 2 As shown, the first opening 5a penetrates both the surface of the auxiliary semiconductor layer 5 near the substrate 1 and the surface away from the substrate 1. This configuration allows the first opening 5a on the auxiliary semiconductor layer 5 to be formed using a selective epitaxial growth process. Simultaneously, the thickness of the auxiliary semiconductor layer 5 located in the region of the first opening 5a can be reduced to zero.

[0055] In other embodiments, such as Figure 5As shown, the first opening 5a can also be groove-shaped, penetrating only the surface of the auxiliary semiconductor layer 5 away from the substrate 1. This configuration can improve the film continuity of the auxiliary semiconductor layer 5 and enhance the structural strength of the semiconductor device.

[0056] In some embodiments, the semiconductor device may have one first opening 5a or at least two first openings 5a. The total width of the first openings 5a is greater than or equal to 20% of the distance between the gate 63 and the first ohmic electrode 61. This arrangement allows the end of the field plate 8 to fall into the opening as much as possible, thereby improving the effect of reducing electric field spikes.

[0057] In some embodiments, such as Figure 2 As shown, the spacing w2 between the p-type cap layer 7 and the first ohmic electrode 61 is less than or equal to 2µm. This configuration results in a relatively small overall width of the semiconductor device. Furthermore, by providing the first opening 5a on the auxiliary semiconductor layer 5, the sharp peak at the end of the field plate 8 can be avoided. This also circumvents the limitation that multiple field plates 8 cannot be set in the small gap area between the p-type cap layer 7 and the first ohmic electrode 61 to enhance the control of the electric field. In some examples, the spacing w2 between the p-type cap layer 7 and the first ohmic electrode 61 can be 1.8µm, 1.6µm, etc.

[0058] In some embodiments, such as Figure 6 As shown, the semiconductor device also includes an insertion layer 94, which is located on the side of the auxiliary semiconductor layer 5 near the barrier layer 4 and is in contact with the auxiliary semiconductor layer 5. With this configuration, the insertion layer 94 can serve as a lattice transition layer, reducing growth defects in the auxiliary semiconductor layer 5. In some examples, the insertion layer 94 can be made of AlN. Since AlN is a wide bandgap material (6.2 eV, higher than AlGaN), it can block electron tunneling in the off-state, suppress leakage current from the gate 63 to the channel, and mitigate current collapse. Simultaneously, it can enhance polarization charge to further increase the 2DEG concentration.

[0059] In some embodiments, the thickness of the insertion layer 94 can range from 0.5 to 2 nm.

[0060] In some embodiments, the orthographic projection of the insertion layer 94 on the substrate 1 and the orthographic projection of the auxiliary semiconductor layer 5 on the substrate 1 can completely overlap. In this way, the insertion layer 94 and the auxiliary semiconductor layer 5 can be fabricated using the same mask, simplifying the fabrication process.

[0061] In other embodiments, the insert layer 94 may also be a continuous thin film over a single surface. This eliminates the need for patterning, further simplifying the process.

[0062] In some embodiments, such as Figure 7As shown, the semiconductor device also includes a protective layer 95, which is located on the side of the auxiliary semiconductor layer 5 away from the barrier layer 4, and is in contact with the auxiliary semiconductor layer 5. This configuration prevents the auxiliary semiconductor layer 5 from being chemically or physically eroded during the later stages of semiconductor device fabrication, thereby protecting the surface of the auxiliary semiconductor layer 5 away from the barrier layer 4. This ensures that the concentration of 2DEG does not decrease due to erosion and avoids increased contact resistance caused by surface roughness of the auxiliary semiconductor layer 5. In some embodiments, the protective layer 95 may be made of GaN.

[0063] In some embodiments, the auxiliary semiconductor layer 5 includes at least one of p-type and n-type doped materials. In some examples, the auxiliary semiconductor layer 5 may include a p-type doped material, which, when configured, can deplete the 2DEG, further optimizing the electric field. Exemplarily, the p-type doped material may be a Group IIA element, such as Mg. In some examples, the auxiliary semiconductor layer 5 may also include an n-type doped material, which can provide the 2DEG, reducing the on-resistance of the semiconductor device. Exemplarily, the n-type doped material may be at least one of Si, Ge, N, and P.

[0064] In some embodiments, such as Figure 8 As shown, the semiconductor device may simultaneously include an insertion layer 94 and a protective layer 95, with the same beneficial effects as the aforementioned embodiments.

[0065] In some embodiments, such as Figure 9 As shown, there are at least two field plates 8 and at least two first openings 5a. The orthographic projection of the side 81 of each field plate 8 closest to the first ohmic electrode 61 onto the substrate 1 lies within the orthographic projection of one of the first openings 5a onto the substrate 1. In this embodiment, a wider range of electric field control can also be achieved by setting multiple layers of field plates 8.

[0066] In some embodiments, such as Figure 2 As shown, the auxiliary semiconductor layer 5 also has a second opening 5b. The semiconductor layer also includes a p-type cap layer 7, which is located between the barrier layer 4 and the gate 63. The p-type cap layer 7 is located within the second opening 5b, and there is a gap between the side of the second opening 5b and the side of the p-type cap layer 7. In this embodiment, considering that a strong electric field region will be formed around the p-type cap layer 7, the p-type cap layer 7 is placed within the second opening 5b to avoid the strong electric field region and the high concentration 2DEG region from overlapping and weakening the control effect of the field plate 8.

[0067] In some embodiments, such as Figure 2As shown, the orthographic projection of the field plate 8 onto the substrate 1 overlaps with the orthographic projection of the p-type cap layer 7 onto the substrate 1. With this configuration, the field plate 8 can modulate the electric field of the strong electric field region formed around the p-type cap layer 7 to further optimize the electric field.

[0068] In some embodiments, the auxiliary semiconductor layer 5 further includes a second opening 5b, such as... Figure 10 As shown, the gate 63 is in contact with the barrier layer 4, the gate 63 is located within the second opening 5b, and there is a gap between the second opening 5b and the gate 63. Similarly to the previous embodiment, in the previous embodiment, an enhancement-type HEMT can be formed when a p-type cap layer 7 is provided between the gate 63 and the barrier layer 4; in this embodiment, a depletion-type HEMT can be formed when the gate 63 and the barrier layer 4 are in direct contact.

[0069] In some embodiments, such as Figure 2 or Figure 9 As shown, the orthographic projection of the field plate 8 onto the substrate 1 overlaps with the orthographic projection of the gate 63 onto the substrate 1. With this configuration, the field plate 8 can adjust the Miller capacitance C of the semiconductor device. gd and input capacitor C gs The ratio between them, that is, the Miller ratio, is used to prevent the gate 63 from being turned on erroneously and to improve the sensitivity of the semiconductor device.

[0070] In some embodiments, such as Figure 11 As shown, the semiconductor device also includes a shielding structure 96, which is located between the auxiliary semiconductor layer 5 and the field plate 8. The shielding structure 96 is made of semiconductor material. There is a gap between the shielding structure 96, the field plate 8, and the first opening 5a. The orthographic projection of the side 81 of the field plate 8 facing the first ohmic electrode 61 on the substrate 1 is located within the orthographic projection of the shielding structure 96 on the substrate 1.

[0071] In this embodiment, the shielding structure 96 can further improve the peak at the end of the field plate 8, thereby avoiding the overlap between the peak at the end of the field plate 8 and the high-concentration 2DEG region, and enhancing the field plate 8's control over the electric field. In some embodiments, the material of the shielding structure 96 may be the same as or different from the material of the field plate 8. Exemplarily, the material of the shielding structure 96 may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and their compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)), or other suitable materials.

[0072] For ease of understanding, this application also provides an embodiment of a method for fabricating a semiconductor structure, specifically including the following steps: Step 100: As Figure 12aAs shown, a channel layer 3 is formed on the substrate 1 and a barrier layer 4 is formed on the side of the channel layer 3 away from the substrate 1; Step 200: As Figure 12b As shown, a mask structure 97 is formed on the side of the barrier layer 4 away from the substrate 1; Step 300: As Figure 12c As shown, an auxiliary semiconductor layer 5 is grown on the barrier layer 4 in the area excluding the mask structure 97; Step 400: As Figure 12d As shown, the mask structure 97 is removed.

[0073] In this embodiment, an auxiliary semiconductor layer 5 can be grown on the barrier layer 4 using a selective epitaxial process. This ensures the flatness of the surface of the auxiliary semiconductor layer 5 away from the substrate 1, thereby reducing the on-resistance.

[0074] In some embodiments, the following steps are included prior to step 200: like Figure 12a As shown, a p-type cap layer 7 is formed on the side of the barrier layer 4 away from the substrate 1. Thus, the fabricated semiconductor device can be an enhancement-mode HEMT.

[0075] In other embodiments, the semiconductor device can also be fabricated by first forming a thin film of an auxiliary semiconductor layer 5 over an entire surface, and then etching the thin film of the auxiliary semiconductor layer 5 to form a first opening 5a.

[0076] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0077] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate; The first ohmic electrode and the gate are located on the side of the barrier layer away from the channel layer; An auxiliary semiconductor layer is located on the side of the barrier layer away from the channel layer. The auxiliary semiconductor layer is located between the first ohmic electrode and the gate. The auxiliary semiconductor layer is in contact with the barrier layer. The auxiliary semiconductor layer has a first opening. The field plate is located on the side of the auxiliary semiconductor layer away from the barrier layer, and the orthographic projection of the side of the field plate facing the first ohmic electrode on the substrate is located within the orthographic projection of the first opening on the substrate. A first passivation layer is located between the field plate and the auxiliary semiconductor layer, and the first passivation layer covers the first ohmic electrode and the gate, and the first passivation layer fills the first opening.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an insertion layer located on the side of the auxiliary semiconductor layer near the barrier layer, and the insertion layer is in contact with the auxiliary semiconductor layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes a protective layer located on the side of the auxiliary semiconductor layer away from the barrier layer, and the protective layer is in contact with the auxiliary semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, In the direction from the gate to the first ohmic electrode, the distance between the side of the field plate near the first ohmic electrode and the side of the first opening near the gate is one-third to two-thirds of the width of the opening.

5. The semiconductor device according to claim 1, characterized in that, The first opening extends through the surface of the auxiliary semiconductor layer near the substrate and the surface away from the substrate.

6. The semiconductor device according to claim 1, characterized in that, The number of field plates is at least two, the number of the first openings is at least two, and the orthographic projection of the side of each field plate near the first ohmic electrode on the substrate lies within the orthographic projection of one of the first openings on the substrate.

7. The semiconductor device according to claim 1, characterized in that, The auxiliary semiconductor layer also has a second opening, wherein... The semiconductor layer further includes a p-type cap layer, which is located between the barrier layer and the gate. The p-type cap layer is located within the second opening, and there is a gap between the side of the second opening and the side of the p-type cap layer. Alternatively, the gate is in contact with the barrier layer, the gate is located within the second opening, and there is a gap between the second opening and the gate.

8. The semiconductor device according to claim 1, characterized in that, The auxiliary semiconductor layer is made of the same material as the barrier layer.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second ohmic electrode located on the side of the gate away from the first ohmic electrode, and the auxiliary semiconductor layer is located between the second ohmic electrode and the gate.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second ohmic electrode located on the side of the gate away from the first ohmic electrode, and the field plate is electrically connected to the second ohmic electrode or the gate.

11. The semiconductor device according to claim 1, characterized in that, The first ohmic electrode is either the drain or the source.

12. The semiconductor device according to claim 1, characterized in that, The semiconductor layer further includes a p-type cap layer, which is located between the barrier layer and the gate, and the orthogonal projection of the field plate on the substrate overlaps with the orthogonal projection of the p-type cap layer on the substrate.

13. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the field plate on the substrate overlaps with the orthographic projection of the gate on the substrate.

14. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a shielding structure located between the auxiliary semiconductor layer and the field plate. The shielding structure is made of semiconductor material. The shielding structure is spaced apart from the field plate and the first opening. The orthographic projection of the side of the field plate facing the first ohmic electrode onto the substrate is located within the orthographic projection of the shielding structure onto the substrate.

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