Planar silicon carbide power device

Abstract

The application relates to the technical field of semiconductor devices, and discloses a planar silicon carbide power device, which comprises a first metal layer, a substrate, an epitaxial layer, an ion implantation layer, an oxide layer, a polysilicon layer, an interlayer dielectric layer and a second metal layer which are stacked from bottom to top, the oxide layer comprises a first oxide region and a second oxide region, the first oxide region is in contact with the lower surface of the polysilicon layer; the ion implantation layer is provided with a first ion implantation region which comprises a P-type well region and an N+ type ion region arranged from bottom to top; the P-type well region comprises a first well region, the upper surface of the first well region is in contact with the oxide layer, and part of the first well region is in contact with the first oxide region to form an electron channel, and part of the first well region is in contact with the second oxide region to form a channel resistance-free region. When the device is short-circuited, the channel resistance-free region can prevent the saturation current of the device from increasing, avoid the short-circuit current from breaking through the device, and improve the short-circuit capability.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a planar silicon carbide power device. Background Technology

[0002] Wide-bandgap (third-generation) semiconductor materials, primarily silicon carbide (SiC) and gallium nitride (GaN), possess inherent superior properties such as wide bandgap, high thermal conductivity, high breakdown electric field, high radiation resistance, and high electron saturation velocity. These properties allow them to exhibit performance advantages unmatched by the first two generations of semiconductor materials in numerous applications. For example, power devices based on SiC and GaN can operate stably in extreme and harsh environments such as aerospace, military equipment, and the nuclear industry. Compared to traditional silicon-based field-effect transistors (FETs), SiC FETs are easier to achieve with high voltage, low loss, and high power density, thus gradually becoming the mainstream in the market.

[0003] However, due to the poor reliability of the gate oxide of silicon carbide field-effect transistors (SFETs), coupled with the thermal failure caused by excessive current density leading to overheating, SFETs have low short-circuit withstand capability and are easily damaged.

[0004] Conventional planar SiC MOSFET devices have high current density, large saturation current, deteriorated linearity in the saturation region, and poor short-circuit capability. Due to the short channel length of planar SiC MOSFET devices, the drain barrier reduction effect is significant as the drain voltage increases, and the saturation current continues to increase with the drain voltage, thus reducing the short-circuit capability.

[0005] In existing technologies, methods to reduce saturation current and improve short-circuit capability mainly involve reducing the width of the original JFET structure based on the conventional planar SiC MOSFET structure, introducing a new JFET structure by creating a buried layer in the epitaxial layer, or using a split gate structure that only uses half of the cell channel. Currently, the pitch of planar SiC MOSFETs can be made smaller and smaller in terms of process technology, and the JFET width can be reduced to below 1µm. Further reducing the JFET width beyond this is extremely difficult in terms of process technology. If a new JFET structure is formed in the epitaxial layer, multiple epitaxial processes are required. On the other hand, the split gate structure, which only uses half of the cell channel, will increase the on-state voltage drop. Therefore, the above technologies all have problems to varying degrees, either introducing complex processes or sacrificing other performance aspects for short-circuit capability. Summary of the Invention

[0006] This application provides a planar silicon carbide power device, which aims to prevent the increase of the device's saturation current in the channelless resistance region when the device is short-circuited, thereby avoiding short-circuit current breakdown of the device and improving the device's short-circuit capability.

[0007] In a first aspect, embodiments of this application provide a planar silicon carbide power device, comprising: a first metal layer, a substrate, an epitaxial layer, an ion implantation layer, an oxide layer, a polysilicon layer, an interlayer dielectric layer, and a second metal layer stacked from bottom to top; A polycrystalline silicon layer is disposed on the upper surface of the oxide layer; The oxide layer includes a first oxide region and a second oxide region, wherein the first oxide region is in contact with the lower surface of the polycrystalline silicon layer; The ion implantation layer is provided with a first ion implantation region, which includes a P-type well region and an N+ type ion region arranged from bottom to top; the P-type well region includes a first well region whose upper surface is in contact with the oxide layer; a part of the first well region is in contact with the first oxide region to form an electron channel, and a part of the first well region is in contact with the second oxide region to form a channelless resistance region.

[0008] In some embodiments, the N+ type ion region is embedded in the P type trap region, and the N+ type ion region is adjacent to the oxide layer and the second metal layer.

[0009] In some embodiments, the first ion implantation region further includes: a first P+ type ion implantation region; the first P+ type ion implantation region is embedded in the N+ type ion region.

[0010] In some embodiments, the first P+ type ion implantation region borders the oxide layer and the second metal layer.

[0011] In some embodiments, the first ion implantation region further includes a second P+ type ion implantation region; the second P+ type ion implantation region is adjacent to the N+ type ion region on both sides.

[0012] In some embodiments, the upper and lower surfaces of the second P+ type ion implantation region are adjacent to the second metal layer and the P-type well region, respectively.

[0013] In some embodiments, the ion implantation layer further includes a current spreading layer (104) adjacent to the epitaxial layer; the current spreading layer is an N-type ion implantation layer.

[0014] In some embodiments, the planar silicon carbide power device includes two first ion implantation regions spaced apart from each other.

[0015] In some embodiments, the interlayer dielectric layer is in contact with the upper surface of the oxide layer, and the left and right sides and the upper surface of the interlayer dielectric layer are in contact with the second metal layer.

[0016] In some implementations, the planar silicon carbide power device is a metal-oxide-semiconductor transistor.

[0017] In summary, this application provides a planar silicon carbide power device, comprising: a first metal layer, a substrate, an epitaxial layer, an ion implantation layer, an oxide layer, a polysilicon layer, an interlayer dielectric layer, and a second metal layer stacked from bottom to top; the polysilicon layer is disposed on the upper surface of the oxide layer; the oxide layer includes a first oxide region and a second oxide region, wherein the first oxide region is adjacent to the lower surface of the polysilicon layer; the ion implantation layer is provided with a first ion implantation region, which includes a P-type well region and an N+ type ion region disposed from bottom to top; the P-type well region includes a first well region whose upper surface is adjacent to the oxide layer; a portion of the first well region is adjacent to the first oxide region to form an electron channel, and a portion of the first well region is adjacent to the second oxide region to form a channelless resistance region. When the device is turned on, an electron channel is formed in the region where the first well region and the first oxide region meet, while a channelless resistance region is formed in the region where the first well region and the second oxide region meet. Driven by the source-drain voltage difference of the device, electrons can pass through the channelless resistance region, and the on-resistance of the device will not increase. When the device is short-circuited, the channelless resistance region can prevent the device saturation current from increasing, avoid the short-circuit current from breaking down the device, and thus improve the short-circuit capability of the device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a planar silicon carbide power device provided in an embodiment of this application; Figure 2 Another structural schematic diagram of a planar silicon carbide power device provided in an embodiment of this application; Figure 3 This is a partial enlarged schematic diagram of a planar silicon carbide power device provided in an embodiment of this application; Figure 4 A schematic diagram comparing the simulation curves of IdVd of a planar silicon carbide power device and a conventional structure provided in an embodiment of this application; Figure 5 A schematic diagram comparing the short-circuit current curves of a planar silicon carbide power device provided in an embodiment of this application with those of a conventional structure; Figure 6 This is a schematic diagram comparing the lattice temperature change curves of a planar silicon carbide power device provided in an embodiment of this application with those of a conventional structure.

[0020] Figure label: 100. Planar silicon carbide power device; 10. First metal layer; 20. Substrate; 30. Epitaxial layer; 40. Ion implantation layer; 41. First ion implantation region; 411. P-type well region; 412. First well region; 412a. First target region; 412b. Second target region; 413. N+ type ion region; 414. Second well region; 415. First P+ type ion implantation region; 416. Second P+ type ion implantation region; 42. Current spreading layer; 50. Oxide layer; 51. First oxide region; 52. Second oxide region; 60. Polysilicon layer; 70. Interlayer dielectric layer; 80. Second metal layer. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be decomposed, combined, or partially merged; therefore, the actual execution order may change according to the actual situation.

[0022] Wide-bandgap (third-generation) semiconductor materials, primarily silicon carbide (SiC) and gallium nitride (GaN), possess inherent superior properties such as wide bandgap, high thermal conductivity, high breakdown electric field, high radiation resistance, and high electron saturation velocity. These properties allow them to exhibit performance advantages unmatched by the first two generations of semiconductor materials in numerous applications. For example, power devices based on SiC and GaN can operate stably in extreme and harsh environments such as aerospace, military equipment, and the nuclear industry. Compared to traditional silicon-based field-effect transistors (FETs), SiC FETs are easier to achieve with high voltage, low loss, and high power density, thus gradually becoming the mainstream in the market.

[0023] However, due to the poor reliability of the gate oxide of silicon carbide field-effect transistors (SFETs), coupled with the thermal failure caused by excessive current density leading to overheating, SFETs have low short-circuit withstand capability and are easily damaged.

[0024] Conventional planar SiC MOSFET devices have high current density, large saturation current, deteriorated linearity in the saturation region, and poor short-circuit capability. Due to the short channel length of planar SiC MOSFET devices, the drain barrier reduction effect is significant as the drain voltage increases, and the saturation current continues to increase with the drain voltage, thus reducing the short-circuit capability.

[0025] In existing technologies, methods to reduce saturation current and improve short-circuit capability mainly involve reducing the width of the original JFET structure based on the conventional planar SiC MOSFET structure, introducing a new JFET structure by creating a buried layer in the epitaxial layer, or using a split gate structure that only uses half of the cell channel. Currently, the pitch of planar SiC MOSFETs can be made smaller and smaller in terms of process technology, and the JFET width can be reduced to below 1µm. Further reducing the JFET width beyond this is extremely difficult in terms of process technology. If a new JFET structure is formed in the epitaxial layer, multiple epitaxial processes are required. On the other hand, the split gate structure, which only uses half of the cell channel, will increase the on-state voltage drop. Therefore, the above technologies all have problems to varying degrees, either introducing complex processes or sacrificing other performance aspects for short-circuit capability.

[0026] To address the aforementioned problems, this application provides a planar silicon carbide power device 100. The technical solution of this application will be described below with reference to the accompanying drawings.

[0027] like Figures 1 to 4 As shown, this application provides a planar silicon carbide power device 100, which includes a first metal layer 10, a substrate 20, an epitaxial layer 30, an ion implantation layer 40, an oxide layer 50, a polysilicon layer 60, an interlayer dielectric layer 70, and a second metal layer 80 stacked from bottom to top. The following describes each layer in the planar silicon carbide power device 100 in detail.

[0028] Specifically, a polysilicon layer 60 is disposed on the upper surface of the oxide layer 50. The oxide layer 50 includes a first oxide region 51 and a second oxide region 52, with the first oxide region 51 adjoining the lower surface of the polysilicon layer 60. By way of example and not limitation, the second oxide region 52 does not adjoin the lower surface of the polysilicon layer 60. As one embodiment, the oxide layer 50 is located in the planar silicon carbide power device 100 in a first direction ( Figure 1 The central region (in the left-right direction), the first direction and the thickness direction of the planar silicon carbide power device 100 ( Figure 1 If the direction (up and down) is perpendicular, then the first oxide region 51 is located near the center of the oxide layer 50, and the second oxide region 52 is located on the side of the oxide layer 50 away from the center.

[0029] Specifically, the ion implantation layer 40 is provided with a first ion implantation region 41, which includes a P-type well region 411 and an N+ type ion region 413 (i.e., the active region) arranged from bottom to top. The P-type well region 411 includes at least a first well region 412, and the upper surface of the first well region 412 is in contact with the oxide layer 50. By way of example and not limitation, the P-type well region 411 also includes a second well region 414, in which the first well region 412 is located on the side of the oxide layer 50 closer to the central region, and the second well region 414 is located on the side of the oxide layer 50 away from the central region. The second well region 414 may be directly in contact with the second metal layer 80, or it may not be in contact with the second metal layer 80, for example, separated by a second P+ type ion implantation region. The second P+ type ion implantation region will be further described in detail below.

[0030] In this embodiment, a portion of the upper surface of the first well region 412 borders the first oxide region 51 to form an electron channel, and a portion of the upper surface of the first well region 412 borders the second oxide region 52 to form a channelless resistance region. As one embodiment, the first well region 412 includes a first target region 412a and a second target region 412b that do not overlap. The first target region 412a borders the first oxide region 51 to form an electron channel, and the second target region 412b borders the second oxide region 52 to form a channelless resistance region.

[0031] Specifically, the planar silicon carbide power device 100 provided in this application embodiment partially covers the oxide layer 50 with a polysilicon layer 60 to design and form a first oxide region 51 (the region covered by polysilicon) and a second oxide region 52 on the oxide layer 50. The first oxide region 51 partially covers the first well region 412 of the P-type well region 411. Then, a first target region 412a with the upper surface adjoining the first oxide region 51 and a second target region 412b with the upper surface adjoining the second oxide region 52 are designed and formed on the first well region 412.

[0032] When the device is turned on, as the gate voltage Vg increases, the electric field applied to the polysilicon layer passes through the oxide layer and acts on the first well region 412. The region where the first well region 412 and the first oxide region 51 (the first target region 412a) form an electron channel, while the region where the first well region 412 and the second oxide region 52 (the second target region 412b) form a channelless resistance region. Driven by the source and drain voltage difference of the device, electrons can pass through the channelless resistance region, and the on-resistance of the device will not increase. When the device is short-circuited, the channelless resistance region can prevent the device saturation current from increasing. Thus, the saturation current can be reduced and the short-circuit capability can be improved without increasing the on-resistance.

[0033] On the other hand, since the planar silicon carbide power device 100 provided in this application embodiment only partially covers the first well region 412 of the P-type well region 411 by having the polysilicon layer 60 partially cover it, the process of processing the planar silicon carbide power device 100 can be compatible with conventional processes without adding new process flows. It is only necessary to adjust the coverage of the oxide layer 50 during the process of setting the oxide layer 50, thus reducing the design cost and processing cost of the planar silicon carbide power device 100.

[0034] In some embodiments, the first metal layer 10 is a drain metal layer, the second metal layer 80 is a source metal layer, the oxide layer is a gate oxide layer, and the polysilicon layer 60 is a gate.

[0035] In some implementations, such as Figure 1 The N+ type ion region 413 is embedded in the P type well region 411, and the N+ type ion region is adjacent to the oxide layer 50 and the second metal layer 80.

[0036] It should be noted that the P-type well region 411 refers to the P-type region formed on the surface of the epitaxial layer 30 away from the substrate 20 in the planar silicon carbide power device 100, i.e., the P-type ion implantation region. The N+ type ion region 413 is formed by doping the P-type well region 411 with a high concentration of N+ type ions. Therefore, its doping concentration is higher than that of a typical N+ type ion region, for example, by doping with pentavalent elements (such as phosphorus or arsenic) to form a high concentration of free electrons.

[0037] Optionally, such as Figure 1 A portion of the N+ type ion region near the center of the planar silicon carbide power device 100 is adjacent to the oxide layer 50, while a portion of the N+ type ion region away from the center of the planar silicon carbide power device 100 is adjacent to the second metal layer 80. Specifically, the upper surface of the N+ type ion region is adjacent to the oxide layer 50 and the second metal layer 80, while its left and right sides and bottom side are adjacent to the P-type well region 411.

[0038] In some implementations, such as Figure 2 The first ion implantation region 41 further includes: a first P+ type ion implantation region 415; the first P+ type ion implantation region 415 is embedded in the N+ type ion region 413.

[0039] Specifically, the first P+ type ion implantation region 415 is a P+ type region formed by P+ type ion implantation on the N+ type ion region, and the implantation dose (doping concentration) of the first P+ type ion implantation region 415 is greater than that of the N+ type ion region 413.

[0040] It should be noted that, since the N+ type ion region is embedded in the P-type well region 411 and the first P+ type ion implantation region is embedded in the N+ type ion region, the first P+ type ion implantation region and the P-type well region 411 are separated by the N+ type ion region, and a JFET structure is formed between the first P+ type ion implantation region and the P-type well region 411. Specifically, the first P+ type ion implantation region and the bottom P-type well region 411 form a JFET structure, and the first P+ type ion implantation region and the right P-type well region 411 form a JFET structure. These two JFET structures can reduce the saturation current of the planar silicon carbide power device 100, thereby improving the short-circuit capability of the device.

[0041] In some embodiments, the first P+ type ion implantation region 415 is adjacent to the oxide layer 50 and the second metal layer 80.

[0042] Specifically, a portion of the first P+ type ion implantation region near the center of the planar silicon carbide power device 100 is adjacent to the oxide layer 50, while a portion of the first P+ type ion implantation region away from the center of the planar silicon carbide power device 100 is adjacent to the second metal layer 80.

[0043] In some embodiments, the first ion implantation region 41 further includes a second P+ type ion implantation region 416; the second P+ type ion implantation region 416 is adjacent to the N+ type ion region 413 on both sides.

[0044] The implantation dose (doping concentration) in the second P+ type ion implantation region 416 is greater than that in the N+ type ion region 413.

[0045] Specifically, the second P+ type ion implantation region 416 is located on the side of the N+ type ion region 413 away from the central region of the planar silicon carbide power device 100, for example, Figure 2 The left half of the middle and Figure 3 In the middle, the second P+ type ion implantation region 416 is located to the left of the N+ type ion region 413, while... Figure 2 In the right half of the image, the second P+ type ion implantation region 416 is located to the right of the N+ type ion region 413.

[0046] As an example and not a limitation, the upper and lower surfaces of the second P+ type ion implantation region 416 are adjacent to the second metal layer 80 and the P-type well region 411, respectively.

[0047] It should be noted that since the first P+ type ion implantation region 415 is embedded in the N+ type ion region 413, the second P+ type ion implantation region 416 is also separated from the first P+ type ion implantation region 415 by the N+ type ion region, and a JFET structure is also formed between the first P+ type ion implantation region 415 and the second P+ type ion implantation region 416.

[0048] Specifically, such as Figure 2 The JFET structure formed between the first P+ type ion implantation region 415 and the second P+ type ion implantation region 416, the JFET structure formed between the first P+ type ion implantation region 415 and the bottom P-type well region 411, and the JFET structure formed between the first P+ type ion implantation region 415 and the P-type well region 411 on the side away from the second P+ type ion implantation region, together form an active region JFET structure, which can further reduce the saturation current of the planar silicon carbide power device 100, thereby improving the short-circuit capability of the device.

[0049] In this invention, the newly added JFET structure is designed in the active region and consists of a first P+ type ion implantation region 415, a left second P+ type ion implantation region 416, a bottom P-type well region 411, and a right P-type well region 411 (total). Figure 2 (Taking the first ion implantation region 41 on the left side as an example), the first P+ type ion implantation region 415 and the second P+ type ion implantation region 416 are formed from the same layout, without the introduction of additional layout, which is compatible with conventional planar SiC MOSFET processes, resulting in low production costs and wide applicability. The N+ type ion region 413 (active region) between the active region JFET structures is highly N+ type doped, so electrons can pass normally under low drain voltage Vd, and the on-resistance will not increase. However, under high drain voltage Vd, the active region JFET structure reduces the electron channel width, which can prevent the device saturation current from continuing to increase. Therefore, the design of the active region JFET structure can reduce the device saturation current and improve short-circuit capability.

[0050] In some embodiments, the ion implantation layer 40 further includes a current spreading layer 42 (CSL layer) adjoining the epitaxial layer 30; the current spreading layer 42 is an N-type ion implantation layer 40.

[0051] Specifically, the current spreading layer 42 is formed on the side of the epitaxial layer 30 away from the substrate 20, while the P-type well region 411 is formed on the surface of the current spreading layer 42 away from the epitaxial layer 30 by implanting P-type doped ions. In some embodiments, such as Figure 2 The planar silicon carbide power device 100 includes two first ion implantation regions 41 spaced apart from each other. A portion of the current spreading layer 42 is located between the first ion implantation regions 41 and the epitaxial layer 30, and another portion is located between the two first ion implantation regions 41. Figure 2 The inverted T-shape shown.

[0052] When current flows out of the JFET region, the current spreading layer (CSL layer) allows the current to spread rapidly throughout the entire drift region, thereby reducing the device's on-resistance. In practical manufacturing processes, the current spreading layer can be implemented using high-energy ion implantation. The presence of the CSL layer not only allows the current to spread rapidly after leaving the JFET region, but also increases the doping concentration in the JFET region, mitigating the JFET region effect to some extent and thus reducing the JFET region resistance.

[0053] In some embodiments, the planar silicon carbide power device 100 includes two first ion implantation regions 41 spaced apart from each other. It should be noted that the specific arrangement of the two first ion implantation regions 41, such as the arrangement of P-type well region 411, N+ type ion region, etc., can be referred to the foregoing description and will not be repeated here.

[0054] As an example and not a limitation, part of the current spreading layer 42 is located between the first ion implantation region 41 and the epitaxial layer 30, and another part is located between the two first ion implantation regions 41.

[0055] By way of example and not limitation, the planar silicon carbide power device 100 provided by this utility model is an axisymmetric device, therefore, as Figure 2 As shown, two first ion implantation regions 41 are symmetrically arranged on the left and right sides of the planar silicon carbide power device 100.

[0056] The following is an example of one configuration of the interlayer dielectric layer 70, which does not constitute a specific limitation on the structural shape of the interlayer dielectric layer 70: In some embodiments, the interlayer dielectric layer 70 is in contact with the upper surface of the oxide layer 50, and the left and right sides and the upper surface of the interlayer dielectric layer 70 are in contact with the second metal layer 80. The interlayer dielectric layer 70 and the oxide layer 50 together encapsulate the polysilicon layer 60, and this configuration separates the polysilicon layer 60 from the second metal layer 80.

[0057] In some implementations, the planar silicon carbide power device 100 is a metal-oxide-semiconductor transistor, also known as a MOSFET.

[0058] Please see Figure 4L1 is the simulated Id-Vd curve (simulated curve between drain current and drain voltage) of a planar silicon carbide power device 100 (hereinafter referred to as "this device") provided in an embodiment of the present invention. L2 is the simulated Id-Vd curve L2 of a conventional power device structure in related technologies. Comparing the simulated curves L1 and L2, it can be seen that when the drain voltage Vd < 10V, i.e., in the linear region, the two curves almost overlap, indicating that the on-resistance of this device and the conventional structure is almost equal under low voltage conditions. When the drain voltage Vd > 50V, the drain current Id of this device is stable at around 170A, while the current Id of the conventional structure gradually increases with the increase of the drain voltage Vd. Compared with the current at Vd = 400V, the saturation current of this device decreases significantly.

[0059] Please see Figure 5 L3 is the short-circuit current curve of this device, and L4 is the short-circuit current curve of the conventional structure. The simulation conditions are short-circuit pulse time tw=5us, vdd=800V, where tw is the short-circuit duration and vdd is the bus voltage. Figure 5 The graph shows the change of current Id with time Time when the device is short-circuited. The horizontal axis represents time and the vertical axis represents current. Comparing the short-circuit current curves L3 and L4, it can be seen that the saturation current of this device is much smaller than that of the conventional structure when short-circuited. Under the simulation condition of tw=5us, when the device is turned off, the current of the conventional structure first drops briefly and then rises continuously, resulting in irreversible thermal failure. In contrast, the current Id of this device drops rapidly to 0A after being turned off, and the device can still work normally.

[0060] Please see Figure 6 L5 shows the change in lattice temperature of this device over time when short-circuited, and L6 shows the change in lattice temperature of a conventional structure device over time when short-circuited. The figures show that after the device is turned off, the lattice temperature of the conventional structure initially drops rapidly, then continues to rise due to the large tail current, until thermal failure occurs. In contrast, the lattice temperature of this device also drops rapidly after turn-off, then decreases slowly, without showing a trend towards thermal failure. The simulation results demonstrate that, under the same experimental conditions, this device has a smaller saturation current, and the current Id can still drop to 0A after turn-off, allowing for normal operation. Furthermore, the lattice temperature decreases slowly without causing device failure, indicating that this device has better short-circuit capability.

[0061] In summary, this application provides a planar silicon carbide power device 100, comprising: a first metal layer 10, a substrate 20, an epitaxial layer 30, an ion implantation layer 40, an oxide layer 50, a polysilicon layer 60, an interlayer dielectric layer 70, and a second metal layer 80 stacked from bottom to top; the polysilicon layer 60 is disposed on the upper surface of the oxide layer 50; the oxide layer 50 includes a first oxide region 51 and a second oxide region 52, wherein the first oxide region 51 is adjacent to the lower surface of the polysilicon layer 60; the ion implantation layer 40 is provided with a first ion implantation region 41, which includes a P-type well region 411 and an N+ type ion region disposed from bottom to top; the P-type well region 411 includes a first well region 412 whose upper surface is adjacent to the oxide layer 50; a portion of the first well region 412 is adjacent to the first oxide region 51 to form an electron channel, and a portion of the first well region 412 is adjacent to the second oxide region 52 to form a channelless resistance region. When the device is turned on, an electron channel is formed in the region where the first well region 412 and the first oxide region 51 meet, while a channelless resistance region is formed in the region where the first well region 412 and the second oxide region 52 meet. Driven by the source-drain voltage difference of the device, electrons can pass through the channelless resistance region, and the on-resistance of the device will not increase. When the device is short-circuited, the channelless resistance region can prevent the device saturation current from increasing, avoid the short-circuit current from breaking down the device, and thus improve the short-circuit capability of the device.

[0062] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application. These modifications or substitutions should all be covered within the scope of protection of this application, and the scope of protection of this application should be determined by the scope of the claims.

[0063] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate medium; or a connection within two elements. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances. As used in this specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms. It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system.

Claims

1. A planar silicon carbide power device, characterized in that, include: The first metal layer, substrate, epitaxial layer, ion implantation layer, oxide layer, polysilicon layer, interlayer dielectric layer and second metal layer are stacked from bottom to top; The polycrystalline silicon layer is disposed on the upper surface of the oxide layer; The oxide layer includes a first oxide region and a second oxide region, wherein the first oxide region is in contact with the lower surface of the polycrystalline silicon layer. The ion implantation layer is provided with a first ion implantation region, which includes a P-type well region and an N+ type ion region arranged from bottom to top; the P-type well region includes a first well region whose upper surface is in contact with the oxide layer; a portion of the first well region is in contact with the first oxide region to form an electron channel, and a portion of the first well region is in contact with the second oxide region to form a channelless resistance region.

2. The planar silicon carbide power device as described in claim 1, characterized in that, The N+ type ion region is embedded in the P type well region, and the N+ type ion region is adjacent to the oxide layer and the second metal layer.

3. The planar silicon carbide power device as described in claim 2, characterized in that, The first ion implantation region further includes: a first P+ type ion implantation region; the first P+ type ion implantation region is embedded in the N+ type ion region.

4. The planar silicon carbide power device as described in claim 3, characterized in that, The first P+ type ion implantation region is adjacent to the oxide layer and the second metal layer.

5. The planar silicon carbide power device as described in claim 4, characterized in that, The first ion implantation region further includes a second P+ type ion implantation region; the second P+ type ion implantation region is adjacent to the N+ type ion region on both sides.

6. The planar silicon carbide power device as described in claim 5, characterized in that, The upper and lower surfaces of the second P+ type ion implantation region are respectively in contact with the second metal layer and the P-type well region.

7. The planar silicon carbide power device according to any one of claims 1-6, characterized in that, The ion implantation layer further includes a current spreading layer bordering the epitaxial layer; the current spreading layer is an N-type ion implantation layer.

8. The planar silicon carbide power device as described in claim 7, characterized in that, The planar silicon carbide power device includes two first ion implantation regions spaced apart from each other.

9. The planar silicon carbide power device as described in claim 8, characterized in that, The interlayer dielectric layer is in contact with the upper surface of the oxide layer, and the left and right sides and the upper surface of the interlayer dielectric layer are in contact with the second metal layer.

10. The planar silicon carbide power device as described in claim 9, characterized in that, The planar silicon carbide power device is a metal oxide semiconductor transistor.

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