semiconductor element

Abstract

A semiconductor element is provided. The semiconductor element includes a semiconductor substrate composed of a first fin structure and a second fin structure; a first metal gate section over the semiconductor substrate and the first fin structure; a second metal gate section over the semiconductor substrate and the second fin structure, wherein the first metal gate section and the second metal gate section are collinear and separated by a gap; and an insulating structure in the gap and insulating the first metal gate section and the second metal gate section, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall defining a thickness therebetween; wherein the first fin structure has a first sidewall and a second sidewall; wherein a pitch dimension is defined from the first sidewall to the second sidewall; and wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic devices that can simultaneously support a multitude of increasingly complex and sophisticated functions is constantly growing. Therefore, manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) is a persistent trend in the semiconductor industry. To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., minimizing feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor integrated circuits and devices require advancements similar to those in semiconductor manufacturing processes and technologies.

[0003] The purpose of introducing multi-gate devices is to improve gate control, reduce off-state current, and reduce short-channel effects (SCE) by increasing gate channel coupling. One such multi-gate device is the FinFET (Fin Field-Effect Transistor). FinFETs are named for their fin-like structure, which extends from the substrate forming the FET channel. Another type of multi-gate device is the Gate All-Around (GAA) transistor, introduced in part to address the performance challenges associated with FinFETs. GAA devices are named for their gate structure, which extends entirely around the channel, providing better electrostatic control than FinFETs. Both FinFETs and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows them to scale significantly while maintaining gate control and mitigating SCEs. Utility Model Content

[0004] Some embodiments described herein provide a semiconductor device. The semiconductor device includes: a semiconductor substrate comprising a first fin structure and a second fin structure; a first metal gate segment located above the semiconductor substrate and the first fin structure; a second metal gate segment located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart by a gap; and an insulating structure located within the gap and insulating the first metal gate segment and the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first side wall and a second side wall; wherein the pitch dimension is defined from the first side wall to the second side wall; and wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension.

[0005] Some embodiments described herein provide a semiconductor device. The semiconductor device includes: a semiconductor substrate comprising a first fin structure and a second fin structure; a first metal gate segment located above the semiconductor substrate and the first fin structure; a second metal gate segment located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart by a gap; and an insulating structure located within the gap and insulating the first metal gate segment and the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first side wall and a second side wall; wherein a pitch dimension is defined from the first side wall to the second side wall; wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension; and wherein each of the metal gate segments includes a metal filler and a dielectric pad, and wherein the metal filler is in direct contact with the first end wall and the second end wall of the insulating structure.

[0006] Some embodiments described herein provide a semiconductor device. The semiconductor device includes: a semiconductor substrate comprising a first fin structure and a second fin structure; a first metal gate segment located above the semiconductor substrate and the first fin structure; a second metal gate segment located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart by a gap; and an insulating structure located within the gap and insulating the first metal gate segment and the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first side wall and a second side wall; wherein a pitch dimension is defined from the first side wall to the second side wall; wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension; and wherein each of the metal gate segments includes a metal filler and a dielectric pad, and wherein the dielectric pad is located between the first end wall and the second end wall of the insulating structure and the insulating structure. Attached Figure Description

[0007] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a plan view of the layout of multi-gate elements according to some embodiments;

[0009] Figure 2 This is a flowchart of a method according to some embodiments;

[0010] Figures 3A-10 These are cross-sectional views of a multi-gate device at various manufacturing stages according to some embodiments;

[0011] Figure 11 This is a plan view of the layout of multi-gate elements according to some embodiments;

[0012] Figure 12 This is a flowchart of a method according to some embodiments;

[0013] Figures 13A-19 These are cross-sectional views of a multi-gate device at various manufacturing stages according to some embodiments;

[0014] Figure 20 This is a flowchart of a method according to some embodiments;

[0015] Figures 21A-33B It is based on Figure 20 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0016] Figure 34 This is a flowchart of a method according to some embodiments;

[0017] Figures 35-41 It is based on Figure 34 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0018] Figures 42-45 Based on some embodiments Figure 20 and / or Figure 34 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0019] Figures 46-49 Based on some embodiments Figure 20 and / or Figure 34 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0020] Figures 50-52 It is based on Figure 20 and / or Figure 34 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0021] Figures 53-55 It is based on Figure 20 and / or Figure 34 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0022] Figures 56-58 It is based on Figure 20 and / or Figure 34 A cross-sectional view of a multi-gate device in a continuous manufacturing stage using the method;

[0023] Figure 59 It is based on Figure 20 and / or Figure 34 A cross-sectional view of a multi-gate device formed by the method described above.

[0024] [Symbol Explanation]

[0025] 10: Substrate (material)

[0026] 11: Unit

[0027] 12,12': Fin (structure)

[0028] 13: Substrate portion

[0029] 14: Shallow Trench Isolation Feature (STI Feature)

[0030] 15: Nanosheet Channel Layer (Nanosheet Layer)

[0031] 16: Intermediary layer

[0032] 17: Sacrificial Layer (Dummy Gate Structure) (Sacrificial Gate Structure)

[0033] 18: Masking layer

[0034] 19: Padding

[0035] 20: Active Zone

[0036] 21: Hard Mask

[0037] 30: Gate line (metal gate) (common metal line)

[0038] 31: Gate dielectric layer (dielectric pad)

[0039] 32: Filler material

[0040] 40: Insulation structure

[0041] 41,42:End wall

[0042] 50: Trench

[0043] 60: Insulation characteristics

[0044] 70: Gate cavity (void)

[0045] 90: Source / Drain Characteristics

[0046] 100: Components

[0047] 151, 152: Sidewall

[0048] 200: Method

[0049] 300: Protective layer (protective gasket)

[0050] 301: Section

[0051] 302: Section

[0052] 303: Gap

[0053] 312: Masking layer

[0054] 314: Masking layer

[0055] 316: Spacers

[0056] 318: Dielectric layer

[0057] 320: Void

[0058] 322: Gap

[0059] 328: Protective lining material

[0060] 330: Pad

[0061] 331: Inner layer

[0062] 332: Outer layer

[0063] 333: Surface

[0064] 336: Terminal Area

[0065] 338: Central Area

[0066] 340: Internal spacer

[0067] 345: Interface

[0068] 346: Terminal

[0069] 348: Vertex

[0070] 350: Source / Drain Characteristics

[0071] 360: Interlayer Dielectric (ILD)

[0072] 370: Gate cavity

[0073] 380: Metal gate

[0074] 381: Dielectric Pad (Gate Dielectric Layer) (High-K Gate Dielectric Layer)

[0075] 382: Filler material

[0076] 390: Internal diffusion region

[0077] 398: Central Area

[0078] 399: Corner

[0079] 400: Method

[0080] 500: Nanosheet Channel Layer

[0081] 501: Top nanosheet channel layer

[0082] 502: Intermediate Nanosheet Channel Layer

[0083] 503: Bottom Nanosheet Channel Layer

[0084] 511: Left edge

[0085] 512: Center

[0086] 513: Right edge

[0087] 521: Upper surface

[0088] 522: Lower surface

[0089] 531, 532, 533: Thickness

[0090] 540: Length

[0091] 812,840,914,915,921,940: Plane

[0092] D4, D5, D6: Distance

[0093] Da: Pitch (horizontal distance)

[0094] Db, Dc, Dd: Critical dimensions (horizontal width)

[0095] De: Vertical depth

[0096] Df: Horizontal spacing

[0097] H D H L :thickness

[0098] L1, L2: Length

[0099] La: Pitch (horizontal distance)

[0100] Lb, Lc, Ld1, Ld2: Critical dimensions (horizontal width)

[0101] Le: Vertical Depth

[0102] S202, S204, S206, S208, S210, S212, S214: Squares

[0103] S402, S406, S408, S410, S412, S414, S416, S418, S419, S420, S422, S424, S426, S427, S428, S430, S450, S460: Square

[0104] S404: Operation

[0105] X, Y: Direction Detailed Implementation

[0106] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0107] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0108] In some embodiments herein, a “material layer” is one comprising at least 50 wt.% of an identified material, such as at least 60 wt.% of an identified material, or at least 75 wt.% of an identified material, or at least 90 wt.% of an identified material; a layer as “material” comprises at least 50 wt.% of an identified material, such as at least 60 wt.% of an identified material, or at least 75 wt.% of an identified material, or at least 90 wt.% of an identified material. For example, in some embodiments, each of the titanium nitride layers is at least 50 wt.% of a layer, at least 60 wt.% of a layer, at least 75 wt.% of a layer, titanium nitride, or at least 90 wt.% of titanium nitride.

[0109] For the sake of brevity, conventional techniques associated with the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive processes or technologies with additional functionalities not described in detail herein. Specifically, various processes in semiconductor device manufacture are well-known; therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading this disclosure that the structures disclosed herein can be used with a variety of technologies and can be incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the illustrations may represent multiple components.

[0110] This document presents embodiments of semiconductor devices and methods for manufacturing such devices. The methods described herein can be easily integrated into current process flows.

[0111] In advanced technology nodes, narrower STI feature widths and more nanosheet channels are required to increase transistor density. Channel lengths may approach the lithographic limit in advanced nodes (approximately 10 nm). Parasitic capacitance caused by high-k dielectrics can depend on the STI feature width and the number of nanosheets (i.e., the height of the nanosheet stack). At the scaling limit, as the STI width decreases, the pitch size shrinks, and the nanosheet stack height increases, resulting in larger sidewall parasitic capacitance and lower STI parasitic capacitance. Therefore, embodiments reduce the impact of high-k dielectrics on the sidewalls to reduce sidewall parasitic capacitance.

[0112] The embodiments provided herein are for reducing or minimizing metal boundary effects at the interface between the CPODE or CMODE insulating structure and the metal gate.

[0113] For example, high-k dielectric pads formed on the end walls of an insulating structure can cause metallic boundary effects. Due to scaling, the high-k dielectric on the insulating structure walls can significantly affect the threshold voltage of adjacent transistors.

[0114] Some embodiments described herein eliminate the need for high-k dielectric pads formed on the end walls of the insulating structure.

[0115] Some embodiments described herein reduce metal boundary effects by increasing the distance between the high-k dielectric on the sidewalls of the insulating structure and adjacent transistors.

[0116] Some embodiments described herein provide reduced metal boundary effects without performing a metal dicing process to etch the interface between the insulating features and the metal gate. Such a metal dicing process can lead to damage to adjacent nanosheet channels.

[0117] The embodiments disclosed herein offer advantages over the prior art. Although it should be understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and not all embodiments need to have specific advantages.

[0118] For the purposes of the following discussion, Figure 1 A simplified top-down layout diagram of a semiconductor element 100 (e.g., a multi-gate element 100) is provided. The multi-gate element 100 includes transistors whose gate structures are formed on at least both sides of a channel region. These multi-gate elements may include P-type metal-oxide-semiconductor (MOS) elements or N-type MOS multi-gate elements.

[0119] In various embodiments, the multi-gate element 100 may include a FinFET element, a gate all-around (GAA) element, or other types of multi-gate elements. A GAA element includes any element whose gate structure or a portion thereof is formed on the four sides of the channel region (e.g., around a portion of the channel region). Elements presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Hereinafter, "nanosheet channel" is intended to include nanowire channel and strip channel configurations. Embodiments of element 100 are presented herein, which may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will recognize that this spirit can be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art will recognize other paradigms of semiconductor elements that may benefit from the aspects of this disclosure.

[0120] A multi-gate element 100 is formed over a substrate 10. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. As is known in the art, the substrate 10 may include various doping configurations depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 10 may optionally include an epitaxial layer, which may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancing features.

[0121] Figure 1This is a top view of unit cell 11 (i.e., a portion of semiconductor substrate 10). As shown, parallel active regions 20 are spaced apart from each other and extend along the X direction. Source / drain features 90 are formed in the parallel active regions 20. Furthermore, parallel gate lines 30 are spaced apart from each other and extend along the Y direction perpendicular to the X direction. Example: The gate lines 30 are formed of a conductive material such as metal and form the gate structure of the multi-gate element 100. As shown, a gate dielectric layer 31 surrounds the conductive gate lines 30.

[0122] Further as Figure 1 As shown, a diced region or trench is formed in a gate line 30 and filled with an insulating material to form an insulating structure 40, which can isolate adjacent elements from each other as described below. As used herein, “insulating,” “isolate,” and “dielectric” can be considered synonyms and are used in different contexts only for clarity of description.

[0123] The methods described herein relate to the formation of an insulating structure 40, such as a continuous poly on diffusion edge (CPODE) structure 40 that divides one or more fins into two parts. In some embodiments, a portion of a selected fin structure is removed and replaced with an insulating material.

[0124] For the purposes of this disclosure, "diffusion edge" may be equivalently referred to as active edge, where, for example, an active edge is adjacent to an adjacent active region. Furthermore, the active region includes areas forming transistor structures (e.g., including source, drain, and gate / channel structures). In some embodiments, the active regions may be disposed between insulating regions. The CPODE process can provide an isolation region between adjacent active regions by performing a dry etching process along the active edge (e.g., at the boundary of adjacent active regions), thereby providing an isolation region between adjacent transistors to form a cut region and fill it with a dielectric, such as silicon nitride (SiN).

[0125] Prior to the CPODE process, the active edge may include a GAA dummy structure with gate stacks and multiple channels (e.g., nanosheet channels). Each of the multiple channels may include a chemical oxide layer formed thereon, and a high-k dielectric / metal gate layer may be formed above the chemical oxide layer and between adjacent channels. Furthermore, internal spacers may be disposed between adjacent channels at the lateral ends of the multiple channels. In various embodiments, source / drain epitaxial layers of adjacent active regions are disposed on both sides of the GAA dummy structure (formed at the active edge), such that the adjacent source / drain epitaxial layers contact the internal spacers and the multiple channels of the GAA dummy structure.

[0126] In some embodiments herein, a CPODE-first process method is employed, i.e., prior to the formation of the metal gate.

[0127] Please refer to Figure 2 The document illustrates a method 200 for fabricating a semiconductor device 100 (such as a multi-gate device) using a CPODE process according to various embodiments. Method 200 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, strip-shaped) and sizes. However, it should be understood that aspects of method 200, including the disclosed CPODE process, can be equally applied to other types of multi-gate devices without departing from the scope of this disclosure. In some embodiments, method 200 can be used to fabricate multi-gate device 100, as described above. Figure 1 Therefore, one or more aspects discussed above with reference to the multi-gate element 100 can also be applied to method 200. It should be understood that method 200 includes steps characterized by complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore will only be briefly described here. Additionally, further steps may be performed before, after, and / or during method 200.

[0128] The following is for reference Figures 3A-9C Description method 200, Figures 3A-9C Semiconductor element 100 at various manufacturing stages according to method 200 is shown. Figures 3A-9A Embodiments of semiconductor element 100 are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the X-axis passing through fin 12.

[0129] Figures 3B-9B An embodiment of semiconductor element 100 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the Y-axis passing through gate line 30.

[0130] Figures 3C-9C An embodiment of semiconductor element 100 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the Y-axis passing through gate line 30.

[0131] Figures 3B-9B and Figures 3C-9C The number and size of the fins that can be removed to form an insulating structure vary. Figures 3B-9B and Figures 3C-9C The embodiments may exist at different locations within the same unit 11, or may be considered alternative embodiments that do not exist simultaneously.

[0132] Semiconductor element 100 may include various other devices and features, such as other types of devices like additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but are simplified for better understanding of the concepts disclosed herein. In some embodiments, semiconductor element 100 includes multiple semiconductor elements (e.g., transistors), including PFETs and NFETs, which may be interconnected. Furthermore, it should be noted that the process steps of method 200, including any descriptions given with reference to the accompanying drawings, are merely exemplary and are not intended to limit the scope beyond what is specifically described in the appended claims.

[0133] Method 200 begins with block S202, which provides a partially fabricated multi-gate element 100. Please refer to [reference needed]. Figures 3A-3C In an embodiment of block S202, method 200 forms a structure 12, such as a fin, over a substrate 10. The fins 12 extend in the X direction and are spaced apart from each other in the Y direction perpendicular to the X direction. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 10 may include various doping configurations as known in the art, depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 10 may optionally include an epitaxial layer, which may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancing features.

[0134] Fin 12 may include a nanosheet channel layer, designated 15, interleaved with an interposer layer, designated 16. In some embodiments, nanosheet channel layer 15 may include silicon (Si) and interposer layer 16 may include silicon-germanium (SiGe). However, in some embodiments, nanosheet channel layer 15 may include other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, and alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, interposer layer 16 may include silicon (Si) or another material different from that of nanosheet channel layer 15. For example, nanosheet channel layer 15 may be epitaxially grown using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0135] As shown in the figure, a liner 19 can be formed along the sidewalls of the stack of layers 15 and 16 and the top of the stack of layers 15 and 16. In this embodiment, the liner 19 is silicon oxide.

[0136] In various embodiments, each fin 12 includes a substrate portion 13 formed from the substrate 10. It should be noted that although the fin 12 is shown as comprising three nanosheet channel layers 15, this is for illustrative purposes only and is not intended to limit the scope beyond what is specifically set forth in the claims. It should be understood that any number of nanosheet channel layers 15 can be formed, wherein, for example, the number of nanosheet channel layers 15 depends on the desired number of channel regions of the GAA element (e.g., element 100). In some embodiments, the number of nanosheet channel layers 15 is between three and ten.

[0137] Shallow trench isolation (STI) feature 14 may also be formed within fin 12. In some embodiments, STI feature 14 comprises silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various embodiments, the dielectric layer for forming the STI feature may be deposited by CVD processes, subatmospheric pressure CVD (SACVD) processes, flow CVD processes, ALD processes, PVD processes, and / or other suitable processes.

[0138] As shown in the figure, a hard mask 21 is formed over the STI feature 14. The STI hard mask 21 can be silicon nitride or other suitable materials.

[0139] like Figures 3A-3C As further shown, the partially fabricated multi-gate element 100 also includes a sacrificial layer 17, such as a sacrificial or dummy gate structure 17 extending along the Y direction. The sacrificial gate structures 17 are spaced apart from each other in the X direction and formed over portions of the fins 12 that will become channel regions. The sacrificial gate structures 17 may extend over multiple adjacent fins 12, as shown. The sacrificial gate structures 17 are located directly over and define the channel region of the GAA element to be formed. Each sacrificial gate structure 17 may include a sacrificial gate dielectric and a sacrificial gate electrode above the sacrificial gate dielectric.

[0140] The sacrificial gate structure 17 is formed by first depositing a sacrificial gate dielectric layer over the fin 12. Then, a sacrificial gate electrode layer is deposited over the sacrificial gate dielectric layer and over the fin 12. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nm to about 5 nm. In some embodiments, the sacrificial gate structure 17 is planarized. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited by CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. The sacrificial gate dielectric layer and the sacrificial gate electrode layer may be masked and patterned to form the sacrificial gate structure 17.

[0141] As shown in the figure, a mask layer 18 is formed over the sacrificial gate structure 17. The mask layer 18 may comprise a mask layer such as silicon oxide or a mask layer such as silicon nitride.

[0142] Cross-reference Figure 2 and Figures 4A-4C Method 200 can continue at block S204, initiating the CPODE etching process. Specifically, the mask layer is patterned before performing etching to remove a portion of the sacrificial gate structure 17 located above the selected fin 12'. As a result, trench 50 is formed.

[0143] The etching process at block S204 can be used on pad 19 and STI hard mask 21, so that pad 19 remains above and around the stack of layers 15 and 16, and STI hard mask 21 remains covering STI feature 14.

[0144] Cross-reference Figure 2 and Figures 5A-5C As shown in the figure, method 200 can continue at block S206 to complete the CPODE etching process. Specifically, in block S206, a portion of the selected fin 12' formed by the uncovered pad 19 stacked below layers 15 and 16 is removed. As a result, trench 50 extends into substrate 10.

[0145] The etching process at block S206 can be used on STI hard mask 21, so that STI hard mask 21 retains coverage of STI feature 14.

[0146] As shown in the figure, method 200 includes removing a portion of at least one structure 12' to form a groove 50. The groove 50 extends through the fin 12, i.e., along the Y direction.

[0147] Cross-reference Figure 2 and Figures 6A-6CMethod 200 can continue at block S208, forming a CPODE insulating structure 40 in the trench. The CPODE insulating structure 40 can be formed from a filler material deposited in the trench 50. For example, the filler material can be silicon oxide. Overloaded portions of the filler material can be removed by a planarization process.

[0148] The CPODE insulation structure 40 extends from the first end wall 41 to the second end wall 42 in the Y direction. Therefore, each end wall 41 and end wall 42 extends in the X direction.

[0149] Therefore, method 200 forms an insulating structure 40 in the trench 50, and the insulating structure 40 terminates at the first end wall 41, terminates at the second end wall 42, and extends from the first end wall 41 to the second end wall 42 in the Y direction.

[0150] Cross-reference Figure 2 and Figures 7A-7C Method 200 can continue at block S210, removing the sacrificial gate structure 17 to form the gate cavity 70. As shown, the gate cavity 70 is partially defined (i.e., defined) by end walls 41 and 42 of the CPODE insulating structure 40. The etching performed at block S210 for removing the sacrificial gate structure 17 is applied to the pad 19 and the STI hard mask 21, such that the pad 19 remains above and around the stack of layers 15 and 16, and the STI hard mask 21 remains covering the STI feature 14.

[0151] Cross-reference Figure 2 and Figures 8A-8C Method 200 can continue at block S212, removing the interposer layer 16 and leaving the nanosheet channel layer 15 spaced above the fin 12 to define the nanosheet channel region. As shown, the etching performed at block S212 removes the pad 19 before removing the interposer layer 16. The etching performed at block S212 is applied to the STI hard mask 21, ensuring that the STI hard mask 21 still covers the STI feature 14.

[0152] Cross-reference Figure 2 and Figures 9A-9C Method 200 continues at block S214, forming a metal gate 30 in the gate cavity 70. Specifically, method 200 may include depositing a gate cavity 70 with a dielectric pad 31. For example, a high-k gate dielectric layer 31 may be deposited along endwalls 41 and 42 extending in the X direction, along cavity sidewalls extending in the Y direction, on an STI hard mask 21 at the bottom of the cavity, and around the nanosheet channel layer 15.

[0153] High-k gate dielectrics as used and described herein include dielectric materials having a high dielectric constant, such as greater than that of thermally oxidized silicon (about 3.9). Example high-k gate dielectric layer 31 may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, high-k gate dielectric layer 31 may include other high-k dielectric materials such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxides of nitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer 31 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods.

[0154] The formation of the metal gate 30 further includes filling the gate cavity 70 with a filler material 32. The filler material 32 may include a multilayer metal, a metal alloy, or a metal silicide. The filler material 32 may include a single layer or alternating multilayer structures, such as various combinations of metal layers (work function metal layers) having a selected work function to enhance device performance, padding layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the filler material 32 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the filler material 32 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the filler material 32 may be formed separately for N-type and P-type transistors that may use different metal layers. Additionally, the filler material 32 can provide an N-type or P-type work function and can be used as a transistor gate electrode. In at least some embodiments, the filler material 32 may include a polysilicon layer. In some embodiments, the filler material 32 may include selectively grown tungsten (W) and / or fluorine-free tungsten (FFW) layers.

[0155] like Figures 9A-9C As shown, a chemical mechanical planarization (CMP) process can be performed to remove overloaded portions of the pad 31 and filler material 32 to define the metal gate 30 in the gate cavity 70.

[0156] like Figure 2 As shown, method 200 can continue further processes at block S216, such as performing mid-end (MEOL) and back-end (BEOL) processes.

[0157] Figure 10 It is similar Figure 9B and Figure 9C The Y-section view shows an embodiment of the insulating structure 40 formed between the two fins 12.

[0158] like Figure 10 As shown, fin 12 has two opposing sidewalls 151 and 152. Sidewall 151 of fin 12 defines a vertical plane 812, while endwall 41 of insulating structure 40 defines a vertical plane 840. As further shown, the upper surface of top nanosheet layer 15 defines upper nanosheet plane 915, the upper surface of STI feature 14 defines upper STI plane 914, and the bottom valley point of insulating structure 40 defines bottom plane 940.

[0159] like Figure 10 As shown, the insulating structure 40 is formed having a pitch or horizontal distance Da from plane 812 to plane 840. In some embodiments, the pitch Da is 63.2 nm to 63.9 nm, for example 63.6 nm.

[0160] like Figure 10 As shown, the fin 12 is formed to have a critical dimension or horizontal width Db at the plane 914. In some embodiments, the critical dimension Db is 24.4 nm to 25.5 nm, for example 24.9 nm.

[0161] like Figure 10 As shown, the insulating feature 60 is formed to have a critical dimension or horizontal width Dc at plane 915. In some embodiments, the critical dimension Dc is 36.3 nm to 39.3 nm, for example 38.0 nm.

[0162] like Figure 10 As shown, the insulating feature 60 is formed to have a critical dimension or horizontal width Dd at the plane 914. In some embodiments, the critical dimension Dd is 27.1 nm to 35.2 nm, for example 30.9 nm.

[0163] like Figure 10 As shown, the insulating feature 60 is formed with a vertical depth De from plane 915 to plane 940. In some embodiments, the vertical depth De is 187.9 nm to 192.4 nm, for example 195.7 nm.

[0164] like Figure 10As shown, the sidewall 152 of the insulating feature 60 and the endwall 41 of the insulating structure 40 are separated by a lateral spacing Df. In some embodiments, the lateral spacing Df is at least 20 nm, for example at least 25 nm, at least 30 nm, at least 32 nm, at least 34 nm, at least 36 nm, at least 37 nm, at least 38 nm, at least 39 nm, at least 40 nm, at least 41 nm, at least 42 nm, at least 43 nm, at least 44 nm, or at least 45 nm. In some embodiments, the lateral spacing Df is at most 22 nm, for example at most 25 nm, at most 30 nm, at most 32 nm, at most 34 nm, at most 36 nm, at most 37 nm, at most 38 nm, at most 39 nm, at most 40 nm, at most 41 nm, at most 42 nm, at most 43 nm, at most 44 nm, at most 45 nm, or at most 46 nm.

[0165] In some embodiments, the critical dimension Dc is 50% to 80% of the pitch Da. For example, the critical dimension Dc can be at least 50%, at least 51%, at least 52%, at least 53%, at least 54%, at least 55%, at least 56%, at least 57%, at least 58%, at least 59%, at least 60%, at least 61%, or at least 62% of the pitch Da. Furthermore, the critical dimension Dc can be at most 51%, at most 52%, at most 53%, at most 54%, at most 55%, at most 56%, at most 57%, at most 58%, at most 59%, at most 60%, at most 61%, at most 62%, at most 63%, at most 64%, or at most 65% of the pitch Da.

[0166] In some embodiments, the critical dimension Dd is 30% to 70% of the pitch Da. For example, the critical dimension Dd can be at least 30%, at least 35%, at least 40%, at least 41%, at least 42%, at least 43%, at least 44%, at least 45%, at least 46%, at least 47%, at least 48%, at least 49%, at least 50%, at least 51%, at least 52%, at least 53%, at least 54%, or at least 55% of the pitch Da. Furthermore, the critical dimension Dd can be at most 40%, at most 41%, at most 42%, at most 43%, at most 44%, at most 45%, at most 46%, at most 47%, at most 48%, at most 49%, at most 50%, at most 51%, at most 52%, at most 53%, at most 54%, at most 55%, or at most 56% of the pitch Da.

[0167] Figures 1-10 An embodiment is described in which the CPODE process is performed before the formation of the metal gate 30 to form the insulating structure 40. In some embodiments, the metal gate 30 may be formed before the CMODE process to form the insulating structure 40. Figures 11-19 Such embodiments are described.

[0168] Figure 11 A simplified top-down layout diagram of a semiconductor element 100 (e.g., a multi-gate element 100) is provided. The multi-gate element 100 includes transistors whose gate structures are formed on at least both sides of a channel region. These multi-gate elements may include P-type metal-oxide-semiconductor elements or N-type metal-oxide-semiconductor multi-gate elements.

[0169] In various embodiments, the multi-gate element 100 may comprise a FinFET element, a gate all-around (GAA) element, or other types of multi-gate elements. A GAA element comprises any element whose gate structure or a portion thereof is formed on the four sides of the channel region (e.g., around a portion of the channel region). Elements presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Hereinafter, “nanosheet channel” is intended to include nanowire channel and strip channel configurations. Embodiments of element 100 are presented herein, which may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will recognize that this spirit can be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art will recognize other paradigms of semiconductor elements that may benefit from the aspects of this disclosure.

[0170] A multi-gate element 100 is formed over a substrate 10. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. As is known in the art, the substrate 10 may include various doping configurations depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 10 may optionally include an epitaxial layer, which may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancing features.

[0171] Figure 11 This is a top view of unit cell 11 (i.e., a portion of semiconductor substrate 10). As shown, parallel active regions 20 are spaced apart from each other and extend along the X direction. Source / drain features 90 are formed in the parallel active regions 20. Furthermore, parallel gate lines 30 are spaced apart from each other and extend along the Y direction perpendicular to the X direction. Example: The gate lines 30 are formed of a conductive material such as metal and form the gate structure of the multi-gate element 100. As shown, a gate dielectric layer 31 surrounds the conductive gate lines 30.

[0172] Further as Figure 11As shown, a diced region or trench is formed in a gate line 30 and filled with an insulating material to form an insulating structure 40, which can isolate adjacent elements from each other as described below. As used herein, “insulating,” “isolate,” and “dielectric” can be considered synonyms and are used in different contexts only for clarity of description.

[0173] The methods described herein relate to the formation of an insulating structure 40, such as a continuous metal on diffusion edge (CMODE) structure 40 that divides one or more fins into two parts. In some embodiments, a portion of a selected fin structure is removed and replaced with an insulating material.

[0174] For the purposes of this disclosure, "diffusion edge" may be equivalently referred to as active edge, where, for example, an active edge is adjacent to an adjacent active region. Furthermore, active regions include areas forming transistor structures (e.g., including source, drain, and gate / channel structures). In some embodiments, active regions may be disposed between insulating regions. The CMODE process can provide isolation regions between adjacent active regions by performing a dry etching process along the active edge (e.g., at the boundary of adjacent active regions), thereby providing isolation regions between adjacent transistors to form diced regions and fill these diced regions with a dielectric, such as silicon nitride (SiN).

[0175] Prior to the CMODE process, the active edge may include a metal gate structure having a gate stack and multiple channels (e.g., nanosheet channels). Each of the multiple channels may include a chemical oxide layer formed thereon, and a high-k dielectric / metal gate layer may be formed above the chemical oxide layer and between adjacent channels. Furthermore, internal spacers may be disposed between adjacent channels at the lateral ends of the multiple channels. In various embodiments, source / drain epitaxial layers of adjacent active regions are disposed on both sides of the GAA dummy structure (formed at the active edge), such that the adjacent source / drain epitaxial layers contact the internal spacers and the multiple channels of the GAA dummy structure.

[0176] In some embodiments herein, a CMODE-first process method is employed, i.e., after the metal gate is formed.

[0177] Please refer to Figure 12The document illustrates a method 200 for fabricating a semiconductor device 100 (such as a multi-gate device) using a CPODE process according to various embodiments. Method 200 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, strip-shaped) and sizes. However, it should be understood that aspects of method 200, including the disclosed CPODE process, can be equally applied to other types of multi-gate devices without departing from the scope of this disclosure. In some embodiments, method 200 can be used to fabricate multi-gate device 100, as described above. Figure 11 Therefore, one or more aspects discussed above with reference to the multi-gate element 100 can also be applied to method 200. It should be understood that method 200 includes steps characterized by complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore will only be briefly described here. Additionally, further steps may be performed before, after, and / or during method 200.

[0178] The following is for reference Figures 13A-18B Description method 200, Figures 13A-18B Semiconductor element 100 at various manufacturing stages according to method 200 is shown. Figures 13A-18A An embodiment of semiconductor element 100 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the X-axis passing through fin 12.

[0179] Figures 13B-18B An embodiment of semiconductor element 100 is provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by the Y-axis passing through gate line 30.

[0180] Semiconductor element 100 may include various other devices and features, such as other types of devices like additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but are simplified for better understanding of the concepts disclosed herein. In some embodiments, semiconductor element 100 includes multiple semiconductor elements (e.g., transistors), including PFETs and NFETs, which may be interconnected. Furthermore, it should be noted that the process steps of method 200, including any descriptions given with reference to the accompanying drawings, are merely exemplary and are not intended to limit the scope beyond what is specifically described in the appended claims.

[0181] Method 200 begins with block S202, which provides a partially fabricated multi-gate element 100. Please refer to [reference needed]. Figures 13A-13BIn an embodiment of block S202, method 200 forms a structure 12, such as a fin, over a substrate 10. The fins 12 extend in the X direction and are spaced apart from each other in the Y direction perpendicular to the X direction. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 10 may include various doping configurations as known in the art, depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 10 may optionally include an epitaxial layer, which may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancing features.

[0182] Fin 12 may include a nanosheet channel layer, designated 15, interleaved with an interposer layer, designated 16. In some embodiments, nanosheet channel layer 15 may include silicon (Si) and interposer layer 16 may include silicon-germanium (SiGe). However, in some embodiments, nanosheet channel layer 15 may include other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, and alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. For example, nanosheet channel layer 15 may be epitaxially grown using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0183] As shown in the figure, a liner 19 can be formed along the sidewalls of the stack of layers 15 and 16 and the top of the stack of layers 15 and 16. In this embodiment, the liner 19 is silicon oxide.

[0184] In various embodiments, each fin 12 includes a substrate portion 13 formed from the substrate 10. It should be noted that although the fin 12 is shown as comprising three nanosheet channel layers 15, this is for illustrative purposes only and is not intended to limit the scope beyond what is specifically set forth in the claims. It should be understood that any number of nanosheet channel layers 15 can be formed, wherein, for example, the number of nanosheet channel layers 15 depends on the desired number of channel regions of the GAA element (e.g., element 100). In some embodiments, the number of nanosheet channel layers 15 is between three and ten.

[0185] Shallow trench isolation (STI) feature 14 may also be formed within fin 12. In some embodiments, STI feature 14 comprises silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various embodiments, the dielectric layer for forming the STI feature may be deposited by CVD processes, subatmospheric pressure CVD (SACVD) processes, flow CVD processes, ALD processes, PVD processes, and / or other suitable processes.

[0186] As shown in the figure, a hard mask 21 is formed over the STI feature 14. The STI hard mask 21 can be silicon nitride or other suitable materials.

[0187] like Figures 13A-13B As further shown, the partially fabricated multi-gate element 100 also includes a sacrificial layer 17, such as a sacrificial or dummy gate structure 17 extending along the Y direction. The sacrificial gate structures 17 are spaced apart from each other in the X direction and formed over portions of the fins 12 that will become channel regions. The sacrificial gate structures 17 may extend over multiple adjacent fins 12, as shown. The sacrificial gate structures 17 are located directly over and define the channel region of the GAA element to be formed. Each sacrificial gate structure 17 may include a sacrificial gate dielectric and a sacrificial gate electrode above the sacrificial gate dielectric.

[0188] The sacrificial gate structure 17 is formed by first depositing a sacrificial gate dielectric layer over the fin 12. Then, a sacrificial gate electrode layer is deposited over the sacrificial gate dielectric layer and over the fin 12. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nm to about 5 nm. In some embodiments, the sacrificial gate structure 17 is planarized. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited by CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. The sacrificial gate dielectric layer and the sacrificial gate electrode layer may be masked and patterned to form the sacrificial gate structure 17.

[0189] As shown in the figure, a mask layer 18 is formed over the sacrificial gate structure 17. The mask layer 18 may comprise a mask layer such as silicon oxide or a mask layer such as silicon nitride.

[0190] Cross-reference Figure 12 and Figures 14A-14BMethod 200 can continue at block S210 to remove the sacrificial gate structure 17 to form the gate cavity 70. The etching performed at block S210 to remove the sacrificial gate structure 17 is applied to the pad 19 and the STI hard mask 21, such that the pad 19 remains on and around the stack of layers 15 and 16, and the STI hard mask 21 remains covering the STI feature 14.

[0191] Cross-reference Figure 12 and Figures 15A-15B Method 200 can continue at block S212, removing the interposer layer 16 and leaving the nanosheet channel layer 15 spaced above the fin 12 to define the nanosheet channel region. As shown, the etching performed at block S212 removes the pad 19 before removing the interposer layer 16. The etching performed at block S212 is applied to the STI hard mask 21, ensuring that the STI hard mask 21 still covers the STI feature 14.

[0192] Cross-reference Figure 12 and Figures 16A-16B Method 200 continues at block S212, forming a metal gate 30 in the gate cavity 70. Specifically, method 200 may include laying the gate cavity 70 with a dielectric pad 31. For example, a high-k gate dielectric layer 31 may be deposited along the cavity sidewalls extending in the Y direction, deposited on the STI hard mask 21 at the bottom of the cavity, and deposited around the nanosheet channel layer 15.

[0193] High-k gate dielectrics as used and described herein include dielectric materials having a high dielectric constant, such as greater than that of thermally oxidized silicon (about 3.9). Example high-k gate dielectric layer 31 may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, high-k gate dielectric layer 31 may include other high-k dielectric materials such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxides of nitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer 31 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods.

[0194] The formation of the metal gate 30 further includes filling the gate cavity 70 with a filler material 32. The filler material 32 may include a multilayer metal, a metal alloy, or a metal silicide. The filler material 32 may include a single layer or alternating multilayer structures, such as various combinations of metal layers (work function metal layers) having a selected work function to enhance device performance, padding layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the filler material 32 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the filler material 32 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the filler material 32 may be formed separately for N-type and P-type transistors that may use different metal layers. Additionally, the filler material 32 can provide an N-type or P-type work function and can be used as a transistor gate electrode. In at least some embodiments, the filler material 32 may include a polysilicon layer. In some embodiments, the filler material 32 may include selectively grown tungsten (W) and / or fluorine-free tungsten (FFW) layers.

[0195] like Figures 16A-16B As shown, a chemical mechanical planarization (CMP) process can be performed to remove overloaded portions of the pad 31 and filler material 32 to define the metal gate 30 in the gate cavity 70. As shown, a masking layer 18 can be formed over the metal gate 30.

[0196] Cross-reference Figure 12 and Figures 17A-17B Method 200 can continue the CMODE etching process at block S214. Specifically, the mask layer is patterned before etching is performed to remove a portion of the metal gate 30 located above the selected fin 12'. As a result, trench 50 is formed. The etching process at block S214 can be used on pad 19 and STI hard mask 21, such that pad 19 remains above and around the stack of layers 15 and 16, and STI hard mask 21 remains covering STI feature 14. During the CMODE etching process, the uncovered pad 19 forming the portion of the selected fin 12' is removed from the stack below layers 15 and 16. As a result, trench 50 extends into substrate 10.

[0197] The etching process at block S214 can be used on STI hard mask 21, so that STI hard mask 21 retains coverage of STI feature 14.

[0198] As shown in the figure, method 200 includes removing a portion of at least one structure 12' to form a groove 50. The groove 50 extends through the fin 12, i.e., along the Y direction.

[0199] Cross-reference Figure 2 and Figures 18A-18B Method 200 can continue at block S208, forming a CMODE insulating structure 40 in the trench. The CMODE insulating structure 40 can be formed from a filler material in the trench 50. For example, the filler material can be silicon oxide. Overloaded portions of the filler material can be removed by a planarization process.

[0200] As shown in the figure, the insulating structure 40 terminates at the first end wall 41, terminates at the second end wall 42, and extends from the first end wall 41 to the second end wall 42 along the Y direction.

[0201] like Figure 12 As shown, method 200 can continue with further processes at block S214, such as performing mid-cycle (MEOL) and back-end (BEOL) processes.

[0202] Figure 19 It is similar Figure 18B The Y-section view shows an embodiment of the insulating structure 40 formed between the two fins 12.

[0203] like Figure 19 As shown, the sidewall of fin 12 defines a vertical plane 812, while the sidewall of insulating structure 40 defines a vertical plane 840. As further shown, the upper surface of the top nanosheet layer 15 defines an upper nanosheet plane 915, the upper surface of STI feature 14 defines an upper STI plane 914, the upper surface of STI hard mask 21 defines an upper STI plane 921, and the bottom valley point of insulating structure 40 defines the bottommost plane 940.

[0204] like Figure 19 As shown, the insulating structure 40 is formed having a pitch or horizontal distance La from plane 812 to plane 840. In some embodiments, the pitch La is 63.8 to 64.0 nm, for example 63.9 nm.

[0205] like Figure 19 As shown, the fin 12 is formed to have a critical dimension or horizontal width Lb at the plane 914. In some embodiments, the critical dimension Lb is 23.2 to 23.9 nm, for example 24.8 nm.

[0206] like Figure 19 As shown, the insulating feature 60 is formed to have a critical dimension or horizontal width Lc at plane 915. In some embodiments, the critical dimension Lc is 41.1 to 44.5 nm, for example 43.2 nm.

[0207] like Figure 19As shown, the insulating feature 60 is formed to have a critical dimension or horizontal width Ld2 at the plane 914. In some embodiments, the critical dimension Ld2 is 28.6 to 32.0 nm, for example 30.4 nm.

[0208] like Figure 19 As shown, the insulating feature 60 is formed having a vertical depth Le from plane 915 to plane 940. In some embodiments, the vertical depth Le is 177.6 to 200.8 nm, for example 187.4 nm.

[0209] like Figure 19 As shown, the sidewall 152 of the insulating feature 60 and the endwall 41 of the insulating structure 40 are separated by a lateral spacing Lf. In some embodiments, the lateral spacing Lf is at least 20 nm, for example at least 25 nm, at least 30 nm, at least 32 nm, at least 34 nm, at least 36 nm, at least 37 nm, at least 38 nm, at least 39 nm, at least 40 nm, at least 41 nm, at least 42 nm, at least 43 nm, at least 44 nm, or at least 45 nm. In some embodiments, the lateral spacing Lf is at most 22 nm, for example at most 25 nm, at most 30 nm, at most 32 nm, at most 34 nm, at most 36 nm, at most 37 nm, at most 38 nm, at most 39 nm, at most 40 nm, at most 41 nm, at most 42 nm, at most 43 nm, at most 44 nm, at most 45 nm, or at most 46 nm.

[0210] In some embodiments, the critical dimension Lc is 50% to 80% of the pitch La. For example, the critical dimension Lc may be at least 50%, at least 51%, at least 52%, at least 53%, at least 54%, at least 55%, at least 56%, at least 57%, at least 58%, at least 59%, at least 60%, at least 61%, at least 62%, at least 63%, at least 64%, at least 65%, at least 66%, at least 67%, at least 68%, at least 69%, or at least 70% of the pitch La. Furthermore, the critical dimension Lc can be up to 51%, up to 52%, up to 53%, up to 54%, up to 55%, up to 56%, up to 57%, up to 58%, up to 59%, up to 60%, up to 61%, up to 62%, up to 63%, up to 64%, up to 65%, up to 66%, up to 67%, up to 68%, up to 69%, up to 70%, up to 71%, up to 72%, up to 73%, up to 74%, up to 75%, up to 76%, up to 77%, up to 78%, up to 79%, or up to 80% of the pitch La.

[0211] In some embodiments, the critical dimension Ld1 is 30% to 70% of the pitch La. For example, the critical dimension Ld1 can be at least 30%, at least 35%, at least 40%, at least 41%, at least 42%, at least 43%, at least 44%, at least 45%, at least 46%, at least 47%, at least 48%, at least 49%, at least 50%, at least 51%, at least 52%, at least 53%, at least 54%, or at least 55% of the pitch La. Furthermore, the critical dimension Ld1 can be at most 40%, at most 41%, at most 42%, at most 43%, at most 44%, at most 45%, at most 46%, at most 47%, at most 48%, at most 49%, at most 50%, at most 51%, at most 52%, at most 53%, at most 54%, at most 55%, or at most 56% of the pitch La.

[0212] In some embodiments, the critical dimension Ld2 is 20% to 60% of the pitch La. For example, the critical dimension Ld2 can be at least 20%, at least 25%, at least 30%, at least 31%, at least 32%, at least 33%, at least 34%, at least 35%, at least 36%, at least 37%, at least 38%, at least 39%, at least 40%, at least 41%, at least 42%, at least 43%, at least 44%, or at least 45% of the pitch La. Furthermore, the critical dimension Ld2 can be at most 30%, at most 31%, at most 32%, at most 33%, at most 34%, at most 35%, at most 36%, at most 37%, at most 38%, at most 39%, at most 40%, at most 41%, at most 42%, at most 43%, at most 44%, at most 45%, or at most 46% of the pitch La.

[0213] The STI hard mask 21 has a vertical thickness from plane 914 to plane 921. In some embodiments, the vertical thickness of the STI hard mask 21 is 10.6 nm to 13.1 nm, for example 11.8 nm.

[0214] Figures 11-19 An embodiment is described in which a CMODE process is performed after the formation of the metal gate 30 to form an insulating structure 40. Figures 11-19 In this configuration, the gate dielectric pad 31 is not present on the end walls 41 and 42 of the insulating structure 40 (except at the interface with the upper surface of the STI hard mask 21).

[0215] Cross-reference Figure 10 and Figure 19The element 100 forms an insulating structure 40 that separates a first metal gate segment 301 and a second metal gate segment 302 formed by bisecting the common metal line 30. Therefore, the first metal gate segment 301 and the second metal gate segment 302 are collinear and extend away from the insulating structure 40 along the Y direction. The first metal gate segment 301 and the second metal gate segment 302 are separated by a gap 303, in which an insulating feature 60 is formed.

[0216] While the above embodiments are described with regard to reducing or minimizing the metal boundary effect at the interface between the CPODE or CMODE insulating structure and the metal gate, other embodiments are provided herein.

[0217] For example, certain embodiments are provided to control the metal gate boundary to control the channel length. Specifically, it has been found that non-uniform channel lengths in nanosheet transistors can be obtained due to in-diffusion from the interposer to the nanosheet channel layer. This in-diffusion can occur during the activation of source / drain features by thermal treatment. Specifically, high-temperature annealing, for example, at a temperature of at least 1000 degrees Celsius to activate source / drain carriers, causes interposer impurities to diffuse in-difuse through vacancies in the nanosheet channel layer. The embodiments described herein can avoid, reduce, and / or minimize in-diffusion from the interposer to the nanosheet channel layer.

[0218] In some embodiments, the interposer can be completely removed and replaced by a protective liner. Such embodiments may be particularly useful for narrow or short nanosheet channel layers (i.e., nanosheet channel layers with a length of less than 60 nanometers). In wide or long nanosheet channel layers (i.e., nanosheet channel layers with a length of at least 60 nanometers), complete removal of the interposer may be difficult to achieve.

[0219] In some embodiments, a protective liner is located at the interface between the interposer and the nanosheet channel layer. Such embodiments may be particularly useful for wide or long nanosheet channel layers because they avoid difficult interposer removal processes.

[0220] Furthermore, certain embodiments are provided to specifically avoid, reduce, and / or minimize the inward diffusion of the interposer layer in the nanosheet channel layer at the terminal region, i.e., the region adjacent to the inner spacer, such as the corner of the nanosheet channel layer. Specifically, if the terminal region of the nanosheet channel layer is transformed into an inwardly diffused region and removed, the metal boundary length can be altered. Therefore, protection of the terminal region of the nanosheet channel layer can particularly provide for the formation of a consistent metal boundary.

[0221] To protect the terminal regions of the nanosheet channel layer, some embodiments use a protective layer with a hardness gradient. Specifically, the terminal regions of the protective liner, i.e., the regions adjacent to the inner spacers, are relatively hard, while the central region of the protective liner is relatively soft. As a result, less internal diffusion occurs in the terminal regions of the nanosheet channel layer located beneath the hard terminal regions of the protective layer during the heat source / drain feature activation process.

[0222] Furthermore, some embodiments are provided to specifically avoid, reduce, and / or minimize the inward diffusion of the interposer layer in the nanosheet channel layer located at the terminal region of the nanosheet channel layer by controlling the shape of the inner spacers. Specifically, it has been found that providing inner spacers with a convex profile shields the terminal region of the nanosheet layer and reduces inward diffusion therein.

[0223] Some embodiments provide precise control over the original nanosheet channels and channel length. Such embodiments may use an oxide protective liner between the nanosheet channel layer and the intercalation layer to prevent internal diffusion through vacancies and interstitial sites.

[0224] The embodiments disclosed herein offer advantages over the prior art. Although it should be understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and not all embodiments need to have specific advantages.

[0225] Please refer to Figure 20 According to various embodiments, a method 400 for manufacturing a semiconductor device 100 (such as a multi-gate device) with reduced internal diffusion is illustrated. Method 400 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, strip-shaped) and sizes. However, it should be understood that aspects of method 400, including the disclosed CPODE process, can be equally applied to other types of multi-gate devices without departing from the scope of this disclosure. It should be understood that method 400 includes steps characteristic of complementary metal-oxide-semiconductor (CMOS) technology processes, and therefore are only briefly described herein. Additionally, additional steps may be performed before, after, and / or during method 400.

[0226] The following is for reference Figures 21A-32B Method 400 is described. Figures 21A-32B Semiconductor element 100 at various manufacturing stages according to method 400 is shown. Figures 21A-32A A cross-sectional view of an embodiment of a semiconductor element 100 is provided along a plane substantially parallel to the X-axis that passes through the fin. Figures 21B-32B A cross-sectional view of an embodiment of a semiconductor element 100 is provided along a plane substantially parallel to the Y-axis that passes through the gate.

[0227] Semiconductor element 100 may include a variety of other elements and features, such as other types of elements like additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but are simplified for better understanding of the concepts disclosed herein. In some embodiments, semiconductor element 100 includes multiple semiconductor elements (e.g., transistors), including PFETs and NFETs, which may be interconnected. Furthermore, it should be noted that the process steps of method 400, including any descriptions given with reference to the accompanying drawings, are merely exemplary and are not intended to limit the scope beyond what is specifically described in the appended claims.

[0228] Method 400 begins with block S402, which provides a partially fabricated multi-gate element 100. Please refer to [reference needed]. Figures 21A-21B In an embodiment of block S402, method 400 forms a structure 12, such as a fin, over a substrate 10. The fins 12 extend in the X direction and are spaced apart from each other in the Y direction perpendicular to the X direction. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 10 may include various doping configurations as known in the art, depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 10 may optionally include an epitaxial layer, which may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancing features.

[0229] Fin 12 may include a nanosheet channel layer, designated 15, interleaved with an interposer layer, designated 16. In some embodiments, nanosheet channel layer 15 may include silicon (Si) and interposer layer 16 may include silicon-germanium (SiGe). However, in some embodiments, nanosheet channel layer 15 may include other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, and alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, interposer layer 16 may include silicon (Si) or another material different from that of nanosheet channel layer 15. For example, nanosheet channel layer 15 may be epitaxially grown using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0230] As shown in the figure, a liner 19 can be formed along the sidewalls of the stack of layers 15 and 16 and the top of the stack of layers 15 and 16. In this embodiment, the liner 19 is silicon oxide.

[0231] In various embodiments, each fin 12 includes a substrate portion 13 formed from the substrate 10. It should be noted that although the fin 12 is shown as comprising three nanosheet channel layers 15, this is for illustrative purposes only and is not intended to limit the scope beyond what is specifically set forth in the claims. It should be understood that any number of nanosheet channel layers 15 can be formed, wherein, for example, the number of nanosheet channel layers 15 depends on the desired number of channel regions of the GAA element (e.g., element 100). In some embodiments, the number of nanosheet channel layers 15 is between three and ten.

[0232] Shallow trench isolation (STI) feature 14 may also be formed within fin 12. In some embodiments, STI feature 14 comprises silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various embodiments, the dielectric layer for forming the STI feature may be deposited by CVD processes, subatmospheric pressure CVD (SACVD) processes, flow CVD processes, ALD processes, PVD processes, and / or other suitable processes.

[0233] like Figures 21A-21B As further shown, the partially fabricated multi-gate element 100 also includes a sacrificial layer 17, such as a sacrificial or dummy gate structure 17 extending along the Y direction. The sacrificial gate structures 17 are spaced apart from each other in the X direction and formed over portions of the fins 12 that will become channel regions. The sacrificial gate structures 17 may extend over multiple adjacent fins 12. The sacrificial gate structures 17 are located directly over and define the channel region of the GAA element to be formed. Each sacrificial gate structure 17 may include a sacrificial gate dielectric and a sacrificial gate electrode above the sacrificial gate dielectric.

[0234] The sacrificial gate structure 17 is formed by first depositing a sacrificial gate dielectric layer over the fin 12. Then, a sacrificial gate electrode layer is deposited over the sacrificial gate dielectric layer and over the fin 12. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nm to about 5 nm. In some embodiments, the sacrificial gate structure 17 is planarized. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited by CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. The sacrificial gate dielectric layer and the sacrificial gate electrode layer can be masked and patterned using masking layers 312 and 314 to form the sacrificial gate structure 17.

[0235] In operation S404, method 400 further includes depositing a low-k spacer 316 over the sacrificial gate structure 17 to form a sidewall spacer, as shown. Additionally, a dielectric layer 318, such as a silicon nitride layer, may be deposited over the low-k spacer 316.

[0236] Cross-reference Figure 20 and Figures 22A-22B Method 400 continues at block S406, etching the source / drain regions. Specifically, the portions of layers 15 and 16, and the underlying substrate 10 not covered by the sacrificial gate structure 17, are oriented to form source / drain region voids 320 in each fin 12. Horizontal portions of the dielectric layer 318 and the low-k spacer 316 are also removed, for example, between and above the sacrificial gate structures 17, while remaining on the sidewalls of the sacrificial gate structures 17.

[0237] Cross-reference Figure 20 and Figures 23A-23B Method 400 continues at block S408, removing the interposer layer 16 to form voids 322, leaving nanosheet channel layers 15 spaced above the fins 12 to define the nanosheet channel regions. For example, etching can be performed through voids 320 to selectively etch the interposer layer 16.

[0238] Cross-reference Figure 20 and Figures 24A-24B Method 400 continues at block S410, depositing a protective liner material 328. In an exemplary embodiment, the protective liner material 328 is conformally deposited along the exposed surface of the structure of element 100, for example, along the sidewall of void 320. As shown, the protective liner material 328 fills void 322.

[0239] In some embodiments, the protective liner material 328 is silicon oxide and / or silicon nitride.

[0240] Cross-reference Figure 20 and Figures 25A-25B Method 400 continues at block S412, where a protective liner 330 is formed from the protective liner material 328. For example, the protective liner material 328 can be trimmed and removed from the sidewalls of the cavity 320 and the upper surface of the structure of element 100, such that the protective liner material 328 remains in the gaps 322 between the nanosheet layers 15 as the protective liner 330. Furthermore, block S412 may include recesses in the side surfaces 333 of the protective liner 330.

[0241] Cross-reference Figure 20 and Figures 26A-26B Method 400 continues at block S414, forming an inner spacer 340 adjacent to the protective liner 330. For example, the inner spacer material can be formed on the protective liner 330. Excess material extending into the cavity 320 can be trimmed. Thus, the inner spacer 340 is formed. The inner spacer 340 separates the protective liner 330 from the cavity 320.

[0242] Cross-reference Figure 20 and Figures 27A-27B Method 400 continues at block S416, forming source / drain features 350 in the void 320. For example, epitaxial material can be grown on substrate 10 and nanosheet 15.

[0243] Cross-reference Figure 20 and Figures 28A-28B Method 400 continues at block S418, forming an interlayer dielectric (ILD) 360 over the source / drain feature 350. Block S418 may include planarizing the ILD 360, for example, to the upper surface on which the masking layer 314 is formed.

[0244] like Figure 20 As shown, method 400 includes performing a process at block S450 to activate source / drain feature 350. In some embodiments, the process at block S450 may be a high-temperature annealing process. For example, a high-temperature annealing process may be performed at a temperature of at least 1000 degrees Celsius. In other embodiments, the process at block S419 may be a low-temperature annealing process. For example, a low-temperature annealing process may be performed at a temperature of less than 1000 degrees Celsius.

[0245] During the annealing process, method 400 includes preventing internal diffusion in the nanosheet layer 15 at block S460. Specifically, protective pad 330 forms a barrier layer to prevent impurities (e.g., from SiGe or Ge) from diffusing through vacancies in the nanosheet layer 15.

[0246] Cross-reference Figure 20 and Figures 29A-29BMethod 400 can continue at block S420, exposing the sacrificial gate structure 17. Block S420 may include performing a planarization process to remove masking layers 312 and 314.

[0247] Cross-reference Figure 20 and Figures 30A-30B Method 400 can continue at block S422, removing the sacrificial gate structure 17 to form the gate cavity 370.

[0248] Cross-reference Figure 20 and Figures 31A-31B Method 400 can continue at block S424, removing pad 19 from the top of the stack of sidewalls, layer 15, and protective pad 330.

[0249] Cross-reference Figure 20 and Figures 32A-32B Method 400 can continue at block S426, removing the protective liner 330 from between the nanosheet channel layers 15, for example in a sheet release process.

[0250] Cross-reference Figure 20 and Figures 33A-33B Method 400 can continue at block S428 to form a metal gate 380 in the gate cavity 370. Specifically, method 400 may include depositing a dielectric pad 381 in the gate cavity 370. For example, a high-k gate dielectric layer 381 may be deposited along the cavity sidewall, deposited above the STI hard mask 21 located at the bottom of the cavity, and deposited around the nanosheet channel layer 15.

[0251] High-k gate dielectrics as used and described herein include dielectric materials having a high dielectric constant, such as a dielectric constant greater than that of thermally oxidized silicon (about 3.9). Example high-k gate dielectric layer 381 may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, high-k gate dielectric layer 381 may include other high-k dielectric materials such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxides of nitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer 381 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods.

[0252] The formation of the metal gate 380 further includes filling the gate cavity 370 with a filler material 382. The filler material 382 may include a multilayer metal, a metal alloy, or a metal silicide. The filler material 382 may include a single layer or alternating multilayer structures, such as various combinations of metal layers (work function metal layers) having a selected work function to enhance device performance, padding layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the filler material 382 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the filler material 32 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the filler material 382 may be formed separately for N-type and P-type transistors that may use different metal layers. Additionally, the filler material 382 can provide an N-type or P-type work function and can be used as a transistor gate electrode. In at least some embodiments, the filler material 382 may include a polycrystalline silicon layer. In some embodiments, the filler material 382 may include selectively grown tungsten (W) and / or fluorine-free tungsten (FFW) layers.

[0253] like Figures 33A-33B As shown, a chemical mechanical planarization (CMP) process can be performed to remove overloaded portions of the pad 381 and filler material 382 to define the metal gate 380 in the gate cavity 370.

[0254] like Figure 20 As shown, method 400 can continue further processes at block S430, such as performing mid-end (MEOL) and back-end (BEOL) processes.

[0255] Although Figures 20-33B In one embodiment, the interposer 16 is completely removed and replaced with a protective pad 330, but other embodiments may provide a protective pad 330 formed around the interposer 16.

[0256] For example, refer to Figure 34 Method 400 is illustrated according to such an embodiment. Figure 34 Combination Figures 35-41 Method 400 is described. Figures 35-41 These are all Y-section views.

[0257] Cross-reference Figure 34 and Figure 35 Method 400 includes providing a multi-gate element 100 partially manufactured as described above.

[0258] However, in Figure 34In some embodiments, block S402 includes execution blocks S410 and S412, namely, depositing and forming a protective liner 330 between the interposer 16 and the nanosheet layer 15. Therefore, the fin 12 may include a nanosheet channel layer 15 interleaved with the protective liner 330 and the interposer 16. In some embodiments, the nanosheet channel layer 15 may include silicon (Si) and the interposer 16 may include silicon germanium (SiGe). However, in some embodiments, the nanosheet channel layer 15 may include other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, and alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, the interposer 16 may include silicon (Si) or another material different from the material of the nanosheet channel layer 15. For example, the nanosheet channel layer 15 can be epitaxially grown using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. The protective liner 300 can be formed of silicon oxide, silicon nitride, or another suitable material used to inhibit the diffusion of material from the interposer 16 into the nanosheet channel layer 15.

[0259] like Figure 35 As shown, each protective pad 330 is located between the interposer layer 16 and the nanosheet layer 15. The stack of layers can be formed over the substrate portion 13 of the fin 12 as a stack of pads 330, layer 16, pads 330, layer 15, pads 330, etc., up to the top layer, such as the top layer 15.

[0260] Figure 36 yes Figure 35 A partial schematic diagram of the cross-section, focusing on layers 15, 16, and the protective gasket 330. As shown, the protective gasket 330 completely separates layers 15 and 16, meaning that a portion of layer 16 does not contact layer 15.

[0261] In some embodiments, the protective pad 330 is silicon oxide.

[0262] like Figure 35 As shown, liner 19 can be formed along the sidewalls and above the stack of layers 15, 16 and liner 330.

[0263] As described above, shallow trench isolation (STI) feature 14 can also be formed to insert fin 12.

[0264] like Figure 35 As further shown above, a sacrificial or dummy gate structure 17 is formed above the fin 12.

[0265] In operation S404, method 400 further includes forming sidewall spacers by depositing low-k spacers over the sacrificial gate structure 17. Furthermore, as described above, a dielectric layer, such as a silicon nitride layer, may be deposited over the low-k spacers.

[0266] exist Figure 34 In the embodiment described above, method 400 continues at block S406, etching the source / drain regions.

[0267] exist Figure 34 In this embodiment, method 400 continues at block S414, forming an inner spacer adjacent to the interposer 16 and the protective liner 330. For example, the sidewall surfaces of the interposer 16 and the protective liner 330 that were not covered during the etching of the source / drain regions may be concave. Next, an inner spacer material may be deposited and trimmed to form the inner spacer as described above.

[0268] exist Figure 34 In one embodiment, as described above, method 400 continues at block S416, forming source / drain features in the void. Furthermore, as described above, method 400 may continue at block S418, forming an in-layer dielectric (ILD) above the source / drain features.

[0269] Figure 37 It is a partial schematic diagram, similar to Figure 36 The diagram illustrates the structure of element 100 after the formation of inner spacer 340 and source / drain features 350. As shown, a protective liner 330 extends from inner spacer 340 and completely separates layer 15 from layer 16, i.e., a portion of layer 16 does not contact layer 15.

[0270] In addition, the protective gasket 330 is formed to have a thickness H L Furthermore, the nanosheet channel layer 15 contacts the inner spacer 340 at interface 345. Each interface 345 independently has a length L1.

[0271] like Figure 34 As shown, method 400 includes performing a process at block S450 to activate source / drain characteristics. In some embodiments, the process at block S450 may be a high-temperature annealing process. For example, a high-temperature annealing process may be performed at a temperature of at least 1000 degrees Celsius. In other embodiments, the process at block S419 may be a low-temperature annealing process. For example, a low-temperature annealing process may be performed at a temperature of less than 1000 degrees Celsius.

[0272] During the annealing process, method 400 includes preventing or reducing internal diffusion in the nanosheet layer 15 at block S460. Specifically, a protective liner 330 forms a barrier layer to prevent impurities (e.g., SiGe or Ge from the interposer layer 16) from diffusing through vacancies in the nanosheet layer 15.

[0273] Therefore, during the annealing process of the block S450, the protective liner prevents material from diffusing from the interposer 16 (e.g., germanium or silicon germanium) into the nanosheet layer 15.

[0274] Figure 38 It is a partial schematic diagram, similar to Figure 37 The structure of element 100 following blocks S450 and S460 is shown. Figure 39 It is focused on Figure 38 A schematic diagram of a portion of element 100. Specifically, focus is on the corner 399 where the protective liner 330 contacts the inner spacer 340.

[0275] like Figure 39 As most clearly shown, the internal diffusion region 390 is formed in the nanosheet channel layer 15 below the protective layer 300, wherein material from the interposer layer 16 diffuses internally into the nanosheet channel layer 15. The internal diffusion region 390 does not exist below the internal spacer 340, i.e., it has zero thickness below the internal spacer 340 and grows to a maximum thickness H. D For example, at the maximum distance from the inner spacer 340, that is, at the midpoint between the opposing inner spacers 340.

[0276] Cross-reference Figure 37 and Figure 39 Thickness H L and thickness H D They are inversely proportional. For example, when the protective gasket 330 is absent and the thickness H... L When the value is zero, the size of the inner diffusion region 390 is the largest and the thickness H is the largest. D Maximum. When the thickness H L When it is very large, the thickness H D It could be zero.

[0277] Figure 34 An embodiment may continue to expose the sacrificial gate structure 17 at block S420, remove the sacrificial gate structure 17 at block S422 to form a gate cavity, remove the pad 19 from the sidewalls and over the top of the stack of layers 15, 16 and the protective pad 330 at block S424, and remove the protective pad 330 and the interposer layer 16 from between the nanosheet channel layers 15 at block S426, for example in a wafer release process.

[0278] Figure 40 It is similar to Figure 38A partial schematic diagram shows the structure of element 100 after block S426 is executed. As shown, after removing the protective pad 330 and the interposer 16, the nanosheet channel layer 15 is retained. Figure 40 As further shown, the internal diffusion region 390 is retained on the nanosheet channel layer 15.

[0279] exist Figure 34 In this method 400, the inner diffusion region 390 is further removed at block S427. For example, selective etching of the material in the inner diffusion region 390 can be performed.

[0280] Figure 41 It is similar to Figure 40 A partial schematic diagram illustrates the structure of element 100 after execution of block S427. As shown, the nanosheet channel layer 15 thins in the central region but substantially retains its original thickness at the inner spacer 340. As shown, there is a length L2 at the interface 345 between the inner spacer 340 and the nanosheet channel layer 15. In some embodiments, length L2 is equal to length L1. In some embodiments, length L2 is at least 99% of length L1, for example, at least 95%, at least 90%, at least 85%, or at least 80% of length L1.

[0281] Figure 34 The embodiment may continue to form a metal gate in the metal cavity at block S428, and perform further processes at block S430 as described above.

[0282] Figures 42-45 An embodiment of method 400 is shown, wherein a protective liner 330 with a hardness gradient is formed. Specifically, as Figure 42 As shown, the protective liner 330 is relatively hard in the terminal region 336, and relatively soft in the central region 338. The protective liner 330 can be formed of silicon oxide or other suitable materials. In some embodiments, the protective liner 330 is formed of flowable silicon oxide. The protective liner can be customized according to... Figure 20 or Figure 34 Method 400 is used to form it.

[0283] Figure 43 The structure following the formation of the inner spacer 340 and the source / drain feature 350 is shown, such as after blocks S414 and S416 in method 400.

[0284] Figure 44The structure is shown after a process that activates the source / drain characteristics while preventing or reducing internal diffusion in the nanosheet layer 15, for example, after blocks S450 and S460. As shown, the internal diffusion region 390 is formed within a central region 398 aligned with the soft central region 338 of the protective liner 330. No internal diffusion region is formed in the terminal region of the nanosheet channel layer 15 adjacent to the central region 398.

[0285] Figure 45 The structure after removing the inner diffusion region 390, for example, after block S427, is shown. As shown, by removing the inner diffusion region 390, only the central region 398 is thinned. Therefore, the nanosheet channel layer 15 maintains its thickness at the interface with the inner spacer 340.

[0286] Figures 46-49 An embodiment of method 400 is shown, wherein a protective liner 330 forms an inner layer 331 and an outer layer 332.

[0287] like Figure 46 As shown, the inner layer 331 forms a continuous interface with the nanosheet layer 15, so that no part of the outer layer 332 is in contact with the nanosheet layer 15.

[0288] Inner layer 331 can be as described above regarding Figure 34 The method involves forming the pad 330. Next, the outer layer 332 can be formed as described above. Figure 42 The described formation has a softer central region 338 and a harder terminal region 336.

[0289] Figure 47 The structure following the formation of the inner spacer 340 and source / drain features 350 is shown, for example, after blocks S414 and S416 in method 400. It should be noted that the inner layer 331 may terminate at the inner spacer 340, as... Figure 47 The upper inner layer 331 is shown. Alternatively, the inner layer 331 may extend beyond the inner spacer 340 and separate the inner spacer 340 from the nanosheet layer 15, as shown. Figure 47 The lower inner layer 331 is shown. Furthermore, it should be noted that in a typical embodiment, both the upper and lower inner layers 331 terminate at the inner spacer 340 or both extend beyond the inner spacer 340. Figure 47 Examples of each type of internal spacer 340 are shown in a single schematic diagram.

[0290] Figure 48The structure following a process that prevents or reduces internal diffusion in the nanosheet layer 15 while performing source / drain characteristic activation is shown, for example, after blocks S450 and S460. As shown, an internal diffusion region 390 is formed within a central region 398 aligned with the soft central region 338 of the protective liner 330. No internal diffusion region is formed in the terminal region of the nanosheet channel layer 15 adjacent to the central region 398.

[0291] Because the inner layer 331 is added to the outer layer 332 where the soft central region 338 is formed, therefore... Figure 44 Compared to the previous embodiment, the thickness of the inner diffusion region 390 can be reduced.

[0292] Figure 49 The structure after removing the inner diffusion region 390 is shown, for example, after block S427. As shown, by removing the inner diffusion region 390, only the central region 398 becomes thinner. Therefore, the nanosheet channel layer 15 maintains its thickness at the interface with the inner spacer 340.

[0293] Figures 50-52 The process for forming, for example, the protective pad 330 or the outer layer 332 of the protective pad 330 according to blocks S410 and S412 is shown. Figures 50-53 are Y-section views of the nanosheet channel layer 15 below the sacrificial gate structure 17.

[0294] Figure 50 The structure of element 100 after the removal of interposer layer 16, for example after block S408, is shown. As shown, voids 322 are formed between nanosheet layers 15.

[0295] Figure 51 The structure of element 100 is shown after the deposition of protective liner material 328, for example, after block S410. As shown, the protective liner material fills voids 322. In some embodiments, the protective liner material 328 is flowable silicon oxide deposited in a refill process.

[0296] Figure 52 The structure of element 100 is shown after the protective liner 330 is formed from the protective liner material 328, for example, after block S412. Specifically, in the embodiment of Figures 50-53, a process is performed to cure the protective liner material 328 or to transform the protective liner material 328 into the protective liner 330 (or outer layer 332). In some embodiments, an ultraviolet (UV) or synthesis gas (e.g., H2 gas) curing process is performed. As a result, the terminal region 336 is hardened, while the central region 338 remains soft.

[0297] Figures 53-55The process is shown in which the interface between each inner spacer 340 and the corresponding intermediate layer 16 and protective liner 330 forms a convex profile.

[0298] Figure 53 The structure of the component after the inner spacer 340 is formed at block S414 and the source / drain feature 350 is formed at block S416 is shown. As shown, interface 345 is formed between the inner spacer 340, the interposer 16, and the protective gasket 330. In the cross-sectional view shown, interface 345 is convex. Specifically, interface 345 extends from terminal 346 in contact with gasket 330 to vertex 348, and then to terminal 346 in contact with gasket 330. As shown, vertex 348 is located at the maximum distance D4 from the source / drain feature 350, and each terminal 346 is located at the minimum distance D5 from the source / drain feature 350. As shown, distance D4 is greater than distance D5 by distance D6.

[0299] Figure 54 The structure following a process that prevents or reduces internal diffusion in the nanosheet layer 15 while performing source / drain characteristic activation is shown, for example, after blocks S450 and S460. As shown, an internal diffusion region 390 is formed within the central region 398. No internal diffusion region is formed in the terminal region of the nanosheet channel layer 15 adjacent to the central region 398.

[0300] It is known that the convex shape of the inner spacer 340 reduces internal diffusion and minimizes the size of the internal diffusion region 390, especially in the end region of the nanosheet channel layer 15.

[0301] Figure 55 The structure after removing the inner diffusion region 390, for example, after block S427, is shown. As shown, by removing the inner diffusion region 390, only the central region 398 is thinned. Therefore, the nanosheet channel layer 15 maintains its thickness at the interface with the inner spacer 340.

[0302] exist Figures 53-55 In this configuration, the protective liner 330 extends to and terminates at the inner spacer 340. However, the protective liner 330 may extend through the inner spacer 340 to reach the source / drain feature 350.

[0303] For example, Figures 56-58 The process of forming a convex profile at the interface between each inner spacer 340 and the corresponding intermediate layer 16 and protective gasket 330 is shown. Figures 56-58 In the middle, the protective pad 330 extends to contact the source / drain feature 350.

[0304] Figure 56The structure of the component after the inner spacer 340 is formed at block S414 and the source / drain feature 350 is formed at block S416 is shown. As shown, interface 345 is formed between the inner spacer 340, the interposer 16, and the protective gasket 330. In the cross-sectional view shown, interface 345 is convex. Specifically, interface 345 extends from terminal 346 in contact with gasket 330 to vertex 348, and then to terminal 346 in contact with gasket 330. As shown, vertex 348 is located at the maximum distance D4 from the source / drain feature 350, and each terminal 346 is located at the minimum distance D5 from the source / drain feature 350. As shown, distance D4 is greater than distance D5 by distance D6.

[0305] Figure 57 The structure following a process that prevents or reduces internal diffusion in the nanosheet layer 15 while performing source / drain characteristic activation is shown, for example, after blocks S450 and S460. As shown, an internal diffusion region 390 is formed within the central region 398. No internal diffusion region is formed in the terminal region of the nanosheet channel layer 15 adjacent to the central region 398.

[0306] It is known that the convex shape of the inner spacer 340 reduces internal diffusion and minimizes the size of the internal diffusion region 390, especially in the end region of the nanosheet channel layer 15.

[0307] Figure 58 The structure after removing the inner diffusion region 390, for example, after block S427, is shown. As shown, by removing the inner diffusion region 390, only the central region 398 is thinned. Therefore, the nanosheet channel layer 15 maintains its thickness at the interface with the inner spacer 340.

[0308] According to the embodiments described herein, element 100 may be formed of a plurality of transistors, each transistor having three nanosheet channel layers 500.

[0309] exist Figure 59 The image shows a single transistor of element 100. Each transistor in the element includes a top nanosheet channel layer 501, a middle nanosheet channel layer 502, and a bottom nanosheet channel layer 503. Each nanosheet channel layer 500 has a left edge 511, a center 512, and a right edge 513.

[0310] In the exemplary embodiment, the nanosheet channel layer 500 has a uniform thickness throughout the entire element.

[0311] For example, the top nanosheet channel layer has a thickness of 531 at the left edge 511, at the center 512, and at the right edge 513.

[0312] In the example device with multiple transistors, the thickness 531 at the left edge 511 has a minimum of 5.8 nm, a maximum of 5.9 nm, and an average of 5.9 nm. In the example device, the thickness 531 at the center 512 has a minimum of 5.6 nm, a maximum of 6.0 nm, and an average of 5.6 nm. In the example device, the thickness 531 at the right edge 513 has a minimum of 6.4 nm, a maximum of 6.5 nm, and an average of 6.4 nm.

[0313] As shown in the figure, the intermediate nanosheet channel layer 502 has a thickness of 532 at the left edge 511, the center 512, and the right edge 513.

[0314] In the example device with multiple transistors, the thickness 532 at the left edge 511 has a minimum of 6.2 nm, a maximum of 6.2 nm, and an average of 6.2 nm. In the example device, the thickness 532 at the center 512 has a minimum of 6.2 nm, a maximum of 6.5 nm, and an average of 6.3 nm. In the example device, the thickness 532 at the right edge 513 has a minimum of 6.4 nm, a maximum of 6.5 nm, and an average of 6.5 nm.

[0315] As shown in the figure, the bottom nanosheet channel layer 503 has a thickness of 533 at the left edge 511, the center 512, and the right edge 513.

[0316] In the example device with multiple transistors, the thickness 533 at the left edge 511 has a minimum of 6.2 nm, a maximum of 6.3 nm, and an average of 6.2 nm. In the example device, the thickness 533 at the center 512 has a minimum of 6.2 nm, a maximum of 6.9 nm, and an average of 6.6 nm. In the example device, the thickness 533 at the right edge 513 has a minimum of 6.5 nm, a maximum of 6.7 nm, and an average of 6.6 nm.

[0317] Therefore, for all nanosheet channel layers 500, the channel thickness variation does not exceed 0.7 nm. In some embodiments, the channel thickness variation of the nanosheet channel layer 500 is less than 0.7 nm, for example less than 0.6 nm, less than 0.5 nm, less than 0.4 nm, less than 0.3 nm, less than 0.2 nm, less than 0.1 nm, or less than 0.05 nm.

[0318] In some embodiments, the channel thickness variation of the nanosheet channel layer 500 is less than 12.5% ​​based on the minimum thickness of the nanosheet channel layer 500. For example, the channel thickness variation of the nanosheet channel layer 500 may be less than 12%, less than 11%, less than 10%, less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, or less than 0.5%, all based on the minimum thickness of the nanosheet channel layer 500.

[0319] In an exemplary embodiment, the nanosheet channel layer 500 has a uniform length 540 on element 100.

[0320] For example, the top nanosheet channel layer 501 has a length 540 at the upper surface 521. In the example element, the length 540 of the top nanosheet channel layer 501 at the upper surface 521 has a minimum of 14.7 nm, a maximum of 14.7 nm, and an average of 14.7 nm.

[0321] Furthermore, the top nanosheet channel layer 501 has a length 540 at the lower surface 522. In the example element, the length 540 of the top nanosheet channel layer 501 at the lower surface 522 has a minimum of 14.9 nm, a maximum of 14.9 nm, and an average of 14.9 nm.

[0322] For the top nanosheet channel layer 501, the variation between the length 540 at the upper surface and the length 540 at the lower surface is less than 0.2 nm.

[0323] The intermediate nanosheet channel layer 502 has a length of 540 at the upper surface 521. In the example element, the length 540 of the intermediate nanosheet channel layer 502 at the upper surface 521 has a minimum of 15.7 nm, a maximum of 16.4 nm, and an average of 16.0 nm.

[0324] Furthermore, the intermediate nanosheet channel layer 502 has a length 540 at the lower surface 522. In the example element, the length 540 of the intermediate nanosheet channel layer 502 at the lower surface 522 has a minimum of 16.0 nm, a maximum of 17.4 nm, and an average of 16.7 nm.

[0325] For the intermediate nanosheet channel layer 502, the variation between the length 540 at the upper surface and the length 540 at the lower surface is less than 0.7 nm.

[0326] The bottom nanosheet channel layer 503 has a length of 540 at the upper surface 521. In the example element, the length 540 of the bottom nanosheet channel layer 503 at the upper surface 521 has a minimum of 17.3 nm, a maximum of 18.6 nm, and an average of 17.9 nm.

[0327] Furthermore, the bottom nanosheet channel layer 503 has a length 540 at the lower surface 522. In the example element, the length 540 of the bottom nanosheet channel layer 503 at the lower surface 522 has a minimum of 18.2 nm, a maximum of 18.4 nm, and an average of 18.3 nm.

[0328] For the bottom nanosheet channel layer 503, the variation between the length 540 at the upper surface and the length 540 at the lower surface is less than 0.4 nm.

[0329] Therefore, for all nanosheet channel layers 500, the channel length variation does not exceed 1.5 nm. In some embodiments, the channel thickness variation of the nanosheet channel layer 500 is less than 1.5 nm, for example, less than 1.4 nm, less than 1.3 nm, less than 1.2 nm, less than 1.1 nm, less than 1.0 nm, less than 0.9 nm, less than 0.8 nm, less than 0.7 nm, less than 0.6 nm, less than 0.5 nm, less than 0.4 nm, less than 0.3 nm, less than 0.2 nm, less than 0.1 nm, or less than 0.05 nm.

[0330] In some embodiments, the channel length variation of the nanosheet channel layer 500 is less than 11% based on the minimum length of the nanosheet channel layer 500. For example, the channel length variation of the nanosheet channel layer 500 may be less than 10%, less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, or less than 0.5%, all based on the minimum length of the nanosheet channel layer 500.

[0331] Although relative to Figure 20 and Figure 34 Method 400 illustrates various features, but it should be noted that embodiments may include any particular feature in combination, even if such a combination is not specifically described herein.

[0332] In one embodiment, the method includes forming a plurality of nanosheet channel layers over a semiconductor material; forming a protective pad on each nanosheet channel layer; forming a plurality of fin structures from the nanosheet channel layers and a portion of the semiconductor material; forming a sacrificial gate over the semiconductor material; performing a thermal annealing process while the protective pad is located on the nanosheet channel layers; removing at least a portion of a selected fin structure and a covering portion of the sacrificial gate located over a portion of the selected fin structure to form a trench; forming an insulating structure in the trench; removing the remaining portion of the sacrificial gate to form a gate cavity, wherein the gate cavity is partially defined by end walls of the insulating structure; removing the protective pad from the nanosheet channel layers; and forming a metal gate in the gate cavity.

[0333] In some embodiments, the method further includes forming a plurality of STI features above and adjacent to the first fin structure on the semiconductor substrate, wherein the thickness of the insulating structure is 35% to 50% of the pitch dimension at the plane defined by the uppermost surface of the STI features.

[0334] In some embodiments, the method further includes forming a plurality of interposer layers over a semiconductor material, wherein the interposer layers are interleaved with nanosheet channel layers; and removing the interposer layers to form a plurality of voids; wherein a protective liner is formed on each nanosheet channel layer, including forming the protective liner in the voids.

[0335] In some embodiments of the method, the selected protective liner contacts multiple adjacent nanosheet channel layers.

[0336] In some embodiments of the method, a protective liner is formed on each nanosheet channel layer, including making each protective liner have a relatively soft central region and a relatively hard terminal region.

[0337] In some embodiments of the method, a protective liner is formed on each nanosheet channel layer, including depositing and curing the protective liner material.

[0338] In some embodiments, the method further includes forming a plurality of interposers over a semiconductor material, wherein the interposers are interleaved with protective pads and nanosheet channel layers, and wherein each interposer is separated from a corresponding nanochannel layer by a corresponding protective layer; and removing the interposers after performing a thermal annealing process.

[0339] In some embodiments, the method further includes forming a plurality of inner spacers laterally adjacent to each intermediary layer, wherein each inner spacer has a convex profile.

[0340] In some embodiments of the method, each nanosheet channel layer has a central region located between opposing terminal regions, and the method further includes preventing the formation of an internal diffusion region in the terminal region of the nanosheet channel layer.

[0341] In some embodiments of the method, each nanosheet channel layer has a central region located between opposing terminal regions, wherein an inner diffusion region is formed in the central region of each nanosheet channel layer during a thermal annealing process, and wherein the method further includes removing the inner diffusion region.

[0342] In some embodiments, the method further includes etching a nanosheet channel layer around the sacrificial gate to form a source / drain region void; forming an inner spacer between the nanosheet channel layer and the source / drain region void; and forming source / drain features in the source / drain region void, wherein a thermal annealing process activates the source / drain features.

[0343] In other embodiments, the method includes forming a nanosheet channel layer over a semiconductor material; forming a fin structure over the semiconductor material; forming a sacrificial gate structure over the nanosheet channel layer; etching the nanosheet channel layer around the sacrificial gate structure to form source / drain region voids; forming source / drain features in the source / drain region voids; preventing inward diffusion of the nanosheet channel layer with a protective pad while performing a thermal annealing process to activate the source / drain features; replacing the sacrificial gate structure with a metal gate consisting of a gate dielectric pad and a metal filler; removing at least a portion of the fin structure and the covering portion of the metal gate above the portion of the fin structure to form a trench; and forming an insulating structure in the trench, wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first sidewall and a second sidewall; wherein the pitch dimension is defined from the first sidewall to the first end wall; and wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension.

[0344] In some embodiments of the method, an insulating structure is formed in the trench, including forming an insulating structure in direct contact with the metal filler of the metal gate.

[0345] In some embodiments of the method, the thickness of the insulating structure is 60% to 70% of the pitch dimension at the plane defined by the uppermost surface of the first fin structure.

[0346] In some embodiments of the method, the second sidewall of the first fin structure is 20 nm to 45 nm away from the insulating structure.

[0347] In some embodiments, the method further includes forming an STI feature adjacent to the first fin structure, wherein the thickness of the insulating structure is 35% to 50% of the pitch dimension at the plane defined by the uppermost surface of the STI feature.

[0348] In another embodiment, the semiconductor element includes a semiconductor substrate comprising a first fin structure and a second fin structure; a first metal gate segment located above the semiconductor substrate and the first fin structure; a second metal gate segment located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart from each other by a gap; and an insulating structure located within the gap and insulating the first metal gate segment and the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first side wall and a second side wall; wherein the pitch dimension is defined from the first side wall to the second side wall; and wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension.

[0349] In some embodiments of the semiconductor device, each metal gate segment includes a metal filler and a dielectric pad, wherein the metal filler is in direct contact with the endwall of the insulating structure.

[0350] In some embodiments of the semiconductor device, each metal gate segment includes a metal filler and a dielectric pad, wherein the dielectric pad is located between the end wall of the insulating structure and the insulating structure.

[0351] In some embodiments of the semiconductor device, the thickness of the insulating structure at the plane defined by the uppermost surface of the fin structure is 60% to 70% of the pitch dimension.

[0352] In another embodiment, the semiconductor element 100 includes a semiconductor substrate 10 having a first fin structure 12 and a second fin structure 12; a first metal gate segment 301 located above the semiconductor substrate and the first fin structure; a second metal gate segment 302 located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart from each other by a gap 303; and an insulating structure 40 located in the gap, insulating the first metal gate segment from the second metal gate segment, wherein a dielectric structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall 41 and a second end wall 42, the thickness between the first end wall 41 and the second end wall 42 being Dc / Lc; wherein the first fin structure has a first side wall 151 and a second side wall 152; wherein the pitch dimension Da / La defines the first side wall 151 and the first end wall 41; and wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension.

[0353] In some embodiments of the semiconductor device, each metal gate segment includes a metal filler and a dielectric pad, with the metal filler in direct contact with the endwall of the insulating structure.

[0354] In some embodiments of the semiconductor device, each metal gate segment includes a metal filler and a dielectric pad, and the dielectric pad is located between the end wall of the insulating structure and the insulating structure.

[0355] In some embodiments of the semiconductor device, at the plane 915 defined by the uppermost surface of the fin structure, the thickness of the insulating structure is 60% to 70% of the pitch dimension.

[0356] In some embodiments of the semiconductor device, the second sidewall of the first fin structure is 20 nm to 45 nm away from the insulating structure.

[0357] In some embodiments, the semiconductor element further includes an STI feature above and adjacent to the fin structure on the semiconductor substrate, wherein at plane 914 defined by the uppermost surface of the STI feature, the thickness of the insulating structure is 35% to 50% of the pitch dimension.

[0358] In some embodiments, the semiconductor element further includes an STI feature above and adjacent to the fin structure on the semiconductor substrate; and an STI hard mask 21 located above the STI feature, wherein at a plane 921 defined by the uppermost surface of the STI hard mask, the thickness of the insulating structure is 45% to 55% of the pitch dimension.

[0359] In some embodiments, the semiconductor element further includes an STI feature above and adjacent to the fin structure on the semiconductor substrate; and an STI hard mask 21 located above the STI feature, wherein the STI hard mask separates each metal gate segment from the STI feature.

[0360] In some embodiments of the semiconductor device, the STI hard shield contact insulation structure is combined with the first fin structure.

[0361] In another embodiment, the method includes forming a fin structure 12 over a semiconductor material 10; forming a sacrificial layer 17 over the semiconductor material; removing at least a portion of the fin structure and a portion of the sacrificial layer covering that portion of the fin structure to form a trench 50; forming an insulating structure 40 in the trench; removing the remaining portion of the sacrificial layer to form a cavity 70, wherein the cavity 70 is partially defined by an end wall 41 of the insulating structure. A metal gate 301 is formed within the cavity.

[0362] In some embodiments of the method, forming a metal gate in a cavity includes padding the cavity with a pad, wherein the pad is formed on an insulating structure; and filling the cavity with a filler material.

[0363] In some embodiments of the method, the insulating structure has a first end wall 41 and a second end wall 42, the thickness between the first end wall 41 and the second end wall 42 being Dc / Lc; the fin structure has a first side wall 151 and a second side wall 152; a pitch dimension Da / La is defined from the first side wall 151 to the first end wall 41; the thickness of the insulating structure is 35% to 70% of the pitch dimension.

[0364] In some embodiments of the method, at plane 915 defined by the uppermost surface of the fin structure, the thickness of the insulating structure is 60% to 70% of the pitch dimension.

[0365] In some embodiments of the method, the distance between the second sidewall of the fin structure and the insulating structure is 20 nm to 45 nm.

[0366] In some embodiments, the method further includes forming an STI feature above and adjacent to the fin structure on the semiconductor substrate, wherein at a plane 914 defined by the uppermost surface of the STI feature, the thickness of the insulating structure is 35% to 50% of the pitch dimension.

[0367] In some embodiments, the method further includes forming an STI feature above and adjacent to the fin structure on a semiconductor substrate; and forming an STI hard mask above the STI feature, wherein the STI hard mask separates the metal gate from the STI feature.

[0368] In another embodiment, the method includes forming a fin structure 12 over a semiconductor material 10; forming a sacrificial layer 17 over the semiconductor material; replacing the sacrificial gate with a metal gate consisting of a gate dielectric pad and a metal filler; removing at least a portion of the fin structure and the covering portion of the metal gate located above the portion of the fin structure to form a trench 50; and forming an insulating structure 40 in the trench, wherein the insulating structure has a first end wall 41 and a second end wall 42, defining a thickness Dc / Lc between the first end wall and the second end wall; wherein the first fin structure has a first side wall 151 and a second side wall 152; wherein the pitch dimension is defined from the first side wall 151 to the first end wall 41; and wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension.

[0369] In some embodiments of the method, an insulating structure 40 is formed in the trench, including forming an insulating structure in direct contact with the metal filler of the metal gate.

[0370] In some embodiments of the method, at the plane 915 defined by the uppermost surface of the first fin structure, the thickness of the insulating structure is 60% to 70% of the pitch dimension.

[0371] In some embodiments of the method, the second sidewall of the fin structure is 20 nm to 45 nm away from the insulating structure.

[0372] In some embodiments of the method, an STI feature is formed above and adjacent to the fin structure on the semiconductor substrate, wherein at plane 914 defined by the uppermost surface of the STI feature, the thickness of the insulating structure is 35% to 50% of the pitch dimension.

[0373] In one embodiment, the method includes forming a plurality of nanosheet channel layers over a semiconductor material; forming a protective pad on each nanosheet channel layer; performing a thermal annealing process while the protective pad is on the nanosheet channel layer; and removing the protective pad from the nanosheet channel layer.

[0374] In some embodiments of the method, the selected protective liner contacts multiple adjacent nanosheet channel layers.

[0375] In some embodiments of the method, a protective liner is formed on each nanosheet channel layer, including making each protective liner have a relatively soft central region and a relatively hard terminal region.

[0376] In some embodiments of the method, a protective liner is formed on each nanosheet channel layer, including depositing and curing the protective liner material.

[0377] In some embodiments, the method further includes forming a plurality of interposers over a semiconductor material, wherein the interposers are interleaved with protective pads and nanosheet channel layers, and wherein each interposer is separated from a corresponding nanochannel layer by a corresponding protective layer; and removing the interposers after performing a thermal annealing process.

[0378] In some embodiments, the method further includes forming a plurality of inner spacers laterally adjacent to each intermediary layer, wherein each inner spacer has a convex profile.

[0379] In some embodiments of the method, each nanosheet channel layer has a central region located between opposing terminal regions, and the method further includes preventing the formation of internal diffusion regions in the terminal regions of the nanosheet channel layers.

[0380] In some embodiments of the method, each nanosheet channel layer has a central region located between opposing terminal regions, wherein an inner diffusion region is formed in the central region of each nanosheet channel layer during a thermal annealing process, and the method further includes removing the inner diffusion region.

[0381] In some embodiments, the method further includes forming a sacrificial gate structure over the nanosheet channel layer; etching the nanosheet channel layer around the sacrificial gate structure to form source / drain region voids; forming an inner spacer between the nanosheet channel layer and the source / drain region voids; forming source / drain features in the source / drain region voids, wherein a thermal annealing process activates the source / drain features; removing the sacrificial gate structure to form a gate cavity; and forming a metal gate around the nanosheet channel layer after removing the protective pad from the nanosheet channel layer.

[0382] In another embodiment, the method includes forming a plurality of nanosheet channel layers over a semiconductor material; forming a sacrificial gate structure over the plurality of nanosheet channel layers; etching the nanosheet channel layers around the sacrificial gate structure to form source / drain region voids; forming source / drain features in the source / drain region voids; and using a protective pad to prevent inward diffusion of the nanosheet channel layers when a thermal annealing process is performed to activate the source / drain features.

[0383] In some embodiments, the method further includes removing the sacrificial gate structure to form a gate cavity; removing the protective pad; and forming a metal gate around the nanosheet channel layer.

[0384] In some embodiments, the method further includes forming a protective liner interlaced with the nanosheet channel layer prior to forming the sacrificial gate structure.

[0385] In some embodiments, the method further includes forming a protective liner and an interlayer interleaved with the nanosheet channel layer prior to forming the sacrificial gate structure.

[0386] In some embodiments, the method further includes forming an interlayer interleaved with the nanosheet channel layer before forming the sacrificial gate structure; removing the interlayer to define a plurality of voids after forming source / drain region voids; and forming a protective pad in the voids.

[0387] In some embodiments, the method further includes forming an inner portion of a protective pad and an interposer layer interleaved with the nanosheet channel layer before forming the sacrificial gate structure; removing the interposer layer to form a plurality of voids after forming source / drain region voids; and forming an outer portion of the protective pad in the voids.

[0388] In some embodiments of the method, forming the outer portion of the protective liner includes forming each outer portion having a relatively soft central region and a relatively hard terminal region.

[0389] In another embodiment, the intermediate structure of the gate all-around (GAA) transistor element includes a nanosheet channel layer having a central region located between terminal regions; a protective liner in contact with the nanosheet channel layer; and an inner diffusion region located in the central region, wherein the inner diffusion region does not extend to the terminal regions.

[0390] In some embodiments, the intermediate structure of the GAA transistor element further includes an interposer layer, wherein a protective pad contacts the interposer layer, and wherein the protective pad is located between the nanosheet channel layer and the interposer layer.

[0391] In some embodiments, the intermediate structure of the GAA transistor element further includes a sacrificial gate structure located above the nanosheet channel layer; and source / drain features, wherein the nanosheet channel layer, the protective pad, and the interposer are all located between the source / drain features.

[0392] In some embodiments, a semiconductor element includes: a semiconductor substrate comprising a first fin structure and a second fin structure; a first metal gate segment located above the semiconductor substrate and the first fin structure; a second metal gate segment located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart by a gap; and an insulating structure located within the gap and insulating the first metal gate segment and the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first side wall and a second side wall; wherein the pitch dimension is defined from the first side wall to the second side wall; wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension; and wherein each of the metal gate segments includes a metal filler and a dielectric pad, and wherein the metal filler is in direct contact with the first end wall and the second end wall of the insulating structure.

[0393] In some embodiments, a semiconductor element includes: a semiconductor substrate comprising a first fin structure and a second fin structure; a first metal gate segment located above the semiconductor substrate and the first fin structure; a second metal gate segment located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and spaced apart by a gap; and an insulating structure located within the gap and insulating the first metal gate segment and the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; wherein the insulating structure has a first end wall and a second end wall, defining a thickness between the first end wall and the second end wall; wherein the first fin structure has a first side wall and a second side wall; wherein a pitch dimension is defined from the first side wall to the second side wall; wherein the thickness of the insulating structure is 35% to 70% of the pitch dimension; and wherein each of the metal gate segments includes a metal filler and a dielectric pad, and wherein the dielectric pad is located between the first end wall and the second end wall of the insulating structure and the insulating structure.

[0394] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A semiconductor substrate is composed of a first fin structure and a second fin structure; A first metal gate segment is located above the semiconductor substrate and the first fin structure; A second metal gate segment is located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and separated by a gap; as well as An insulating structure is located within the gap and insulates the first metal gate segment from the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; The insulating structure has a first end wall and a second end wall, and a thickness is defined between the first end wall and the second end wall; The first fin structure has a first sidewall and a second sidewall; One of the pitch dimensions is defined as the distance from the first sidewall to the second sidewall; and The thickness of the insulation structure is 35% to 70% of the pitch dimension.

2. The semiconductor device as claimed in claim 1, characterized in that, Each of the metal gate segments includes a metal filler and a dielectric pad, and the metal filler is in direct contact with the first end wall and the second end wall of the insulating structure.

3. The semiconductor device as claimed in claim 1, characterized in that, Each of the metal gate segments includes a metal filler and a dielectric pad, wherein the dielectric pad is located between the first end wall and the second end wall of the insulating structure and the insulating structure.

4. The semiconductor device as claimed in claim 1, characterized in that, in, At a plane defined by the uppermost surface of the fin structure, the thickness of the insulating structure is 60% to 70% of the pitch dimension.

5. A semiconductor element, characterized in that, Include: A semiconductor substrate is composed of a first fin structure and a second fin structure; A first metal gate segment is located above the semiconductor substrate and the first fin structure; A second metal gate segment is located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and separated by a gap; as well as An insulating structure is located within the gap and insulates the first metal gate segment from the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; The insulating structure has a first end wall and a second end wall, and a thickness is defined between the first end wall and the second end wall; The first fin structure has a first sidewall and a second sidewall; One of the pitch dimensions is defined as the distance from the first sidewall to the second sidewall; The thickness of the insulation structure is 35% to 70% of the pitch dimension; and Each of the metal gate segments includes a metal filler and a dielectric pad, and the metal filler is in direct contact with the first end wall and the second end wall of the insulating structure.

6. The semiconductor device as claimed in claim 5, characterized in that, The dielectric pad is located between the first end wall and the second end wall of the insulating structure and the insulating structure.

7. The semiconductor device as claimed in claim 5, characterized in that, in, At a plane defined by the uppermost surface of the fin structure, the thickness of the insulating structure is 60% to 70% of the pitch dimension.

8. A semiconductor element, characterized in that, Include: A semiconductor substrate is composed of a first fin structure and a second fin structure; A first metal gate segment is located above the semiconductor substrate and the first fin structure; A second metal gate segment is located above the semiconductor substrate and the second fin structure, wherein the first metal gate segment and the second metal gate segment are collinear and separated by a gap; as well as An insulating structure is located within the gap and insulates the first metal gate segment from the second metal gate segment, wherein the insulating structure extends into the semiconductor substrate; The insulating structure has a first end wall and a second end wall, and a thickness is defined between the first end wall and the second end wall; The first fin structure has a first sidewall and a second sidewall; One of the pitch dimensions is defined as the distance from the first sidewall to the second sidewall. The thickness of the insulation structure is 35% to 70% of the pitch dimension; and Each of the metal gate segments includes a metal filler and a dielectric pad, wherein the dielectric pad is located between the first end wall and the second end wall of the insulating structure and the insulating structure.

9. The semiconductor element as claimed in claim 8, characterized in that, The metal filler is in direct contact with the first end wall and the second end wall of the insulating structure.

10. The semiconductor device as claimed in claim 8, characterized in that, in, At a plane defined by the uppermost surface of the fin structure, the thickness of the insulating structure is 60% to 70% of the pitch dimension.

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