A trench-type silicon carbide semiconductor device

Abstract

The utility model discloses a kind of trench type silicon carbide semiconductor devices, it is related to semiconductor technical field, the semiconductor device includes the drain metal layer, substrate, epitaxial layer, gate oxide area and source metal layer sequentially arranged from bottom to top, polycrystalline silicon area is arranged in gate oxide area;It further includes P well area, N-type active area, which are sequentially arranged from bottom to top and all with gate oxide area bordering, wherein, P well area borders with epitaxial layer, N-type active area includes first doped active area, P-type high resistance area and second doped active area sequentially arranged from bottom to top, the N-type doping concentration of second doped active area is greater than the N-type doping concentration of first doped active area, second doped active area borders with source metal layer.The utility model not only can improve the short-circuit resistance of silicon carbide semiconductor device, also has the advantages that structure is simple, manufacturing cost is lower.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a trench-type silicon carbide semiconductor device. Background Technology

[0002] Silicon carbide (SiC), as an important wide-bandgap semiconductor material, has been widely used in electronic and power devices in recent years. Its excellent electrical and thermal properties give it irreplaceable advantages in high-temperature, high-power, and high-frequency applications. Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are currently one of the main types of power devices. Among them, trench-type MOSFETs have attracted much attention in recent years due to their lower conduction losses, better switching performance, increased wafer density, and avoidance of parasitic JFET effects compared to traditional planar MOSFETs.

[0003] Improving the short-circuit withstand capability of silicon carbide semiconductor devices is crucial for the reliability and lifespan of power devices. However, current methods for improving the short-circuit withstand capability of silicon carbide semiconductor devices involve highly complex structural designs and high production costs. Utility Model Content

[0004] This application provides a trench-type silicon carbide semiconductor device, which not only improves the short-circuit withstand capability of silicon carbide semiconductor devices, but also has the advantages of simple structure and low manufacturing cost.

[0005] To address the aforementioned issues, this application discloses a trench-type silicon carbide semiconductor device, comprising a drain metal layer, a substrate, an epitaxial layer, a gate oxide region, and a source metal layer arranged sequentially from bottom to top, wherein a polysilicon region is disposed within the gate oxide region; further comprising a P-well region and an N-type active region, both adjacent to the gate oxide region and arranged sequentially from bottom to top, wherein the P-well region is adjacent to the epitaxial layer, and the N-type active region comprises a first doped active region, a P-type high-resistivity region, and a second doped active region arranged sequentially from bottom to top, wherein the N-type doping concentration of the second doped active region is greater than that of the first doped active region, and the second doped active region is adjacent to the source metal layer.

[0006] In one embodiment of this application, the P well region and the N-type active region are disposed on both sides of the gate oxide region, forming a symmetrical structure.

[0007] In one embodiment of this application, the semiconductor device has an axisymmetric structure.

[0008] In one embodiment of this application, the upper surface of the polysilicon region is higher than the upper surface of the P well region.

[0009] In one embodiment of this application, the upper surface of the gate oxide region is higher than the upper surface of the P well region, and the upper surface of the polysilicon region is lower than the upper surface of the P well region but higher than the lower surface of the P well region.

[0010] In one embodiment of this application, the upper surface of the gate oxide region is flush with the upper surface of the second doped active region.

[0011] In one embodiment of this application, the lower surface of the polysilicon region is lower than the lower surface of the P well region and higher than the lower surface of the gate oxide region.

[0012] In one embodiment of this application, an interlayer dielectric layer is further included, the lower surface of which covers the upper surface of the gate oxide region, and the upper surface of the interlayer dielectric layer is adjacent to the source metal layer.

[0013] In one embodiment of this application, the first doped active region is an N-type doped active region, and the second doped active region is an N+ type doped active region.

[0014] In one embodiment of this application, a deep P+ region is also included; the upper surface of the deep P+ region is in contact with the source metal layer, the lower surface of the deep P+ region is in contact with the epitaxial layer, and the side surface of the deep P+ region is in contact with the P well region, the first doped active region, the P-type high-resistivity region, and the second doped active region.

[0015] This application has the following advantages: The trench-type silicon carbide semiconductor device provided in this application includes a drain metal layer, a substrate, an epitaxial layer, a gate oxide region, and a source metal layer arranged sequentially from bottom to top. A polysilicon region is disposed within the gate oxide region. It also includes a P-well region and an N-type active region, both adjacent to the gate oxide region and arranged sequentially from bottom to top. The P-well region is adjacent to the epitaxial layer. The N-type active region includes a first doped active region, a P-type high-resistivity region, and a second doped active region arranged sequentially from bottom to top. The N-type doping concentration of the second doped active region is greater than that of the first doped active region, and the second doped active region is adjacent to the source metal layer. Based on the design of the N-type active region consisting of the first doped active region, the P-type high-resistivity region, and the second doped active region, this application not only ensures ohmic contact between the N-type active region and the source metal layer but also significantly reduces the overall N-type concentration of the N-type active region, thereby reducing the saturation current of the trench-type silicon carbide semiconductor device and improving its short-circuit withstand capability.

[0016] The trench silicon carbide semiconductor device provided in this application is compatible with conventional trench SiC MOSFET processes and has the advantages of simple structure and low manufacturing cost. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application.

[0018] Figure 1 This is a schematic diagram of the structure of a trench-type silicon carbide semiconductor device according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a trench-type silicon carbide semiconductor device according to another embodiment of this application; Figure 3 This is a schematic diagram of the Id-Vd simulation curves of the structure in the embodiment of this application and the conventional structure; Figure 4 This is a schematic diagram of the short-circuit current curves of the embodiment of this application and the conventional structure; Figure 5 This is a schematic diagram showing the change of lattice temperature over time between the structure of the embodiment of this application and the conventional structure.

[0019] Explanation of reference numerals in the attached figures: 101-Drain metal layer, 102-Substrate, 103-Epipolar layer, 104-Gate oxide region, 1041-A region, 1042-B region, 105-Polysilicon region, 106-Source metal layer, 107-Interlayer dielectric layer, 108-P well region, 109-First doped active region, 110-P-type high resistance region, 111-Second doped active region, 112-Deep P+ region, 113-Electron channel, 114-Channel-free resistance region. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0021] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature.

[0022] In related technologies, to improve the short-circuit withstand capability of SiC MOSFETs, methods such as introducing degenerate semiconductor regions, JFET structures, HK interlayer dielectric layers, or sub-gates are mainly employed. However, the inventors discovered that these solutions all require the introduction of new processes into conventional trench SiC MOSFET fabrication. Among these, degenerate semiconductor processes, multiple epitaxial fabrication of JFET structures, HK interlayer dielectric layer processes, or split-gate processes present complex technological challenges.

[0023] In view of this, embodiments of this application propose a trench-type silicon carbide semiconductor device, which may specifically be a silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET).

[0024] refer to Figure 1 and Figure 2 The semiconductor device includes, from bottom to top, a drain metal layer 101, a substrate 102, an epitaxial layer 103, a gate oxide region 104, and a source metal layer 106, wherein a polysilicon region 105 is disposed within the gate oxide region 104; it also includes a P-well region 108 and an N-type active region, both of which are adjacent to the gate oxide region 104 and are disposed from bottom to top. The P-well region 108 is adjacent to the epitaxial layer 103, and the N-type active region includes, from bottom to top, a first doped active region 109, a P-type high-resistivity region 110, and a second doped active region 111, wherein the N-type doping concentration of the second doped active region 111 is greater than the N-type doping concentration of the first doped active region 109, and the second doped active region 111 is adjacent to the source metal layer 106.

[0025] In some implementations, the N-type active region of the trench-type silicon carbide semiconductor device may consist of only three parts: the first doped active region 109, the P-type high-resistivity region 110, and the second doped active region 111. Of course, in other implementations, the N-type active region of the trench-type silicon carbide semiconductor device may include other parts besides the first doped active region 109, the P-type high-resistivity region 110, and the second doped active region 111; this application does not impose any limitations on this.

[0026] In this embodiment, the N-type doping concentration of the second doped active region 111 is greater than that of the first doped active region 109. The high concentration of the second doped active region 111 can ensure that the N-type active region and the source metal layer 106 can make ohmic contact smoothly. The setting of the first doped active region 109 and the P-type high resistance region 110 can significantly reduce the overall N-type concentration of the N-type active region, thereby reducing the saturation current of the trench silicon carbide semiconductor device and improving the short-circuit withstand capability.

[0027] While ensuring ohmic contact between the N-type active region and the source metal layer 106, compared to using only a low-concentration first doped active region 109 to reduce the overall concentration of the N-type active region, this embodiment of the application utilizes the combined effect of the first doped active region 109 and the P-type high-resistance region 110 to reduce the overall concentration of the N-type active region, which can significantly reduce the concentration of the active region and effectively reduce the device saturation current.

[0028] Furthermore, the first doped active region 109 can be an N-type doped active region, and the second doped active region 111 can be an N+ type doped active region.

[0029] In this embodiment, the substrate 102 can be N-type, and the epitaxial layer 103 can be N-type (which can be understood as an N-drift region). The drain metal layer 101, substrate 102, epitaxial layer 103, gate oxide region 104, and source metal layer 106 are arranged sequentially from bottom to top. Specifically, they can be... Figure 1 The structure shown has the drain metal layer 101, substrate 102, epitaxial layer 103, gate oxide region 104 and source metal layer 106 sequentially connected from bottom to top.

[0030] The fabrication processes for the P-well region 108, drain metal layer 101, substrate 102, epitaxial layer 103, gate oxide region 104, and source metal layer 106 can refer to existing trench silicon carbide semiconductor device processes, such as those implemented using trench SiCMOSFET processes, which will not be elaborated upon in this application. When fabricating the trench silicon carbide semiconductor device of this application, the P-type high-resistance region 110 and the P-well region 108 can share a single layout, as can the first doped active region 109 and the second doped active region 111. This simplifies the process steps, avoids introducing additional layouts, is compatible with conventional trench silicon carbide semiconductor device processes, has low production costs, and is widely applicable.

[0031] In trench-type silicon carbide semiconductor devices, trenches are formed by etching trenches on the epitaxial layer 103, and gate oxide regions 104 are grown in the trenches. For example... Figure 1 and Figure 2 As shown, a polysilicon region 105 is disposed within the gate oxide region 104, and the P-well region 108 adjacent to the polysilicon region 105 can generate an electron channel 113 (or conductive channel). It is understood that the polysilicon region 105 is the gate of the semiconductor device. The gate oxide region 104 serves as an intermediate dielectric between the polysilicon region 105 and the P-well region 108. When a voltage is applied to the polysilicon region 105 to generate an electric field, the electric field can penetrate the gate oxide region 104 and act on the sidewall surface of the P-well region, forming an electron channel 113, thereby enabling the source metal layer 106 and the drain metal layer 101 to conduct.

[0032] In some embodiments, the polysilicon region 105 within the gate oxide region 104 has the following structure: Figure 1 As shown, the upper surface of the polysilicon region 105 is higher than the upper surface of the P-well region 108, and the lower surface of the polysilicon region 105 is lower than the lower surface of the P-well region 108 but higher than the lower surface of the gate oxide region 104. In this embodiment, since the upper surface of the polysilicon region 105 is higher than the upper surface of the P-well region 108 and the lower surface of the polysilicon region 105 is lower than the lower surface of the P-well region 108, the entire sidewall of the P-well region 108 is connected to the polysilicon region 105 through the gate oxide region 104. That is, the entire sidewall of the P-well region 108 faces the polysilicon region 105, and the entire sidewall where the P-well region 108 and the gate oxide region 104 meet can form an electron channel 113. The lower surface of the polysilicon region 105 is higher than the lower surface of the gate oxide region 104, ensuring the isolation of the polysilicon region 105 from other regions (such as the epitaxial layer 103).

[0033] In other embodiments, the polysilicon region 105 within the gate oxide region 104 has the following structure: Figure 2 As shown, the upper surface of the gate oxide region 104 is higher than the upper surface of the P-well region 108, the upper surface of the polysilicon region 105 is lower than the upper surface of the P-well region 108 but higher than the lower surface of the P-well region 108, and the lower surface of the polysilicon region 105 is lower than the lower surface of the P-well region 108 but higher than the lower surface of the gate oxide region 104. In this embodiment, since the upper surface of the gate oxide region 104 is higher than the upper surface of the P-well region 108, and the upper surface of the polysilicon region 105 is lower than the upper surface of the P-well region 108 but higher than the lower surface of the P-well region 108, a portion (see attached diagram) of the entire region where the gate oxide region 104 and the P-well region 108 meet is partially (see attached diagram). Figure 2 Region A (1041) contains polycrystalline silicon region 105, and some (see attached) Figure 2 Region B (1042) does not have a polysilicon region 105. Correspondingly, the sidewall of the Pwell region 108 bordering region A (1041) can form an electron channel 113; that is, the sidewall of the Pwell region 108 directly opposite the polysilicon region 105 can form an electron channel 113. However, the sidewall of the Pwell region 108 bordering region B (1042) cannot form an electron channel 113, and can be referred to as a channelless resistance region 114. This channelless resistance region 114 does not affect the device's turn-on process, but it can prevent the electron channel 113 from continuing to grow when the semiconductor device is short-circuited. That is, the device turns on normally in the low-voltage region (Vd), and prevents the electron channel 113 from growing in the high-voltage region (Vd), which can further reduce the device's saturation current and improve its short-circuit withstand capability.

[0034] In other embodiments, not shown in the figures, the lower surface of the polysilicon region 105 may be flush with the lower surface of the P well region 108, and the lower surface of the polysilicon region 105 may be higher than the lower surface of the gate oxide region 104.

[0035] It is worth noting that, compared to using only the first doped active region 109 to reduce the overall concentration of the N-type active region, this application utilizes the combined effect of the first doped active region 109 and the P-type high-resistance region 110. This not only significantly reduces the concentration of the active region and effectively reduces the device saturation current, but also avoids the on-resistance from becoming too large due to the first doped active region 109 separating the P-type high-resistance region 110 and the P-well region 108.

[0036] Furthermore, based on the fact that the upper surface of the gate oxide region 104 is higher than the upper surface of the P-well region 108, and the upper surface of the polysilicon region 105 is lower than the upper surface of the P-well region 108 but higher than the lower surface of the P-well region 108, as... Figure 2 As shown, the upper surface of the gate oxide region 104 can be flush with the upper surface of the second doped active region 111.

[0037] like Figure 1 and Figure 2 As shown, the trench-type silicon carbide semiconductor device of this application embodiment may further include an interlayer dielectric layer 107. The lower surface of the interlayer dielectric layer 107 covers the upper surface of the gate oxide region 104, and the upper surface of the interlayer dielectric layer 107 is adjacent to the source metal layer 106. Through the provision of the interlayer dielectric layer 107, the source metal layer 106 and the gate oxide region 104 can be effectively electrically isolated. The lower surface of the interlayer dielectric layer 107 covering the upper surface of the gate oxide region 104 can mean that the interlayer dielectric layer 107 is exactly completely overlapped with the upper surface of the gate oxide region 104, or the coverage area of ​​the interlayer dielectric layer 107 extends beyond the upper surface of the gate oxide region 104 (e.g., ...). Figure 1 and Figure 2 As shown, the lower surface of the interlayer dielectric layer 107 borders the upper surface of the gate oxide region 104 and partly borders the second doped active region 111 to ensure coverage.

[0038] The trench-type silicon carbide semiconductor device in this application embodiment may further include a deep P+ region 112, such as Figure 1 and Figure 2As shown, the upper surface of the deep P+ region 112 is adjacent to the source metal layer 106, the lower surface of the deep P+ region 112 is adjacent to the epitaxial layer 103, and the side surface of the deep P+ region 112 is adjacent to the P well region 108, the first doped active region 109, the P-type high-resistivity region 110, and the second doped active region 111. Through the above-described structure of the deep P+ region 112, on the one hand, the gate oxide at the bottom of the trench can be protected to cope with the extremely high critical electric field of the SiC material, preventing the high electric field from directly acting on the fragile gate oxide, thus significantly improving the long-term reliability of the gate oxide region and the device's breakdown voltage capability; on the other hand, since the deep P+ region 112 can protect the gate oxide, the thickness of the gate oxide used to encapsulate the polysilicon region 105 can be made thinner, while ensuring yield and process efficiency, which helps to reduce the on-resistance of the device.

[0039] Optionally, the substrate 102, epitaxial layer 103, P-well region 108, first doped active region 109, P-type high-resistivity region 110, second doped active region 111, and deep P+ region 112 can be made of 4H-SiC or other polymorphs of silicon carbide, and this application is not limited thereto. The gate oxide region 104 can be made of silicon dioxide. The interlayer dielectric layer 107 can be made of an insulating material capable of isolating electrical components, such as silicon dioxide or other high dielectric constant (high k) materials. The drain metal layer 101 and source metal layer 106 can be made of nickel alloy, titanium alloy, aluminum alloy, molybdenum alloy, silver alloy, or other metals or metal alloys, and this application is not limited thereto.

[0040] like Figure 1 and Figure 2 As shown, optionally, the P well region 108 and the N-type active region are provided on both sides of the gate oxide region 104 to form a symmetrical structure.

[0041] Furthermore, the trench-type silicon carbide semiconductor device provided in this application embodiment can be an overall axisymmetric structure.

[0042] by Figure 2 Taking the trench-type silicon carbide semiconductor device structure shown (hereinafter referred to as the structure of the embodiment of this application) as an example, Figures 3-5 The simulation comparison between the conventional trench SiC MOSFET structure (hereinafter referred to as the conventional structure) and the structure of the embodiment of this application is shown. It can be concluded that the structure of the embodiment of this application can effectively improve the short-circuit withstand capability and ensure the safety of the device.

[0043] Figure 3The diagram shows the simulated Id-Vd curves of the structure in this embodiment and the conventional structure. The horizontal axis represents the drain voltage Vd (V), and the vertical axis represents the drain current Id (A). It can be seen that the two curves almost overlap in the linear region, indicating that the on-resistance of the structure in this embodiment and the conventional structure is almost equal under low-voltage conditions. However, in the saturation region, due to the channel length modulation effect, Id in the conventional structure still increases relatively quickly with increasing Vd. In contrast, in the structure of this embodiment, Id increases very slowly with increasing Vd, and the saturation current decreases significantly, thus improving short-circuit withstand capability.

[0044] Figure 4 The diagram shows the short-circuit current curves of the embodiment of this application and the conventional structure. The horizontal axis represents time (Time), in seconds (s); the vertical axis represents drain current (Id), in amperes (A). The simulation conditions are short-circuit pulse time tw = 4.5µs and vdd = 800V, where tw is the short-circuit duration and vdd is the bus voltage. It can be seen that during a short circuit, the saturation current of the embodiment of this application is reduced by nearly 40% compared to the conventional structure. Under this short-circuit time tw = 4.5µs condition, the tail current after the conventional structure device is turned off is too large, resulting in thermal failure. However, after the device in the embodiment of this application is turned off, Id returns to 0A, and the device continues to operate normally.

[0045] Figure 5 This diagram illustrates the lattice temperature variation over time between the structure of this application embodiment and the conventional structure. The horizontal axis represents time (seconds), and the vertical axis represents lattice temperature (Kelvin). It can be seen that after the conventional structure is turned off, the lattice temperature initially drops rapidly, then continues to rise due to the large tail current until the device thermally fails. In contrast, after the structure of this application embodiment is turned off, the lattice temperature also initially drops rapidly, but then decreases slowly, without showing a trend towards thermal failure.

[0046] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0047] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand this application, and the content of this specification should not be construed as a limitation of this application. Furthermore, for those skilled in the art, there will be different forms of changes in the specific implementation methods and application scope based on this application. It is neither necessary nor possible to exhaustively list all implementation methods here, and obvious changes or modifications derived therefrom are still within the protection scope of this application.

Claims

1. A trench-type silicon carbide semiconductor device, characterized in that, It includes a drain metal layer, a substrate, an epitaxial layer, a gate oxide region, and a source metal layer arranged sequentially from bottom to top, wherein a polysilicon region is disposed within the gate oxide region; It also includes a P-well region and an N-type active region, both of which are adjacent to the gate oxide region and arranged sequentially from bottom to top. The P-well region is adjacent to the epitaxial layer. The N-type active region includes a first doped active region, a P-type high-resistivity region, and a second doped active region arranged sequentially from bottom to top. The N-type doping concentration of the second doped active region is greater than that of the first doped active region. The second doped active region is adjacent to the source metal layer.

2. The trench-type silicon carbide semiconductor device according to claim 1, characterized in that, The P well region and the N-type active region are both located on both sides of the gate oxide region, forming a symmetrical structure.

3. The trench-type silicon carbide semiconductor device according to claim 2, characterized in that, The semiconductor device has an axisymmetric structure.

4. The trench-type silicon carbide semiconductor device according to any one of claims 1-3, characterized in that, The upper surface of the polycrystalline silicon region is higher than the upper surface of the P well region.

5. The trench-type silicon carbide semiconductor device according to any one of claims 1-3, characterized in that, The upper surface of the gate oxide region is higher than the upper surface of the P well region, and the upper surface of the polysilicon region is lower than the upper surface of the P well region but higher than the lower surface of the P well region.

6. The trench-type silicon carbide semiconductor device according to claim 5, characterized in that, The upper surface of the gate oxide region is flush with the upper surface of the second doped active region.

7. The trench-type silicon carbide semiconductor device according to any one of claims 1-3, characterized in that, The lower surface of the polysilicon region is lower than the lower surface of the P well region and higher than the lower surface of the gate oxide region.

8. The trench-type silicon carbide semiconductor device according to any one of claims 1-3, characterized in that, It also includes an interlayer dielectric layer, the lower surface of which covers the upper surface of the gate oxide region, and the upper surface of which is adjacent to the source metal layer.

9. The trench-type silicon carbide semiconductor device according to claim 1, characterized in that, The first doped active region is an N-type doped active region, and the second doped active region is an N+ type doped active region.

10. The trench-type silicon carbide semiconductor device according to any one of claims 1-3, characterized in that, It also includes the deep P+ region; The upper surface of the deep P+ region is in contact with the source metal layer, the lower surface of the deep P+ region is in contact with the epitaxial layer, and the side surface of the deep P+ region is in contact with the P well region, the first doped active region, the P-type high-resistivity region, and the second doped active region.

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