Semiconductor device

Abstract

Some embodiments of the present disclosure disclose a semiconductor device comprising a source region and a drain region in a substrate; a first gate structure disposed over a first channel region in the substrate and between the source region and the drain region, wherein the first gate structure comprises a first gate dielectric disposed over the first channel region and a first gate electrode disposed over the first gate dielectric; and a second gate structure disposed over a second channel region in the substrate and between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the source region and the second gate structure is disposed closer to the drain region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to high-voltage semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] According to some embodiments of this disclosure, a semiconductor device includes a first transistor. The first transistor includes a first source region and a drain region located in a substrate, a first gate structure disposed on a first channel region in the substrate and located between the first source region and the drain region, and a second gate structure disposed on a second channel region in the substrate and located between the first gate structure and the drain region. The first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric. The first gate structure is disposed closer to the first source region, and the second gate structure is disposed closer to the drain region.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a source region and a drain region located in a substrate, a first gate structure disposed on the substrate and located between the source region and the drain region, and a second gate structure disposed on the substrate and located between the source region and the drain region. The first gate structure is closer to the source region, and the second gate structure is closer to the drain region. The second gate structure has a first oxide layer, a trapping layer located above the first oxide layer and including a small bandgap material, and a second oxide layer located above the trapping layer.

[0006] In some embodiments, the technology described herein relates to a semiconductor device including a first transistor, the first transistor including a first source region and a drain region located in a substrate; a first gate structure disposed on a first channel region in the substrate and located between the first source region and the drain region, wherein the first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and a second gate structure disposed on a second channel region in the substrate and located between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the first source region and the second gate structure is disposed closer to the drain region. The second gate structure includes a tunneling oxide layer disposed on the second channel region, a trapping layer disposed on the tunneling oxide layer, and a control oxide layer disposed on the tunneling oxide layer, wherein the thickness of the control oxide layer is greater than the thickness of the tunneling oxide layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0009] Figure 1B This is a cross-sectional view of the control gate according to some embodiments;

[0010] Figure 1C This is a cross-sectional view of the control gate according to some embodiments;

[0011] Figure 1D This is a cross-sectional view of the modulation gate according to some embodiments;

[0012] Figure 1E This is a cross-sectional view of the modulation gate according to some embodiments;

[0013] Figure 1F This is a cross-sectional view of a high-voltage device according to some embodiments;

[0014] Figure 2A The cross-sectional view along the X-X' tangent 2 according to some embodiments illustrates the charge state of the modulation gate at the start of the conduction state of the high-voltage device;

[0015] Figure 2B The cross-sectional view along the X-X' tangent 2 according to some embodiments illustrates the charge state of the modulation gate during the conduction state of a high-voltage device after the carrier-filled electrons in the trapping layer;

[0016] Figure 2C The cross-sectional view along the X-X' tangent 2 according to some embodiments illustrates the charge state of the modulation gate during the off state of the high voltage device 100.

[0017] Figure 2D The cross-sectional view along the Y-Y' tangent 2 according to some embodiments illustrates the charge state of the modulation gate during the off-state of the high-voltage device.

[0018] Figure 3A This is a top view of an example semiconductor structure according to some embodiments, wherein the example semiconductor structure includes a plurality of gate structures connected in series between a source region and a drain region;

[0019] Figure 3B This is a flowchart depicting an example method of manufacturing a high-voltage device according to some embodiments, wherein the high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region.

[0020] Figure 4A The illustration shows that p-type metal-oxide-semiconductor high-voltage fin field-effect transistor devices according to some embodiments can benefit from high work function metals (Ψm≥5.0), such as Pt or Au;

[0021] Figure 4B The illustration shows that n-type metal-oxide-semiconductor high-voltage fin field-effect transistor devices according to some embodiments can benefit from low work function metals (Ψm≤4.1), such as Ti or Al;

[0022] Figure 4C A cross-sectional view of an example modulation gate during a shutdown state according to some embodiments;

[0023] Figure 4D A cross-sectional view of an example modulation gate during a shutdown state according to some embodiments;

[0024] Figure 5A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0025] Figure 5B This is a cross-sectional view of the depleted gate along the X-X' tangent 3 according to some embodiments;

[0026] Figure 5C This is a cross-sectional view of a high-voltage device along the fins between the control gate and the depletion gate according to some embodiments;

[0027] Figure 5DThis is a cross-sectional view of a high-voltage device along the fins between the control gate and the depletion gate according to some embodiments, wherein doping is implanted in the contact etch stop layer to extend the slightly doped depletion channel region, thereby resulting in a larger breakdown voltage;

[0028] Figure 5E It is a flowchart depicting an example method of manufacturing a high-voltage device according to some embodiments, wherein the high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region.

[0029] Figure 5F This is a cross-sectional view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0030] Figure 6A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0031] Figure 6B This is a cross-sectional view of the inverted depletion gate in the on state according to some embodiments, along the X-X' tangent 4;

[0032] Figure 6C and Figure 6D This is a cross-sectional view of the inverted depleted gate in the off state along the X-X' tangent 4 according to some embodiments;

[0033] Figure 6E It is a flowchart depicting an example method of manufacturing a high-voltage device according to some embodiments, wherein the high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region.

[0034] Figure 7A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0035] Figure 7B This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0036] Figure 7C This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0037] Figure 7D This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0038] Figure 7E This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0039] Figure 7F This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0040] Figure 8A This is a cross-sectional view of an example n-type metal-oxide-semiconductor high-voltage device according to some embodiments, wherein the example n-type metal-oxide-semiconductor high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0041] Figure 8B This is a cross-sectional view of an inverted depleted gate according to some embodiments;

[0042] Figure 8C This is a cross-sectional view of an example p-type metal-oxide-semiconductor high-voltage device according to some embodiments;

[0043] Figure 8D This is a cross-sectional view of an inverted depleted gate according to some embodiments;

[0044] Figure 8E This is a cross-sectional view of the depletion gate around the channel layer along the Y-Y' tangent of a high-voltage device according to some embodiments;

[0045] Figure 8F It is a graph illustrating the electrical properties of a depleted gate according to some embodiments;

[0046] Figure 9A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0047] Figure 9B This is a cross-sectional view of a high-voltage device according to some embodiments;

[0048] Figure 9C This is a cross-sectional view of a high-voltage device during the conduction state of current flowing through a metal wire, according to some embodiments;

[0049] Figure 9D This is another cross-sectional view of a high-voltage device during the on-state according to some embodiments;

[0050] Figure 9E This is another cross-sectional view of a high-voltage device during the on-state according to some embodiments;

[0051] Figure 9FThis is a cross-sectional view of another embodiment of a high-voltage device according to some embodiments;

[0052] Figure 10A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0053] Figure 10B This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0054] Figure 11A This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes a plurality of gate structures connected in series between a source region and a drain region;

[0055] Figure 11B This is a cross-sectional view of an example high-voltage device according to some embodiments;

[0056] Figure 11C This is a cross-sectional view of an example high-voltage device according to some embodiments;

[0057] Figure 12 This is a top view of an example semiconductor structure according to some embodiments, wherein the example semiconductor structure includes a plurality of gate structures connected in series between a source region and a drain region;

[0058] Figure 13A A cross-sectional view of a high-voltage device operating in the on-state according to some embodiments is shown.

[0059] Figure 13B A cross-sectional view of a high-voltage device operating in the off-state according to some embodiments is shown.

[0060] Figure 14A This is a flowchart of an example method for manufacturing a semiconductor device according to some embodiments;

[0061] Figure 14B This is a cross-sectional view of a semiconductor device in the manufacturing stage according to some embodiments.

[0062] [Symbol Explanation]

[0063] 100: High voltage device

[0064] 102:Substrate

[0065] 104: Source Region

[0066] 106: Drain region

[0067] 108: Fins

[0068] 110: Control gate

[0069] 112: Modulation gate

[0070] 114: Source terminal

[0071] 116: Leakage extremes

[0072] 118: Control gate terminal

[0073] 120: Modulation gate terminal

[0074] 122: Interface Layer

[0075] 124: High dielectric constant dielectric layer

[0076] 126: Metal gate material layer

[0077] 128: Contact Etching Stop Layer

[0078] 130: Interlayer dielectric layer

[0079] 132: Shallow trench isolation features

[0080] 134: Highly doped portion

[0081] 136: Tunneling oxide layer

[0082] 138: Capture Layer

[0083] 140: Control of oxide layer

[0084] 142: Metal gate material layer

[0085] 144: Contact Etching Stop Layer

[0086] 202: Carrier

[0087] 204: Current

[0088] 206: Electronics

[0089] 208: Exhausted Channel

[0090] 210: Electric field

[0091] 300: Semiconductor Structure

[0092] 302: First High Voltage Device

[0093] 304: Second High Voltage Device

[0094] 306: Drain region

[0095] 308: First Source Region

[0096] 310: Second source pole region

[0097] 312: Control gate

[0098] 314: Secondary gate

[0099] 330: Method

[0100] 332,334,336,338,340,342: Square

[0101] 402: Modulation gate

[0102] 404: Metal gate layer

[0103] 406: Capture Layer

[0104] 408: Exhaustion Zone

[0105] 412: Modulation gate

[0106] 414: Metal gate layer

[0107] 416: Capture Layer

[0108] 418: Exhaustion Zone

[0109] 500: High Voltage Device

[0110] 504: Source Region

[0111] 506: Drain region

[0112] 508: Fins

[0113] 510: Control gate

[0114] 512: Gate depletion

[0115] 514: Source terminal

[0116] 516: Leakage Extreme Particle

[0117] 518: Control gate terminal

[0118] 520: Depletion gate terminal

[0119] 522: Interlayer Capture Layer

[0120] 524: Tunneling oxide layer

[0121] 526: Slightly Doped Depleted Channel Region

[0122] 528: Highly doped portion

[0123] 530: Interface Layer

[0124] 531: High dielectric constant dielectric layer

[0125] 532: Shallow trench isolation features

[0126] 533: Metal gate material layer

[0127] 534: Contact Etching Stop Layer

[0128] 536: Contact Etching Stop Layer

[0129] 537: Contact Etching Stop Layer

[0130] 538: ILD0 layer

[0131] 550: Method

[0132] 552,554,556,558,560,562: Squares

[0133] 570: High Voltage Device

[0134] 572: Fins

[0135] 574: Highly doped portion

[0136] 576: Interface Layer

[0137] 578: Control Gate

[0138] 580: High dielectric constant dielectric layer

[0139] 582: Metal gate material layer

[0140] 584: Tunneling oxide layer

[0141] 586: Modulated Gate

[0142] 588: Capture Layer

[0143] 590: Control of oxide layer

[0144] 592: Metal gate material layer

[0145] 593: Slightly Doped Depleted Channel Region

[0146] 594: Contact Etching Stop Layer

[0147] 596: Contact Etching Stop Layer

[0148] 598: ILD0 layer

[0149] 600: High Voltage Device

[0150] 604: Source Region

[0151] 606: Drain region

[0152] 608: Fins

[0153] 610: Control gate

[0154] 612: Inversion Depletion Gate

[0155] 614: Source terminal

[0156] 616: Leakage extremes

[0157] 618: Control gate terminal

[0158] 620: Inverted gate terminal

[0159] 622: Polycrystalline silicon region

[0160] 624: Highly doped portion

[0161] 626: PN reverse junction

[0162] 628: Exhaustion Zone

[0163] 632: Shallow trench isolation features

[0164] 650: Method

[0165] 652, 654, 656, 658, 660, 662: Square

[0166] 700: High Voltage Device

[0167] 702: Control Gate

[0168] 704: Modulation Gate

[0169] 706: Source

[0170] 708: Drain

[0171] 720: High Voltage Device

[0172] 722: Control Gate

[0173] 724: Modulated Gate

[0174] 726: Source

[0175] 728: Drain

[0176] 740: High Voltage Device

[0177] 742: Control Gate

[0178] 744: Modulation Gate

[0179] 746: Source

[0180] 748: Drain

[0181] 760: High Voltage Device

[0182] 762: Control Gate

[0183] 764: Modulated gate

[0184] 765: Gate depletion

[0185] 766: Source Extreme

[0186] 768: Drain

[0187] 780: High Voltage Device

[0188] 782: Control Gate

[0189] 785: Gate Depletion

[0190] 786: Source

[0191] 788: Drain

[0192] 790: High Voltage Device

[0193] 792: Control Gate

[0194] 795: Gate depletion

[0195] 796: Source Extreme

[0196] 798: Drain

[0197] 800: High Voltage Device

[0198] 802: Fins

[0199] 804: Source Region

[0200] 806: Drain region

[0201] 808: Control Gate

[0202] 810: Inversion Depletion Gate

[0203] 812: n-type trap

[0204] 814: Source terminal

[0205] 816: Leakage Extreme Particle

[0206] 818: Control gate terminal

[0207] 820: Depletion gate terminal

[0208] 822: Gate spacer

[0209] 824: Gate spacer

[0210] 826: ILD0 layer

[0211] 828: ILD1 layer

[0212] 830: Interlayer Capture Layer

[0213] 832: PN reverse junction

[0214] 834: Electronics

[0215] 836: Direction

[0216] 850: High Voltage Device

[0217] 852: Fins

[0218] 854: Source Region

[0219] 856: Drain region

[0220] 858: Control Gate

[0221] 860: Inversion Depletion Gate

[0222] 862: p-type trap

[0223] 864: Source terminal

[0224] 866: Leakage Extreme Particle

[0225] 868: Control gate terminal

[0226] 870: Depletion gate terminal

[0227] 872: Gate spacer

[0228] 873: Channel Layer

[0229] 874: Gate spacer

[0230] 876: ILD0 layer

[0231] 878: ILD1 layer

[0232] 880: Interlayer Capture Layer

[0233] 882: PN reverse junction

[0234] 884: Hole

[0235] 886: Direction

[0236] 900: High Voltage Device

[0237] 902: Control Gate

[0238] 904: Modulation gate

[0239] 906: Source Region

[0240] 908: Drain region

[0241] 910: Source terminal

[0242] 912: Leakage Extreme

[0243] 914: Control gate terminal

[0244] 916: Modulation gate terminal

[0245] 918: Metal Wire

[0246] 920: First through hole

[0247] 922: Second through hole

[0248] 924: Magnetic Field

[0249] 926: Tangent

[0250] 928: Fin Structure

[0251] 930: Etching Stop Layer

[0252] 932: ILD0 layer

[0253] 934: ILD1 layer

[0254] 936: Metal Contact Etching Stop Layer

[0255] 938: ILD2 layer

[0256] 940: DC

[0257] 942: Current

[0258] 944: Electron Carrier

[0259] 946: Positive ion

[0260] 948: Electric Field

[0261] 950: Carrier Path

[0262] 952: Carrier Path

[0263] 954: Soft magnetic materials

[0264] 956: Deep p-type trap

[0265] 958:Substrate

[0266] 960: n-type trap

[0267] 1000: High voltage device

[0268] 1002: Control gate

[0269] 1004: Modulated gate

[0270] 1006: Source Region

[0271] 1008: Drain region

[0272] 1010: Source terminal

[0273] 1012: Leakage Extreme Particle

[0274] 1014: Control gate terminal

[0275] 1016: Modulation gate terminal

[0276] 1017: First Metal Wire

[0277] 1018: Second Metal Wire

[0278] 1019: Third Metal Wire

[0279] 1020: First through hole

[0280] 1021: First through hole

[0281] 1022: Second through hole

[0282] 1023: Second through hole

[0283] 1024: Magnetic Field

[0284] 1025: First through hole

[0285] 1027: Second through hole

[0286] 1028: Soft magnetic materials

[0287] 1050: High Voltage Device

[0288] 1052: Control Gate

[0289] 1054: Modulated gate

[0290] 1056: Source Region

[0291] 1058: Drain region

[0292] 1060: Source terminal

[0293] 1062: Leakage Extreme Particle

[0294] 1064: Control gate terminal

[0295] 1066: Modulation gate terminal

[0296] 1068: Metal Wire

[0297] 1070: First through hole

[0298] 1072: Second through hole

[0299] 1074: Magnetic Field

[0300] 1078: Soft magnetic materials

[0301] 1100: High Voltage Device

[0302] 1101:Substrate

[0303] 1102: Control gate

[0304] 1103: Tangent

[0305] 1104: Auxiliary gate

[0306] 1105: Dielectric Materials

[0307] 1106: Source Region

[0308] 1107: n-type trap

[0309] 1108: Drain region

[0310] 1110: Source terminal

[0311] 1112: Leakage Extreme Particle

[0312] 1114: Control gate terminal

[0313] 1118: Metal Wire

[0314] 1120: First through hole

[0315] 1122: Second through hole

[0316] 1123: Interlayer dielectric material layer

[0317] 1124: Magnetic Field

[0318] 1126: Magnetic Field

[0319] 1128: Soft magnetic materials

[0320] 1130: Carrier Path

[0321] 1132: Etching Stop Layer

[0322] 1134: ILD1 layer

[0323] 1136: Metal Contact Etching Stop Layer

[0324] 1138: ILD2 layer

[0325] 1140: Deep p-type well

[0326] 1200: Semiconductor Structure

[0327] 1202: First High Voltage Device

[0328] 1204: Second High Voltage Device

[0329] 1206: Drain region

[0330] 1208: First Source Region

[0331] 1210: Second source pole region

[0332] 1212: Control gate

[0333] 1214: Auxiliary gate

[0334] 1216: Metal wire

[0335] 1300: High Voltage Device

[0336] 1307: n-type trap

[0337] 1308: Drain region

[0338] 1330: Carrier Path

[0339] 1340: Deep p-type trap

[0340] 1342: Carrier

[0341] 1344: Exhaustion Zone

[0342] 1400: Method

[0343] 1402, 1404, 1406, 1408: Squares

[0344] 1410:Substrate

[0345] 1412: Oxide layer

[0346] 1414: Silicon nitride layer

[0347] 1416: Fins Detailed Implementation

[0348] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0349] For simplicity, this document may not describe in detail the known techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in semiconductor device manufacture are well-known; therefore, for simplicity, this document will only briefly mention many known processes, or omit them entirely without providing details of well-known processes. After a full reading of this disclosure, those skilled in the art will readily understand that the structures disclosed herein can be employed with a variety of techniques and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the illustrations may represent multiple components.

[0350] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “on top,” “upper,” “top,” “below,” “submerged,” “under,” “lower,” “bottom,” and similar terms are used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. When spatial relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on the other element, or there may be an intermediate element or layer present.

[0351] Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0352] It should be noted that references such as "an embodiment," "an example embodiment," "exemplary embodiment," "exemplary," and "example" in the specification indicate that the embodiment may include specific features, structures, or characteristics, but each embodiment does not necessarily include specific features, structures, or characteristics. Furthermore, such terms do not necessarily represent the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments falls within the knowledge of those skilled in the art.

[0353] It should be understood that the phrases or terms used herein are for descriptive rather than limiting purposes, and therefore the terms or phrases in this specification will be interpreted by those skilled in the art based on the teachings herein.

[0354] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Throughout the description herein, unless otherwise stated, the same reference numerals in different figures refer to the same or similar components formed using the same or similar materials(s) by the same or similar methods.

[0355] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or parts, which should not be limited by these terms. These terms may be used only to distinguish one element, component, area, layer, or part from another. Unless the context clearly indicates otherwise, the terms such as “first,” “second,” and “third” as used herein do not imply any order or sequence.

[0356] As used herein, the terms “approximately,” “substantially,” “substantial,” and “about” are used to describe and explain small errors. When used in conjunction with an event or situation, these terms can refer to the exact occurrence of the event or situation, or the situation being close to its occurrence. For example, when used in conjunction with a numerical value, these terms can represent a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered "substantially" the same or equal. For example, "substantially" parallel can mean an angular variation relative to 0° of less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to 0.05°. For example, “substantially” vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0357] Figure 1A This is a top view of an example high-voltage device 100 according to some embodiments, wherein the example high-voltage device 100 includes a plurality of gate structures connected in series between the source and drain regions. The example high-voltage device 100 is a high-voltage fin field-effect transistor (FinFET) device for many high-voltage applications such as amplifiers, including microwave power amplifiers, radio frequency power amplifiers, audio power amplifiers, and the like. The example high-voltage device 100 includes a control gate for turning the high-voltage FinFET device on or off, and a secondary gate for improving the high-voltage performance of the device. In this example, the secondary gate is a modulated gate.

[0358] An example high-voltage device 100 is formed on a substrate (e.g., a p-type substrate), wherein the example high-voltage device 100 includes a source region 104, a drain region 106, one or more fins 108 disposed between the source region 104 and the drain region 106, and shallow trench isolation features 132 for isolating various components. The high-voltage device 100 further includes a control gate 110 and a modulation gate 112, wherein the control gate 110 is disposed above and adjacent to the source region 104, the one or more fins 108 between the source region 104 and the drain region 106, and the modulation gate 112 is disposed above and adjacent to the drain region 106, the one or more fins 108 between the source region 104 and the drain region 106. The high-voltage device 100 also includes a source terminal 114 for the source region 104, a drain terminal 116 for the drain region 106, a control gate terminal 118 for the control gate 110, and a modulation gate terminal 120 for the modulation gate 112.

[0359] The modulation gate 112 has a heavily doped channel (not shown) and the following references Figure 1D and Figure 1E The special gate structure described. Using the modulation gate 112 allows for a shorter distance between the drain region 106 and the control gate 110 in high-voltage applications, thereby reducing the substrate area required to house the high-voltage device 100. Since the high-voltage device 100 includes both the control gate 110 and the modulation gate 112, the high-voltage device 100 includes a control channel (not shown) below the control gate 110 and a modulation channel (highly doped channel) below the modulation gate 112.

[0360] Figure 1B This is a cross-sectional view of the control gate 110 along the X-X' tangent 1. Figure 1C This is a cross-sectional view of the control gate 110 along the Y-Y' tangent 1. The illustrated example control gate 110 includes fins 108 disposed on a substrate 102 between shallow trench isolation features 132, an interface layer 122 (IL) disposed above the fins 108, a high-k (HK) dielectric layer 124 disposed above the interface layer 122, and a metal gate material layer 126 disposed above the high-k dielectric layer 124 and between a contact etch stop layer 128 (CESL) and an interlayer dielectric layer 130 (ILD) (ILD0). In various embodiments, the fins 108 comprise pure silicon (Si) or are lightly p-type doped. In various embodiments, the doping concentration of the lightly p-type doped fins is less than 5 × 10⁻⁶. 16 / cm 3 .

[0361] Figure 1D This is a cross-sectional view of the modulation gate 112 along the X-X' tangent 2. Figure 1E This is a cross-sectional view of the modulation gate 112 along the Y-Y' tangent 2. The illustrated example modulation gate 112 includes a fin 108 disposed on a substrate 102 between shallow trench isolation features 132 and including a highly doped portion 134, a tunneling oxide layer 136 disposed on the highly doped portion 134, a trapping layer 138 disposed on the tunneling oxide layer 136, a control oxide layer 140 disposed on the trapping layer 138, and a metal gate material layer 142 disposed on the control oxide layer 140 and between the contact etch stop layer 144 and the interlayer dielectric layer 130.

[0362] In various embodiments, the highly doped portion 134 comprises a highly doped n-type well (N+) region of a Si fin. In various embodiments, the control oxide layer 140 comprises a high-dielectric-constant oxide. In various embodiments, the tunneling oxide layer 136 comprises a thin SiO2 layer. In various embodiments, the doping concentration of the highly doped portion 134 is greater than 2 × 10⁻⁶. 18 / cm 3 In various embodiments, the thickness of the oxide layer 140 is greater than the thickness of the tunneling oxide layer 136. In various embodiments, the tunneling oxide layer 136 has a thickness greater than or equal to 8 angstroms. The thickness of ).

[0363] In various embodiments, the metal gate material layer 142 comprises a work function metal composition. In various embodiments, the work function metal composition comprises Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, Ti, Ta, Zr, and / or metal compounds / alloys (TiN, brass, phosphor bronze, cast steel, etc.). In various embodiments, the control oxide layer 140 comprises Si, Hf, La, Zr, Zn, Y, or the like. In various embodiments, the tunneling oxide layer 136 comprises Si, O, or the like. In various embodiments, the trapping layer 138 comprises Si, Ge, InSb, InAs, InP, N, Hf, Zr, Zn, Y, or the like. In various embodiments, the fin 108 comprises Si, C, N, Ge, Ga, Sb, In, As, P, Al, Sn, or the like.

[0364] Figure 1FThis is a cross-sectional view of the high-voltage device 100 along tangent 1 and tangent 2 of X-X', located between the two tangents. The figure depicts a fin 108 and a highly doped portion 134 of the fin 108, an interface layer 122 disposed on the fin 108 of the control gate 110, a high dielectric constant dielectric layer 124 disposed on the interface layer 122, a metal gate material layer 126 of the control gate 110 disposed on the high dielectric constant dielectric layer 124, a tunneling oxide layer 136 disposed on the highly doped portion 134 of the modulation gate 112, a trapping layer 138 disposed on the tunneling oxide layer 136, a control oxide layer 140 disposed on the trapping layer 138, and a metal gate material layer 142 of the modulation gate 112 disposed on the control oxide layer 140. Additionally, the accompanying drawings depict a contact etch stop layer 128 around the control gate 110, a contact etch stop layer 144 around the modulation gate 112, and an interlayer dielectric layer 130 disposed between the contact etch stop layer 128 and the contact etch stop layer 144 and on the highly doped portion 134 of the fin 108 between the control gate 110 and the modulation gate 112.

[0365] FinFET devices can have narrow channels and provide small junctions. These junctions can provide a depletion region within the channel due to the electric field from the drain. To reduce channel depletion, some high-voltage devices extend the distance between the gate and drain to reduce the electric field. Example high-voltage device 100 reduces the electric field by using a modulated gate. Using a modulated gate reduces the electric field during the off-state while reducing the extension distance between the gate and drain. Therefore, example high-voltage device 100 saves area or space on the substrate.

[0366] The modulation gate 112 is used to trap charge in the trap layer 138 during the on-state to reduce the depletion region during the off-state. The use of a highly doped portion 134 allows for a highly doped channel beneath the modulation gate 112, resulting in a highly doped channel providing lower resistance and thus increasing the on-current. During the off-state, the drain region 106 has a higher voltage and a stronger electric field than the source region 104, creating a depletion region in the channel region between the source and drain regions 104 and 106. During the off-state, charge in the trap layer 138 is released to the source side of the channel beneath the modulation gate 112 to reduce the electric field formed by the drain region 106 and reduce the channel depletion region.

[0367] Figure 2A This is a cross-sectional view along tangent 2 (X-X'), illustrating the charge state of the modulation gate 112 at the start of the conduction state of the high-voltage device 100. In the example embodiment, during the conduction state, the modulation gate 112 has a source voltage of approximately 0V and a voltage of approximately V. ddThe drain voltage and the gate voltage V are 0V. mg The trapping layer 138 is doped with multiple carriers 202. During this on-state, current 204 flows from the source to the drain, and some electrons 206 from the current are trapped by the multiple carriers 202 in the trapping layer 138. Figure 2B It is a cross-sectional view along the X-X' tangent 2, illustrating the charge state of the modulation gate 112 after the carrier 202 of the capture layer 138 is filled with electrons 206 during the conduction state of the high voltage device 100.

[0368] Figure 2C This is a cross-sectional view along the tangent line 2 of X-X'. Figure 2D This is a cross-sectional view along the tangent line 2 of Y-Y'. Figure 2C and Figure 2D The diagram illustrates the charge state of the modulation gate 112 during the off-state of the high-voltage device 100. In an example embodiment, during the off-state, the modulation gate 112 has a source voltage of approximately 0V and a voltage of approximately 0V. dd The drain voltage and the gate voltage V greater than 0V mg The current from the source to the drain stops, and due to the drain voltage V... dd The electric field forms a depletion channel 208. This is because the non-zero gate voltage V... mg An electric field 210 is formed in the metal gate material layer 142 by applying an electric field 210 to release electrons 206 to the source side of the channel region below the modulation gate 112, thereby reducing the electric field formed by the drain region 106 and reducing depletion of the channel 208. The modulation gate 112 provides inverse carriers to reduce channel depletion. The FinFET device within the 3-D structure provides better gate control, making it easier to drive electrons to tunnel into the channel below the modulation gate 112, thereby reducing depletion near the drain side.

[0369] Figure 3A This is a top view of an example semiconductor structure 300 according to some embodiments, wherein the example semiconductor structure 300 includes a plurality of gate structures connected in series between a source region and a drain region. The example semiconductor structure 300 illustrates a configuration with drain symmetry, wherein a first high-voltage device 302 and a second high-voltage device 304 share a drain region 306, the first high-voltage device 302 has a first source region 308, and the second high-voltage device 304 has a second source region 310. In this example, each of the first high-voltage device 302 and the second high-voltage device 304 includes a control gate 312 and a secondary gate 314. Since the two high-voltage devices share the drain region 306, a smaller surface area can be used to form them compared to two high-voltage devices that do not share a drain region.

[0370] Figure 3BThis is a flowchart depicting an example method 330 for manufacturing a high-voltage device according to some embodiments, wherein the high-voltage device includes multiple gate structures connected in series between the source and drain regions. It should be noted that method 330 may not produce a complete semiconductor device. Method 330 is merely an example and is not intended to limit this disclosure to the scope expressly referenced in the claims. Additional steps may be provided before, during, and after example method 330, and some described steps may be moved, substituted, or eliminated for additional embodiments of example method 330. Furthermore, it should be understood that a portion of the high-voltage device can be manufactured using typical semiconductor technology process flows; therefore, only some processes are briefly described herein.

[0371] At block 332, example method 330 includes forming fins on a substrate. In various embodiments, forming fins includes forming an epitaxial layer over the substrate and patterning the epitaxial layer to form semiconductor fins (also referred to as fins). The epitaxial layer can be formed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. Fins can be fabricated using suitable processes, including photolithography and etching processes.

[0372] At block 334, example method 330 includes forming a shallow trench isolation feature on a substrate. In various embodiments, forming the shallow trench isolation feature includes forming a shallow trench isolation feature between fins.

[0373] At block 336, example method 330 includes forming a dummy gate structure on the fin. In various embodiments, forming the dummy gate structure involves forming one or more sacrificial layers / features over the fin and patterning the one or more sacrificial layers or features to form a dummy gate on a channel region of the fin. When forming a dummy gate to become a modulation gate in a transistor, the formation steps include removing interlayer oxide (e.g., an interface layer) and depositing a tunneling oxide layer, a trapping layer, and a control oxide layer under the polysilicon used to form the dummy gate.

[0374] At block 338, example method 330 includes forming a source region and a drain region. In various embodiments, forming the source and drain regions involves forming gate sidewall spacers on the sidewalls of the dummy gate structure, recessing fins in the source / drain regions, and forming internal gate spacers prior to performing an epitaxial growth process to form the source and drain regions. In various embodiments, forming the source and drain regions also involves forming a contact etch stop layer and an interlayer dielectric layer around the source / drain regions.

[0375] At block 340, example method 330 includes replacing the dummy gate structure with the final gate structure. In the metal gate process of the control gate, this involves replacing the dummy gate structure with a high-dielectric-constant metal gate structure. In the capture gate process of the modulation gate, this involves retaining the tunneling oxide layer, the capture layer, and the control oxide layer, and replacing the dummy gate structure with a metal gate material layer.

[0376] At block 342, example method 330 includes performing further manufacturing steps. The semiconductor device may undergo further processing to form various features and regions known in the art.

[0377] Figure 4A A cross-sectional view of an example modulation gate 402 for a high-voltage FinFET device using a p-type metal oxide semiconductor (PMOS). Figure 4B A cross-sectional view depicting an example modulation gate 412 for a high-voltage FinFET device using an n-type metal oxide semiconductor (NMOS). Figure 4A In the example, during the on-state, the modulation gate 402 has a source voltage of approximately 0V and a drain voltage V less than or equal to 0V. dd and a gate voltage of approximately 0V V mg .exist Figure 4B In the example, during the on-state, the modulation gate 412 has a source voltage of approximately 0V and a drain voltage V greater than or equal to 0V. dd and a gate voltage of approximately 0V V mg . Figure 4A and Figure 4B The performance of a high-voltage FinFET device can be tuned based on the type of work function metal (WFM) used in the metal gate layer. Figure 4A In the example, the metal gate layer 404 includes a high work function metal (HWFM). Figure 4B In the example, the metal gate layer 414 includes a low work function metal (LWFM). The choice of work function metal can reduce the turn-on voltage. Figure 4A The illustration shows that high-voltage PMOS FinFET devices may benefit from high work function metals (Ψm ≥ 5.0), such as Pt or Au. Other high work function metals that can be used include Se, Ir, Ni, and Co. Figure 4BThe illustration shows that NMOS high-voltage FinFET devices may benefit from low work function metals (Ψm ≤ 4.1), such as Ti or Al. Other low work function metals that can be used include Rb, Tb, Sr, Nd, and Y.

[0378] Figure 4C A cross-sectional view of an example modulation gate 402 during the off-state is shown. Figure 4D A cross-sectional view depicting an example modulation gate 412 during the off-state. Figure 4C In the example, in the off state, the modulation gate 402 has a source voltage of approximately 0V and a drain voltage V less than or equal to 0V. dd and a gate voltage V less than or equal to 0V mg In the off state, the drain region has a higher voltage and a stronger electric field than the source region, creating a depletion region 408 in the channel region between the source and drain regions. During the off state, charges (e.g., holes) in the trapping layer 406 are released to the channel region below the modulation gate 402 to reduce the electric field and reduce the channel depletion region.

[0379] exist Figure 4D In the example, in the off state, the modulation gate 412 has a source voltage of approximately 0V, a drain voltage Vdd greater than or equal to 0V, and a gate voltage Vmg greater than or equal to 0V. In the off state, the drain region has a higher voltage and a stronger electric field than the source region, creating a depletion region 418 in the channel region between the source and drain regions. During the off state, charge (e.g., electrons) in the trapping layer 416 is released into the channel region below the modulation gate 412 to reduce the electric field formed by the drain region and reduce the channel depletion region.

[0380] Figure 5A This is a top view of an example high-voltage device 500 according to some embodiments, wherein the example high-voltage device 500 includes a plurality of gate structures connected in series between the source and drain regions. The example high-voltage device 500 is a high-voltage FinFET device for many high-voltage applications such as amplifiers, including microwave power amplifiers, radio frequency power amplifiers, and audio power amplifiers, and the like. The example high-voltage device 500 includes a control gate 510 for turning the high-voltage FinFET device on or off, and a secondary gate for improving the high-voltage performance of the device. In this example, the secondary gate is a depletion gate 512.

[0381] An example high-voltage device 500 is formed on a substrate (e.g., a p-type substrate) and includes a source region 504, a drain region 506, one or more fins 508 disposed between the source region 504 and the drain region 506, and shallow trench isolation features 532 for isolating various components. The high-voltage device 500 further includes a control gate 510 and a depletion gate 512. The control gate 510 is disposed above and adjacent to the source region 504, while the depletion gate 512 is disposed above and adjacent to the drain region 506. The high-voltage device 500 also includes a source terminal 514 for the source region 504, a drain terminal 516 for the drain region 506, a control gate terminal 518 for the control gate 510, and a depletion gate terminal 520 for the depletion gate 512.

[0382] In various embodiments, control gate 510 is similar to control gate 110 and includes similar components. In various embodiments, example control gate 510 includes a fin 508 disposed between shallow trench isolation features, an interface layer disposed over the fin structure, a high-k dielectric layer disposed over the interface layer, and a metal gate material layer disposed over the high-k dielectric layer and between the contact etch stop layer and the interlayer dielectric (ILD0). In various embodiments, the fin structure comprises pure silicon (Si) or lightly p-type doped. In various embodiments, the doping concentration of the lightly p-type doped fin is less than 5 x 10⁻⁶. 16 / cm 3 .

[0383] The depletion gate 512 has a lightly doped gate structure. Using the depletion gate 512 allows for a shorter distance between the drain region 506 and the control gate 510 in high-voltage applications, thereby reducing the substrate area required to house the high-voltage device 500. Because the high-voltage device 500 includes both the control gate 510 and the depletion gate 512, the high-voltage device 500 includes a control channel below the control gate 510 and a depletion channel below the depletion gate 512.

[0384] Figure 5B This is a cross-sectional view of the depletion gate 512 along tangent 3 (X-X'). The depletion gate 512 includes an interlayer trapping layer 522 containing polysilicon and lightly n-type doped with an n-type dopant (e.g., phosphorus for NMOS, boron for PMOS), a tunneling oxide layer 524 beneath the interlayer trapping layer 522, and a highly doped portion 528 of the fin 508. In various embodiments, the interlayer trapping layer 522 includes one or more of Si, C, N, Ge, Ga, Sb, In, As, or the like. In various embodiments, the interlayer trapping layer 522 comprises approximately 1 x 10⁻⁶. 16Up to approximately 5x10 19 / cm 3 The interlayer trapping layer 522 contains n-type dopants. The doping charge in this layer is used to move electrons from the channel surface into the substrate, thus making the slightly doped depletion channel region 526 slightly doped (N-). This slightly doped region allows for greater diffusion (the depletion region between N- and N+ is larger in the off-state), thereby increasing the breakdown voltage (BV). The depletion gate 512 has tunable charge injection based on the doping level of the interlayer trapping layer 522.

[0385] Figure 5C This is a cross-sectional view of the high-voltage device 500 along the fin 508 between the control gate 510 and the depletion gate 512. The figure depicts the fin 508 and the highly doped portion 528 of the fin 508, the interface layer 530 disposed on the fin 508 of the control gate 510, the high dielectric constant dielectric layer 531 disposed on the interface layer 530, the metal gate material layer 533 of the control gate 510 disposed on the high dielectric constant dielectric layer 531, the tunneling oxide layer 524 disposed on the lightly doped depletion channel region 526 of the depletion gate 512, and the interlayer trapping layer 522 disposed on the tunneling oxide layer 524. Additionally, the accompanying drawings depict a contact etch stop layer 534 around the control gate 510, a contact etch stop layer 536 around the depletion gate 512, and an ILD0 layer 538 disposed between the contact etch stop layer 534 and the contact etch stop layer 536 and on a highly doped portion 528 of the fin 508 between the control gate 510 and the depletion gate 512.

[0386] Figure 5DThis is a cross-sectional view of the high-voltage device 500 along the fin 508 between the control gate 510 and the depletion gate 512, wherein doping is implanted in the contact etch stop layer 537 (the material may be Si4N3) to extend the slightly doped depletion channel region 526 below the contact etch stop layer 537, thereby increasing the breakdown voltage. The figure depicts the fin 508 and the highly doped portion 528 of the fin 508, the interface layer 530 disposed on the fin 508 of the control gate 510, the high dielectric constant dielectric layer 531 disposed on the interface layer 530, the metal gate material layer 533 of the control gate 510 disposed on the high dielectric constant dielectric layer 531, the tunneling oxide layer 524 disposed on the slightly doped depletion channel region 526 of the modulation gate 112, and the interlayer trapping layer 522 disposed on the tunneling oxide layer 524. Additionally, the accompanying drawings depict a contact etch stop layer 534 around the control gate 510, a contact etch stop layer 537 around the depletion gate 512, and an ILD0 layer 538 disposed between the contact etch stop layer 534 and the contact etch stop layer 537 and on a highly doped portion 528 of the fin 508 between the control gate 510 and the depletion gate 512.

[0387] Figure 5E This is a flowchart describing an example method 550 for manufacturing a high-voltage device according to some embodiments, wherein the high-voltage device includes multiple gate structures connected in series between the source and drain regions. It should be noted that method 550 may not produce a complete semiconductor device. Method 550 is merely an example and is not intended to limit this disclosure to the scope expressly referenced in the claims. Additional steps may be provided before, during, and after example method 550, and some described steps may be moved, substituted, or eliminated for additional embodiments of example method 550. Furthermore, it should be understood that a portion of the high-voltage device can be manufactured using typical semiconductor technology process flows; therefore, only some processes are briefly described herein.

[0388] At block 552, example method 550 includes forming fins on a substrate. In various embodiments, forming fins includes forming an epitaxial layer over the substrate and patterning the epitaxial layer to form semiconductor fins (also referred to as fins). The epitaxial layer can be formed by molecular beam epitaxy, metal-organic chemical vapor deposition, and / or other suitable epitaxial growth processes. Fins can be manufactured using suitable processes, including photolithography and etching processes.

[0389] At block 554, example method 550 includes forming a shallow trench isolation feature on a substrate. In various embodiments, forming the shallow trench isolation feature includes forming a shallow trench isolation feature between fins.

[0390] At block 556, example method 550 includes forming a dummy gate structure on the fin. In various embodiments, forming the dummy gate structure involves forming one or more sacrificial layers / features over the fin and patterning the one or more sacrificial layers or features to form a dummy gate on a channel region of the fin. When forming a dummy gate to become a depletion gate in a transistor, the formation steps include removing interlayer oxide (e.g., an interface layer), depositing a tunneling oxide layer, forming a polysilicon structure for the dummy gate over the tunneling oxide layer, and doping the polysilicon structure. In various embodiments, the polysilicon structure is doped with an n-type dopant.

[0391] At block 558, example method 550 includes forming a source region and a drain region. In various embodiments, forming the source and drain regions involves forming gate sidewall spacers on the sidewalls of the dummy gate structure, recessing fins in the source / drain regions, and forming internal gate spacers prior to performing an epitaxial growth process to form the source and drain regions. In various embodiments, forming the source and drain regions also involves forming a contact etch stop layer and an interlayer dielectric layer around the source / drain regions.

[0392] At block 560, example method 550 includes replacing the dummy gate structure with the final gate structure. In a metal gate process for controlling the gate, this involves replacing the dummy gate structure with a high-dielectric-constant metal gate structure. In a trap gate process for depleted gates, this involves retaining the tunneling oxide layer and the doped polysilicon structure.

[0393] At block 562, example method 550 includes performing further manufacturing. The semiconductor device may undergo further processing to form various features and areas known in the art.

[0394] Figure 5F This is a cross-sectional view of an example high-voltage device 570 according to some embodiments (e.g., along...). Figure 1A (X-X' tangent 1 and X-X' tangent 2 and between them), wherein the example high-voltage device 570 includes a plurality of gate structures connected in series between the source region and the drain region. Figure 5F The diagram illustrates a slightly doped depletion channel region and an extension region of the slightly doped depletion channel region generated from the doped contact etch stop layer. The slightly doped depletion channel region and the extension region can be applied to high-voltage devices that include a depletion gate as a secondary gate.

[0395] The accompanying drawings depict a fin 572 and a highly doped portion 574 of the fin 572, an interface layer 576 disposed above the fin 572 of the control gate 578, a high-k dielectric layer 580 disposed above the interface layer 576, a metal gate material layer 582 of the control gate 578 disposed above the high-k dielectric layer 580, a tunneling oxide layer 584 disposed above the highly doped portion 574 of the modulation gate 586, a trapping layer 588 disposed above the tunneling oxide layer 584, a control oxide layer 590 disposed above the trapping layer 588, a metal gate material layer 592 of the modulation gate 586 disposed above the control oxide layer 590, and a slightly doped depletion channel region 593 below the tunneling oxide layer 584 and within the highly doped portion 574 of the fin 572. Doping can be used to make the slightly doped depletion channel region 593 slightly doped (N-). Slight doping increases diffusion, thereby increasing the breakdown voltage. Additionally, the accompanying drawings depict a contact etch stop layer 594 around the control gate 578, a contact etch stop layer 596 around the modulation gate 586, and an ILD0 layer 598 disposed between the contact etch stop layers 594 and 596 and above the highly doped portion 574 of the fin 572 between the control gate 578 and the modulation gate 586. With the implantation of doping in the contact etch stop layer 596, the slightly doped depletion channel region 593 below the contact etch stop layer 596 can extend to allow for a larger breakdown voltage of the high-voltage device 570.

[0396] Figure 6A This is a top view of an example high-voltage device 600 according to some embodiments, wherein the example high-voltage device 600 includes a plurality of gate structures connected in series between the source and drain regions. The example high-voltage device 600 is a high-voltage FinFET device for many high-voltage applications such as amplifiers, including microwave power amplifiers, radio frequency power amplifiers, and audio power amplifiers, and the like. The example high-voltage device 600 includes a control gate 610 for turning the high-voltage FinFET device on or off and a secondary gate for improving the high-voltage performance of the device. In this example, the secondary gate is an inversion depletion gate 612.

[0397] An example high-voltage device 600 is formed on a substrate (e.g., a p-type substrate) and includes a source region 604, a drain region 606, one or more fins 608 disposed between the source region 604 and the drain region 606, and shallow trench isolation features 632 for isolating various components. The high-voltage device 600 further includes a control gate 610 and an inversion depletion gate 612. The control gate 610 is disposed above and adjacent to the source region 604 of the one or more fins 608 between the source region 604 and the drain region 606, and the inversion depletion gate 612 is disposed above and adjacent to the drain region 606 of the one or more fins 608 between the source region 604 and the drain region 606. The high-voltage device 600 also includes a source terminal 614 for the source region 604, a drain terminal 616 for the drain region 606, a control gate terminal 618 for the control gate 610, and an inversion gate terminal 620 for the inversion depletion gate 612.

[0398] In various embodiments, control gate 610 is similar to control gate 110 and includes similar components. In various embodiments, example control gate 610 includes fins 608 disposed between shallow trench isolation features 632, an interface layer disposed over the fin structure, a high-k dielectric layer disposed over the interface layer, and a metal gate material layer disposed over the high-k dielectric layer and between the contact etch stop layer and the interlayer dielectric (ILD0). In various embodiments, the fin structure comprises pure silicon (Si) or lightly p-type doped. In various embodiments, the doping concentration of the lightly p-type doped fin is less than 5 x 10⁻⁶. 16 / cm 3 .

[0399] The inversion depletion gate 612 has a lightly doped structure. Using the inversion depletion gate 612 allows for a shorter distance between the drain region 606 and the control gate 610 in high-voltage applications, thereby reducing the substrate area required to house the high-voltage device 600. Because the high-voltage device 600 includes both the control gate 610 and the inversion depletion gate 612, it includes a control channel (not shown) below the control gate 610 and an inversion channel below the inversion depletion gate 612.

[0400] Figure 6B This is a cross-sectional view of the inverted depletion gate 612 in the on-state along the X-X' tangent 4. Figure 6C and Figure 6D This is a cross-sectional view of the inverted depletion gate 612 in the off state along the X-X' tangent 4. The inverted depletion gate 612 comprises p-type dopant (e.g., 5x10⁻⁶). 16The polysilicon region 622 is doped with an inversion depletion gate 612 which has no oxide layer beneath it, and the inversion depletion gate 612 includes a highly doped portion 624 in the channel region of the fin, wherein a PN reverse junction 626 is formed between the polysilicon region 622 and the highly doped portion 624. In various embodiments, the p-type dopant comprises approximately 1 x 102 16 / cm 3 Up to approximately 5x10 19 / cm 3 The PN reverse junction 626 creates a depletion region 628 in the channel region below the inverted depletion gate 612. In the off state, the depletion region 628 increases in size, as... Figure 6C and Figure 6D As shown. Drain voltage V dd The increase in voltage can further increase the size of the depletion region 628 by generating a larger electric field. The inverted depletion gate 612 has a voltage based on the drain voltage V. dd Tunable charge injection at the level of the target.

[0401] Figure 6E This is a flowchart depicting an example method 650 for manufacturing a high-voltage device according to some embodiments, wherein the high-voltage device includes multiple gate structures connected in series between the source and drain regions. It should be noted that method 650 may not produce a complete semiconductor device. Method 650 is merely an example and is not intended to limit this disclosure to the scope expressly referenced in the claims. Additional steps may be provided before, during, and after example method 650, and some described steps may be moved, substituted, or eliminated for additional embodiments of example method 650. Furthermore, it should be understood that a portion of the high-voltage device can be manufactured using typical semiconductor technology process flows; therefore, only some processes are briefly described herein.

[0402] At block 652, example method 650 includes forming fins on a substrate. In various embodiments, forming fins includes forming an epitaxial layer over the substrate and patterning the epitaxial layer to form semiconductor fins (also referred to as fins). The epitaxial layer can be formed by molecular beam epitaxy, metal-organic chemical vapor deposition, and / or other suitable epitaxial growth processes. Fins can be manufactured using suitable processes, including photolithography and etching processes.

[0403] At block 654, example method 650 includes forming a shallow trench isolation feature on a substrate. In various embodiments, forming the shallow trench isolation feature includes forming a shallow trench isolation feature between fins.

[0404] At block 656, example method 650 includes forming a dummy gate structure on the fin. In various embodiments, forming the dummy gate structure involves forming one or more sacrificial layers / features over the fin and patterning the one or more sacrificial layers or features to form a dummy gate on a channel region of the fin. When forming a dummy gate to become an inversion depletion gate in a transistor, the forming steps include removing interlayer oxides (e.g., interface layers), forming a polysilicon structure for the dummy gate without oxide layers, and doping the polysilicon structure. In various embodiments, the polysilicon structure is doped with a p-type dopant.

[0405] At block 658, example method 650 includes forming a source region and a drain region. In various embodiments, forming the source and drain regions includes forming gate sidewall spacers on the sidewalls of the dummy gate structure to recess the fins in the source / drain regions, and forming internal gate spacers prior to performing an epitaxial growth process to form the source and drain regions. In various embodiments, forming the source and drain regions further includes forming a contact etch stop layer and an interlayer dielectric layer around the source / drain regions.

[0406] At block 660, example method 650 includes replacing the dummy gate structure with the final gate structure. In a metal gate process for controlling the gate, this involves replacing the dummy gate structure with a high-dielectric-constant metal gate structure. In a trap gate process for an inversion depletion gate, this involves retaining the doped polysilicon structure without an oxide layer.

[0407] At block 662, example method 650 includes performing further manufacturing. The semiconductor device may undergo further processing to form various features and areas known in the art.

[0408] Figures 7A to 7F This is a top view of an example high-voltage device according to some embodiments, wherein the example high-voltage device includes multiple gate structures connected in series between the source and drain regions. In these examples, high-voltage devices with different numbers and / or relative sizes of control gates, modulation gates, and / or depletion gates are illustrated.

[0409] Figure 7A This is a top view of an example high-voltage device 700 according to some embodiments, wherein the example high-voltage device 700 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 700 includes a control gate 702, a modulation gate 704, a source 706, and a drain 708. In this example, the control gate 702 and the modulation gate 704 have the same width. In various embodiments, the width of the control gate 702 is 20 nanometers, and the width of the modulation gate 704 is 20 nanometers.

[0410] Figure 7BThis is a top view of an example high-voltage device 720 according to some embodiments, wherein the example high-voltage device 720 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 720 includes a control gate 722, a plurality of modulation gates 724, a source 726, and a drain 728. In this example, each of the control gate 722 and the modulation gates 724 has the same width. In various embodiments, the width of the control gate 722 is 20 nanometers, and the width of the modulation gates 724 is 20 nanometers.

[0411] Figure 7C This is a top view of an example high-voltage device 740 according to some embodiments, wherein the example high-voltage device 740 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 740 includes a control gate 742, a modulation gate 744, a source 746, and a drain 748. In this example, the width of the modulation gate 744 is greater than the width of the control gate 742. In various embodiments, the width of the modulation gate 744 can be up to 15 times the width of the control gate 742. In various embodiments, the width of the control gate 742 is 20 nanometers, and the width of the modulation gate 744 is 240 nanometers.

[0412] Figure 7D This is a top view of an example high-voltage device 760 according to some embodiments, wherein the example high-voltage device 760 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 760 includes a control gate 762, a modulation gate 764, a depletion gate 765, a source 766, and a drain 768. In this example, each of the control gate 762, modulation gate 764, and depletion gate 765 has the same width. In various embodiments, the width of the control gate 762 is 20 nanometers, the width of the modulation gate 764 is 20 nanometers, and the width of the depletion gate 765 is 20 nanometers.

[0413] Figure 7E This is a top view of an example high-voltage device 780 according to some embodiments, wherein the example high-voltage device 780 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 780 includes a control gate 782, a depletion gate 785, a source 786, and a drain 788. In this example, the width of the depletion gate 785 is greater than the width of the control gate 782. In various embodiments, the width of the depletion gate 785 can be up to 15 times the width of the control gate 782. In various embodiments, the width of the control gate 782 is 20 nanometers, and the width of the depletion gate 785 is 240 nanometers.

[0414] Figure 7FThis is a top view of an example high-voltage device 790 according to some embodiments, wherein the example high-voltage device 790 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 790 includes a control gate 792, a plurality of depletion gates 795, a source 796, and a drain 798. In this example, each of the control gate 792 and the depletion gates 795 has the same width. In various embodiments, the width of the control gate 792 is 20 nanometers, and the width of the plurality of depletion gates 795 is 20 nanometers.

[0415] Figure 8A This is a cross-sectional view of an example NMOS high-voltage device 800 according to some embodiments, wherein the example NMOS high-voltage device 800 includes a plurality of gate structures connected in series between a source region and a drain region. The NMOS high-voltage device 800 includes a fin 802 formed in a substrate (e.g., a p-type substrate) and includes a source region 804, a drain region 806, a control gate 808 disposed between the source region 804 and the drain region 806 and adjacent to the source region 804, an inversion depletion gate 810 disposed between the drain region 806 and the source region 804 and adjacent to the drain region 806, and an n-type well 812 formed between the end of the control gate 808 and the drain region 806 and below the inversion depletion gate 810. The NMOS high-voltage device 800 further includes a source terminal 814 for the source region 804, a drain terminal 816 for the drain region 806, a control gate terminal 818 for the control gate 808, and a depletion gate terminal 820 for the inversion depletion gate 810. The control gate 808 is defined by a gate spacer 822 (e.g., a contact etch stop layer), and the inversion depletion gate 810 is defined by a gate spacer 824. An ILD0 layer 826 surrounds the control gate 808, the inversion depletion gate 810, the gate spacer 822, and the gate spacer 824. An ILD1 layer 828 is disposed above the ILD0 layer 826. In operation, a ground voltage level is applied at the source terminal 814, and a voltage less than or equal to zero is applied at the depletion gate terminal 820. A control signal for turning the NMOS high-voltage device 800 on or off is applied at the control gate terminal 818, while the inversion depletion gate 810 is not switched.

[0416] Figure 8B This is a cross-sectional view of the inversion depletion gate 810. The inversion depletion gate 810 includes an interlayer trapping layer 830 of polysilicon material, wherein the polysilicon material is doped with approximately 1x10⁻⁶ ppm. 16 / cm 3 Up to approximately 5x10 19 / cm 3The material is p-type doped. An interlayer trapping layer 830 is disposed above the n-type well 812, and a PN reverse junction 832 is formed between the interlayer trapping layer 830 and the n-type well 812. During the conduction state of the inversion depletion gate 810, electrons 834 flow in the direction 836 from the source terminal 814 to the drain terminal 816, but do not flow through the PN reverse junction 832 to the interlayer trapping layer 830.

[0417] Figure 8C This is a cross-sectional view of an example PMOS high-voltage device 850. The PMOS high-voltage device 850 includes fins 852 formed in a substrate (e.g., a p-type substrate), and includes a source region 854, a drain region 856, a control gate 858 disposed between the source region 854 and the drain region 856 and adjacent to the source region 854, an inversion depletion gate 860 disposed between the source region 854 and the drain region 856 and adjacent to the drain region 856, and a p-type well 862 formed between the end of the control gate 858 and the drain region 856 and below the inversion depletion gate 860. The PMOS high-voltage device 850 further includes a source terminal 864 for the source region 854, a drain terminal 866 for the drain region 856, a control gate terminal 868 for the control gate 858, and a depletion gate terminal 870 for the inversion depletion gate 860. The control gate 858 is defined by gate spacer 872 (e.g., a contact etch stop layer), and the inversion depletion gate 860 is defined by gate spacer 874. An ILD0 layer 876 surrounds the control gate 858, the inversion depletion gate 860, gate spacer 872, and gate spacer 874. An ILD1 layer 878 is disposed above the ILD0 layer 876. In operation, a ground voltage level is applied at the source terminal 864, and a voltage greater than or equal to zero is applied at the depletion gate terminal 870. A control signal for turning the PMOS high-voltage device 850 on or off is applied at the control gate terminal 868, while the inversion depletion gate 860 is not switched.

[0418] Figure 8D This is a cross-sectional view of the inversion depletion gate 860. The inversion depletion gate 860 includes an interlayer trapping layer 880 made of polysilicon material, wherein the polysilicon material is doped with approximately 1x10⁻⁶ ppm. 16 / cm 3 Up to approximately 5x10 19 / cm 3 The material is n-type doped. An interlayer trapping layer 880 is disposed above the p-type well 862, and a PN reverse junction 882 is formed between the interlayer trapping layer 880 and the p-type well 862. During the conduction state of the inversion depletion gate 860, holes 884 flow in the direction 886 from the source terminal 864 to the drain terminal 866, but do not flow through the PN reverse junction 882 to the interlayer trapping layer 880.

[0419] Figure 8E This is a cross-sectional view of the inversion depletion gate 860 around channel layer 873 along the Y-Y' tangent of the high-voltage device. Figure 8F This is a diagram illustrating the electrical properties of the inverted depletion gate 860. In some embodiments, the channel layer 873 beneath the inverted depletion gate 860 may be formed of an intermediate bandgap material, such as Si, Ge, GaA, and the like. In an example embodiment, the depletion gate is formed of a wide bandgap material, such as SiC, GaN, and the like. By using a wide bandgap material for the channel layer 873, a four-aspect depletion can be achieved using the depletion gate structure, whereas only one-aspect depletion is achieved using an intermediate bandgap material. Wide bandgap materials increase the PN barrier, such as... Figure 8F As shown, this can provide better breakdown voltage performance for high-voltage devices.

[0420] Figure 9A This is a top view of an example high-voltage device 900 according to some embodiments, wherein the example high-voltage device 900 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 900 includes a control gate 902 (e.g., control gate 110), a modulation gate 904 (e.g., modulation gate 112), a source region 906, and a drain region 908. The control gate 902 and the modulation gate 904 are disposed between the source region 906 and the drain region 908, wherein the control gate 902 is disposed closer to the source region 906, and the modulation gate 904 is disposed closer to the drain region 908. The high-voltage device 900 also includes a source terminal 910 for the source region 906, a drain terminal 912 for the drain region 908, a control gate terminal 914 for the control gate 902, and a modulation gate terminal 916 for the modulation gate 904. Metal wire 918 is coupled to a first via 920 on the control gate 902 and a second via 922 on the modulation gate 904. Metal wire 918 is disposed on the channel region between the control gate 902 and the modulation gate 904. When a current is applied between the first via 920 and the second via 922, a magnetic field 924 is induced in the channel between the control gate 902 and the modulation gate 904.

[0421] Figure 9B It is a high voltage device 900. Figure 9AA cross-sectional view of tangent 926 is shown in the figure. An example high-voltage device 900 includes a fin structure 928, in which a source region 906 and a drain region 908 are disposed. A control gate 902 and a modulation gate 904 are disposed between the source region 906 and the drain region 908, wherein the control gate 902 is disposed closer to the source region 906 and the modulation gate 904 is disposed closer to the drain region 908. The figure also depicts a source terminal 910 for the source region 906 and a drain terminal 912 for the drain region 908. Metal line 918 is coupled to a first via 920 above the control gate 902 and to a second via 922 above the modulation gate 904. Metal line 918 is separated from the control gate 902 and the modulation gate 904 by an etch stop layer 930 (ESL), and is disposed on the channel region between the control gate 902 and the modulation gate 904. The high-voltage device 900 further includes an ILD0 layer 932, an ILD1 layer 934, a metal contact etch stop layer 936 (MESL), and an ILD2 layer 938. When the high-voltage device 900 is in the ON state, current flows at DC 940 between the source region 906 and the drain region 908.

[0422] Figure 9C This is a cross-sectional view of the high-voltage device 900 during the on-state, where current 942 flows through metal line 918. Reverse charge from control gate 902 causes electron carriers 944 to remain near the bottom surface of control gate 902 in the channel below control gate 902. Positive ions 946 in modulation gate 904 cause electron carriers 944 to remain near the bottom surface of modulation gate 904 in the channel below modulation gate 904. Current 942 induces an electric field 948 via metal line 918, which forces electron carriers 944 downwards and away from ILD0 layer 932.

[0423] Figure 9D This is another cross-sectional view of the high-voltage device 900 during the conduction state. This figure illustrates that the carrier path 950 can be longer due to the Lorentz force generated by the current 942 through the metal wire 918.

[0424] Figure 9E This is another cross-sectional view of the high-voltage device 900 during the conduction state. This figure illustrates that the carrier path 952 can be longer due to the Lorentz force generated by the current 942 via the metal line 918 and the magnetic field generated by the soft magnetic material 954 (e.g., Fe, Ni, Mo, Co, Zn or similar) formed in the ILD0 layer 932 between the control gate 902 and the modulation gate 904.

[0425] Figure 9F This is a cross-sectional view of another embodiment of the high-voltage device 900 along tangent 926. In this example, the high-voltage device 900 includes a reference... Figure 9A and Figure 9B The components described also include a deep p-type well 956 formed in a substrate 958 beneath the n-type well 960. The deep p-type well 956 provides a bottom boundary for carrier paths (e.g., carrier path 950 or carrier path 952) and forces the carrier paths to bend upwards in the drain region 908. Ordinary magnetoresistance (ORM) increases the electron path, resulting in a larger breakdown voltage for the high-voltage device 900. The reverse PN junction between the n-type well 960 and the deep p-type well 956 allows electrons to return to the N+ channel.

[0426] Figure 10A This is a top view of an example high-voltage device 1000 according to some embodiments, wherein the example high-voltage device 1000 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 1000 includes a control gate 1002, a modulation gate 1004, a source region 1006, and a drain region 1008. The control gate 1002 and the modulation gate 1004 are disposed between the source region 1006 and the drain region 1008, wherein the control gate 1002 is disposed closer to the source region 1006, and the modulation gate 1004 is disposed closer to the drain region 1008. The high-voltage device 1000 also includes a source terminal 1010 for the source region 1006, a drain terminal 1012 for the drain region 1008, a control gate terminal 1014 for the control gate 1002, and a modulation gate terminal 1016 for the modulation gate 1004. A first metal line 1017 is coupled to a first via 1020 on the control gate 1002 and a second via 1022 on the modulation gate 1004. A second metal line 1018 is coupled to another first via 1021 on the control gate 1002 and another second via 1023 on the modulation gate 1004. A third metal line 1019 is coupled to another first via 1025 on the control gate 1002 and another second via 1027 on the modulation gate 1004. The first metal line 1017, the second metal line 1018, and the third metal line 1019 are disposed on the channel region between the control gate 1002 and the modulation gate 1004. When a current is applied between the first through hole 1020 and the second through hole 1022, between the first through hole 1021 and the second through hole 1023, and between the first through hole 1025 and the second through hole 1027, a magnetic field 1024 is induced in the channel between the control gate 1002 and the modulation gate 1004.

[0427] Because of the contributions of multiple (three in this example) metal lines (e.g., first metal line 1017, second metal line 1018, and third metal line 1019) to the magnetic field 1024, the magnetic field 1024 is enhanced and can be stronger than the magnetic field 924. The magnetic field 1024 is further enhanced and becomes stronger by using a soft magnetic material 1028 (e.g., Fe, Ni, Mo, Co, Zn, or the like) included in the interlayer dielectric material between the control gate 1002 and the modulation gate 1004. The magnetic field 1024 allows for a longer carrier path between the control gate 1002 and the modulation gate 1004.

[0428] Figure 10B This is a top view of an example high-voltage device 1050 according to some embodiments, wherein the example high-voltage device 1050 includes a plurality of gate structures connected in series between a source region and a drain region. The example high-voltage device 1050 includes a control gate 1052, a modulation gate 1054, a source region 1056, and a drain region 1058. The control gate 1052 and the modulation gate 1054 are disposed between the source region 1056 and the drain region 1058, wherein the control gate 1052 is disposed closer to the source region 1056, and the modulation gate 1054 is disposed closer to the drain region 1058. The high-voltage device 1050 also includes a source terminal 1060 for the source region 1056, a drain terminal 1062 for the drain region 1058, a control gate terminal 1064 for the control gate 1052, and a modulation gate terminal 1066 for the modulation gate 1054. Metal line 1068 is coupled to a first via 1070 on the control gate 1052 and a second via 1072 on the modulation gate 1054. Metal line 1068 is disposed over the channel region between the control gate 1052 and the modulation gate 1054. Metal line 1068 is substantially wider than metal line 918 (e.g., more than 1.5 times wider). When a current is applied between the first via 1070 and the second via 1072, a magnetic field 1074 is induced in the channel between the control gate 1052 and the modulation gate 1054.

[0429] Because of the contribution of the width of the metal line 1068 to the magnetic field 1074, the magnetic field 1074 is enhanced and can be stronger than the magnetic field 924. The magnetic field 1074 is further enhanced and becomes stronger by using a soft magnetic material 1078 (e.g., Fe, Ni, Mo, Co, Zn, or the like) included in the interlayer dielectric material between the control gate 1052 and the modulation gate 1054. The magnetic field 1074 allows for a longer carrier path between the control gate 1052 and the modulation gate 1054.

[0430] Figure 11A This is a top view of an example high-voltage device 1100 according to some embodiments, wherein the example high-voltage device 1100 includes a plurality of gate structures connected in series between the source region and the drain region. Figure 11B This is a cross-sectional view along tangent 1103 of an example high-voltage device 1100 on a substrate 1101 (e.g., pure Si or slightly p-type doped). The example high-voltage device 1100 includes a control gate 1102, an auxiliary gate 1104, a source region 1106, and a drain region 1108. The auxiliary gate 1104 includes a soft magnetic material 1128 (e.g., Fe, Ni, Mo, Co, Zn, or the like) and a dielectric material 1105 disposed on an n-type well 1107 in the substrate 1101. The control gate 1102 and the auxiliary gate 1104 are disposed between the source region 1106 and the drain region 1108, wherein the control gate 1102 is disposed closer to the source region 1106, and the auxiliary gate 1104 is disposed closer to the drain region 1108. The high-voltage device 1100 also includes a source terminal 1110 for the source region 1106, a drain terminal 1112 for the drain region 1108, and a control gate terminal 1114 for the control gate 1102.

[0431] Metal line 1118 is coupled to a first via 1120 on the interlayer dielectric layer 1123 between the control gate 1102 and the auxiliary gate 1104, and to a second via 1122 on the auxiliary gate 1104. Metal line 1118 is disposed on the channel region between the control gate 1102 and the auxiliary gate 1104 (e.g., below the interlayer dielectric layer 1123), and also on the channel region below the auxiliary gate 1104. Metal line 1118 is separated from the interlayer dielectric layer 1123 and the auxiliary gate 1104 by an etch stop layer 1132. The high-voltage device 1100 further includes an ILD1 layer 1134, a metal contact etch stop layer 1136, and an ILD2 layer 1138.

[0432] When a current is applied between the first via 1120 and the second via 1122, a magnetic field 1124 is induced in the channel region between the control gate 1102 and the auxiliary gate 1104, and a magnetic field 1126 is induced in the channel region below the auxiliary gate 1104. Because a soft magnetic material 1128 (e.g., Fe, Ni, Mo, Co, Zn, or similar) is used, magnetic field 1126 is stronger than magnetic field 1124. Magnetic fields 1124 and 1126 make the carrier path 1130 between the ends of the control gate 1102 and the auxiliary gate 1104 longer.

[0433] Figure 11C This is a cross-sectional view of an example high-voltage device 1100 according to some embodiments, along tangent 1103. In this example, the high-voltage device 1100 includes a reference... Figure 11A and Figure 11BThe components described, but the high-voltage device 1100 also includes a deep p-type well 1140 formed in a substrate 1101 beneath the n-type well 1107. The deep p-type well 1140 provides a bottom boundary for the carrier path 1130 and forces the carrier path 1130 to bend upwards into the drain region 1108. Conventional magnetoresistance increases the length of the carrier path 1130, resulting in a larger breakdown voltage for the high-voltage device 900. The reverse PN junction between the n-type well 1107 and the deep p-type well 1140 returns the carrier path 1130 to the N+ channel.

[0434] Figure 12 This is a top view of an example semiconductor structure 1200 according to some embodiments, wherein the example semiconductor structure 1200 includes a plurality of gate structures connected in series between a source region and a drain region. The example semiconductor structure 1200 is illustrated in a configuration with drain symmetry, wherein a first high-voltage device 1202 and a second high-voltage device 1204 share a drain region 1206, and the first high-voltage device 1202 has a first source region 1208, and the second high-voltage device 1204 has a second source region 1210. In this example, each of the first high-voltage device 1202 and the second high-voltage device 1204 includes a control gate 1212 and an auxiliary gate 1214. A metal line 1216 is disposed over the channel region between the control gate 1212 and the auxiliary gate 1214. When current is applied to the metal line 1216, a magnetic field is induced in the channel between the control gate 1212 and the auxiliary gate 1214. This increases the current path in the channel region and increases the breakdown voltage of the first high-voltage device 1202 and the second high-voltage device 1204. By sharing the drain region 1206, the two high-voltage devices can be formed with a smaller surface area than two high-voltage devices that do not share a drain region.

[0435] Figure 13A This is a cross-sectional view of a high-voltage device 1300 according to some embodiments, wherein the high-voltage device 1300 includes a plurality of gate structures connected in series between the source region and the drain region. Figure 13A The diagram illustrates the on-state operation of the high-voltage device 1300. Figure 13B This is a cross-sectional view of the high-voltage device 1300 in its off-state operation. Figure 13A In the example, the deep p-type well 1340 formed of doped SiN has carriers 1342, forcing the carrier path 1330 to bend upwards into the drain region 1308. In various embodiments, the SiN is filled with a negative charge (e.g., electrons from the conduction current are captured by Si3N4). The negative electric field between the n-type well 1307 and the deep p-type well 1340 causes the carrier path 1330 to return to the N+ channel. Figure 13BIn the example, in the off state, the deep p-type well 1340 can reduce the size of the depletion region 1344 by injecting charge into the depletion region from the deep p-type well 1340.

[0436] Figure 14A This is a flowchart of an example method 1400 for manufacturing a semiconductor device according to some embodiments. For illustrative purposes, reference will be made to... Figure 14B describe Figure 14A The operation shown, Figure 14B Cross-sectional views of a semiconductor device in the manufacturing stage according to some embodiments are provided. It should be noted that method 1400 may not produce a complete semiconductor device. Method 1400 is merely an example and is not intended to limit this disclosure to the scope expressly referenced in the claims. Additional steps may be provided before, during, and after example method 1400, and some described steps may be moved, substituted, or eliminated for additional embodiments of example method 1400. Furthermore, it should be understood that a portion of a high-voltage device can be manufactured using typical semiconductor technology process flows; therefore, only some processes are briefly described herein.

[0437] At block 1402, example method 1400 includes providing a substrate. (Reference) Figure 14B For example, substrate 1410 is provided.

[0438] At block 1404, example method 1400 includes forming a deep p-type well in a substrate, which includes forming a pad (PAD) oxide layer and / or a self-aligned contact (SAC) oxide layer over the substrate, and forming a silicon nitride (SiN) layer over a portion of the substrate. Reference Figure 14B In one example, a PAD / SAC oxide layer 1412 is formed over a substrate 1410, and a silicon nitride layer 1414 is formed over the PAD / SAC oxide layer 1412.

[0439] At block 1406, example method 1400 includes forming one or more fins. (See reference) Figure 14B In the example, fin 1416 is formed on top of silicon nitride layer 1414.

[0440] According to some embodiments, at block 1408, example method 1400 includes forming a transistor device in a fin, the transistor device including a plurality of gate structures connected in series between a source region and a drain region. The transistor device includes a control gate and a secondary gate. In some embodiments, the secondary gate is a modulation gate. In some embodiments, the secondary gate is a depletion gate. In some embodiments, the secondary gate is an inversion depletion gate. In some embodiments, the secondary gate is an auxiliary gate made of a soft magnetic material. In various embodiments, forming the transistor device may be performed by any of method 330, method 550, method 650, or other methods.

[0441] The example high-voltage device has several designable features, including: (a) heavily doped fin channels and gate modulators; (b) adjustable features of the modulated gates; (c) tunable charge injection of the depleted gates; (d) the number of modulated gates; (e) the width of the modulated gates; and (f) magnetoresistive features through layout design.

[0442] In some embodiments, the technology described herein relates to a semiconductor device including a first transistor, the first transistor including a first source region and a drain region located in a substrate; a first gate structure disposed on a first channel region in the substrate and located between the first source region and the drain region, wherein the first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and a second gate structure disposed on a second channel region in the substrate and located between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the first source region and the second gate structure is disposed closer to the drain region.

[0443] In some embodiments, the technology described herein relates to a semiconductor device in which a second gate structure includes a tunneling oxide layer over a second channel region, a trapping layer over the tunneling oxide layer, a control oxide layer over the tunneling oxide layer, and a work function metal layer over the control oxide layer.

[0444] In some embodiments, the technology described herein relates to a semiconductor device in which the work function metal layer comprises one or more of Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, Ti, Ta, Zr, TiN, brass, phosphor bronze, or cast steel; the control oxide layer comprises one or more of Si, Hf, La, Zr, Zn, or Y; the trapping layer comprises one or more of Si, Ge, InSb, InAs, InP, N, Hf, Zr, Zn, or Y; and the tunneling oxide layer comprises one or more of Si or O.

[0445] In some embodiments, the technology described herein relates to a semiconductor device in which the thickness of the control oxide layer is greater than the thickness of the tunneling oxide layer, and the doping concentration of the second channel region is greater than the doping concentration of the first channel region.

[0446] In some cases, the technology described herein relates to a semiconductor device in which a first transistor has a first polarity type (e.g., NMOS) and a work function metal layer comprises a low work function metal.

[0447] In some cases, the technology described herein relates to a semiconductor device in which a first transistor has a second polarity type (e.g., PMOS) and a work function metal layer comprises a high work function metal.

[0448] In some embodiments, the technology described herein relates to a semiconductor device in which a second gate structure includes a tunneling oxide layer over a second channel region and a trapping layer over the tunneling oxide layer and including a polycrystalline silicon layer doped with negative ions.

[0449] In some embodiments, the technology described herein relates to a semiconductor device that further includes spacers defining sidewalls of a second gate structure, wherein the spacers are doped with negative ions.

[0450] In some embodiments, the technology described herein relates to a semiconductor device in which a second channel region includes an n-type well, a second gate structure includes a PN reverse junction over the second channel region, and a trapping layer over the PN reverse junction that includes a polysilicon layer doped with positive ions.

[0451] In some embodiments, the technology described herein relates to a semiconductor device, which further includes a second source region located in a substrate, wherein a drain region is located between a first source region and a second source region; and a second transistor. The second transistor includes a second source region and a drain region; a first gate structure disposed on a first channel region in the substrate and located between the second source region and the drain region, the first gate structure including a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and a second gate structure disposed on a second channel region in the substrate and located between the second source region and the drain region, wherein the first gate structure is disposed closer to the second source region and the second gate structure is disposed closer to the drain region, wherein the first transistor and the second transistor are electrically coupled to the drain region.

[0452] In some embodiments, the technology described herein relates to a method of forming a semiconductor device including the following steps: forming a deep p-type well in a substrate; forming a fin over the deep p-type well and the substrate; forming a transistor device in the fin, wherein the transistor device includes a source region and a drain region, a first gate structure disposed over a first channel region in the substrate and including a first gate dielectric and a first gate electrode disposed over the first gate dielectric, a second gate structure disposed over a second channel region in the substrate and located between the first gate structure and the drain region, an interlayer dielectric layer region located between the first gate structure and the second gate structure, and a metal layer located over the interlayer dielectric layer region, wherein the second channel region includes an n-type well, and wherein the second channel region is disposed over the deep p-type well.

[0453] In some embodiments, the techniques described herein relate to a method of forming a semiconductor device, wherein forming a deep p-type well includes forming an oxide layer over a substrate and forming a silicon nitride layer over the oxide layer.

[0454] In some cases, the techniques described herein relate to a method for forming a semiconductor device, the method further comprising forming a soft magnetic material in an interlayer dielectric layer region.

[0455] In some embodiments, the technology described herein relates to a method of forming a semiconductor device, the method further comprising extending a metal layer over a second gate structure and forming a soft magnetic material in the second gate structure.

[0456] In some embodiments, the technology described herein relates to a method of forming a semiconductor device, the method further comprising extending a metal layer over a second gate structure and forming a second gate structure, wherein the second gate structure has a first oxide layer, a trapping layer over the first oxide layer and including a small bandgap material, a second oxide layer over the trapping layer, and a work function metal layer over the second oxide layer.

[0457] In some embodiments, the technology described herein relates to a semiconductor device including a source region and a drain region located in a substrate, a first gate structure disposed above the substrate and between the source region and the drain region and closer to the source region, and a second gate structure disposed above the substrate and between the source region and the drain region and closer to the drain region, wherein the second gate structure has a first oxide layer, a trapping layer located above the first oxide layer and including a small bandgap material, and a second oxide layer located above the trapping layer.

[0458] In some cases, the technology described herein relates to a semiconductor device in which the width of the second gate structure is approximately equal to the width of the first gate structure.

[0459] In some cases, the technology described herein relates to a semiconductor device in which the width of the second gate structure is at least 1.5 to 15 times the width of the first gate structure.

[0460] In some embodiments, the technology described herein relates to a semiconductor device, which further includes a third gate structure having a first oxide layer, a trapping layer above the first oxide layer and including a small bandgap material, and a second oxide layer above the trapping layer. The third gate structure is disposed between a second gate structure and a drain region, and the width of the third gate structure is approximately equal to the width of the first gate structure and the width of the second gate structure.

[0461] In some embodiments, the technology described herein relates to a semiconductor device, which further includes a third gate structure having a doped polysilicon layer, the third gate structure being disposed between a second gate structure and a drain region, and the width of the third gate structure being approximately equal to the width of the first gate structure and the width of the second gate structure.

[0462] In some embodiments, the technology described herein relates to a semiconductor device including a first transistor, the first transistor including a first source region and a drain region located in a substrate; a first gate structure disposed on a first channel region in the substrate and located between the first source region and the drain region, wherein the first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and a second gate structure disposed on a second channel region in the substrate and located between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the first source region and the second gate structure is disposed closer to the drain region. The second gate structure includes a tunneling oxide layer disposed on the second channel region, a trapping layer disposed on the tunneling oxide layer, and a control oxide layer disposed on the tunneling oxide layer, wherein the thickness of the control oxide layer is greater than the thickness of the tunneling oxide layer.

[0463] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first transistor, comprising: A first source region and a drain region are located in a substrate; A first gate structure is disposed on a first channel region in the substrate and located between the first source region and the drain region, wherein the first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and A second gate structure is disposed on a second channel region in the substrate and located between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the first source region and the second gate structure is disposed closer to the drain region.

2. The semiconductor device as claimed in claim 1, characterized in that, The second gate structure includes a tunneling oxide layer on the second channel region, a capture layer on the tunneling oxide layer, a control oxide layer on the tunneling oxide layer, and a work function metal layer on the control oxide layer.

3. The semiconductor device as claimed in claim 1, characterized in that, The second gate structure includes a tunneling oxide layer located on the second channel region, and a trapping layer located on the tunneling oxide layer and including a polycrystalline silicon layer doped with multiple negative ions.

4. The semiconductor device as claimed in claim 1, characterized in that, The second channel region includes an n-type well, and the second gate structure includes a PN reverse junction located on the second channel region and a trapping layer located on the PN reverse junction and including a polysilicon layer doped with a plurality of positive ions.

5. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second source region is located in the substrate, wherein the drain region is located between the first source region and the second source region; and A second transistor, comprising: The second source region and the drain region; A first gate structure is disposed on a first channel region in the substrate and located between the second source region and the drain region, wherein the first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and A second gate structure is disposed on a second channel region in the substrate and located between the second source region and the drain region, wherein the first gate structure is disposed closer to the second source region and the second gate structure is disposed closer to the drain region. The first transistor and the second transistor are electrically coupled to the drain region.

6. A semiconductor device, characterized in that, include: A source region and a drain region are located in a substrate; A first gate structure is disposed on the substrate and located between the source region and the drain region, wherein the first gate structure is closer to the source region; and A second gate structure is disposed on the substrate and located between the source region and the drain region, wherein the second gate structure is closer to the drain region, and the second gate structure has a first oxide layer, a trapping layer above the first oxide layer, and a second oxide layer above the trapping layer.

7. The semiconductor device as claimed in claim 6, characterized in that, The width of the second gate structure is equal to the width of the first gate structure.

8. The semiconductor device as claimed in claim 6, characterized in that, The width of the second gate structure is at least 1.5 to 15 times the width of the first gate structure.

9. The semiconductor device as claimed in claim 6, characterized in that, Further includes: A third gate structure has a first oxide layer, a trapping layer above the first oxide layer, and a second oxide layer above the trapping layer. The third gate structure is disposed between the second gate structure and the drain region, and the width of the third gate structure is equal to the width of the first gate structure and the width of the second gate structure.

10. A semiconductor device, characterized in that, include: A first transistor, comprising: A first source region and a drain region are located in a substrate; A first gate structure is disposed on a first channel region in the substrate and located between the first source region and the drain region, wherein the first gate structure includes a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric; and A second gate structure is disposed on a second channel region in the substrate and located between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the first source region and the second gate structure is disposed closer to the drain region. The second gate structure includes a tunneling oxide layer on the second channel region, a trapping layer on the tunneling oxide layer, and a control oxide layer on the tunneling oxide layer, wherein the thickness of the control oxide layer is greater than the thickness of the tunneling oxide layer.

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