Semiconductor device structure

Abstract

A semiconductor device structure includes a first type of transistor (e.g., a p-type transistor) and a second type of transistor (e.g., an n-type transistor). The first type of transistor includes a first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer. The second type of transistor includes a second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer. The second insulating layer has a nitrogen concentration greater than a nitrogen concentration of the first insulating layer, and the second insulating layer has a thickness of at least 3 nm.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor device structures. Background Technology

[0002] Recently, multi-gate devices have been introduced to improve gate control. These devices have gates that extend partially or completely around a channel to provide a path to the channel on at least both sides. Exemplary multi-gate devices include fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors, such as nanowire transistors. Multi-gate devices can significantly miniaturize integrated circuit (IC) technology, maintain gate control, and mitigate short-channel effects (SCE), while seamlessly integrating with conventional IC manufacturing processes. As multi-gate devices continue to miniaturize, advanced technologies are needed to optimize their reliability and / or performance. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device structure to solve at least one of the above-mentioned problems.

[0004] In other embodiments, a semiconductor device structure is provided, the semiconductor device structure including a first type transistor including a first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer; and a second type transistor including a second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer, wherein the nitrogen concentration of the second insulating layer is greater than the nitrogen concentration of the first insulating layer, and wherein the thickness of the second insulating layer is at least 3 nm.

[0005] According to one embodiment of the present invention, the first source / drain structure further includes a third insulating layer, and the first doped epitaxial layer is disposed between the third insulating layer and the first insulating layer.

[0006] According to one embodiment of the present invention, the thickness of the third insulating layer is less than the thickness of the second insulating layer.

[0007] According to one embodiment of the present invention, a dielectric layer is further included, disposed above the first source / drain structure and the second source / drain structure.

[0008] According to one embodiment of the present invention, the dielectric layer contacts the third insulating layer.

[0009] According to one embodiment of the present invention, the dielectric layer contacts the second doped epitaxial layer of the second source / drain structure.

[0010] According to one embodiment of the present invention, the first source / drain structure and the second source / drain structure further include an undoped semiconductor layer, which is located below the first insulating layer and the second insulating layer.

[0011] According to one embodiment of the present invention, it further includes a substrate, wherein the first type transistor and the second type transistor are located on the substrate.

[0012] According to one embodiment of the present invention, the undoped semiconductor layer extends into the substrate.

[0013] According to one embodiment of the present invention, a portion of the first insulating layer and a portion of the second insulating layer extend into the undoped semiconductor layer. Attached Figure Description

[0014] The embodiments of this utility model can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0015] Figure 1 A flowchart illustrating a method for manufacturing part or all of a source / drain structure with bottom insulation, based on various aspects of embodiments of the present invention.

[0016] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I In accordance with various aspects of the embodiments of this utility model, Figure 1 A partial or complete cross-sectional schematic diagram of the apparatus for each manufacturing stage of the method.

[0017] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F In accordance with various aspects of the embodiments of this utility model, Figure 1 A partial or complete perspective view of the apparatus at each manufacturing stage of the method.

[0018] Figure 4Provided are partial or complete cross-sectional schematic diagrams of the source / drain structure having an untreated bottom insulating layer and a treated bottom insulating layer according to various embodiments of the present utility model.

[0019] The attached figures are labeled as follows: 10: Method 15,20,25,30,35,40,45,50,55,60,65,70: Squares 100: Device 105: Base 105', 105P': Base 102A, 102B: Device Area 110: Multi-layer stacked objects 115: Sacrificial Layer 120: Semiconductor layer 120': Channel layer 125: Substrate isolation structure 130A, 130B: Gate structure 132: Dummy gate stack 134: Gate spacer 136: Dummy gate 138: Hard mask 140, 140A, 140B: Source / Drain notches 145: Internal spacers 150, 150A, 150B: Source / Drain Structure 152: Undoped semiconductor layer 154A, 154B, 154A': Insulation layer 156A, 156B, 158A, 158B, 160A, 160B: Doped semiconductor layers 162,168: Mask 163,169: Opening 165, 170: Processing technology 175: Dielectric layer 180A, 180B: Gate stack 182A, 182B: Gate dielectric 184A, 184B: Gate electrode d,D: Depth h: height t1, t2, t3: Thickness W: Width Before Treatment: Untreated After treatment: Detailed Implementation

[0020] This invention relates generally to multi-gate devices and methods of manufacturing the same, and particularly to reducing leakage current in multi-gate devices.

[0021] It is important to understand that the following content provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, embodiments in which the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and embodiments in which additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, to facilitate the description of the relationship between one component and another in the drawings, spatially related terms such as "lower," "upper," "horizontal," "vertical," "above," "above," "below," "below," "top," "bottom," etc., and their derivative terms (e.g., "horizontally," "downward," "upward," etc.) are used. Spatially related terms are used to cover orientations different from those of the depicted device containing components. Furthermore, when using terms such as “about,” “approximately,” “roughly,” and similar terms to describe numbers or ranges of numbers, the purpose of these terms is to encompass numbers within a reasonable range that takes into account the variations inherent in manufacturing as understood by those skilled in the art. For example, a number or range of numbers encompasses a reasonable range including the described number, such as within + / -10% of the described number, based on known manufacturing tolerances associated with the features having characteristics related to the number. For example, a material layer having a thickness of “about 5 nm” can encompass a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -15%. Additionally, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0022] Multi-gate devices include gate structures that extend partially or completely around a channel region to provide paths to the channel region on at least two sides. One such multi-gate device is a gate-all-around (GAA) device, which includes vertically or horizontally stacked channel layers suspended in a manner above a substrate to allow the gate stack to wrap around (or surround) and engage the channel layers. The channel layers extend between a source region and a drain region (e.g., an epitaxial source / drain), and a voltage can be applied to the gate stack, the source region, and / or the drain region to control the current between the source and drain regions. GAA devices can significantly increase the contact area between the gate stack and the channel region, and have been observed to reduce subthreshold swing (SS), reduce short channel effects (SCEs), increase drive current, and / or improve channel control compared to other multi-gate devices (e.g., fin field-effect transistors).

[0023] However, with the miniaturization of integrated circuit (IC) technology nodes (i.e., by increasing device density (i.e., the number of interconnect devices in a given wafer area) and / or reducing geometry (i.e., the size and / or dimensions of device components and / or the spacing between them)), leakage current in fully wound gate devices has become a significant challenge. For example, parasitic transistors may form between the gate stack, the raised portion of the substrate (on which the channel layer and gate stack are disposed), and the epitaxial source / drain, and current may undesirably flow through / leak through the raised portion of the substrate between the epitaxial source / drain. Because the gate stack surrounds the raised portion of the substrate in a conventional fully wound gate device, rather than surrounding the substrate as in a channel layer, the gate stack's control over the off-state leakage current in the raised portion of the substrate is limited to three sides (e.g., tri-gate control). This has proven insufficient with the miniaturization of IC technology nodes and has been observed to induce and / or exacerbate drain voltage-induced barrier-lowering (DIBL) in fully wound gate devices.

[0024] This invention provides bottom isolation technology (also referred to as substrate isolation technology and / or pedestal isolation technology) to improve leakage current through an underlying substrate (e.g., a pedestal of the substrate), and passivation technology to reduce source / drain losses during the fabrication of source / drain structures for different types of transistors. The substrate isolation technology of this invention undergoes nitrogen thermal treatment to improve the quality of the bottom source / drain insulating layer, and the passivation technology of this invention undergoes nitrogen thermal treatment to improve the quality of the source / drain mask. A nitrogen-treated bottom source / drain insulating layer with a thickness of at least 3 nm and / or more uniform thickness is provided, as a thickness of at least 3 nm and / or more uniform thickness improves bottom source / drain isolation. The nitrogen-treated bottom source / drain insulating layer also exhibits a reduced etch rate to a given etchant, thereby reducing the removal of the bottom source / drain insulating layer during subsequent processing. Nitrogen-treated source / drain masks exhibit greater density and / or lower etch rates for a given etchant, thereby reducing the need for source / drain mask removal during subsequent processing. This improves protection for one type of source / drain structure while simultaneously forming another type of source / drain structure. In some embodiments, the substrate isolation technique of this invention further incorporates a silicon implantation process to improve the quality of the bottom source / drain insulating layer. A silicon-treated bottom source / drain insulating layer with greater thickness and / or lower etch rate can be provided. The bottom source / drain isolation and passivation processes of this invention are seamlessly and easily integrated into existing multi-gate device manufacturing processes. The bottom source / drain isolation and passivation techniques of this invention are further described below. As will be apparent from the following description, the multi-gate devices described in the embodiments of this invention offer advantages over conventional multi-gate devices. However, it is understood that other embodiments may offer additional advantages, and it is not necessary to mention all advantages herein, nor is any particular advantage required for any embodiment.

[0025] Figure 1This is a flowchart illustrating a method 10 for manufacturing a source / drain structure with bottom insulation, according to various embodiments of the present invention. In block 15, method 10 includes forming a first source / drain recess in a first device region and forming a second source / drain recess in a second device region. In some embodiments, the first device region is a p-type device region, and the second device region is an n-type device region. In block 20, method 10 includes forming a first undoped semiconductor layer in the first source / drain recess and forming a second undoped semiconductor layer in the second source / drain recess. The first and second undoped semiconductor layers may be formed simultaneously. In blocks 25, 30, and 35, method 10 includes forming a first mask over the second device region, forming a first insulating layer in the first source / drain recess above the first undoped semiconductor layer, forming a first doped semiconductor layer in the first source / drain recess above the first insulating layer, and removing the first mask. In some embodiments, the first doped semiconductor layer is a p-type doped semiconductor layer, such as a boron-doped silicon-germanium layer. In some embodiments, the first insulating layer is a nitride layer. In some embodiments, the processing associated with blocks 25, 30, 35 may be performed after the processing associated with blocks 40, 45, 50, 55, 60, 65, 70.

[0026] In blocks 40 and 45, method 10 includes forming a second insulating layer in a second source / drain recess above the second undoped semiconductor layer and performing a nitrogen thermal treatment on the second insulating layer. In some embodiments, the second insulating layer is a nitride layer, such as a silicon nitride layer. In some embodiments, the nitrogen thermal treatment is an annealing process performed in a nitrogen-containing environment, such as N2 annealing. In some embodiments, the nitrogen thermal treatment increases the thickness of the second insulating layer. In some embodiments, the nitrogen thermal treatment alters the composition of the second insulating layer, which may increase the resistance of the second insulating layer to a given etchant (e.g., by reducing the etch rate of the given etchant on the second insulating layer). In some embodiments, the first device region is masked when the second insulating layer is formed and / or when the second insulating layer is nitrogen thermally treated. In some embodiments, the first device region is not masked when the second insulating layer is formed and / or when the second insulating layer is nitrogen thermally treated, such that the second insulating layer can be formed above the first doped semiconductor layer. The thickness of the second insulating layer in the first device region may also be increased by the nitrogen thermal treatment. In some embodiments, method 10 may include performing a silicon implantation process on the second insulating layer before or after the nitrogen thermal treatment. In some embodiments, the silicon implantation process increases the thickness of the second insulating layer. In some embodiments, the silicon implantation process alters the composition of the second insulating layer, which can increase the resistance of the second insulating layer to a given etchant (e.g., by reducing the etch rate of the given etchant on the second insulating layer).

[0027] In blocks 50, 55, and 60, method 10 includes forming a second mask over the first device region and the second device region, removing the second mask from the second device region, and performing a nitrogen thermal treatment on the second mask. In some embodiments, the second mask is a metal oxide layer, such as an aluminum oxide layer. In some embodiments, the nitrogen thermal treatment is an annealing process performed in a nitrogen-containing environment, such as N2 annealing. In some embodiments, the nitrogen thermal treatment alters the composition of the second mask (e.g., the nitrogen thermal treatment can make the second mask denser), which can increase the resistance of the second mask to a given etchant (e.g., by reducing the etch rate of the given etchant on the second mask). In block 65, method 10 includes forming a second doped semiconductor layer in a second source / drain recess over the second insulating layer. In some embodiments, the second doped semiconductor layer is an n-type doped semiconductor layer, such as a phosphorus-doped silicon layer. In some embodiments, method 10 includes performing a pre-cleaning process before forming the second doped semiconductor layer over the second insulating layer. In block 70, method 10 includes removing the second mask from the first device region. Additional processing is considered in this embodiment of the invention. Additional steps may be provided before, during, and after method 10, and for additional embodiments of method 10, some described steps may be moved, substituted, or eliminated. The following discussion illustrates a device having a source / drain structure manufactured according to method 10.

[0028] Figures 2A to 2I In accordance with various aspects of the embodiments of this utility model, in conjunction with Figure 1 A partial or complete cross-sectional schematic diagram of the apparatus 100 associated with each manufacturing stage of method 10. Figures 3A to 3F In accordance with various aspects of the embodiments of this utility model, in conjunction with Figure 1 A partial or complete perspective view of the apparatus 100 associated with each manufacturing stage of method 10. Figure 3A correspond Figure 2C The manufacturing stage, in which Figure 2C along Figure 3A Lines 1-1' and 2-2' are cut to provide cross-sectional schematic diagrams of device area 102A and device area 102B, respectively. Figure 3B correspond Figure 2E The manufacturing stage, in which Figure 2E along Figure 3B Lines 1-1' and 2-2' are cut to provide cross-sectional schematic diagrams of device area 102A and device area 102B, respectively. Figure 3C correspond Figure 2F The manufacturing stage, in which Figure 2F along Figure 3C Lines 1-1' and 2-2' are cut to provide cross-sectional schematic diagrams of device area 102A and device area 102B, respectively. Figure 3D and Figure 3E correspond Figure 2G The manufacturing stage, in which Figure 2G along Figure 3E Lines 1-1' and 2-2' are cut to provide cross-sectional schematic diagrams of device area 102A and device area 102B, respectively. Figure 3F correspond Figure 2H The manufacturing stage, in which Figure 2H along Figure 3F Lines 1-1' and 2-2' are cut to provide cross-sectional schematic diagrams of device area 102A and device area 102B, respectively. Figure 4 This invention provides partial or complete cross-sectional schematic diagrams of source / drain structures with an untreated bottom insulating layer, and partial or complete cross-sectional schematic diagrams of source / drain structures with a treated bottom insulating layer (e.g., treated with nitrogen and / or silicon as described herein), according to various embodiments of the present invention. For ease of description and understanding... Figures 2A to 2I , Figures 3A to 3F and Figure 4 This article also discusses these topics. For clarity, [the following has been noted / explained]. Figures 2A to 2I , Figures 3A to 3F and Figure 4 The present invention has been simplified to better understand the concept of the embodiments thereof. Additional components may be added to the device 100, and in other embodiments of the device 100, some of the components described below may be replaced, modified, or eliminated.

[0029] After going through with Figures 2A to 2IFollowing associated processing, device 100 may include at least one fully wound gate transistor (i.e., a transistor having a gate that at least partially surrounds a suspended channel (e.g., nanowire, nanosheet, nanorod, or the like) extending between the source and drain). For example, device 100 may be processed to form a first transistor in device region 102A and a second transistor in device region 102B. In the illustrated embodiment, device 100 is processed to form an n-type transistor in device region 102A and a p-type transistor in device region 102B. In these embodiments, device 100 may include complementary metal-oxide-semiconductor (CMOS) transistors, such as n-type and p-type transistors. In some embodiments, both the first and second transistors are n-type transistors or both are p-type transistors. Device 100 may be included in a microprocessor, memory, other integrated circuit devices, or combinations thereof. In some embodiments, device 100 is part of an integrated circuit wafer, a system on chip (SoC), or a part of the foregoing, and device 100 may include various passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0030] Please refer to Figure 2AThe fabrication of device 100 may include forming and / or receiving a device precursor comprising a substrate 105, a multilayer stack 110 (including, for example, a base 105', a sacrificial layer 115, and a semiconductor layer 120), a substrate isolation structure 125, a gate structure 130A, and a gate structure 130B. In the illustrated embodiment, gate structure 130A and gate structure 130B each include a corresponding dummy gate stack 132 and a corresponding gate spacer 134, and each dummy gate stack 132 may include a corresponding dummy gate 136 and a corresponding hard mask 138. After forming and / or receiving the device precursor, the fabrication of device 100 may include forming a source / drain notch 140A in device region 102A and a source / drain notch 140B in device region 102B, as further described below. Before forming the source / drain notches 140A and 140B, the multilayer stack 110 extends generally continuously along the x-direction, has a length along the x-direction, a width along the y-direction, and a height along the z-direction. The multilayer stack 110 may be referred to as a fin, fin element, active fin region, active region, etc. In some embodiments, the base 105' is a patterned, protruding portion, and / or extension of the substrate 105, and the base 105' may be referred to as a substrate extension, substrate fin portion, fin portion, etched substrate portion, etc.

[0031] Substrate 105 comprises elemental semiconductors (e.g., silicon and / or germanium), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof), or combinations thereof. In some embodiments, substrate 105 is a silicon substrate. In some embodiments, substrate 105 is a semiconductor-on-insulator substrate, such as a semiconductor-on-silicon (SOI) substrate, a semiconductor-on-silicon germanium (SGOI) substrate, or a semiconductor-on-germanium (GOI) substrate. Substrate 105 (and pedestal 105') may comprise various doped regions, such as p-type doped regions (e.g., p-type wells), n-type doped regions (e.g., n-type wells), or combinations thereof. The n-type doped region contains an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped region contains a p-type dopant, such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped region contains both p-type and n-type dopants. The doped region may be formed on and / or in the substrate 105, for example, providing a p-type well structure, an n-type well structure, a dual-well structure, a lift structure, other suitable structures, or combinations thereof. In some embodiments, the substrate 105 and / or the pedestal 105' and the semiconductor layer thereon may contain n-type wells and / or p-type wells. For example, the pedestal 105' may contain a p-type well in device region 102A (e.g., an n-type transistor formed in a p-type well) and an n-type well in device region 102B (e.g., a p-type transistor formed in an n-type well), or vice versa.

[0032] The sacrificial layer 115 and the semiconductor layer 120 are vertically stacked from the top of the substrate 105 in an alternating and / or staggered configuration (e.g., along the z-direction). The composition of the sacrificial layer 115 differs from that of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial layer 115 and the semiconductor layer 120 may contain different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial layer 115 comprises silicon germanium, the semiconductor layer 120 comprises silicon, and for a given etchant, the etch rate of the semiconductor layer 120 differs from the etch rate of the sacrificial layer 115. In some embodiments, the sacrificial layer 115 and the semiconductor layer 120 may contain the same material but have different atomic percentages. For example, the sacrificial layer 115 and the semiconductor layer 120 may comprise silicon germanium, and the sacrificial layer 115 and the semiconductor layer 120 may have different percentages of germanium atoms to achieve etch selectivity. The sacrificial layer 115 and the semiconductor layer 120 may contain any combination of materials that provide desired etch selectivity, desired oxidation rate differences and / or desired performance characteristics (e.g., materials that maximize current), including any materials mentioned in the embodiments of the present invention.

[0033] Semiconductor layer 120 and a portion thereof may form channels for transistors in device 100. Figure 2A In this configuration, the multilayer stack 110 includes three sacrificial layers 115 and three semiconductor layers 120. Therefore, the multilayer stack 110 includes three pairs of semiconductor layers disposed over the substrate 105, each pair having a corresponding sacrificial layer 115 and a corresponding semiconductor layer 120. After processing of the multilayer stack 110, this configuration can form a transistor with three channels. However, in some embodiments, the multilayer stack 110 includes a different number of semiconductor layers 120, depending on, for example, the number of channels of the transistors in the desired device 100 and / or the design requirements of the device 100. For example, the multilayer stack 110 may include two to six pairs of semiconductor layers, each pair having a corresponding sacrificial layer 115 and a corresponding semiconductor layer 120.

[0034] The substrate isolation structure 125 may be formed adjacent to and surrounding the lower portion of the multilayer stack 110 (e.g., the base 105' of the multilayer stack 110), and the multilayer stack 110 may be separated from other multilayer stacks and / or other devices by the substrate isolation structure 125. The substrate isolation structure 125 may electrically isolate active device regions (e.g., multilayer stack 110) from other device regions (e.g., other multilayer stacks). The substrate isolation structure 125 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof) or combinations thereof. The substrate isolation structure 125 may have a multilayer structure. For example, the substrate isolation structure 125 may comprise a bulk dielectric (e.g., oxide layer) above a dielectric pad (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or combinations thereof). In another example, the substrate isolation structure 125 may comprise a bulk dielectric over a doped pad (e.g., a borosilicate glass (BSG) pad and / or a phosphosilicate glass (PSG) pad). The dimensions and / or characteristics of the substrate isolation structure 125 may be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof.

[0035] Gate structures 130A and 130B may be formed above the channel region (C) of the multilayer stack 110 and between the corresponding source / drain regions (S / D) of the multilayer stack 110. A dummy gate stack 132 extends longitudinally in a direction different from (e.g., perpendicular to) the longitudinal direction of the multilayer stack 110. For example, the dummy gate stack 132 extends in the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. The dummy gate stack 132 may extend substantially parallel to each other. Figure 2A In a cross-sectional view along the YZ plane, the dummy gate stack 132 is disposed on top of the corresponding channel region and between the corresponding source / drain regions. In a cross-sectional view along the YZ plane, the dummy gate stack 132 may surround the corresponding channel region (e.g., disposed on top of the channel region and above the sidewalls), and the dummy gate stack 132 may be disposed on top of the substrate isolation structure 125.

[0036] The dummy gate 136 may include a dummy gate dielectric and a dummy gate electrode. The dummy gate dielectric includes a dielectric material, such as silicon oxide and / or other suitable dielectric materials. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon. A hard mask 138 may be configured to protect the dummy gate 136 during processing. For example, the hard mask 138 may include a material resistant to etching processes (e.g., source / drain etching) to protect the dummy gate 136 from the etching process. In some embodiments, the hard mask 138 has a multilayer structure, such as a first mask layer disposed above a second mask layer. The hard mask 138 includes any suitable hard mask material.

[0037] Gate spacer 134 is formed adjacent to dummy gate stack 132 and extends along the sidewall of dummy gate stack 132. Gate spacer 134 comprises a dielectric material, which may comprise silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon carbide carbon oxide, silicon carbide nitride carbon oxide, or combinations thereof). In some embodiments, gate spacer 134 has a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, gate spacer 134 comprises more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, primary spacers, or combinations thereof. In some embodiments, the sets of spacers may have different compositions.

[0038] exist Figure 2AIn this process, source / drain etching removes portions of the multilayer stack 110 not covered by gate structures 130A and 130B, thereby forming source / drain notches 140A and 140B (collectively referred to as source / drain notches 140) (source / drain notches are sometimes also referred to as source / drain trenches). For example, source / drain etching removes the semiconductor layer 120 and sacrificial layer 115 in the source / drain region of the multilayer stack 110, thereby exposing the substrate 105'. Source / drain etching may further remove some, but not all, of the substrate 105' in the source / drain region of the multilayer stack 110, such that the source / drain notch 140 extends to the substrate 105', but does not extend through the substrate 105'. After source / drain etching, the sacrificial layer 115, the semiconductor layer 120, and the protrusion formed by the base 105' (hereinafter also referred to as base 105P') remain in the channel region of the multilayer stack 110, and the source / drain notch 140 exposes the sidewalls of the sacrificial layer 115, the semiconductor layer 120, and the base 105P' retained in the channel region. In the illustrated embodiment, the source / drain notch 140 extends through the multilayer stack 110 to a depth d in the base 105', has a depth D between the top of the multilayer stack 110 and the bottom of the source / drain notch 140, and has a width W. The depth D may be the sum of the height h of the multilayer stack 110 and the depth d of the source / drain notch 140.

[0039] Source / drain etching can be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, source / drain etching is a multi-step etching process that may use alternating etchants to remove the sacrificial layer 115 and the semiconductor layer 120 separately and alternately. In some embodiments, source / drain etching parameters (e.g., the etchant used in source / drain etching) are adjusted to selectively remove semiconductor materials (e.g., semiconductor layer 120, sacrificial layer 115, and substrate 105') while negligible (or even no) removal of dielectric materials (e.g., hard mask 138, gate spacer 134, substrate isolation structure 125, etc.).

[0040] Please refer to Figure 2B The internal spacer 145 may be formed along the sidewall of the sacrificial layer 115 below the gate spacer 134. The internal spacer 145 may replace the edge / end of the sacrificial layer 115 disposed below the gate spacer 134. In the illustrated embodiment, the remaining portion of the sacrificial layer 115 is disposed along the x-direction between the corresponding internal spacers 145, the top internal spacer 145 and the middle internal spacer 145 are disposed along the z-direction between the ends of the corresponding semiconductor layer 120, and the bottom internal spacer 145 is disposed along the z-direction between the end of the bottom semiconductor layer 120 and the base 105P'.

[0041] The steps of forming the internal spacer 145 may include a first etching process, a deposition process, and a second etching process. The first etching process may selectively etch the sacrificial layer 115 while ignoring (or even not etching) the semiconductor layer 120, the substrate 105P', the dummy gate stack 132 (e.g., a hard mask 138 of the dummy gate stack 132), the gate spacer 134, the substrate isolation structure 125, or a combination thereof. The first etching process may be configured to laterally etch (e.g., along the x-direction and / or y-direction) the sacrificial layer 115 to reduce the length of the sacrificial layer 115 along the x-direction, such that the length of the sacrificial layer 115 is less than the length of the semiconductor layer 120. The first etching process may form internal spacer notches between the semiconductor layers 120 and between the semiconductor layer 120 and the substrate 105P'. In some embodiments, the internal spacer notches extend laterally (e.g., along the x-direction) below the dummy gate stack 132. The first etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the first etching process is anisotropic etching.

[0042] A deposition process forms an internal spacer layer above device 100 that can fill internal spacer recesses. In some embodiments, a single deposition process is performed to form the internal spacer layer that fills the internal spacer recesses. In some embodiments, the internal spacer 145 has a multilayer structure. For example, more than one deposition process may be performed to form the internal spacer layer, such as a first deposition process forming a first internal spacer sublayer and a second deposition process forming a second internal spacer sublayer. The first internal spacer sublayer partially fills the internal spacer recesses, and the second internal spacer sublayer partially or completely fills the internal spacer recesses. The composition and / or material of the first internal spacer sublayer may be the same as or different from the composition and / or material of the second internal spacer sublayer. In some embodiments, the internal spacer 145 includes air gaps (voids).

[0043] The second etching process selectively etches the internal spacer layer while ignoring (or even not etching) the semiconductor layer 120, substrate 105P', dummy gate stack 132 (e.g., a hard mask 138 of the dummy gate stack 132), gate spacer 134, substrate isolation structure 125, or combinations thereof. The remaining portion of the internal spacer layer provides internal spacer 145, as shown. To achieve the desired etching selectivity, the internal spacer layer (and consequently the internal spacer 145) has a composition different from that of the semiconductor layer 120, substrate 105P', dummy gate stack 132, gate spacer 134, substrate isolation structure 125, or combinations thereof. In some embodiments, the internal spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof. For example, the internal spacer layer may be a silicon carbide layer, a silicon nitride layer, a silicon nitride oxide layer, a silicon carbide layer, or combinations thereof. The second etching process is dry etching, wet etching, other suitable etching, or combinations thereof.

[0044] Please refer to Figures 2B to 2H A source / drain structure 150A is formed in a source / drain recess 140A, and a source / drain structure 150B is formed in a source / drain recess 140B. The source / drain structures 150A and 150B herein are collectively referred to as source / drain structure 150. Source / drain structure 150A may include a corresponding undoped semiconductor layer 152, a corresponding insulating layer 154A, and a corresponding doped semiconductor layer 156A. In some embodiments, the doped semiconductor layer 156A has a multilayer structure, such as doped semiconductor layer 158A and doped semiconductor layer 160A. Source / drain structure 150B may include a corresponding undoped semiconductor layer 152, a corresponding insulating layer 154B, and a corresponding doped semiconductor layer 156B. In some embodiments, the doped semiconductor layer 156B has a multilayer structure, such as doped semiconductor layer 158B and doped semiconductor layer 160B. In the illustrated embodiment, device region 102A is an n-type transistor region and device region 102B is a p-type transistor region. Source / drain structure 150A forms the source / drain of the n-type transistor, and source / drain structure 150B forms the source / drain of the p-type transistor. In these embodiments, source / drain structure 150A may comprise a semiconductor material doped with an n-type dopant (e.g., carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof), while source / drain structure 150B may comprise a semiconductor material doped with a p-type dopant (e.g., boron, gallium, other p-type dopants, or combinations thereof). As described in more detail below, the source / drain structure fabrication process described herein incorporates processing techniques, such as nitrogen thermal treatment (e.g., nitrogen-containing annealing), to improve bottom source / drain insulation, thereby reducing leakage current, and / or to improve passivation during source / drain patterning, thereby reducing unwanted losses in the source / drain structure.

[0045] Please refer to this again. Figure 2B An undoped semiconductor layer 152 may be formed in source / drain recess 140A (e.g., at the bottom of source / drain recess 140A) and source / drain recess 140B (e.g., at the bottom of source / drain recess 140B). In the illustrated embodiment, the undoped semiconductor layer 152 is formed simultaneously in device region 102A and device region 102B. In some embodiments, the undoped semiconductor layer 152 is formed in device region 102A before or after the formation of device region 102B. The undoped semiconductor layer 152 is free of dopants (i.e., substantially free of n-type and p-type dopants). For example, no deliberate doping is performed when forming the undoped semiconductor layer 152. The undoped semiconductor layer 152 may provide a high-resistance path at the bottom of the source / drain recess 140, thereby suppressing leakage current into the substrate 105. The undoped semiconductor layer 152 comprises silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is a doped silicon layer or a doped silicon-germanium layer. In some embodiments, it has a dopant concentration of less than about 5 x 10⁻⁶. 18 cm -3 (e.g., approximately 1 x 10) 18 cm -3 To approximately 5 x 10 18 cm -3 Semiconductor materials that are undoped and / or unintentionally doped (UID) are considered to be undoped and / or unintentionally doped.

[0046] An undoped semiconductor layer 152 is disposed on a substrate 105P' and / or substrate 105'. In the illustrated embodiment, the undoped semiconductor layer 152 has a recessed top surface (e.g., a concave and / or trench-shaped top surface), and at least a portion of the thickness of the undoped semiconductor layer 152 (e.g., the central portion of the undoped semiconductor layer 152) is less than the height of the substrate 105P', such that the source / drain recess 140 still extends to a certain depth in the substrate 105P'. This depth can be determined by the difference between the initial depth d of the source / drain recess 140 and the minimum thickness of the undoped semiconductor layer 152. Furthermore, in the illustrated embodiment, the undoped semiconductor layer 152 has a thickness less than or equal to the height of the substrate 105P', but greater than the minimum thickness at the edge / end portions. In these embodiments, the undoped semiconductor layer 152 may not extend above the top of the substrate 105P'. In some embodiments, the thickness of the edge / end portions of the undoped semiconductor layer 152 is the maximum thickness of the undoped semiconductor layer 152. This document considers embodiments in which the undoped semiconductor layer 152 completely fills the bottom of the source / drain recess 140 and / or the undoped semiconductor layer 152 extends over the top of the base 105P'.

[0047] The undoped semiconductor layer 152 may be deposited on and / or grown from the substrate 105, substrate 105', substrate 105P', or a combination thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a selective epitaxial growth (SEG) process, which selectively deposits / grows a semiconductor material (e.g., silicon) on or from an exposed top surface. In these embodiments, the undoped semiconductor layer 152 may be referred to as an undoped epitaxial layer. Selective epitaxial growth processes may employ chemical vapor deposition (CVD) techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or similar methods), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a bottom-up deposition process (which may be a selective epitaxial growth process) such that semiconductor material is deposited on the substrate 105P', the substrate 105', and / or the base 105 (i.e., deposited in the bottom of the source / drain recess 140), while minimizing (or even eliminating) the deposition of semiconductor material on the semiconductor layer 120. In some embodiments, an etching process may be performed after the bottom-up deposition process to remove any semiconductor material formed on the semiconductor layer 120. This post-deposition etching can be dry etching, wet etching, other suitable etching, or a combination thereof.

[0048] Please refer to Figure 2CFabrication of device 100 may include forming a mask 162 that covers device region 102A (e.g., an n-type transistor region) but does not cover device region 102B (e.g., a p-type transistor region), and forming an additional layer of source / drain structure 150B in device region 102B. For example, mask 162 has an opening 163 therein that overlaps with device region 102B. In some embodiments, mask 162 is formed by depositing a hard mask material over device regions 102A and 102B and performing a patterning process to remove the hard mask material from device region 102B, thereby exposing source / drain notches 140B. The patterning process may include performing a photolithography process to form a patterned photoresist layer that covers the hard mask material above device region 102A and exposes the hard mask material above device region 102B (e.g., the patterned photoresist layer has an opening therein that overlaps with device region 102B), and performing an etching process to selectively remove the exposed hard mask material. The composition of mask 162 differs from that of source / drain structure 150A (e.g., the undoped semiconductor layer 152 of source / drain structure 150A), semiconductor layer 120, gate structure 130A, gate structure 130B, internal spacer 145, or a combination thereof, to achieve selective removal / etching therebetween. In some embodiments, mask 162 comprises metal and oxygen and / or nitrogen (e.g., mask 162 is a metal oxide mask and / or a metal nitride mask). For example, mask 162 may contain aluminum and oxygen and / or nitrogen, and mask 162 may be an aluminum oxide mask, an aluminum oxynitride mask, an aluminum nitride mask, or a combination thereof. In some embodiments, mask 162 is a patterned photoresist layer.

[0049] An insulating layer 154B may be formed in the source / drain recess 140B above the undoped semiconductor layer 152, while a mask 162 covers the device region 102A. The insulating layer 154B partially fills the source / drain recess 140B, and the insulating layer 154B may be disposed on the bottommost inner spacer 145 and / or the base 105P'. In some embodiments, the insulating layer 154B fills the remaining portion of the bottom of the source / drain recess 140B, and the insulating layer 154B is at least partially disposed above the top of the base 105P'. The insulating layer 154B comprises an electrically insulating material, such as a dielectric material, which reduces unwanted leakage currents, such as currents that may undesirably flow between the doped semiconductor layers 156B through the base 105P'. In some embodiments, insulating layer 154B comprises a dielectric material including silicon, such as silicon nitride, silicon oxynitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbide, other dielectric materials including silicon (which may comprise silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof) or combinations thereof. In some embodiments, insulating layer 154B comprises a dielectric material including metal, such as a metal oxide material and / or a metal nitride material. In some embodiments, insulating layer 154B comprises a doped semiconductor material comprising a dopant of the same type as that of doped semiconductor layer 156B. For example, in the illustrated embodiment, where doped semiconductor layer 156B is part of the source / drain of a p-type transistor (e.g., a p-type doped semiconductor layer), insulating layer 154B may comprise an n-type doped semiconductor material, such as phosphorus-doped silicon.

[0050] The insulating layer 154B can be formed by depositing and etching an insulating material over the device 100, such that the remaining portion of the insulating material fills the bottom of the source / drain recess 140B. The deposited insulating material can be disposed on the top of the gate structure 130B (e.g., the top of the gate spacer 134 and the dummy gate stack 132), the sidewalls of the gate structure 130B (e.g., the sidewalls of the gate spacer 134), the sidewalls of the semiconductor layer 120, the sidewalls of the internal spacer 145, the sidewalls of the base 105P', and the top of the base 105' in the source / drain region. In some embodiments, due to the nature of the deposition process (e.g., physical vapor deposition, PVD), the thickness of the insulating material above horizontally oriented surfaces (e.g., the top of the undoped semiconductor layer 152 in the source / drain regions and the top of the gate structure 130B) can be greater than the thickness of the insulating material above vertically oriented surfaces (e.g., the sidewalls of the gate structure 130B, the sidewalls of the semiconductor layer 120, and the sidewalls of the internal spacer 145). Therefore, etching parameters can be adjusted to remove vertically oriented portions of the insulating material, such as those on the sidewalls of the gate structure 130B, the semiconductor layer 120, and the internal spacer 145. In these embodiments, due to the etch load effect, etching may also remove horizontally oriented portions of the insulating material on top of the gate structure 130B, but without removing (or minimizing removal) horizontally oriented and / or vertically oriented portions of the insulating material at the bottom of the source / drain recess 140B, such as portions disposed on the undoped semiconductor layer 152 (i.e., the etching process may thin these, but substantially not remove these portions). In some embodiments, the deposited insulating material fills the source / drain recess 140B, and etching recesses the insulating material into at least the bottom sacrificial layer 115 and / or the bottom internal spacer 145. This etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0051] A doped semiconductor layer 156B may also be formed in the source / drain recess 140B above the insulating layer 154B and / or the undoped semiconductor layer 152, while the mask 162 covers the device region 102A. The doped semiconductor layer 156B fills the remaining portion of the source / drain recess 140B and is coupled to the edge / end portion of the semiconductor layer in the device region 102B. In the illustrated embodiment, the doped semiconductor layer 156B includes a doped semiconductor layer 158B and a doped semiconductor layer 160B. The doped semiconductor layer 158B may be formed above the semiconductor layer 120 (e.g., above the sidewalls and / or ends of the semiconductor layer 120) and partially fills the source / drain recess 140B, and the doped semiconductor layer 160B may be formed above the doped semiconductor layer 158B and / or the insulating layer 154B and fill the remaining portion of the source / drain recess 140B. A doped semiconductor layer 160B is separated from semiconductor layer 120 by a doped semiconductor layer 158B, and is separated from undoped semiconductor layer 152 by an insulating layer 154B. In the illustrated embodiment, the doped semiconductor layer 158B is discontinuous and formed by discrete and spaced portions, each doped semiconductor layer 158B being disposed at the end of a corresponding semiconductor layer 120, i.e., portions of the doped semiconductor layers 158B disposed on adjacent semiconductor layers 120 are not connected to each other. In these embodiments, the doped semiconductor layer 160B may surround the doped semiconductor layer 158B, and the doped semiconductor layer 160B may extend to the inner spacer 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158B may surround semiconductor layer 120, such that the discrete and spaced portions are formed above the top and / or bottom of the corresponding semiconductor layer 120. In some embodiments, the discrete and spaced portions extend above and / or to the inner spacer 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158B are connected. In these embodiments, the doped semiconductor layers 158B may form sidewalls of the source / drain structure 150B above the base 105P'. Furthermore, in these embodiments, the doped semiconductor layer 160B may be spaced from the internal spacer 145 by the doped semiconductor layers 158B.

[0052] Doped semiconductor layer 158B and doped semiconductor layer 160B comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, doped semiconductor layer 158B and doped semiconductor layer 160B comprise the same semiconductor material but have different concentrations. For example, doped semiconductor layer 158B and doped semiconductor layer 160B may comprise silicon-germanium and p-type dopant (e.g., boron and / or gallium), but with different germanium concentrations and / or different p-type dopant concentrations. In some embodiments, doped semiconductor layer 158B has a smaller germanium concentration (e.g., Ge%) and / or a smaller p-type dopant concentration (e.g., B%) than doped semiconductor layer 160B, which can reduce crystal dislocations, reduce other crystal defects, maximize strain (and thus enhance carrier mobility, and thus increase drive current), or combinations thereof. In some embodiments, the germanium concentration in doped semiconductor layer 158B is from about 10% to about 20%, and the germanium concentration in doped semiconductor layer 160B is from about 30% to about 60%. In some embodiments, the doped semiconductor layer 158B has a p-type dopant concentration (e.g., boron concentration) of approximately 1 x 10⁻⁶. 20 cm -3 To approximately 5 x 10 20 cm -3 Furthermore, the doped semiconductor layer 160B has a p-type dopant concentration (e.g., boron concentration) of approximately 5 x 10⁻⁶. 20 cm -3 To approximately 2 x 10 21 cm -3 In these embodiments, doped semiconductor layer 160B may be referred to as a heavily doped semiconductor layer, while doped semiconductor layer 158B may be referred to as a lightly doped semiconductor layer. In some embodiments, doped semiconductor layer 158B and doped semiconductor layer 160B have different semiconductor materials, which may have the same or different composition concentrations. In some embodiments, doped semiconductor layer 156B includes a material and / or dopants that provide the desired compressive stress in the channel region (e.g., semiconductor layer 120).

[0053] A doped semiconductor layer 158B may be deposited on and / or grown from semiconductor layer 120, and a doped semiconductor layer 160B may be deposited on and / or grown from doped semiconductor layer 158B. In some embodiments, doped semiconductor layer 158B and doped semiconductor layer 160B are formed by individual selective epitaxial growth processes, which may be chemical vapor deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (PECVD), or similar methods), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. The selective epitaxial growth process may use gaseous and / or liquid precursors that react with the composition of semiconductor layer 120, doped semiconductor layer 158B, or combinations thereof. Epitaxial growth / deposition conditions, such as those described herein, are adjusted to selectively deposit (grow) semiconductor materials (e.g., silicon-germanium) on semiconductor surfaces (e.g., semiconductor layer 120 and / or doped semiconductor layer 158B), while limiting (or preventing) the growth of semiconductor materials from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacers 145, dummy gate stacks 132, gate spacers 134, and / or substrate isolation structures 125). In some embodiments, doped semiconductor layer 158B and / or doped semiconductor layer 160B are doped during deposition (i.e., in-situ doping), for example, by adding dopants to the source material of a selective epitaxial growth process. In some embodiments, doped semiconductor layer 158B and / or doped semiconductor layer 160B are doped after deposition, for example, by an ion implantation process. In some embodiments, annealing is performed to activate the dopants in doped semiconductor layer 158B, doped semiconductor layer 160B, other source / drain regions (e.g., source / drain junction implantation regions), or combinations thereof.

[0054] Please refer to Figure 3A After the additional layer of source / drain structure 150B is formed, mask 162 can be removed by any suitable process, such as etching and / or photoresist stripping. Please refer to... Figure 2D to Figure 2H and Figures 3B to 3F Fabrication of device 100 may include forming additional layers, such as an insulating layer 154A and a doped semiconductor layer 156A, for forming the source / drain structure 150A in device region 102A. When the insulating layer 154A is formed, device region 102B may be exposed, and when the doped semiconductor layer 156A is formed, device region 102B may be covered, as described herein.

[0055] Please refer to Figure 2D , Figure 2E , Figure 3BAn insulating layer 154A may be formed in a source / drain recess 140A above the undoped semiconductor layer 152. The insulating layer 154A partially fills the source / drain recess 140A and may be disposed on the bottommost inner spacer 145 and / or the base 105P'. In some embodiments, the insulating layer 154A fills the remaining portion of the bottom of the source / drain recess 140A and is at least partially disposed above the top of the base 105P'. The insulating layer 154A comprises an electrically insulating material, such as a dielectric material, which reduces unwanted leakage currents, such as currents that may undesirably flow through the base 105P' between the doped semiconductor layers 156A. In the illustrated embodiment, the insulating layer 154A is a nitride layer. The nitride layer may comprise silicon and nitrogen, including dielectric materials, such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbon oxynitride, other suitable silicon and nitrogen comprising dielectric materials, or combinations thereof. For example, insulating layer 154A may be a silicon nitride layer. In some embodiments, the nitride layer comprises metal and nitrogen, including dielectric materials, and insulating layer 154A may be a metal nitride layer.

[0056] Please refer to Figure 2DThe insulating layer 154A can be formed by depositing and etching an insulating material over the device 100, such that the remaining portion of the insulating material provides an insulating layer 154A' with a first nitrogen concentration. For example, the insulating layer 154A' has a thickness t1 that can fill the bottom of the source / drain recess 140A, and the insulating layer 154A' has a thickness t2 that can be disposed over the source / drain structure 150B. The deposited insulating material can be disposed on the top of the gate structures 130A and 130B (e.g., the top of the gate spacer 134 and the dummy gate stack 132), the sidewalls of the gate structures 130A and 130B (e.g., the sidewalls of the gate spacer 134), the top and / or sidewalls of the source / drain structure 150B (e.g., the doped semiconductor layer 160B of the source / drain structure 150B), the sidewalls of the semiconductor layer 120, the sidewalls of the internal spacer 145, the sidewalls of the base 105P', and the top of the base 105'. In some embodiments, due to the nature of the deposition process (e.g., physical vapor deposition), the thickness of the insulating material above the horizontally oriented surfaces (e.g., the top of the undoped semiconductor layer 152, the top of the gate structure 130A, the top of the gate structure 130B, and the top of the source / drain structure 150B) may be greater than the thickness of the insulating material above the vertically oriented surfaces (e.g., the sidewalls of the gate structure 130A, the sidewalls of the gate structure 130B, the sidewalls of the semiconductor layer 120, and the sidewalls of the internal spacer 145). In these embodiments, etching parameters can be adjusted to remove vertically oriented portions of the insulating material, such as those on the sidewalls of gate structure 130A, gate structure 130B, semiconductor layer 120, and internal spacer 145. Due to the etching load effect, etching can also remove horizontally oriented portions of the insulating material on the top of gate structure 130A and gate structure 130B, but without removing (or minimizing removal) the horizontally and / or vertically oriented portions of the insulating material at the bottom of source / drain recess 140A. For example, this etching process can thin the portions of the insulating material at the bottom of source / drain recess 140, but without substantially removing these portions. Furthermore, due to the etching load effect, this etching process can make the insulating material disposed above source / drain structure 150B thinner than the insulating material disposed above the undoped semiconductor layer 152 of source / drain structure 150A, such that in the illustrated embodiment, thickness t2 is less than thickness t1. In some embodiments, thickness t2 is approximately the same as thickness t1. In some embodiments, the etching process completely removes the insulating material disposed above the source / drain structure 150B, and device region 102B has no insulating layer 154A' / insulating layer 154A. In some embodiments, the deposited insulating material fills the source / drain recess 140A, and the etching recesses the insulating material into at least the bottom sacrificial layer 115 and / or the bottom internal spacer 145.In these embodiments, the etching process may partially (e.g., thin) or completely remove the insulating material disposed above the source / drain structure 150B. This etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0057] This embodiment of the invention recognizes that subsequent processing of the device 100 may undesirably reduce the thickness t1 of the insulating layer 154A'. For example, an etching process is performed to remove the mask and / or patterned layer from the device region 102a, as described in reference... Figure 2G and Figure 3D The description suggests that the insulating layer 154A' may be undesirably etched. In some examples, the thickness t1 is reduced to less than 3 nm. It has been observed that an insulating layer 154A' with a thickness less than 3 nm negligibly reduces and / or prevents leakage current, even if present, thus negating the purpose of incorporating the insulating layer 154A' into the source / drain structure 150A. This problem is exacerbated when the thickness t1 of the insulating layer 154A' is non-uniform. For example, the thickness t1 of the edge / end portion of the insulating layer 154A' may be less than the thickness t1 of the central portion of the insulating layer 154A', making the edge / end portion of the insulating layer 154A' more susceptible to the effects of subsequent etching processes. In some examples, subsequent etching processes may completely remove the thinner edges of the insulating layer 154A' in the device region 102A, undesirably exposing and / or damaging the undoped semiconductor layer 152 and / or the substrate 105P' beneath the device region 102A. Therefore, an insulating layer 154A' with a thickness less than 3 nm may cause rather than prevent leakage current. It has been observed that simply increasing the thickness t1 by increasing the thickness of the deposited insulating material and / or etching less of the deposited insulating material to compensate for and / or address thickness reduction that may occur during subsequent manufacturing leaves residual insulating material along the sidewalls of the source / drain recess 140A (e.g., along the sidewalls of the semiconductor layer 120 and / or the sidewalls of the internal spacer 145). This inhibits the growth and / or deposition of the doped semiconductor layer 156A, thereby reducing source / drain strain.

[0058] Please refer to Figure 2E and Figure 3B This embodiment of the invention proposes a processing method 165 for the insulating layer 154A'. Processing method 165 is configured to alter the composition and / or quality of the insulating layer 154A', thereby forming the insulating layer 154A. For example, processing method 165 is configured to provide that the thickness t3 of the insulating layer 154A is greater than the thickness t1 of the insulating layer 154A', the second nitrogen concentration of the insulating layer 154A is greater than the first nitrogen concentration of the insulating layer 154A', the etching rate (e.g., wet etching rate) of the insulating layer 154A with a given etchant (e.g., a fluorine-based etchant, such as diluted hydrofluoric acid) is less than the etching rate of the insulating layer 154A' with the given etchant, or a combination of the aforementioned characteristics of the insulating layer 154A. Figure 4 This illustrates another embodiment of insulating layer 154A' (before treatment) and insulating layer 154A (after treatment), wherein processing 165 increases the thickness of the bottom insulating layer. Figure 4 In this embodiment, the undoped semiconductor layer 152, the insulating layer 154A' and the insulating layer 154A have convex top surfaces rather than concave top surfaces. In some embodiments, source / drain structures 150 having these appearances are considered herein.

[0059] Process 165 includes nitrogen heat treatment, such as an annealing process performed in a nitrogen-containing environment. In the illustrated embodiment, the nitrogen-containing environment is N2, and the nitrogen heat treatment is N2 annealing. In some embodiments, the annealing process is rapid thermal annealing (RTA), such as N2 rapid thermal annealing. In some embodiments, the annealing process is peak annealing, such as N2 peak annealing (e.g., peak rapid thermal annealing). In some embodiments, the annealing process is in-furnace annealing, such as N2 in-furnace annealing. Parameters of the annealing process (e.g., annealing temperature, annealing time, annealing environment, pressure, etc.) can be configured to increase the thickness of insulating layer 154A', increase the nitrogen concentration of insulating layer 154A', increase the silicon-nitrogen bonding of insulating layer 154A', decrease the nitrogen-hydrogen bonding of insulating layer 154A', or a combination thereof. In some embodiments, the annealing temperature is from about 600°C to about 900°C. In some embodiments, the annealing time is from about 1 second to about 5 minutes. In some embodiments, the pressure maintained in the process chamber during annealing is from about 1 to about 100 torr. In some embodiments, nitrogen heat treatment heats the device 100, components of the device 100 (e.g., insulating layer 154A'), the surrounding / environment containing the device 100, or a combination thereof, to a temperature (e.g., annealing temperature) to increase the thickness of the insulating layer 154A', the nitrogen concentration in the insulating layer 154A', the silicon-nitrogen bonding in the insulating layer 154A', or a combination thereof. In some embodiments, nitrogen heat treatment introduces (diffuseds) nitrogen into the insulating layer 154A'.

[0060] In some embodiments, process 165 further includes a silicon implantation process that implants and / or introduces silicon into insulating layer 154A'. The silicon implantation process may be performed before or after nitriding. The silicon implantation process can provide insulating layer 154A with a silicon concentration greater than that of insulating layer 154A', and / or further reduce the etch rate of insulating layer 154A to a given etchant (e.g., a fluorine-based etchant, such as diluted hydrofluoric acid) compared to the etch rate of insulating layer 154A' to a given etchant. Parameters of the silicon implantation process (e.g., implantation energy, implantation dose / concentration, implantation angle (e.g., tilt angle and / or twist angle), implantation temperature, implantation time, implantation environment, pressure, etc.) can be configured to increase silicon concentration and / or increase silicon-nitrogen bonding in insulating layer 154A'. In some embodiments, the silicon implantation energy is from about 3 keV to about 19 keV. In some embodiments, the silicon implantation dose is from about 1 x 10⁻⁶. 19 cm -2 To approximately 1 x 10 20 cm -2 In some embodiments, the insulating layer 154A is silicon-rich after the silicon implantation process. In some embodiments, the parameters of the nitrogen thermal treatment may depend on whether process 165 also includes a silicon implantation process. For example, when process 165 includes a silicon implantation process, the nitrogen thermal treatment can be performed at a higher temperature for a shorter time. In some embodiments, the nitrogen thermal treatment can be performed at a temperature of about 800°C to about 950°C for about 1.5 seconds to about 2 seconds. In these embodiments, the nitrogen thermal treatment may be a rapid N2 spike annealing. Furthermore, in these embodiments, the nitrogen thermal treatment may introduce a low concentration of oxygen, and the annealing process can be performed in a nitrogen- and oxygen-containing environment. For example, the concentration of oxygen (e.g., O2) in the nitrogen- and oxygen-containing environment may be less than about 500 parts per million (ppm).

[0061] Process 165 provides an insulating layer 154A having a thickness (e.g., thickness t3) of at least 3 nm. In some embodiments, the thickness t3 is from about 3 nm to about 8 nm. For example, the thickness t3 is from about 3.5 nm to about 4.5 nm. The bottom insulating layer having a thickness of at least 3 nm can withstand subsequent processing such that even if the bottom insulating layer is etched and / or thinned during subsequent processing, a sufficient amount of bottom insulating layer remains between the doped semiconductor layer 156A and the underlying undoped semiconductor layer 152 / base 105P', providing the source / drain structure 150A with sufficient bottom source / drain isolation to suppress and / or prevent leakage current. Reducing the source / drain-base leakage current improves the performance of device 100, for example, by improving the transistor gain in device region 102A. In some embodiments, process 165 increases the insulating layer thickness by about 0.4 nm to about 1.4 nm (i.e., increases the thickness t1 by about 0.4 nm to about 1.4 nm), such that the thickness t3 is at least 3 nm. In some embodiments, the increased insulating layer thickness (e.g., from about 0.7 nm to about 1.4 nm) from the nitrogen thermal treatment combined with the silicon implantation process is greater than the increased insulating layer thickness (e.g., from about 0.4 nm to about 0.6 nm) from the nitrogen thermal treatment alone. In some embodiments, the thickness t3 of the edge / end portion of the insulating layer 154A is less than the thickness t3 of the center portion of the insulating layer 154A, and at least the thickness t3 of the center portion of the insulating layer 154A is greater than 3 nm. In some embodiments, both the thickness t3 of the edge / end portion of the insulating layer 154A and the thickness t3 of the center portion of the insulating layer 154A are greater than 3 nm. Processing 165 may also provide the insulating layer 154A with a more consistent thickness compared to the insulating layer 154A'. For example, the difference between the thickness t3 of the edge / end portion of the insulating layer 154A and the thickness t3 of the center portion of the insulating layer 154A may be less than the difference between the thickness t1 of the edge / end portion of the insulating layer 154A' and the thickness t1 of the center portion of the insulating layer 154A'. Therefore, process 165 can also improve the uniformity of the bottom insulating layer (e.g., by reducing the thickness difference from its center to the edge) (see example). Figure 4 This improves the bottom source / drain insulation. In some embodiments, process 165 increases the thickness of the edge / end portion of the bottom source / drain insulation layer to be greater than the thickness of the center portion of the bottom source / drain insulation layer. For example, the difference between the thickness t1 of the edge / end portion of insulation layer 154A' and the thickness t3 of the edge / end portion of insulation layer 154A can be greater than the difference between the thickness t1 of the center portion of insulation layer 154A' and the thickness t3 of the center portion of insulation layer 154A, see, for example... Figure 4 .

[0062] Processing technology 165 can also create, repair, and / or enhance silicon-nitrogen bonding (e.g., Si-N bonding) and reduce nitrogen-hydrogen bonding (e.g., N(-H) bonding) in insulating layer 154A'. x (Bonding), which allows insulating layer 154A to have more Si-N bonds and fewer NH bonds (e.g., N(-H)) compared to insulating layer 154A'. x (Bonding). Compared to the etch rate of insulating layer 154A' to a given etchant, increasing silicon-nitrogen bonding and decreasing nitrogen-hydrogen bonding can increase the insulating layer thickness and / or decrease the etch rate of insulating layer 154A to a given etchant, as further described below. In some embodiments, processing insulating layer 154A' using process 165 can provide a wet etch rate of insulating layer 154A to a given etchant (e.g., a fluorine-based etchant, such as diluted hydrofluoric acid) that is about 35% to about 75% lower than the wet etch rate of insulating layer 154A' to a given etchant. For example, the amount of insulating layer 154A removed per minute by the etchant (e.g., angstroms (Å)) is less than the amount of insulating layer 154A' removed per minute by the etchant. Therefore, the bottom source / drain insulating layer has greater etch resistance to subsequent processing (i.e., a lower etch rate means less removal of the bottom source / drain insulating layer during subsequent processing), thereby improving bottom source / drain insulation.

[0063] Referring to Figures 2F and 3C, the fabrication of device 100 may include forming a mask 168 over device regions 102A and 102B. The composition of mask 168 differs from that of source / drain structures 150A (e.g., insulating layer 154A of source / drain structure 150A), source / drain structures 150B (e.g., doped semiconductor layer 160B of source / drain structure 150B), semiconductor layer 120, gate structure 130A, gate structure 130B, internal spacer 145, or combinations thereof, to achieve selective removal / etching therebetween. In some embodiments, mask 168 comprises metal and oxygen and / or nitrogen (i.e., mask 168 is a metal oxide mask and / or metal nitride mask). For example, mask 168 may comprise aluminum and oxygen and / or nitrogen, and mask 168 may be an aluminum oxide mask, an aluminum oxynitride mask, or an aluminum nitride mask. In the illustrated embodiment, the mask 168 is an aluminum oxide mask (e.g., an Al2O3 mask). The mask 168 may be a passivation layer over the source / drain structure 150B. The passivation layer protects the source / drain structure 150B when an additional layer is formed for the source / drain structure 150A. For example, the passivation layer can prevent the deposition and / or growth of semiconductor material (e.g., epitaxial material) on the doped semiconductor layer 156B when the doped semiconductor layer 156A is formed in the source / drain recess 140A, prevent unwanted doping of the source / drain structure 150B (e.g., n-type dopant), and prevent other alterations and / or defects in the source / drain structure 150B, or combinations thereof.

[0064] It is understood in this embodiment of the invention that the composition and / or quality of the deposited mask 168 may be insufficient to withstand the processing associated with the formation of the additional layer of the source / drain structure 150A. For example, the mask 168 may be damaged and / or undesirably removed / thinned during a pre-cleaning process (e.g., etching) of the source / drain recess 140A prior to the formation of the doped semiconductor layer 156A in the source / drain recess 140A. In embodiments where the pre-cleaning process is wet etching, the etching solution (e.g., containing ammonia (NH3) and / or hydrogen fluoride (HF)) may undesirably react with the mask 168, resulting in unwanted etching of the mask 168. This undesirable reaction is particularly common when the mask 168 is an alumina mask, as the etchant (e.g., NH3 and / or HF) may react with the mask 168 (e.g., Al(OH)3 bonds that may be present on its surface) and form (NH4)3AlF6 and venting. In some examples, the etchant may completely remove a portion of the mask 168, exposing the underlying source / drain structure 150B. This can lead to unwanted etching and / or wear of the source / drain structure 150B (e.g., the doped semiconductor layer 160B) and / or undesirable deposition / growth of semiconductor material for device region 102A on the source / drain structure 150B. It has been observed that simply increasing the thickness of the deposition mask 168 to compensate for and / or address thickness reduction, and thus potentially during pre-cleaning processes and / or other processes associated with the formation of the doped semiconductor layer 156A, may leave residual masking material (e.g., aluminum oxide) in the source / drain notch 140A. This residual masking material inhibits the growth and / or deposition of the doped semiconductor layer 156A, thereby reducing source / drain strain.

[0065] This embodiment of the invention therefore proposes a processing method 170 for mask 168. Processing method 170 is configured to modify the composition and / or quality of mask 168, enabling mask 168 to better withstand source / drain pre-cleaning processes and / or other subsequent processing. For example, processing method 170 is configured to increase density, reduce hydrogen concentration (e.g., on the surface of mask 168), improve hydrogen bonding, reduce the etch rate (e.g., wet etch rate) for a given etchant (e.g., NH3 and / or HF), or a combination thereof. Increasing the density of mask 168, reducing the hydrogen content of mask 168, and / or improving hydrogen bonding can reduce the etch rate of mask 168 for a given etchant (compared to the etch rate of mask 168 without treatment). In some embodiments, processing method 170 for mask 168 reduces the hydrogen concentration (H%) of mask 168 by more than about 20%. In some embodiments, processing method 170 for mask 168 increases the density of mask 168 by more than about 2%. In some embodiments, the mask 168 is processed by process 170 such that the wet etch rate of the mask 168 to a given etchant (e.g., NH3 and / or HF) is reduced by more than about 10%. For example, the amount of treated mask 168 removed per minute (e.g., Å) by the etchant is less than the amount of untreated mask 168 removed per minute by the etchant. Therefore, the mask 168 has greater etch resistance to source / drain pre-cleaning processes and / or other processes associated with the additional layers forming the source / drain structure 150A, thereby reducing and / or preventing wear of the mask 168 and damage to the source / drain structure 150B.

[0066] Process 170 includes nitrogen heat treatment, such as an annealing process performed in a nitrogen-containing environment. In the illustrated embodiment, the nitrogen-containing environment is N2, and the nitrogen heat treatment is N2 annealing. In some embodiments, the annealing process is rapid thermal annealing, such as N2 rapid thermal annealing. In some embodiments, the annealing process is peaked annealing, such as N2 peaked annealing (e.g., peaked rapid thermal annealing). In some embodiments, the annealing process is in-furnace annealing, such as N2 in-furnace annealing. Configurable annealing process parameters (e.g., annealing temperature, annealing time, annealing environment, pressure, etc.) can be used to increase the density of the mask 168, reduce the hydrogen concentration of the mask 168 (e.g., on the surface of the mask 168), improve hydrogen bonding in the mask 168 (e.g., improve the strength of hydrogen bonding in and / or on the surface of the mask 168, which may slow the reaction of the etchant (e.g., NH3 and / or HF) with the hydrogen components of the mask 168 (e.g., Al(OH)3 bonds), thereby slowing the removal of hydrogen and a portion of the mask 168), or a combination thereof. In some embodiments, nitrogen heat treatment heats the device 100, components of the device 100 (e.g., the mask 168), the surrounding / environment containing the device 100, or a combination thereof, to a temperature (e.g., the annealing temperature). In some embodiments, nitrogen heat treatment introduces (diffuses) nitrogen into the mask 168. In some embodiments, the annealing temperature is from about 600°C to about 900°C. While such a high annealing temperature (e.g., greater than about 700°C) reduces the thickness of the mask 168, the increased density resulting from this high annealing temperature significantly improves the composition of the mask 168, making it more resistant to pre-cleaning processes and / or other subsequent processes. In some embodiments, the annealing time is from about 1 second to about 5 minutes. In some embodiments, the pressure maintained in the process chamber during nitrogen heat treatment is from about 1 torr to about 100 torr.

[0067] Please refer to Figure 2G and Figure 3DMask 168 is removed from device region 102A through a patterning process, thereby exposing source / drain notches 140A (e.g., exposing insulating layer 154A). For example, mask 168 has an opening 169 therein, which overlaps with device region 102A, such that mask 168 covers device region 102B (e.g., p-type transistor region) but does not cover device region 102A (e.g., n-type transistor region). The patterning process may include performing a photolithography process to form a patterned photoresist layer that covers mask 168 over device region 102B and exposes mask 168 over device region 102A (e.g., the patterned photoresist layer has an opening therein that overlaps with device region 102A), and performing an etching process to selectively remove the exposed mask 168. In the illustrated embodiment, the etching process is configured to selectively remove the mask 168 (e.g., nitrogen-treated alumina material) while negligibly (or even not at all) etching the source / drain structure 150A (e.g., the insulating layer 154A of the source / drain structure 150A (e.g., nitrogen-treated silicon nitride material)), gate structure 130A, substrate isolation structure 125, or combinations thereof. The etching process can be dry etching, wet etching, other suitable etching, or combinations thereof. For example, the etching process can be wet etching using a hydrofluoric acid (HF) solution or a diluted hydrofluoric acid (DHF) solution. As described above, due to the insulating layer 154A (e.g., nitrogen-treated silicon nitride material) becoming thicker through the processing process 165 and / or the NH bonds (e.g., N(-H)) in the insulating layer 154A... x The Si-N bonds have been reduced through processing 165, giving the insulating layer 154A greater resistance to wet etching, allowing it to be etched (or negligibly) by wet etchants (e.g., diluted hydrofluoric acid solutions). For example, HF-based etchants can interact with the Si-N bonds and / or NH bonds (e.g., N(-H)) of the insulating layer 154A. x The insulating layer 154A undergoes a reaction to break its Si-N bonds and replace the Si-NH2 bonds with Si-F bonds, thereby slightly etching and / or modifying the insulating layer 154A. However, insulating layer 154A has fewer NH bonds (e.g., N(-H)) than insulating layer 154A'. x The HF-based etchant is less likely to react with the insulating layer 154A, disrupting the Si-N bonds and replacing the Si-NH2 bonds with Si-F bonds. Furthermore, since the insulating layer 154A is at least 3 nm thick, it can withstand some etching while remaining thick enough to provide sufficient bottom source / drain insulation. Therefore, due to the source / drain fabrication process described herein using process 165, any removal of the insulating layer 154A is negligible, and it can still provide bottom source / drain insulation to reduce / prevent leakage current.

[0068] Please refer to Figure 2G and Figure 3E A doped semiconductor layer 156B may be formed in the source / drain recess 140B above the insulating layer 154B and / or the undoped semiconductor layer 152, while a mask 168 (e.g., a nitrogen-doped alumina mask) covers the device region 102B. The doped semiconductor layer 156A fills the remaining portion of the source / drain recess 140A and is coupled to the edge / end portion of the semiconductor layer 120 in the device region 102A. In the illustrated embodiment, the doped semiconductor layer 156A includes a doped semiconductor layer 158A and a doped semiconductor layer 160A. The doped semiconductor layer 158A may be formed above the semiconductor layer 120 (e.g., above the sidewalls and / or ends of the semiconductor layer 120) and partially fills the source / drain recess 140A, while the doped semiconductor layer 160A may be formed above the doped semiconductor layer 158A and / or the insulating layer 154A and fill the remaining portion of the source / drain recess 140A. A doped semiconductor layer 160A is separated from semiconductor layer 120 by a doped semiconductor layer 158A, and is separated from undoped semiconductor layer 152 by an insulating layer 154A. In the illustrated embodiment, the doped semiconductor layer 158A is discontinuous and formed by discrete and spaced portions, each doped semiconductor layer 158A being disposed at the end of a corresponding semiconductor layer 120, i.e., portions of doped semiconductor layers 158A disposed on adjacent semiconductor layers 120 are not connected to each other. In these embodiments, the doped semiconductor layer 160A may surround the doped semiconductor layer 158A, and the doped semiconductor layer 160A may extend to the inner spacer 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158A may surround semiconductor layer 120, such that the discrete and spaced portions are formed above the top and / or bottom of the corresponding semiconductor layer 120. In some embodiments, the discrete and spaced portions extend above and / or to the inner spacer 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158A are connected such that the doped semiconductor layers 158A can form the sidewalls of the source / drain structure 150A above the base 105P', and / or the doped semiconductor layer 160A can be separated from the internal spacer 145 by the doped semiconductor layer 158A.

[0069] Doped semiconductor layers 158A and 160A comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, doped semiconductor layers 158A and 160A comprise the same semiconductor material but with different concentrations. For example, doped semiconductor layers 158A and 160A may comprise silicon and n-type dopants (e.g., phosphorus and / or arsenic) but with different n-type dopant concentrations. In some embodiments, doped semiconductor layer 158A has a smaller n-type dopant concentration (e.g., P%) than doped semiconductor layer 160A, which can reduce crystal dislocations, reduce other crystal defects, maximize strain (and thus enhance carrier mobility, and thus increase drive current), or combinations thereof. In some embodiments, doped semiconductor layer 158A has an n-type dopant concentration (e.g., phosphorus concentration) of about 1 x 10⁻⁶. 20 cm -3 To approximately 5 x 10 20 cm -3 Furthermore, the doped semiconductor layer 160A has an n-type dopant concentration (e.g., phosphorus concentration) of approximately 5 x 10⁻⁶. 20 cm -3 To approximately 2 x 10 21 cm -3 In these embodiments, doped semiconductor layer 160A may be referred to as a heavily doped semiconductor layer, while doped semiconductor layer 158A may be referred to as a lightly doped semiconductor layer. In some embodiments, doped semiconductor layer 158A and doped semiconductor layer 160A are made of different semiconductor materials, which may have the same or different concentrations. In some embodiments, doped semiconductor layer 156A includes a material and / or dopants that provide the desired tensile stress in the channel region (e.g., semiconductor layer 120) of device region 102A.

[0070] A doped semiconductor layer 158A may be deposited on and / or grown from semiconductor layer 120, and a doped semiconductor layer 160A may be deposited on and / or grown from doped semiconductor layer 158A. In some embodiments, doped semiconductor layer 158A and doped semiconductor layer 160A are formed by individual selective epitaxial growth processes, which may be chemical vapor deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (PECVD), or similar methods), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. The selective epitaxial growth process may use gaseous and / or liquid precursors that react with the composition of semiconductor layer 120, doped semiconductor layer 158A, or combinations thereof. Epitaxial growth / deposition conditions, such as those described herein, are adjusted to selectively deposit (grow) semiconductor material (e.g., silicon) on semiconductor surfaces (e.g., semiconductor layer 120 and / or doped semiconductor layer 158A), while limiting (or preventing) the growth of semiconductor material from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacers 145, dummy gate stacks 132, gate spacers 134, and / or substrate isolation structures 125). In some embodiments, doped semiconductor layer 158A and / or doped semiconductor layer 160A are doped during deposition (i.e., in-situ doping), for example, by adding dopants to the source material of the selective epitaxial growth process. In some embodiments, doped semiconductor layer 158A and / or doped semiconductor layer 160A are doped after deposition, for example, by an ion implantation process. In some embodiments, annealing is performed to activate the dopants in doped semiconductor layer 158A, doped semiconductor layer 160A, other source / drain regions (e.g., source / drain junction implantation regions), or combinations thereof.

[0071] In some embodiments, the source / drain recess 140A is etched, for example, pre-cleaned, before forming the doped semiconductor layer 156A in the source / drain recess 140A. For example, the etching process may be wet etching using an NH3 solution and / or an HF solution. As described above, since the mask 168 (e.g., nitrogen-treated alumina material) has become denser through the processing process 170, the hydrogen content (H%) in the mask 168 has been reduced through the processing process 170, and / or the hydrogen bonding in the mask 168 has been improved through the processing process 170 (e.g., the hydrogen bonding strength in the mask 168 and / or at the surface of the mask 168 is greater), the mask 168 has greater resistance to wet etching, so that the mask 168 is not (or negligibly) etched by the wet etchant (e.g., NH3+HF solution). For example, NH3-based and / or HF-based etchants can react with the hydrogen components (e.g., Al(OH)3 bonds) of mask 168, thereby slightly etching and / or altering mask 168. However, because the treated mask 168 is denser, has less hydrogen content, and has stronger hydrogen bonds, the etching reaction can occur less and / or more slowly, thereby reducing any etching / removal of mask 168. Therefore, due to the source / drain manufacturing process of this embodiment of the invention using process 170, any removal of mask 168 is negligible, and mask 168 can still provide sufficient passivation and protection for the source / drain structure 150B, thereby preventing or reducing any wear and tear on the source / drain structure 150B during the formation of the source / drain structure 150A.

[0072] Please refer to Figure 2H and Figure 3F After forming an additional layer of the source / drain structure 150A using any suitable process (e.g., etching), the mask 168 can be removed. In the illustrated embodiment, the etching process is configured to selectively remove the mask 168 (e.g., nitrogen-doped alumina material) while negligibly (or even not at all) etching the source / drain structure 150A, source / drain structure 150B, gate structure 130A, gate structure 130B, substrate isolation structure 125, or combinations thereof. The etching process can be dry etching, wet etching, other suitable etching, or combinations thereof, and the etching process can use an etchant that is the same as or different from the etching process used to pattern the mask 168 (i.e., when a portion of the mask 168 is removed to expose...). Figure 2G and Figure 3D (When in device region 102A). In the illustrated embodiment, the etching process uses different etchants to remove mask 168 from device region 102B. For example, the etching process may use a sulfur peroxide mix (SPM) solution (i.e., a mixture of H2SO4 and H2O2).

[0073] Please refer to Figure 2I Fabrication of device 100 may include forming a dielectric layer 175 over source / drain structure 150 and substrate isolation structure 125. Dielectric layer 175 may fill the space between adjacent gate structures, such as the space between gate spacers 134 of gate structure 130A and gate spacers 134 of gate structure 130B, and the space between adjacent source / drain structures 150. Formation of dielectric layer 175 may include depositing a contact etch stop layer (CESL), depositing an interlayer dielectric (ILD) over the CESL, and performing chemical mechanical polishing and / or planarization processes until the dummy gate stack 132 is reached. The planarization process may partially remove the dummy gate stack 132, such as the hard mask 138 of the dummy gate stack 132, to expose the underlying dummy gate 136 (e.g., a polysilicon gate). The planarization process may reduce the height of the dummy gate stack 132 and / or gate spacers 134.

[0074] The interlayer dielectric comprises a dielectric material, which includes, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, desiccant, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB)-based dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the interlayer dielectric layer comprises a low-dielectric-constant dielectric material having a dielectric constant smaller than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the interlayer dielectric layer comprises a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as porous silica, silicon carbide, carbon-doped oxides (e.g., SiCOH-based materials having, for example, Si-CH3 bonds), or combinations thereof, with each material adjusted / configured to achieve a dielectric constant of less than about 2.5. The contact etch stop layer comprises a material different from that of the interlayer dielectric layer, for example, a dielectric material different from that of the interlayer dielectric layer. For instance, the interlayer dielectric layer comprises silicon and carbon, both low-k dielectric materials, while the contact etch stop layer may comprise silicon and nitrogen, such as silicon nitride or silicon oxynitride. The interlayer dielectric layer and / or the contact etch stop layer may have a multilayer structure and / or comprise multiple dielectric materials.

[0075] Next, a gate replacement process can be performed to replace the dummy gate 136 with gate stacks 180A and 180B. For example, the dummy gate 136 is removed to form a gate opening (formed between gate spacer 134 and / or inner spacer 145) that exposes a channel region of the multilayer stack 110 (e.g., semiconductor layer 120 and sacrificial layer 115). In some embodiments, the etching process may selectively remove the dummy gate 136 with respect to dielectric layer 175, gate spacer 134, inner spacer 145, sacrificial layer 115, semiconductor layer 120, or a combination thereof. In other words, the etching process removes the dummy gate 136 while negligibly (or even not at all) removing dielectric layer 175, gate spacer 134, inner spacer 145, sacrificial layer 115, semiconductor layer 120, or a combination thereof. The etching process may be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 175 and / or the gate spacer 134.

[0076] During the gate replacement process, prior to forming the gate stacks 180A and 180B in the gate openings, a channel release process may be performed to form suspended channel layers. For example, the sacrificial layer 115 exposed by the gate openings may be selectively removed to form air gaps between semiconductor layers 120 and between semiconductor layer 120 and substrate 105P', thereby suspending the channel layers in the channel regions. In the illustrated embodiment, each channel region has three suspended channel layers, subsequently also referred to as channel layers 120', which are stacked vertically along the z-direction to provide three channels through which current can flow between the corresponding source / drain structures 150 during transistor operation of device 100. In some embodiments, the etching process selectively etches the sacrificial layer 115 while minimizing (or even eliminating) etching of semiconductor layer 120, substrate 105P', gate spacer 134, internal spacer 145, dielectric layer 175, or combinations thereof. In some embodiments, the etchant used in the etching process is selected such that the etching rate of silicon germanium (i.e., sacrificial layer 115) is faster than the etching rate of silicon (i.e., semiconductor layer 120 and substrate 105P') and dielectric materials (i.e., gate spacer 134, internal spacer 145, and / or dielectric layer 175) (i.e., the etchant has high etch selectivity for silicon germanium). The etching process may be dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, an oxidation process may be performed prior to the etching process to transform the sacrificial layer 115 into a silicon germanium oxide component, wherein the etching process removes the silicon germanium oxide component. In some embodiments, the etching process may be performed during and / or after the removal of the sacrificial layer 115 to alter the contour of the semiconductor layer 120 to achieve a target size and / or target shape for the channel layer 120'.

[0077] Next, gate stacks 180A and 180B of gate structure 130A and gate structure 130B may be formed in the gate opening. Gate stacks 180A and 180B (also referred to as high-dielectric-constant / metal gates) are disposed between corresponding gate spacers 134, between corresponding internal spacers 145, between corresponding channel layers 120', and between corresponding channel layers 120' and corresponding bases 105P'. In the illustrated embodiment, where device 100 includes a fully wrapped gate transistor, for example, in the YZ plane, gate stacks 180A and 180B may surround the corresponding channel layer 120'. In some embodiments, gate stacks 180A and 180B may surround and / or partially surround the corresponding channel layer 120' (i.e., disposed on at least both sides of the channel layer 120'), for example, where device 100 includes a fork-sheet transistor.

[0078] Gate stack 180A includes gate dielectric 182A, and gate stack 180B includes gate dielectric 182B. Gate dielectric 182A and gate dielectric 182B are disposed on a corresponding channel layer 120', a corresponding internal spacer 145, a corresponding gate spacer 134, a substrate isolation structure 125, or a combination thereof. The composition and / or configuration of gate dielectric 182A and gate dielectric 182B may be the same or different. For example, the composition and / or configuration of gate dielectric 182A may differ from the composition and / or configuration of gate dielectric 182B, for example, where device regions 102A and 102B are configured for different types of transistors. Gate dielectric 182A and gate dielectric 182B each include at least one dielectric layer, such as an interface layer and / or a high-dielectric-constant dielectric layer. The interface layer includes a dielectric material, such as SiO2 or SiGeO. xHigh dielectric constant dielectric layers include high dielectric constant dielectric materials, which are dielectric materials with a dielectric constant greater than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3(BTO), (Ba,Sr)TiO3(BST), HfO2-Al2O3, other high dielectric constant dielectric materials, or combinations thereof. In some embodiments, gate dielectric 182A and gate dielectric 182B each include a hafnium oxide (e.g., HfO2) layer and / or a zirconium oxide (e.g., ZrO2) layer.

[0079] Furthermore, gate stack 180A includes a gate electrode 184A disposed above gate dielectric 182A, while gate stack 180B includes a gate electrode 184B disposed above gate dielectric 182B. The composition and / or configuration of gate electrodes 184A and 184B may be the same or different. For example, the composition and / or configuration of gate electrode 184A may differ from that of gate electrode 184B, for instance, where device regions 102A and 102B are configured for different types of transistors. In some embodiments, gate electrodes 184A and 184B each include a conductive layer formed of a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the conductive layer includes a work function layer, which can be adjusted to have a desired work function (e.g., an n-type work function or a p-type work function). The work function layer comprises a work function metal and / or an alloy of work function metals, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the conductive layer comprises a bulk layer above the gate dielectric and / or the work function layer. The bulk layer may comprise Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or alloys of other suitable metals, or combinations thereof. In some embodiments, the conductive layer comprises a barrier layer above the work function layer and / or the gate dielectric. The barrier layer comprises a material that can prevent diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers (e.g., between the work function layer and the bulk layer). In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0080] Gate stacks 180A and 180B are configured to perform desired functions according to the design requirements of device 100, and gate stacks 180A and 180B may have different layers in different device regions depending on their configuration. For example, the number, configuration, material, or combination thereof of the layers of gate dielectric 182A and / or gate electrode 184A corresponding to device region 102A (e.g., an n-type transistor region) may differ from the number, configuration, material, or combination thereof of the layers of gate dielectric 182B and / or gate electrode 184B corresponding to device region 102B (e.g., a p-type transistor region). Forming gate stacks 180A and 180B may include depositing gate dielectric material (e.g., an interface layer, a high-dielectric-constant dielectric layer, etc.), partially filling the gate opening with the gate dielectric material, depositing gate electrode material (e.g., a work function layer, a barrier layer, a bulk layer, etc.) to fill the remaining portion of the gate opening, and performing a planarization process to remove the portion of the gate dielectric material and / or gate electrode material above the dielectric layer 175. The gate stack 180A of gate structure 130A and the gate stack 180B of gate structure 130B can be formed simultaneously, partially simultaneously, or individually. For example, gate dielectric 182A and gate dielectric 182B (or the aforementioned sublayers) can be formed simultaneously. In another example, the bulk layers of gate electrodes 184A and 184B can be formed simultaneously, while the work function layers (or the aforementioned sublayers) of gate electrodes 184A and 184B can be formed individually. Although the illustrated embodiment manufactures gate stacks 180A and 180B according to a post-gate process, embodiments in which the metal gate stack of device 100 can be manufactured according to a gate-first process or a hybrid gate-first / gate-later process are considered herein.

[0081] Fabrication of device 100 may further include etching back gate stacks 180A and 180B, and forming a hard mask (e.g., a self-aligned cap structure) over the etched-back gate stacks 180A and 180B. The hard mask comprises a material different from dielectric layer 175 and / or subsequently formed dielectric layers to achieve etch selectivity. In some embodiments, the hard mask comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbide nitride, silicon carbide nitride, or combinations thereof. In some embodiments, the hard mask comprises a metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, hafnium aluminum oxide, or combinations thereof.

[0082] The device may include various transistors, such as n-type transistors in device region 102A and p-type transistors in device region 102B. An n-type transistor may include a corresponding channel (e.g., channel layer 120'), a source / drain (e.g., source / drain structure 150A), and a corresponding gate (e.g., gate stack 180A). The gate stack 180A is disposed along the x-direction between the corresponding source / drain (e.g., source / drain structure 150A), and an internal spacer 145 is disposed between the gate stack 180A and its corresponding source / drain. Furthermore, the gate stack 180A connects the corresponding channel (e.g., channel layer 120') and the corresponding channel extending along the x-direction between the corresponding source / drain (e.g., source / drain structure 150A). The gate stack 180A may surround its corresponding channel layer, and along the longitudinal direction of the gate, each gate may include a gate dielectric (e.g., gate dielectric 182A) and a gate electrode (e.g., gate electrode 184A) surrounding its corresponding channel. Furthermore, in the illustrated embodiment, the n-type transistor includes bottom source / drain insulation (e.g., insulating layer 154A and undoped semiconductor layer 152) that isolates and / or isolates the source / drain structure 150A from the underlying substrate (e.g., substrate 105, base 105', base 105P', or a combination thereof). This reduces and / or eliminates leakage current into the underlying substrate, such as leakage current that could flow from the source / drain into the underlying substrate. Reducing and / or eliminating unwanted leakage current improves overall transistor performance. As described herein, because the source / drain fabrication process described herein uses process 165, the provided n-type transistor has improved bottom source / drain insulation, thereby improving leakage current suppression.

[0083] A p-type transistor may include a corresponding channel (e.g., channel layer 120'), a source / drain (e.g., source / drain structure 150B), and a corresponding gate (e.g., gate stack 180B). The gate stack 180B is disposed along the x-direction between the corresponding source / drain (e.g., source / drain structure 150B), and an internal spacer 145 is disposed between the gate stack 180B and its corresponding source / drain. Furthermore, the gate stack 180B connects the corresponding channel (e.g., channel layer 120') and the corresponding channel extending along the x-direction between the corresponding source / drain (e.g., source / drain structure 150B). The gate stack 180B may surround its corresponding channel layer, and along the longitudinal direction of the gate, each gate may include a gate dielectric (e.g., gate dielectric 182B) and a gate electrode (e.g., gate electrode 184B) surrounding its corresponding channel. Furthermore, in the illustrated embodiment, the p-type transistor includes bottom source / drain insulation (e.g., insulating layer 154B and undoped semiconductor layer 152), which isolates and / or isolates the source / drain structure 150B from the underlying substrate (e.g., substrate 105, base 105', base 105P', or a combination thereof). This reduces and / or eliminates leakage current into the underlying substrate, such as leakage current that could flow from the source / drain into the underlying substrate. Reducing and / or eliminating unwanted leakage current improves overall transistor performance.

[0084] Due to the source / drain manufacturing process described herein, the composition and / or configuration of the bottom source / drain insulation of an n-type transistor may differ from that of a p-type transistor. For example, the composition and / or configuration of insulating layer 154A may differ from that of insulating layer 154B. In some embodiments, the nitrogen concentration of insulating layer 154A is greater than that of insulating layer 154B. In some embodiments, the silicon concentration of insulating layer 154A is greater than that of insulating layer 154B. In some embodiments, the thickness of insulating layer 154A is greater than that of insulating layer 154B, for example, insulating layer 154A undergoes process 165, but insulating layer 154B does not undergo process 165. In some embodiments, insulating layers 154A and 154B are formed of the same material (e.g., silicon nitride). In some embodiments, insulating layers 154A and 154B are formed of different materials. Furthermore, due to the source / drain fabrication process described herein, the source / drain structure 150B may have an insulating layer 154A disposed above the doped semiconductor layer 156B (e.g., a doped semiconductor layer 160B of the doped semiconductor layer 156B), and the doped semiconductor layer 160B may be disposed between nitride layers with different nitrogen concentrations, for example, the nitrogen concentration of the insulating layer 154A is greater than that of the insulating layer 154B. In these embodiments, the thickness of the insulating layer 154A of the source / drain structure 150A may be greater than the thickness of the insulating layer 154A of the source / drain structure 150B. Furthermore, in these embodiments, after the source / drain contact is formed, a residual portion of the insulating layer 154A may remain between the dielectric layer 175 and the doped semiconductor layer 160B. In some embodiments, when the insulating layer 154A is formed and / or the insulating material formed above the source / drain structure 150B is removed, the shielding device region 102B is shielded so that the p-type transistor does not include the insulating layer 154A above the doped semiconductor layer 156B.

[0085] In some embodiments, fabrication of device 100 may include replacing sacrificial layer 115 with a different sacrificial layer after forming source / drain recess 140 and before forming internal spacers 145. In these embodiments, after forming source / drain recess 140, fabrication of device 100 may include performing an etching process to selectively remove the sacrificial layer 115 exposed by the source / drain recess 140, thereby forming gaps in the channel region, and after removing the sacrificial layer 115, the semiconductor layer 120 remaining in the channel region provides a channel layer 120' suspended above the substrate 105P'. The etching process may selectively remove sacrificial layer 115 relative to the substrate 105, semiconductor layer 120, gate structure 130A, gate structure 130B, or a combination thereof. In some embodiments, the etchant used for the etching process is selected such that the etching rate of silicon germanium (e.g., sacrificial layer 115) is greater than the etching rate of silicon (e.g., semiconductor layer 120 and substrate 105') and dielectric material (e.g., gate spacers 134 and hard mask 138). The etching process can be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, an oxidation process may be performed prior to the etching process to transform the sacrificial layer 115 into a semiconductor oxide layer (e.g., a silicon-germanium oxide layer). In these embodiments, the etching process removes the semiconductor oxide layer to form gaps.

[0086] In these embodiments, fabrication of device 100 may then include forming a second sacrificial layer in the gaps prior to forming the internal spacer 145. The composition of the second sacrificial layer differs from that of the channel layer 120' to achieve etch selectivity. For example, the second sacrificial layer and channel layer 120' may comprise different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof. In some embodiments, the second sacrificial layer may comprise a dielectric material, which may comprise silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof. For example, the dielectric material may comprise oxygen, and the second sacrificial layer may be an oxide layer (which may be referred to as dummy oxide interposers (DOIs)). In some embodiments, the dummy oxide interposers may be silicon oxide layers.

[0087] In some embodiments, a second sacrificial layer is formed by depositing a dielectric layer over device 100 and then etching the dielectric layer, such that the dielectric layer is removed from the source / drain region of device 100 but not from the channel region. In some embodiments, the deposited dielectric layer may fill gaps. In some embodiments, the dielectric layer is formed by a compliant deposition process and has a compliant thickness. In some embodiments, etching may remove exposed portions of the dielectric layer (e.g., portions that do not fill gaps), such as portions of the dielectric layer disposed on the sidewalls of channel layer 120', the sidewalls of base 105P', the surface of base 105' forming the bottom of source / drain recess 140, the sidewalls and top of gate spacer 134, and the top of dummy gate stack 132 (e.g., portions of the hard mask 138 of dummy gate stack 132). The dielectric material may be removed by dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the second sacrificial layer (e.g., the dielectric layer) is formed by an oxidation process, such as a thermal oxidation process. In some embodiments, the second sacrificial layer is formed by atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), other suitable deposition processes, or a combination thereof.

[0088] In these embodiments, Figure 2B In this process, the first etching process performed when forming the internal spacer 145 can selectively etch the second sacrificial layer, while the etching of the semiconductor layer 120, the substrate 105P', the dummy gate stack 132 (e.g., the hard mask 138 of the dummy gate stack 132), the gate spacer 134, the substrate isolation structure 125, or a combination thereof can be negligible (or even not etched). Furthermore, in these embodiments, in Figure 2I In this embodiment, the fabrication of device 100 may include removing the second sacrificial layer instead of sacrificial layer 115, thereby forming a gap (opening) exposing channel layer 120'. Thus, the gate opening extends between channel layers 120' and between channel layer 120' and base 105P'. In these embodiments, the etching process removes the second sacrificial layer, while the removal of channel layer 120', internal spacer 145, gate spacer 134, dielectric layer 175, or combinations thereof may be negligible (or even nonexistent). For example, the etchant used in the etching process is selected such that the etching rate of dielectric material having a first composition (e.g., the second sacrificial layer) is greater than the etching rate of silicon (e.g., channel layer 120') and dielectric material having a composition different from the first composition (e.g., internal spacer 145, gate spacer 134, dielectric layer 175, etc.), i.e., the etchant has high etch selectivity relative to dielectric material having the first composition. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof.

[0089] Introducing a second sacrificial layer into the fabrication of apparatus 100 can increase the thermal budget margin associated with fabrication apparatus 100. For example, when the sacrificial layer 115 is a semiconductor layer (e.g., a silicon-germanium layer), the temperature used when forming source / drain structures 150A and / or source / drain structures 150B can be limited to a lower temperature to avoid undesirable diffusion and / or mixing of the components of sacrificial layer 115 (e.g., germanium) with semiconductor layer 120. When forming source / drain structures 150A and / or source / drain structures 150B, replacing sacrificial layer 115 with a sacrificial oxide layer eliminates mixing problems (e.g., because these layers will not contain germanium) and allows for the use of higher temperatures, thereby enabling the use of a wider temperature range and increasing process flexibility.

[0090] This document provides numerous different embodiments, with exemplary methods including forming a source / drain recess; forming an insulating layer that partially fills the source / drain recess; treating the insulating layer with a nitrogen thermal treatment; and forming a doped semiconductor layer over the treated insulating layer. The insulating layer is formed at the bottom of the source / drain recess, and the doped semiconductor layer fills the remaining portion of the source / drain recess. In some embodiments, this method includes treating the insulating layer with a silicon implantation process prior to forming the doped semiconductor layer. In some embodiments, this method includes adjusting the parameters of the nitrogen thermal treatment to increase the thickness of the insulating layer to at least 3 nm. In some embodiments, this method includes adjusting the parameters of the nitrogen thermal treatment to reduce the etch rate of the insulating layer to a fluorine-based etchant. In some embodiments, this method includes forming an undoped semiconductor layer in the bottom of the source / drain recess prior to forming the insulating layer. In these embodiments, the insulating layer is formed over the undoped semiconductor layer, and the undoped semiconductor layer partially fills the source / drain recess.

[0091] In some embodiments, the step of forming an insulating layer includes forming a nitride layer, and the nitrogen thermal treatment is N2 annealing. In some embodiments, the nitrogen thermal treatment is a first nitrogen thermal treatment, and the method further includes forming a metal oxide mask over the treated insulating layer; treating the metal oxide mask with a second nitrogen thermal treatment; and removing the metal oxide mask before forming a doped semiconductor layer. In some embodiments, the step of forming a metal oxide mask includes forming an alumina mask, and the second nitrogen thermal treatment is N2 annealing. In some embodiments, the source / drain notch is located in a first device region, and the method includes forming a metal oxide mask over a source / drain structure, the source / drain structure being disposed in a second device region different from the first device region; removing the metal oxide mask from over the treated insulating layer before forming a doped semiconductor layer; and removing the metal oxide mask from over the source / drain structure after forming the doped semiconductor layer.

[0092] Another exemplary method includes forming a first source / drain notch in a first device region; forming a second source / drain notch in a second device region; forming a first source / drain structure in the first source / drain notch; and forming a second source / drain structure in the second source / drain notch. The step of forming the second source / drain structure includes forming an insulating layer in the second source / drain notch; forming a mask over the first source / drain structure after performing a first nitrogen thermal treatment on the insulating layer; and forming a doped semiconductor layer over the insulating layer after performing a second nitrogen thermal treatment on the mask. In some embodiments, this method includes performing a silicon implantation process on the insulating layer before forming the mask over the first source / drain structure. In some embodiments, the step of performing the first nitrogen thermal treatment includes increasing the thickness of the insulating layer. In some embodiments, the step of performing the first nitrogen thermal treatment includes performing a first N2 annealing, and the step of performing the second nitrogen thermal treatment includes performing a second N2 annealing.

[0093] In some embodiments, the first device region is a p-type transistor region and the second device region is an n-type transistor region. In some embodiments, the step of forming a mask includes: depositing an aluminum oxide layer over a first source / drain structure in the first device region and over an insulating layer in the second device region; and removing the aluminum oxide layer from the insulating layer in the second device region after performing a second nitrogen thermal treatment.

[0094] In some embodiments, the insulating layer is a first insulating layer; when the first insulating layer is formed, the first device region is unshielded, and the method includes forming a second insulating layer over the first source / drain structure when the first insulating layer is formed. In some embodiments, the insulating layer is a first insulating layer; the doped semiconductor layer is a first doped semiconductor layer. In these embodiments, the step of forming the first source / drain structure includes: forming a second insulating layer in the first source / drain recess; and forming a second doped semiconductor layer over the second insulating layer, wherein the second insulating layer is not subjected to nitrogen thermal treatment prior to forming the second doped semiconductor layer.

[0095] An exemplary device structure includes a first-type transistor (e.g., a p-type transistor) and a second-type transistor (e.g., an n-type transistor). The first-type transistor includes a first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer. The second-type transistor includes a second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer. The nitrogen concentration of the second insulating layer is greater than that of the first insulating layer, and the thickness of the second insulating layer is at least 3 nm. In some embodiments, the first source / drain structure further includes a third insulating layer, with the first doped epitaxial layer disposed between the third insulating layer and the first insulating layer, and the nitrogen concentration of the third insulating layer is greater than that of the first insulating layer. In some embodiments, the thickness of the third insulating layer is less than the thickness of the second insulating layer.

[0096] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that, include: A first type transistor includes a first source / drain structure, the first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer; and A second type transistor includes a second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer, wherein the thickness of the second insulating layer is at least 3 nm.

2. The semiconductor device structure as described in claim 1, characterized in that, The first source / drain structure further includes a third insulating layer, and the first doped epitaxial layer is disposed between the third insulating layer and the first insulating layer.

3. The semiconductor device structure as described in claim 2, characterized in that, The thickness of the third insulating layer is less than the thickness of the second insulating layer.

4. The semiconductor device structure as described in claim 2, characterized in that, It also includes a dielectric layer disposed above the first source / drain structure and the second source / drain structure.

5. The semiconductor device structure as described in claim 4, characterized in that, The dielectric layer contacts the third insulating layer.

6. The semiconductor device structure as described in claim 4, characterized in that, The dielectric layer contacts the second doped epitaxial layer of the second source / drain structure.

7. The semiconductor device structure according to any one of claims 1 to 6, characterized in that, The first source / drain structure and the second source / drain structure also include an undoped semiconductor layer located below the first insulating layer and the second insulating layer.

8. The semiconductor device structure as described in claim 7, characterized in that, It also includes a substrate, on which the first type transistor and the second type transistor are located.

9. The semiconductor device structure as described in claim 8, characterized in that, The undoped semiconductor layer extends into the substrate.

10. The semiconductor device structure as claimed in claim 9, characterized in that, A portion of the first insulating layer and a portion of the second insulating layer extend into the undoped semiconductor layer.

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