A semiconductor device

Abstract

The utility model provides a kind of semiconductor device, applied to semiconductor technical field.In the utility model, metal oxide layer is located between gate and substrate, and part is located above isolation trench or active region, to construct the gate of different structural shape by combining the different topography of isolation trench bottom, that is, the purpose of improving the performance and reliability of semiconductor device is achieved while proposing the new structure of semiconductor device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Semiconductor memory devices comprise numerous transistors; depending on the required performance (e.g., operating voltage and / or drive current), the transistors integrated in a semiconductor memory device are formed in various structures. For example, complementary mode (CMOS) device structures exist, in which NMOS and PMOS elements have metal gate electrodes with different conductivity types. However, due to limitations in process technology, existing semiconductor memory devices still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related semiconductor memory device components. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device to improve the performance and reliability of semiconductor devices.

[0004] To solve the above-mentioned technical problems, the first embodiment of this utility model provides a semiconductor device, including: a substrate, including a plurality of isolation trenches and an active region defined by the isolation trenches; A channel layer is located on the active region and extends laterally to a portion of the surface of the isolation trench; Multiple gates are located on the isolation trench and the active region, and each gate includes a gate layer and an insulating cap layer stacked sequentially from bottom to top; A metal oxide layer is located between the gate and the substrate, and partly above the isolation trench or the active region, wherein the metal oxide layer located above the isolation trench is in physical contact with the channel layer.

[0005] Furthermore, the isolation trench includes a first trench and a second trench, and the gate includes: The first gate is located on the first trench; The second gate is located on the second trench, and the bottom surface of the first gate is higher than the bottom surface of the second gate.

[0006] Furthermore, the second gate has an air gap, which is disposed between the insulating cap layer and the gate layer.

[0007] Furthermore, the gate layer includes a semiconductor layer and a metal layer stacked sequentially from bottom to top. The first width of the metal layer of the second gate in the horizontal direction is smaller than the second width of the semiconductor layer below it in the horizontal direction, and the second width of the semiconductor layer in the horizontal direction is smaller than the third width of the metal oxide layer below it in the horizontal direction.

[0008] Furthermore, the semiconductor device also includes a spacer wall, at least located on the sidewall of the gate, the spacer wall being in direct contact with the top surface of the underlying metal oxide layer and the semiconductor layer.

[0009] To address the aforementioned issues, the second embodiment of this utility model also provides a semiconductor device, comprising: a substrate, including a plurality of isolation trenches and an active region defined by the isolation trenches, wherein the isolation trenches include a first trench and a second trench; Multiple gates are located on the isolation trench, and each gate includes a gate layer and an insulating cap layer stacked sequentially from bottom to top; A metal oxide layer is located between the gate and the isolation trench, and covers the first trench and the second trench, and the bottom surface of the metal oxide layer located directly above the first trench is higher than the bottom surface of the metal oxide layer located directly above the second trench. The metal oxide layer conformally covers the top surface of the first trench, and the metal oxide layer also includes two ends located on the second trench, the ends extending away from the top surface of the substrate.

[0010] Furthermore, the gate layer includes two extensions located on the metal oxide layer, the extensions extending away from the top surface of the substrate, and the top surface of the extensions being higher than the top surface of the end.

[0011] Furthermore, the bottom surface of the insulating cover layer is lower than the top surface of the extension.

[0012] To address the aforementioned issues, the third embodiment of this utility model also provides a semiconductor device, comprising: a substrate, including a plurality of isolation trenches and an active region defined by the isolation trenches; Multiple gates are located on the isolation trench and the active region, and each gate includes a gate layer and an insulating cap layer stacked sequentially from bottom to top; The metal oxide layer includes a first portion located between the gate and the isolation trench, and a second portion covering the top surface of the isolation trench, wherein the top surface of the second portion is below the top surface of the substrate.

[0013] Furthermore, the first portion conformally covers the substrate surface, and the second portion includes two ends extending away from the substrate surface.

[0014] Furthermore, the second part is U-shaped.

[0015] Furthermore, the semiconductor device may also include: The channel layer, located on the active region, includes an extension extending laterally to a portion of the surface of the isolation trenches, the extension being in direct contact with the end of the second portion.

[0016] As described above, the semiconductor device in this embodiment includes a channel layer, multiple gates, and a metal oxide layer. The metal oxide layer is located between the gate and the substrate, and is partially located directly above the isolation trench or the active region. This allows for the construction of gates with different structural shapes by combining different morphologies of the isolation trench bottom. This is equivalent to laterally extending the width of the metal oxide layer, increasing the process window for forming the metal oxide layer, and avoiding electrical differences at different locations caused by etching the metal oxide layer. Therefore, this invention achieves the goal of improving the performance and reliability of semiconductor devices while proposing a new structure for them. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings: Figures 1-29 These are partial top views and corresponding partial cross-sectional views of the semiconductor device in the embodiments of this utility model, showing each step in the fabrication process; wherein, Figure 1 This is a schematic diagram of the structure of a semiconductor device after multiple isolation trenches, channel layers, metal oxide layers and gate material layers have been formed in an embodiment of the present invention. Figures 2-5 for Figure 1 Enlarged view of local structure A of the semiconductor device and its evolution diagram; Figures 6-10 for Figure 1 Enlarged view and evolution diagram of local structure B of the semiconductor device; Figure 11 This is a schematic diagram of the structure of the semiconductor device after a patterned photoresist layer has been formed in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of the semiconductor device after forming multiple discrete gates in an embodiment of this utility model; Figures 13-16 for Figure 12 Enlarged view of local structure A of the semiconductor device and its evolution diagram; Figures 17-19 for Figure 12 Enlarged view and evolution diagram of local structure B of the semiconductor device; Figure 20 This is a schematic diagram of the semiconductor device structure after the spacer wall is formed in an embodiment of this utility model; Figures 21-24 for Figure 20Enlarged view of local structure A of the semiconductor device and its evolution diagram; Figures 25-28 for Figure 20 Enlarged view of local structure B of the semiconductor device and its evolution diagram.

[0018] Figure 29 This is a schematic diagram of the structure of the semiconductor device in the embodiment of this utility model.

[0019] The attached figures are labeled as follows: 100 - Substrate, 101 - First region, 102 - Second region, AR - Active region, 110 - Isolation trench, 111 - First trench, 112 - Second trench, 113 - Third trench, 112a - First isolation sublayer of the second trench, 112b - Second isolation sublayer of the second trench, 112c - Third isolation sublayer of the second trench, 121 - Epitaxial layer, 122 - Channel layer, 130 - Metal oxide layer, 140 - Gate material layer, 141 - Semiconductor layer (gate layer) 142-Metal layer (gate layer), 143-Insulating cap layer, 101-First recess, 101a-First air gap, 102-Second air gap, 201-Second recess, 201a-Third air gap, 150-Patterned photoresist layer, 140a-First gate, 140b-Second gate, 160-Spacer wall, 161-First spacer wall, 162-Second spacer wall, 170-First dielectric layer, 180-Second dielectric layer, 190-Conductive plug, 200-Isolation layer.

[0020] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0021] To make the technical solutions and advantages of the embodiments of this utility model clearer, the technical solutions of this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this utility model are shown in the accompanying drawings, it should be understood that this utility model can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this utility model and to fully convey the scope of this utility model to those skilled in the art.

[0022] The present invention will be described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It is understood that the meanings of "on," "above," and "over" in the present invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0023] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0024] In the embodiments of this utility model, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of this utility model can be combined arbitrarily without conflict.

[0025] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this utility model may have other forms and is not limited to those described above. The following will further describe other embodiments or variations of the semiconductor device of this utility model. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the various embodiments of this utility model are designated with the same reference numerals to facilitate comparison between the embodiments.

[0026] Please refer to Figure 29 , Figure 29 This is a schematic diagram of the semiconductor device in an embodiment of the present invention. Figure 29As shown, the semiconductor device includes a substrate 100, a channel layer 122, a metal oxide layer 130, and multiple gates (140a, 140b). The substrate 100 includes a first region 101 and a second region 102, where the first region 101 is used to form an NMOS transistor, and the second region 102 is used to form a PMOS transistor. These two regions are exemplarily arranged adjacent to each other. Multiple isolation trenches (111, 112, 113) and multiple active regions AR defined by the isolation trenches are formed within the substrate 100. In this embodiment, the boundary between the first region 101 and the second region 101 can be separated by isolation trenches to distinguish different active regions. The multiple isolation trenches on the substrate 100 can be further divided into at least one first trench 111, at least one second trench 112, and at least one third trench 113; wherein, the first trench 111 is specifically located on the substrate 100 of the first region 101, while the second trench 112 and the third trench 113 can be specifically located on the substrate 100 of the second region 102, and the isolation trench located at the junction between the first region 101 and the second region 102 can be either the first trench 111 or the second trench 112. The first trench 111, the second trench 112, and the third trench 113 are all filled with insulating material, and the number and type of insulating material in each trench can be the same or different depending on their width in the direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). For example, in this embodiment, the first trench 111 and the second trench 112 are each provided with three layers of insulating material, while the third trench 113 is provided with only two layers of insulating material, but this is not a limitation. For example, in conjunction with... Figure 2 As shown, the second trench 112 may be provided with a first isolation sublayer 112a, a second isolation sublayer 112b, and a third isolation sublayer 112c sequentially along a vertical direction away from its inner sidewall. Similarly, the first trench 111 may also be provided with a first isolation sublayer (not shown), a second isolation sublayer (not shown), and a third isolation sublayer (not shown) stacked sequentially. Figure 6 As shown, the third trench 113 is provided with only a first isolation sublayer (not shown) and a second isolation sublayer (not shown) in sequence along the vertical direction away from its inner sidewall, but this is not the only limitation.

[0027] It should be noted that the top surfaces of the multilayer insulating materials in the first trench 111, the second trench 112, and the third trench 113 in the direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction) can have various combinations due to differences in the film deposition process, the width in the horizontal direction, and the materials and stacking methods of the different isolation sublayers. For example... Figure 4The top surfaces of the first isolation sublayer 112a, the second isolation sublayer 112b, and the third isolation sublayer 112c within the second trench 112 shown are all curved surfaces. Furthermore, the highest point of the top surface of the first isolation sublayer 112a is not lower than the highest point of the top surface of the third isolation sublayer 112c, but is higher than the highest point of the top surface of the second isolation sublayer 112b. For example... Figure 5 The top surfaces of the first isolation sublayer 112a, the second isolation sublayer 112b, and the third isolation sublayer 112c within the second trench 112 shown are also curved surfaces. However, the highest point of the top surface of the first isolation sublayer 112a is higher than the highest point of the top surface of the third isolation sublayer 112c, and lower than the highest point of the top surface of the second isolation sublayer 112b. The accompanying drawings in this embodiment are for reference only, and other combinations are within the protection scope of this utility model embodiment.

[0028] The channel layer 122 is located on the active region AR (i.e., substrate 100) of the second region 102 and extends laterally to a portion of the surface of the isolation trench (112 and / or 113) within the second region 102, for example, extending to the first isolation sublayer covering the inner side of the second trench 112; secondly, an epitaxial layer 121 may be further disposed between the channel layer 122 and the substrate 100 or the active region AR. The epitaxial layer 121, due to the different film deposition process and the different widths of the active region AR in the horizontal direction, can have a top surface that protrudes in an arc shape in the direction away from the surface of the substrate 100, and its maximum width in the horizontal direction is smaller than the width of the active region AR located below it in the horizontal direction. The bottom surface of the channel layer 122 conformally covers the epitaxial layer 121. Because the width of the channel layer 122 in the horizontal direction is greater than the width of the epitaxial layer 121 in the horizontal direction, the channel layer 122 not only covers the top surface of the epitaxial layer 121, but also wraps around its sidewalls. As a result, at least a portion of the bottom surface of the two sides of the channel layer 122 can extend to a portion of the top surface of the isolation trenches, such as the second trench 112 and the third trench 113, located on both sides of the active region AR.

[0029] The plurality of gates, located on the isolation trenches (111, 112, 113) and the active region AR, include at least one first gate 140a and at least one second gate 140b; wherein, the first gate 140a is located on the first trench 111 to serve as the gate structure of the NMOS transistor in the first region 101, and the second gate 140b is located on the second trench 112 to serve as the gate structure of the PMOS transistor in the second region 102, and the bottom surface of the first gate 140a is higher than the bottom surface of the second gate 140b; it should be understood that this embodiment also includes a third gate (not shown) located on the active region AR in the first region 101 and the second region 102, which can also serve as the gate structure of the NMOS transistor or the gate structure of the PMOS transistor, and the film structure and material of the third gate are the same as those of the first gate 140a and the second gate 140b. The gate (e.g., the first or third gate) comprises a gate layer stacked from bottom to top and an insulating capping layer 143 thereon. The gate layer comprises a semiconductor layer 141 and a metal layer 142 stacked from bottom to top. Specifically, the second gate 140b located on the second trench 112 has an air gap (a first air gap 101a, for example...). Figure 3 As shown), the air gap can be disposed between the insulating cover layer 143 and the metal layer 142 of the second gate 140b, or it can be disposed within the metal layer 142 of the second gate 140b (the second air gap 102, for example). Figure 4 (as shown) or disposed within the semiconductor layer 141 of the second gate 140b (second air gap 102, for example) Figure 5 As shown), of course, the second gate 140b located on the second trench 112 may also not have an air gap (the first recess 101 is filled, for example...). Figure 2 (as shown); while the second gate 140b located on the third trench 113 may not have an air gap (the second recess 201 is filled, for example, Figure 6 As shown), it may also have air gaps (third air gap 201a, third air gap 201c, third air gap 201d, for example). Figure 7 , Figures 9 to 10 As shown), the third air gap can be disposed within the semiconductor layer 141 in the second gate 140b, or between the semiconductor layer 141 and the underlying metal oxide layer 130; it can also be further disposed within the metal oxide layer 130 (the third air gap 201b, for example). Figure 8 (as shown in the figure). For example, the shape of the air gap may include an ellipse, a semicircle, or other irregular closed structure.

[0030] It should be noted that, based on the different shapes of the air gap within the second gate 140b, the width of the metal layer 142 within the second gate 140b provided in this embodiment, in the horizontal direction, can have various combinations with the width of the semiconductor layer 141 below it in the horizontal direction. For example... Figure 13 , Figure 14 The metal layer 142 of the second gate 140b shown has a first width in the horizontal direction that is smaller than the second width in the horizontal direction of the semiconductor layer 141 located below it, or for example... Figure 15 , Figure 16 The first width of the metal layer 142 of the second gate 140b shown is equal to the second width of the semiconductor layer 141 located below it in the horizontal direction. Furthermore, since the third trench 113 has a smaller width in the horizontal direction, the corresponding second gate 140b thereon may only have one of the semiconductor layer 141, the metal layer 142, and the insulating capping layer 143, for example... Figure 17 The diagram shows only a semiconductor layer 141. Of course, it may also lack materials such as the semiconductor layer 141, metal layer 142, and insulating capping layer 143, for example... Figure 18 , Figure 19 As shown, but not limited to.

[0031] The metal oxide layer 130 is located between the gate (including the first to third gates) and the substrate 100, and between the gate (e.g., the first gate 140a or the second gate 140b) and the isolation trench (e.g., the first trench 111 or the second trench 112 or the third trench 113), and is partially located directly above the isolation trench (the first to third trenches) or the active region AR; wherein the metal oxide layer 130 located directly above the isolation trench (the first to third trenches) is in physical contact with the corresponding channel layer 122, and the bottom surface of the metal oxide layer 130 located directly above the first trench 111 is higher than the bottom surface of the metal oxide layer 130 located directly above the second trench 112. Specifically, in this embodiment, a metal oxide layer 130 is disposed between the gate and the substrate 100 on the first region 101 and the second region 102. Since an epitaxial layer 121 and a channel layer 122 are disposed on the surface of the substrate 100 corresponding to the active region AR in the second region 102, the metal oxide layer 130 is located between the bottom of a portion of the gate (e.g., the third gate) and the channel layer 122 in the second region 102. This is different from the position of the metal oxide layer 130 on the first region 101, that is, in the first region 101, the metal oxide layer 130 is directly located between the first gate 140a and the substrate 100.

[0032] It should be noted that, based on the different shapes of the air gap within the second gate 140b, the width of the metal layer 142 within the second gate 140b provided in this embodiment, along with the width of the metal oxide layer 130 below it, can have various combinations, for example... Figure 13 , Figure 15 , Figure 17 The second width of the semiconductor layer 141 shown is smaller in the horizontal direction than the third width of the metal oxide layer 130 located below it, or for example... Figure 16 The second width of the semiconductor layer 141 shown in the horizontal direction is equal to, but not limited to, the third width of the metal oxide layer 130 located below it in the horizontal direction.

[0033] Furthermore, the semiconductor device in this embodiment also includes a spacer wall 160 and a plurality of conductive plugs 190; wherein, the spacer wall 160 is located on the sidewall of each of the gates (including the first to third gates) on the substrate 100, and the spacer wall 160 is in direct contact with the top surface of the corresponding metal oxide layer 130 or semiconductor layer 141 below it. Specifically, the spacer wall 160 may include a first spacer wall 161 conformally wrapped around the outer surfaces of the first gate 140a, the second gate 140b, and the third gate, and a second spacer wall 162 covering the sidewall of the first spacer wall 161. The conductive plugs 190 pass through the first dielectric layer 170 and the second dielectric layer 180 used to isolate the different gates and the conductive plugs 190, as well as the channel layer 122 and the epitaxial layer 121, and then directly contact the substrates 100 on both sides of each gate to electrically connect the source and drain electrodes (not shown) formed in the substrates 100 on both sides of each gate.

[0034] In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate or other suitable materials, but not limited thereto; the insulating material in the isolation trench can be a dielectric material, and suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but not limited thereto. Preferably, the insulating material in the first trench 111 and the second trench 112 is an ONO stacked layer. For example, the material of the first isolation sublayer 112a and the third isolation sublayer 112c is silicon oxide, while the material of the second isolation sublayer 112b is silicon nitride. The insulating material in the third trench 113 is an ON stacked layer, that is, the material of the O layer covering the inner sidewall of the third trench 113 is silicon oxide, while the N layer covering the O layer and filling the rest is silicon nitride. The material of the epitaxial layer 121 may be the same as that of the substrate 100, for example, a silicon-containing substrate (such as SiGe); the material of the channel layer 122 may be an insulating material such as silicon oxide (SiO2); the material of the semiconductor layer 141 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto; the material of the metal layer 142 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto; the insulating capping layer 143 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. For example, the semiconductor layer 141 is made of polycrystalline silicon, the metal layer 142 is made of tungsten (W), and the insulating capping layer 143 is made of silicon nitride (SiN). The metal oxide layer 130 is a high dielectric material or a compound, alloy, and / or composite layer of a metal material including tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), and tantalum (Ta), and is preferably titanium nitride.The first gap wall 161 and the second gap wall 162 are both made of insulating materials, such as silicon nitride or silicon oxide. The first dielectric layer 170 and the second dielectric layer 180 may be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The conductive plug 190 may be made of a metallic material, such as tungsten, but is not limited thereto.

[0035] It should be understood that "common shape" in this utility model refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0036] Those skilled in the art to which this invention pertains will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further description will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in each embodiment of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0037] In other embodiments of this utility model, the structure of the semiconductor device is generally the same as that of the semiconductor device in the foregoing embodiments, such as including a substrate 100, a channel layer 122, a metal oxide layer 130, and multiple gates (140a, 140b). The substrate 100 includes a first region 101 and a second region 102, in which a plurality of isolation trenches (111, 112, 113) and a plurality of active regions AR defined by the plurality of isolation trenches are formed, and the similarities will not be repeated here. The main difference between the semiconductor device of this embodiment and the previous embodiment is that the metal oxide layer 130 located between the gate and the isolation trench conformally covers the top surface of the first trench 111, and the portion located on the second trench 112 may include two ends, and the ends extend in a direction away from the top surface of the substrate 100. In some embodiments, the gate layer in the gate includes two extensions located on the metal oxide layer 130, the extensions extend in a direction away from the top surface of the substrate 100, and the top surface of the extensions is higher than the top surface of the ends, while the bottom surface of the insulating cap layer 143 is lower than the top surface of the extensions.

[0038] Those skilled in the art to which this invention pertains will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further description will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in each embodiment of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0039] The structure of the semiconductor device in another embodiment of this utility model is largely the same as that of the semiconductor device in the foregoing embodiment, including a substrate 100, a channel layer 122, a metal oxide layer 130, and multiple gates (140a, 140b). The substrate 100 includes a first region 101 and a second region 102, within which multiple isolation trenches (111, 112, 113) and multiple active regions AR defined by the multiple isolation trenches are formed. Similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the foregoing embodiment is that the metal oxide layer 130 includes a first portion located between the gates and the isolation trenches, and a second portion covering the top surface of the isolation trenches, wherein the top surface of the second portion is below the top surface of the substrate 100. Specifically, the first portion conformally covers the surface of the substrate 100, and the second portion includes two ends extending away from the surface of the substrate 100 and is U-shaped. In this configuration, the channel layer 122 located on the active region AR may include an extension that extends laterally to a portion of the surface of the isolation trench, and the extension is in direct contact with the end of the second portion.

[0040] In order to enable those skilled in the art to easily understand the semiconductor device in the first embodiment of the present invention, the present invention also provides a method for manufacturing the semiconductor device in the first embodiment of the present invention. The following will further explain the method for manufacturing the semiconductor device proposed in the embodiment of the present invention with reference to the various structural schematic diagrams in the manufacturing process.

[0041] Please refer to Figures 1 to 29 , Figures 1 to 29 These are partial top views and corresponding partial cross-sectional views of the semiconductor device in the embodiments of this utility model, showing each step in the fabrication process; wherein, Figure 1 This is a schematic diagram of the structure of a semiconductor device after forming multiple isolation trenches, channel layers, metal oxide layers, and gate material layers in an embodiment of this utility model. Figures 2-5 for Figure 1 Enlarged view of local structure A of the semiconductor device and its evolution diagram. Figures 6-10 for Figure 1 Enlarged view of local structure B of the semiconductor device and its evolution diagram. Figures 13-16 for Figure 12 Enlarged view of local structure A of the semiconductor device and its evolution diagram. Figures 17-19 for Figure 12 Enlarged view of local structure B of the semiconductor device and its evolution diagram. Figures 21-24 for Figure 20 Enlarged view of local structure A of the semiconductor device and its evolution diagram. Figures 25-28 for Figure 20Enlarged view of local structure B of the semiconductor device and its evolution diagram. Figure 29 This is a schematic diagram of the structure of the semiconductor device in the embodiment of this utility model.

[0042] like Figure 1As shown, a substrate 100 is first provided, and multiple trenches are formed in the substrate 100 using an etching process. Then, an insulating material (such as silicon oxide, silicon nitride, etc.) is filled in the multiple trenches using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to form multiple isolation trenches (111, 112, 113). The multiple isolation trenches (111, 112, 113) define multiple active regions AR in the substrate 100 and divide the substrate 100 into a first region 101 and a second region 102 that are arranged adjacently. Next, using deposition, etching, and other processes, an epitaxial layer 121 and a channel layer 122 are formed sequentially on the active region AR of the second region 102. Due to the different widths of the active region AR in the horizontal direction during the film deposition process, the top surface of the epitaxial layer 121 can be an arc shape protruding away from the surface of the substrate 100, and its maximum width in the horizontal direction is smaller than the width of the active region AR below it in the horizontal direction. The bottom surface of the channel layer 122 conformally covers the epitaxial layer 121. Because the width of the channel layer 122 in the horizontal direction is greater than the width of the epitaxial layer 121 in the horizontal direction, the channel layer 122 not only covers the top surface of the epitaxial layer 121, but also wraps around its sidewalls. As a result, at least part of the bottom surface of the two sides of the channel layer 122 can extend to part of the top surface of the isolation trenches, such as the second trench 112 and the third trench 113, located on both sides of the active region AR. Then, a metal oxide layer 130 and a gate material layer 140 are conformally formed on the substrate 100 after multiple isolation trenches are formed using a deposition process such as chemical vapor deposition. The gate material layer 140 may include a semiconductor layer 141, a metal layer 142, and an insulating capping layer 143 stacked sequentially from bottom to top, and the semiconductor layer 141 and the metal layer 142 may also be referred to as gate layers. The multiple isolation trenches may include at least one first trench 111, at least one second trench 112, and at least one third trench 113. The first trench 111 is specifically located on the substrate 100 in the first region 101, while the second trench 112 and the third trench 113 may be specifically located on the substrate 100 in the second region 102. The isolation trench located at the boundary between the first region 101 and the second region 102 may be either the first trench 111 or the second trench 112. The first trench 111, the second trench 112, and the third trench 113 are all filled with insulating material, and the number and type of insulating material in each trench can be the same or different depending on their width in the direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). For example, in this embodiment, the first trench 111 and the second trench 112 are each provided with three layers of insulating material, while the third trench 113 is provided with only two layers of insulating material, but this is not a limitation. For example, in conjunction with... Figure 2As shown, the second trench 112 may be provided with a first isolation sublayer 112a, a second isolation sublayer 112b, and a third isolation sublayer 112c sequentially along a vertical direction away from its inner sidewall. Similarly, the first trench 111 may also be provided with a first isolation sublayer (not shown), a second isolation sublayer (not shown), and a third isolation sublayer (not shown) stacked sequentially. Figure 6 As shown, the third trench 113 is provided with only a first isolation sublayer (not shown) and a second isolation sublayer (not shown) in sequence along the vertical direction away from its inner sidewall, but this is not the only limitation.

[0043] like Figures 2 to 5 As shown, due to the special characteristics of the width of the second trench 112 in the horizontal direction and the top surface shape of the ONO stacked layer inside it, there are instances in the enlarged view and its evolution diagram where there is no air gap within the gate material layer 140 located in a certain second trench 112, such as... Figure 2 As shown, no air gaps are formed between the U-shaped or concave semiconductor layer 141, metal layer 142, and insulating cap layer 143 in the gate material layer 140; however, air gaps exist in the gate material layer 140 within a certain second trench 112, for example... Figures 3 to 5 As shown, a first air gap 101a may exist between the metal layer 142 and the insulating cap layer 143 in the gate material layer 140, or a second air gap 102 may exist within the metal layer 142 or the semiconductor layer 141.

[0044] like Figures 6 to 10 As shown, due to the special characteristics of the width of the third trench 113 in the horizontal direction and the top surface shape of the ON stacked layer inside it, there are instances in the enlarged view and its evolution diagram where there is no air gap within the gate material layer 140 located in a certain third trench 113, such as... Figure 6 As shown, no air gaps are formed between the semiconductor layer 141 filled in the U-shaped metal oxide layer 130 in the gate material layer 140, and between the metal layer 142 and the insulating cap layer 143 covering the semiconductor layer 141; however, air gaps exist in the gate material layer 140 within a certain third trench 113, for example... Figures 7 to 10 As shown, a third air gap 201a may exist within the semiconductor layer 141 of the gate material layer 140, or a third air gap 201b may exist within the metal oxide layer 130, or a third air gap 201c may exist between the semiconductor layer 141 and the metal oxide layer 130. Figure 10 An isolation layer 200 is also formed in the third trench 113 shown. The specific formation method includes forming the isolation layer 200 in at least one third trench 113 using a deposition process such as chemical vapor deposition before forming the metal oxide layer 130. The material of the isolation layer 200 can be an insulating material such as silicon oxide or silicon nitride.

[0045] It should be noted that, as follows Figures 11 to 28 They are respectively in Figure 1 The semiconductor structure shown is further formed with discrete gates, spacers, dielectric layers, and conductive plugs. For each step, magnified views and evolution diagrams of local structure A and local structure B are displayed. However, regardless of the subsequent structure formed, it does not affect or change the process. Figures 2 to 10 The various combinations of local structures A and B shown will not be repeated below.

[0046] like Figure 11 As shown, following the steps above, in the formation Figure 1 Following the semiconductor structure shown, a patterned photoresist layer 150 can be further formed on the insulating capping layer 143 on top of the gate material layer 140 using a deposition process; wherein the patterned photoresist layer 150 includes a plurality of gate patterns for forming discrete gates.

[0047] like Figures 12 to 19 As shown, using the patterned photoresist layer 150 as a mask, the gate material layer 140, metal oxide layer 130, part of the channel layer 122, and part of the epitaxial layer 121 are vertically etched downwards to form multiple discrete gates on the substrate 100. Some of these gates are located on isolation trenches (111, 112, 113). In this embodiment, the gate located on the first trench 111 is specifically referred to as the first gate 140a, the gate located on the second trench 112 is referred to as the second gate 140b, and the gate located on the active region AR is referred to as the third gate (not labeled). In this embodiment, based on the different shapes of the air gap within the second gate 140b, the width of the metal layer 142 in the horizontal direction within the second gate 140b and the width of the semiconductor layer 141 below it can have various combinations, for example... Figure 13 , Figure 14 The metal layer 142 of the second gate 140b shown has a first width in the horizontal direction that is smaller than the second width in the horizontal direction of the semiconductor layer 141 located below it, or for example... Figure 15 , Figure 16 The first width of the metal layer 142 of the second gate 140b shown is equal to the second width of the semiconductor layer 141 located below it in the horizontal direction. Furthermore, since the third trench 113 has a smaller width in the horizontal direction, the corresponding second gate 140b thereon may only have one of the semiconductor layer 141, the metal layer 142, and the insulating capping layer 143, for example... Figure 17 The diagram shows only a semiconductor layer 141. Of course, it may also lack materials such as the semiconductor layer 141, metal layer 142, and insulating capping layer 143, for example... Figure 18 , Figure 19As shown, but not limited to.

[0048] like Figures 20 to 28 As shown, a deposition process can then be used to form gap walls 160 on the outer surfaces of the multiple discrete gates, and the gap walls 160 are in direct contact with the top surface of the corresponding metal oxide layer 130 or semiconductor layer 141 below the corresponding gate; wherein, the gap wall 160 may include a first gap wall 161 conformally wrapped on the outer surfaces of the first gate 140a, the second gate 140b and the third gate and a second gap wall 162 covering the sidewall of the first gap wall 161.

[0049] like Figure 29 As shown, a deposition process can be used to first form a first dielectric layer 170 that buries all the gates and a second dielectric layer 180 thereon; then, an etching process is used to form a plurality of vias in the second dielectric layer 180 and the first dielectric layer 170, wherein the bottom of the vias located in the first region 101 and the second region 102 are exposed on the substrate 100, but the vias located in the second region 102 need to pass through the second dielectric layer 180 and the first dielectric layer 170, and further pass through the channel layer 122 and the epitaxial layer 121 below them before being exposed on the substrate 100; then, a metal material such as tungsten is filled into each via to form a plurality of conductive plugs 190, realizing electrical connection between the source and drain electrodes (not shown) formed in the substrate 100 on both sides of each gate.

[0050] It should be understood that the process methods and steps involved in the embodiments of this utility model are only used to explain the semiconductor devices in this embodiment, and are all prior art.

[0051] In summary, the semiconductor device in this embodiment includes a channel layer, multiple gates, and a metal oxide layer. The metal oxide layer is located between the gate and the substrate, and is partially located directly above the isolation trench or the active region. This allows for the construction of gates with different structural shapes by combining different morphologies of the isolation trench bottom. This is equivalent to laterally extending the width of the metal oxide layer, increasing the process window for forming the metal oxide layer, and avoiding electrical differences at different locations caused by etching the metal oxide layer. Therefore, this invention achieves the goal of improving the performance and reliability of semiconductor devices while proposing a new structure for them.

[0052] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes multiple isolation trenches and an active region defined by the isolation trenches; A channel layer is located on the active region and extends laterally to a portion of the surface of the isolation trench; Multiple gates are located on the isolation trench and the active region, and each gate includes a gate layer and an insulating cap layer stacked sequentially from bottom to top; A metal oxide layer is located between the gate and the substrate, and partly above the isolation trench or the active region, wherein the metal oxide layer located above the isolation trench is in physical contact with the channel layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The isolation trench includes a first trench and a second trench, and the gate includes: The first gate is located on the first trench; The second gate is located on the second trench, and the bottom surface of the first gate is higher than the bottom surface of the second gate.

3. The semiconductor device as described in claim 2, characterized in that, The second gate has an air gap, which is disposed between the insulating cover layer and the gate layer.

4. The semiconductor device as described in claim 2, characterized in that, The gate layer includes a semiconductor layer and a metal layer stacked sequentially from bottom to top. The first width of the metal layer of the second gate in the horizontal direction is smaller than the second width of the semiconductor layer below it in the horizontal direction, and the second width of the semiconductor layer in the horizontal direction is smaller than the third width of the metal oxide layer below it in the horizontal direction.

5. The semiconductor device as claimed in claim 4, characterized in that, It also includes a spacer wall, at least located on the sidewall of the gate, which is in direct contact with the top surface of the underlying metal oxide layer and the semiconductor layer.

6. A semiconductor device, characterized in that, include: The substrate includes a plurality of isolation trenches and an active region defined by the isolation trenches, wherein the isolation trenches include a first trench and a second trench. Multiple gates are located on the isolation trench, and each gate includes a gate layer and an insulating cap layer stacked sequentially from bottom to top; A metal oxide layer is located between the gate and the isolation trench, and covers the first trench and the second trench, and the bottom surface of the metal oxide layer located directly above the first trench is higher than the bottom surface of the metal oxide layer located directly above the second trench. The metal oxide layer conformally covers the top surface of the first trench, and the metal oxide layer also includes two ends located on the second trench, the ends extending away from the top surface of the substrate.

7. The semiconductor device as claimed in claim 6, characterized in that, The gate layer includes two extensions located on the metal oxide layer, the extensions extending away from the top surface of the substrate, and the top surface of the extensions being higher than the top surface of the end.

8. The semiconductor device as claimed in claim 7, characterized in that, The bottom surface of the insulating cover is lower than the top surface of the extension.

9. A semiconductor device, characterized in that, include: The substrate includes multiple isolation trenches and an active region defined by the isolation trenches; Multiple gates are located on the isolation trench and the active region, and each gate includes a gate layer and an insulating cap layer stacked sequentially from bottom to top; The metal oxide layer includes a first portion located between the gate and the isolation trench, and a second portion covering the top surface of the isolation trench, wherein the top surface of the second portion is below the top surface of the substrate.

10. The semiconductor device as claimed in claim 9, characterized in that, The first portion conformally covers the substrate surface, and the second portion includes two ends extending away from the substrate surface.

11. The semiconductor device as claimed in claim 10, characterized in that, The second part is U-shaped.

12. The semiconductor device as claimed in claim 10, characterized in that, Also includes: The channel layer, located on the active region, includes an extension extending laterally to a portion of the surface of the isolation trenches, the extension being in direct contact with the end of the second portion.

Images