Semiconductor device structure

Abstract

A semiconductor device structure is described. The structure includes a first semiconductor layer disposed adjacent to a substrate portion and a second semiconductor layer disposed on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are different from one another. The structure further includes a dielectric layer disposed on the second semiconductor layer, a source / drain region disposed on the dielectric layer, an interlayer dielectric layer disposed over the source / drain region, and a first conductive feature disposed through the interlayer dielectric layer. The first conductive feature is electrically connected to the source / drain region.

Description

Technical Field

[0001] Some embodiments of this disclosure provide semiconductor device structures. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per wafer area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This scaling down generally benefits production efficiency and reduces associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, it is necessary to improve the handling and manufacturing of ICs. Utility Model Content

[0004] Some embodiments of this disclosure provide a semiconductor device structure including a first semiconductor layer, a second semiconductor layer, a dielectric layer, source / drain regions, an interlayer dielectric layer, a first conductive feature, a gate structure, and a contact etch-stop layer. The first semiconductor layer is disposed adjacent to a substrate portion. A second semiconductor layer is disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are distinct from each other. The dielectric layer is disposed on the second semiconductor layer. The source / drain regions are disposed on the dielectric layer. The interlayer dielectric layer is disposed above the source / drain regions. The first conductive feature extends through the interlayer dielectric layer, wherein the first conductive feature is electrically connected to the source / drain regions. The gate structure includes a gate dielectric layer and a spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall facing away from the gate structure. The contact etch-stop layer extends along and interfaces with the second sidewall of the spacer.

[0005] Some embodiments of this disclosure provide a semiconductor device structure including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first dielectric layer, a second dielectric layer, a first source / drain region, a second source / drain region, an interlayer dielectric layer, a first conductive feature, a gate structure, and a contact etch-stop layer. The first semiconductor layer is disposed in an N-type metal-oxide-semiconductor region. The second semiconductor layer is disposed in a P-type metal-oxide-semiconductor region, wherein the thickness of the second semiconductor layer is less than the thickness of the first semiconductor layer. The third semiconductor layer is disposed on the second semiconductor layer in the P-type metal-oxide-semiconductor region. The first dielectric layer is disposed on the first semiconductor layer in the N-type metal-oxide-semiconductor region. The second dielectric layer is disposed on the third semiconductor layer in the P-type metal-oxide-semiconductor region, wherein the top surface of the second dielectric layer is at the same level as the top surface of the first dielectric layer. The first source / drain region is disposed on the first dielectric layer in the N-type metal-oxide-semiconductor region. The second source / drain region is disposed on the second dielectric layer in the P-type metal-oxide-semiconductor region. The interlayer dielectric layer is disposed above the first source / drain region. A first conductive feature is disposed through the interlayer dielectric layer, wherein the first conductive feature is electrically connected to a first source / drain region. The gate structure includes a gate dielectric layer and a spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall opposite to the gate structure. A contact etch-stop layer extends along and interfaces with the second sidewall of the spacer.

[0006] Some embodiments of this disclosure provide a semiconductor device structure including a first semiconductor layer, a second semiconductor layer, a dielectric layer, source / drain regions, an interlayer dielectric layer, a first conductive feature, a gate structure, a contact etch-stop layer, and one or more semiconductor layers. The first semiconductor layer is disposed adjacent to a substrate portion. A second semiconductor layer is disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are different from each other. The dielectric layer is disposed on the second semiconductor layer. The source / drain regions are disposed on the dielectric layer. The interlayer dielectric layer is disposed above the source / drain regions. The first conductive feature passes through the interlayer dielectric layer, wherein the first conductive feature is electrically connected to the source / drain regions. The gate structure includes a gate dielectric layer and a spacer, the spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall opposite to the gate structure. The contact etch-stop layer extends along and interfaces with the second sidewall of the spacer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the spacer or the dielectric constant of the contact etch-stop layer. One or more semiconductor layers are in contact with the source / drain regions. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying items. Figure 1The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 ,and Figure 6 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments;

[0009] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G ,and Figure 7H It is according to some embodiments along Figure 6 A partial cross-sectional side view of the various stages of manufacturing a semiconductor device structure, taken by line AA.

[0010] Figure 8 This is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments;

[0011] Figure 9 , Figure 10 , Figure 11 It is according to some embodiments along Figure 8 The BB line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0012] [Symbol Explanation]

[0013] 100: Semiconductor Device Structure / Semiconductor Device

[0014] 101:Substrate

[0015] 102: Substrate portion

[0016] 104: Semiconductor layer stacking

[0017] 106: Semiconductor layer / First semiconductor layer

[0018] 108: Second semiconductor layer

[0019] 110: Masking Structure

[0020] 150: Semiconductor materials / semiconductor layers

[0021] 150t: Top surface

[0022] 151: Masking layer

[0023] 152: Semiconductor layer

[0024] 154: Semiconductor layer

[0025] 156: Dielectric layer

[0026] 158: Source / Drain Region / S / D Region

[0027] 202: Fins

[0028] 204: Trench

[0029] 302: N-type metal-oxide-semiconductor region / NMOS region

[0030] 304: P-type metal-oxide-semiconductor region / PMOS region

[0031] 402: Insulating material

[0032] 404: Sacrificial Gate Stack

[0033] 406: Sacrificial gate dielectric layer

[0034] 408: Sacrificial gate electrode layer

[0035] 410: Masking Structure

[0036] 412: Spacer

[0037] 414: Gap

[0038] 416: Dielectric spacer

[0039] 416b: Bottom surface

[0040] 502: Contact Etching Termination Layer / CESL

[0041] 504: Interlayer dielectric layer / ILD layer

[0042] 505: Gate Structure

[0043] 506: Gate dielectric layer

[0044] 508: Gate electrode layer

[0045] 510: Etching stop layer

[0046] 512: Interlayer dielectric layer / ILD layer

[0047] 514: Electrical conductivity characteristics

[0048] 516: Silicide layer

[0049] 518: Electrical conductivity characteristics

[0050] X: X-axis

[0051] Y: Y-axis

[0052] Z: Z-axis

[0053] D1, D2: Distance

[0054] AA: Line AA

[0055] BB: Line BB Detailed Implementation

[0056] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0057] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “top,” “upper,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0058] Figures 1 to 11 This illustrates the sequential process of manufacturing a semiconductor device structure 100 according to some embodiments. It should be understood that, with respect to additional embodiments of the method, [further details may be needed]. Figures 1 to 11 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be substituted or eliminated. The order of operations / processes is interchangeable.

[0059] Figures 1 to 6 These are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments. Figure 1As shown, a semiconductor layer stack 104 is formed over a substrate 101. The substrate 101 may be a semiconductor substrate. In some embodiments, the substrate 101 includes at least a crystalline semiconductor layer on the surface of the substrate 101. The substrate 101 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In this embodiment, the substrate 101 is made of Si. In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one example, the insulating layer is an oxide.

[0060] The substrate 101 may include one or more buffer layers (not shown) on its surface. The buffer layers can be used to gradually change the lattice constant from that of the substrate to the lattice constant of the source / drain (S / D) region to be grown on the substrate 101. The buffer layers may be formed of epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, Germanium-tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, and InP. In one embodiment, the substrate 101 includes a SiGe buffer layer epitaxially grown on a silicon substrate 101. The germanium concentration of the SiGe buffer layer may increase from 30 atomic percent germanium in the bottom buffer layer to 70 atomic percent germanium in the top buffer layer.

[0061] The substrate 101 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). Dopants include, for example, boron for p-type field-effect transistors (FETs) and phosphorus for n-type FETs.

[0062] The semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 is made of Si, and the second semiconductor layer 108 is made of SiGe. In one embodiment, the first semiconductor layer 106 is made of undoped Si. The second semiconductor layer 108 may be doped to improve the etch selectivity to the first semiconductor layer 106. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108, such as... Figure 1As shown. The first semiconductor layer 106 or a portion thereof may form nanostructure channels(s) of the semiconductor device structure 100 at a later stage. The semiconductor device structure 100 may include nanostructure transistors. The term nanostructure is used herein to refer to any portion of material having nanoscale or even microscale dimensions and having any suitable shape, such as an elongated shape, regardless of the cross-sectional shape of this portion. Thus, the term refers to elongated portions of material with circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped portions of material including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channels(s) of the semiconductor device structure 100 may be surrounded by a gate electrode layer. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode layer surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0063] It should be noted that, such as Figure 1 As shown, the three layers of the first semiconductor layer 106 and the four layers of the second semiconductor layer 108 are alternately arranged. This is for illustrative purposes and is not intended to limit the specific references in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104; the number of layers depends on the predetermined number of channels in the semiconductor device structure 100. In some embodiments, the number of first semiconductor layers 106 (i.e., the number of channels) is between 3 and 8. In some embodiments, the topmost second semiconductor layer 108 is absent.

[0064] As described in more detail below, the first semiconductor layer 106 may be used as a channel of the semiconductor device structure 100, and its thickness is selected based on device performance considerations. In some embodiments, each of the first semiconductor layers 106 has a thickness ranging from about 6 nanometers (nm) to about 12 nanometers. The second semiconductor layer 108 may eventually be removed and is used to define the vertical distance between adjacent channels of the semiconductor device structure 100; its thickness is selected based on device performance considerations. In some embodiments, each of the second semiconductor layers 108 has a thickness ranging from about 2 nanometers to about 10 nanometers.

[0065] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers in the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0066] A mask structure (not shown) can be formed over the semiconductor layer stack 104. The mask structure may include an oxygen-containing layer and a nitrogen-containing layer. The oxygen-containing layer may be a pad oxide layer, such as a SiO2 layer. The nitrogen-containing layer may be a pad nitride layer, such as Si3N4. The mask structure can be formed by any suitable deposition process, such as chemical vapor deposition (CVD).

[0067] Figure 2 This is a perspective view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. For example... Figure 2 As shown, fins 202 are formed. In some embodiments, each fin 202 includes a substrate portion 102 formed from a substrate 101, a portion of a semiconductor layer stack 104, and a portion of a mask structure 110. The fins 202 can be manufactured using suitable processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography with a self-aligned process, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fins 202 can then be patterned using the remaining spacers or mandrels by etching the semiconductor layer stack 104 and the substrate 101. Etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Figure 2 As shown, two fins 202 are formed, but the number of fins 202 is not limited to two.

[0068] In some embodiments, the fins 202 may be fabricated using suitable processes, including optical lithography and etching processes. The optical lithography process may include forming a photoresist layer (not shown) over a mask structure (not shown), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a patterned etchant. In some embodiments, an electron beam (e-beam) lithography process may be used to pattern the photoresist to form a patterned photoresist. The patterned photoresist may then be used to protect areas of the substrate 101 and layers formed thereon, while the etching process forms trenches 204 in unprotected areas that penetrate the mask structure 110, the semiconductor layer stack 104, and into the substrate 101, thereby leaving extended fins 202. The trenches 204 may be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof.

[0069] In some embodiments, the second semiconductor layer 108 is located on top of each fin 202, such as... Figure 2 As shown. In some embodiments, the first semiconductor layer 106 is located on top of each fin 202.

[0070] like Figure 2 As shown, an insulating material 402 is formed on substrate 101. The insulating material 402 may first be formed above substrate 101, such that fins 202 are embedded in the insulating material 402. Next, a planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is performed to expose the top of the fins 202 from the insulating material 402. Then, the insulating material 402 may be recessed by removing a portion of the insulating material 402 located between adjacent fins 202. The recess in the insulating material 402 may be formed by any suitable process, such as dry etching or wet etching, which selectively removes the insulating material 402 but does not remove the semiconductor material of the first semiconductor layer 106 and the second semiconductor layer 108. The recessed insulating material 402 may be shallow trench isolation (STI). The insulating material 402 includes a top surface that may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 102 of substrate 101.

[0071] The insulating material 402 may be made of oxygen-containing materials, such as silicon oxide or fluorosilicone glass (FSG); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-k dielectric materials; or any suitable dielectric material. The insulating material 402 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0072] like Figure 3 As shown, one or more sacrificial gate stacks 404 are formed on the semiconductor device structure 100. The sacrificial gate stack 404 may include a sacrificial gate dielectric layer 406, a sacrificial gate electrode layer 408, and a masking structure 410. The sacrificial gate dielectric layer 406 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer 406 may be deposited using CVD, sub-atmospheric CVD (SACVD), FCVD, ALD, PVD, or other suitable processes. The sacrificial gate electrode layer 408 may include polysilicon (polysilicon). The masking structure 410 may include an oxygen-containing layer and a nitrogen-containing layer.

[0073] The sacrificial gate stack 404 can be formed by first depositing a sacrificial gate dielectric layer 406, a sacrificial gate electrode layer 408, and a cover layer of the mask structure 410, followed by patterning and etching processes. The sacrificial gate dielectric layer 406, the sacrificial gate electrode layer 408, and the cover layer of the mask structure 410 can be formed using various processes, such as CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. Patterning processes include lithography processes (e.g., optical lithography or e-beam lithography), which may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. By patterning the sacrificial gate stack 404, the semiconductor layer stack 104 of the fin 202 is partially exposed on the opposite side of the sacrificial gate stack 404. For example... Figure 3As shown, two sacrificial gate stacks 404 are formed, but the number of sacrificial gate stacks 404 is not limited to two. In some embodiments, more than two sacrificial gate stacks 404 are configured along the X direction.

[0074] like Figure 3 As shown, spacers 412 are formed on the sidewalls of the sacrificial gate stack 404. Spacers 412 can be formed by depositing a conformal layer, which is then etched back to form the sidewall spacers 412. For example, a spacer material layer can be conformally disposed on an exposed surface of the semiconductor device structure 100. The conformal spacer material layer can be formed by an ALD process. Subsequently, anisotropic etching is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material is removed from horizontal surfaces (such as the top of fin 202 and the top of the sacrificial gate stack 404), leaving spacers 412 on vertical surfaces (such as the sidewalls of the sacrificial gate stack 404). Spacers 412 can be made of dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. In some embodiments, spacers 412 comprise multiple layers, such as a main spacer wall, a liner layer, and the like.

[0075] Next, as Figure 4 As shown, the exposed portion of fin 202 not covered by the sacrificial gate stack 404 and spacers 412 is recessed. Recessing the exposed portion of fin 202 can be performed by an etching process, such as dry etching, wet etching, or a combination thereof. In some embodiments, the exposed portion of the semiconductor layer stack 104 of fin 202 is removed, exposing a portion of the substrate portion 102. In some embodiments, a portion of the substrate portion 102 may also be removed. Figure 4 As shown, the exposed portion of the fin 202 is recessed below the top surface of the insulating material 402.

[0076] At this stage, the end portion of the semiconductor layer stack 104 below the sacrificial gate stack 404 and the spacer 412 have substantially flat surfaces that may be flush with the corresponding spacer 412. In some embodiments, the end portion of the semiconductor layer stack 104 below the sacrificial gate stack 404 and the spacer 412 are slightly horizontally etched.

[0077] like Figure 5 As shown, edge portions of each of the second semiconductor layers 108 are removed to form gaps 414. In some embodiments, portions of the second semiconductor layers 108 are removed by a selective wet etching process that does not remove the first semiconductor layer 106. For example, when the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, selective wet etching comprising a mixture of ammonia and hydrogen peroxide (APM) can be used.

[0078] like Figure 6 As shown, a dielectric spacer 416 is formed in the gap 414. In some embodiments, the dielectric spacer 416 may be made of SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the dielectric spacer 416 may be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacer 416. During the anisotropic etching process, the dielectric spacer 416 may be protected by the first semiconductor layer 106 and the spacer 412. In some embodiments, the dielectric spacer 416 may be flush with the spacer 412.

[0079] Figures 7A to 7H It is according to some embodiments along Figure 6 The image shows a partial cross-sectional side view of various stages of manufacturing the semiconductor device structure 100, taken from line AA. For clarity, Figures 7A to 7H The sacrificial gate stack 404 and spacer 412 are omitted. In some embodiments, the regions in the semiconductor device structure 100 that form n-type or p-type devices are referred to herein as "N-type metal-oxide-semiconductor (NMOS) regions" or "P-type metal-oxide-semiconductor (PMOS) regions," respectively. Figure 7A As shown, the semiconductor device 100 includes an NMOS region 302 and a PMOS region 304, which are located in Figure 6 The manufacturing stages are shown in the diagram.

[0080] Next, as Figure 7B As shown, a semiconductor layer 150 is formed on the exposed substrate portion 102 in the NMOS region 302 and the PMOS region 304. The semiconductor layer 150 may be formed adjacent to the substrate portion 102 located below the bottom second semiconductor layer 108, as shown. Figure 7B As shown. In some embodiments, semiconductor layer 150 comprises undoped silicon or undoped SiGe. Semiconductor layer 150 may first be formed on a semiconductor surface, such as on exposed substrate portion 102 and on semiconductor layer 106, by epitaxy. In some embodiments, semiconductor layer 150 is crystalline silicon or crystalline SiGe. A subsequent etching process is performed to remove portions of semiconductor layer 150 formed on first semiconductor layer 106. In some embodiments, semiconductor layer 150 formed on exposed substrate portion 102 may form convex surfaces in NMOS region 302 and PMOS region 304. In some embodiments, semiconductor layer 150 has a thickness ranging from about 5 nanometers to about 50 nanometers along the Z direction.

[0081] like Figure 7C As shown, a masking layer 151 is formed in the NMOS region 302 along the X-direction in the opening between adjacent semiconductor layer stacks 104, and the opening in the PMOS region 304 along the X-axis in the opening between adjacent semiconductor layer stacks 104 is enlarged. The masking layer 151 may comprise any suitable material. In some embodiments, the masking layer 151 is a bottom anti-reflective coating (BARC) layer. The masking layer 151 may fill the space between adjacent semiconductor layer stacks 104 in the NMOS region 302 and may be formed in the sacrificial gate stack 404 in the NMOS region 302. Figure 6 ) and spacers 412 ( Figure 6 Above. Next, an etching process is performed to widen the opening between adjacent semiconductor layer stacks 104 in the PMOS region 304 along the X direction. The etching process may be an isotropic etching process. In some embodiments, the etching process is a wet etching process. In some embodiments, the etching process utilizes an etchant that etches the semiconductor material at a rate faster than etching dielectric material. For example, the etchant may remove portions of the first semiconductor layer 106 and semiconductor layer 150, while the dielectric spacer 416 is substantially unaffected by the etchant. The etching process does not substantially affect the masking layer 151 formed in the NMOS region 302. Therefore, in some embodiments, as Figure 7C As shown, the distance D1 between adjacent first semiconductor layers 106 along the X-direction in PMOS region 304 is greater than the distance D2 between adjacent first semiconductor layers 106 along the X-axis direction in NMOS region 302. In some embodiments, the ratio of distance D1 to distance D2 is in the range of about 1.05:1 to about 1.2:1. In some embodiments, the source / drain regions 158 formed in NMOS region 302 ( Figure 7H The conductivity of ) is higher than that of the source / drain region 158 formed in PMOS region 304. Figure 7H The enlarged opening between adjacent semiconductor layer stacks 104 in PMOS region 304 causes the source / drain region 158 in PMOS region 304 to expand. As a result, the conductivity of the source / drain region 158 in PMOS region 304 increases to match the conductivity of the source / drain region 158 in NMOS region 302.

[0082] In some embodiments, such as Figure 7C As shown, an etching process that enlarges the opening between adjacent semiconductor layer stacks 104 removes a portion of semiconductor layer 150. In some embodiments, the thickness of semiconductor layer 150 is reduced by 2 nanometers to approximately 5 nanometers along the Z direction. As a result, the top surface 150t of semiconductor layer 150 in PMOS region 304 can be located below the bottom surface 416b of dielectric spacer 416, as... Figure 7C As shown. Furthermore, as... Figure 7C As shown, compared to the convex top surface of the semiconductor layer 150 in the NMOS region 302, the top surface 150t of the semiconductor layer 150 in the PMOS region 304 may be substantially flat or have a concave profile due to the etching process.

[0083] In some embodiments, the etching process laterally etches the first semiconductor layer 106 in the PMOS region 304, and the end portion of the first semiconductor layer 106 in the PMOS region 304 has a concave profile, such as... Figure 7C As shown, the first semiconductor layer 106 in NMOS region 302 is not exposed to the etching process. Therefore, the end portion of the first semiconductor layer 106 in NMOS region 302 has a convex profile, as shown... Figure 7C As shown.

[0084] Figure 7D , Figure 7E ,and Figure 7F The diagram illustrates the formation of a semiconductor layer 154 on the semiconductor layer 150 in the PMOS region 304. Figure 7F The semiconductor layer 154 can be formed using a multi-cycle deposition and etching process, which may be referred to as a multi-cycle deposition-etch process. In some embodiments, such as Figure 7D As shown, semiconductor layer 152 is deposited on the exposed surface of semiconductor device structure 100. Semiconductor layer 152 may be an amorphous semiconductor layer, such as an amorphous silicon layer. In subsequent processes (such as...) Figure 7E and Figure 7F During the process illustrated, amorphous semiconductor layers may be easier to process than crystalline semiconductor layers. In some embodiments, the amorphous silicon layer is undoped. Semiconductor layer 152 can be deposited by any suitable process. In some embodiments, semiconductor layer 152 is deposited by PECVD. For example, a silicon-containing precursor (such as SiH4) can be introduced into the processing chamber, and a silicon-containing plasma can be formed in the processing chamber. The plasma can be formed by any suitable method. In some embodiments, the plasma is capacitively coupled plasma (CCP), inductively coupled plasma (ICP), microwave-coupled plasma, or remote plasma. PECVD may have a first plasma frequency, such as less than about 30 MHz. In some embodiments, other gases, such as hydrogen (H2), may be co-flowed into the processing chamber with the precursor to enhance the properties of semiconductor layer 152. In some embodiments, semiconductor layer 152 is a hydrogenated amorphous silicon layer. The dangling bond defects in hydrogenated amorphous silicon layers are substantially smaller than those in unhydrogenated amorphous silicon layers.

[0085] Next, as Figure 7E As shown, an etching process is performed to remove the semiconductor layer 152 formed in the NMOS region 302 and a portion of the semiconductor layer 152 formed in the PMOS region 304. In some embodiments, the etching process is an in-situ etching process. For example, after depositing the semiconductor layer 152, the processing chamber is cleaned, and then an etchant is introduced into the processing chamber to remove the semiconductor layer 152 formed in the NMOS region 302 and a portion of the semiconductor layer 152 formed in the PMOS region 304. In some embodiments, the etchant is hydrogen (H2). In some embodiments, a carrier gas, such as He or Ar, may also flow with H2. The etching process may be a plasma etching process. In some embodiments, the plasma etching process utilizes a CCP and has a second plasma frequency substantially greater than a first plasma frequency. In some embodiments, the second plasma frequency is greater than about 30 MHz, such as from about 30 MHz to about 50 MHz, for example, 40 MHz. The higher the plasma frequency, the wider the ion angle, the lower the hydrogen ion energy, and the more hydrogen radicals. More hydrogen radicals and fewer hydrogen ions tend to perform a more isotropic etching process. As a result, portions of the first semiconductor layer 152 formed on the sidewalls of the NMOS region 302 and the PMOS region 304 are removed.

[0086] Furthermore, in some embodiments, the etching process utilizes pulsed plasma power to further limit the reach of hydrogen ions to the bottom of the opening between adjacent semiconductor layer stacks 104 in NMOS region 302 and PMOS region 304. The pulsed plasma power of the etching process reduces the energy of the hydrogen ions, resulting in a reduction in the number of hydrogen ions reaching the bottom of the opening between adjacent semiconductor layer stacks 104 in NMOS region 302 and PMOS region 304. In some embodiments, the pulsed plasma power has a pulse duty cycle of about 20% to about 80%, such as about 50%. In some embodiments, due to the reduced thickness of the semiconductor material 150 in PMOS region 304, the first aspect ratio of the opening between adjacent semiconductor layer stacks 104 in NMOS region 302 is smaller than the second aspect ratio of the opening between adjacent semiconductor layer stacks 104 in PMOS region 304. In some embodiments, the first aspect ratio is about 5.9 to about 6.1, while the second aspect ratio is about 6.2 to about 6.5. In other words, along the Z-direction, the portion of semiconductor layer 152 in PMOS region 304 at the bottom of the opening between adjacent semiconductor layer stacks 104 is at a level below the portion of semiconductor layer 152 in NMOS region 302 at the bottom of the opening between adjacent semiconductor layer stacks 104. Therefore, in some embodiments, the portion of semiconductor layer 152 at the bottom of the opening between adjacent semiconductor layer stacks 104 in both NMOS and PMOS regions 302 is etched back via a hydrogen radical gradient. As a result, the portion of semiconductor layer 152 at the bottom of the opening between adjacent semiconductor layer stacks 104 in NMOS region 302 is substantially removed, while the majority of the portion of semiconductor layer 152 at the bottom of the opening between adjacent semiconductor layer stacks 104 in PMOS region 304 remains. This is because the portion of semiconductor layer 152 located at the bottom of the opening between adjacent semiconductor layer stacks 104 in NMOS region 302 is located at a level substantially higher along the Z direction than the portion of semiconductor layer 152 located at the bottom of the opening between adjacent semiconductor layer stacks 104 in PMOS region 304.

[0087] In some embodiments, instead of plasma etching processes that utilize higher plasma frequencies and pulsed plasma power to reduce the number of hydrogen ions, other plasma etching processes can be performed. For example, a plasma etching process utilizing distal plasma can be performed to etch back semiconductor layer 154. Distal plasma generates far more hydrogen radicals than hydrogen ions. In this embodiment, the plasma frequency of the plasma etching process utilizing distal plasma can be the same as the plasma frequency of the PECVD process. Furthermore, the plasma power may not be pulsed. In some embodiments, a plasma etching process utilizing ICP with an ion filter is performed. The ion filter prevents hydrogen ions from contacting the semiconductor device structure 100. Similarly, the plasma frequency of the plasma etching process utilizing ICP with an ion filter can be the same as the plasma frequency of the PECVD process, and the plasma power may not be pulsed.

[0088] In respectively Figure 7D and Figure 7E The deposition and etching processes described herein can be one cycle in a multi-cycle deep-etch process for forming semiconductor layer 154. Figure 7F In some embodiments, the deposition rate of the semiconductor layer 152 in the NMOS region 302 is approximately 0.2 angstroms per cycle, while the deposition rate of the semiconductor layer 152 in the PMOS region 304 is approximately 1.5 angstroms per cycle.

[0089] Next, as Figure 7F As shown, semiconductor layers 154 are formed in NMOS region 302 and PMOS region 304 by repeating multiple cycles. Semiconductor layer 154 is the result of forming multiple semiconductor layers 152. In some embodiments, a dep-etch process is performed for approximately 20 cycles, resulting in a semiconductor layer 154 thickness of approximately 3 nanometers in PMOS region 304 and a semiconductor layer 154 thickness of approximately 0.4 nanometers in NMOS region 302. As described above, in some embodiments, the top surface of semiconductor layer 150 has a convex profile. Therefore, in some embodiments, semiconductor layer 154 is formed on the edge portion of semiconductor layer 150 in NMOS region 302, such as... Figure 7F As shown. In some embodiments, the top surface of the semiconductor layer 154 in the PMOS region 304 and the top surface of the semiconductor layer 150 in the NMOS region 302 are located at substantially the same level along the Z direction, as... Figure 7F As shown (dashed lines added to indicate the level of the top surface). In some embodiments, the top surface of semiconductor layer 154 is substantially flat, as... Figure 7F As shown. In some embodiments, due to a multi-cycle deep-etch process, the top surface of the semiconductor layer 154 is curved, such as having a concave profile.

[0090] In some embodiments, the sidewalls of the openings between adjacent semiconductor layer stacks 104 in NMOS region 302 and PMOS region 304 do not have semiconductor layers 154. Semiconductor layers 154 are formed at the bottom of the openings between adjacent semiconductor layer stacks 104 in PMOS region 304, while a small number of semiconductor layers 154 are formed at the bottom of the openings between adjacent semiconductor layer stacks 104 in NMOS region 302. Therefore, in some embodiments, semiconductor layers 154 are selectively formed in PMOS region 304 in a top-to-bottom manner.

[0091] Next, as Figure 7G As shown, a dielectric layer 156 is formed on semiconductor layers 150 and 154 in NMOS region 302 and on semiconductor layer 154 in PMOS region 304. The dielectric layer 156 can be formed by first forming the dielectric layer on an exposed surface of the semiconductor device structure 100, followed by one or more etching processes to remove portions of the dielectric layer other than the dielectric layer 156. A sacrificial layer (not shown), such as a bottom anti-reflective coating (BARC) layer, can be used to help remove portions of the dielectric layer formed on the sidewalls of the semiconductor layer stack 104. The dielectric layer 156 may include any suitable dielectric material. In some embodiments, the dielectric layer 156 includes SiN. The dielectric layer 156 can be formed by any suitable process. In some embodiments, the dielectric layer 156 is formed by CVD or PECVD.

[0092] In some embodiments, such as Figure 7G As shown, the top surface of the dielectric layer 156 in PMOS region 304 and the bottom surface of the dielectric layer 156 in NMOS region 302 are at the same level along the Z direction. In some embodiments, the dielectric layer 156 has a thickness ranging from about 5 nanometers to about 10 nanometers along the Z direction, such as about 7 nanometers. The combined thickness of the semiconductor layer 154 and dielectric layer 156 in PMOS region 304 can range from about 8 nanometers to about 12 nanometers, such as about 10 nanometers. In some embodiments, the top surface of the dielectric layer 156 is located at a level above the centerline of the dielectric spacer 416 along the Z direction, such as at a level above the top surface of the dielectric spacer 416. With the combination of semiconductor layer 154 and dielectric layer 156 formed over the recessed semiconductor layer 150 in PMOS region 304, the risk of exposing the substrate portion 102 in the opening between adjacent semiconductor layer stacks 104 along the X direction is greatly reduced. As a result, source / drain region current leakage is reduced. In some embodiments, as Figure 7G As shown, the combined thickness of semiconductor layer 154 and dielectric layer 156 in PMOS region 304 is greater than the combined thickness of semiconductor layer 154 and dielectric layer 156 in NMOS region 302.

[0093] like Figure 7H As shown, source / drain (S / D) regions 158 are formed from the first semiconductor layer 106. S / D regions 158 can be grown vertically and horizontally to form facets that correspond to crystal planes of the material used in the first semiconductor layer 106. In this disclosure, source and drain regions are used interchangeably and have substantially the same structure. Furthermore, source / drain regions can refer individually or collectively to either the source or the drain, depending on the context. S / D regions 158 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs, or of one or more layers of Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, p-type dopants, such as boron (B), can also be included in S / D regions 146. S / D regions 146 can be formed using epitaxial growth methods such as CVD, ALD, or MBE. In some embodiments, the S / D region 158 is first formed in the PMOS region 304, while the NMOS region 302 is covered by a sacrificial layer. Then, during the formation of the S / D region 158 in the NMOS region 302, the S / D region 158 formed in the PMOS region 304 is covered by the sacrificial layer. As described above, by combining the semiconductor layer 154 and the dielectric layer 156 in the PMOS region 304, the risk of the S / D region 158 contacting the substrate portion 102 is reduced.

[0094] Figure 8 According to some embodiments Figure 7H The semiconductor device structure 100 shown is a perspective view. Figure 8 The diagram illustrates the semiconductor device structure 100 within PMOS region 304. (See diagram for reference.) Figure 8 As shown, semiconductor layer 150, semiconductor layer 154, dielectric layer 156, and S / D region 158 are formed above each substrate portion 102 in each fin 202. As described above, in some embodiments, semiconductor layer 150 comprises undoped crystalline silicon, semiconductor layer 154 comprises undoped amorphous silicon, and S / D region 158 comprises doped crystalline Si or SiGe.

[0095] Figure 9 , Figure 10 ,and Figure 11 According to some embodiments along Figure 8 The image shows a cross-sectional side view of the various stages of manufacturing the semiconductor device structure 100, taken from line BB. After the S / D region 158 is formed, subsequent processes can be performed to complete the semiconductor device structure 100. For example, a contact etch stop layer (CESL) 502 can be formed on the S / D region 158, and an interlayer dielectric (ILD) layer 504 can be formed on the CESL 502, such as... Figure 9As shown. CESL 502 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxide carbon, the like, or combinations thereof. CESL 502 may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, CESL 502 is a conformal layer formed by an ALD process. The material used for ILD layer 504 may comprise tetraethoxysilane (TEOS), silicon-free glass, or oxides formed from doped silicon oxide, such as boro-phospho-silicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. ILD layer 504 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 504, the semiconductor device structure 100 may undergo a thermal process to anneal the ILD layer 504.

[0096] Next, the sacrificial gate stack 404 and the second semiconductor layer 108 are removed to form a gate dielectric layer 506 and a gate electrode layer 508 surrounding the exposed portion of the first semiconductor layer 106, such as... Figure 9As shown. The sacrificial gate electrode layer 408 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 406, which can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 408. Removal of the second semiconductor layer 108 exposes the dielectric spacer 416 and the first semiconductor layer 106. Removal of the second semiconductor layer 108 can be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. The etching process can be a selective etching process. In some embodiments, the gate dielectric layer 506 comprises a high-k dielectric material, such as a dielectric material having a K value greater than 9. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiN, HfTaO, HfTiO, HbZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the dielectric constant of the gate dielectric layer 506 is greater than the dielectric constant of the spacer 412 or the dielectric constant of CESL 502. The gate dielectric layer 506 can be formed by any suitable process, such as ALD. A gate electrode layer 508 is formed on the gate dielectric layer 506 to surround a portion of each of the first semiconductor layers 106. The gate electrode layer 508 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 508 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, the gate electrode layer 508, the gate dielectric layer 506, and the spacer 412 are collectively referred to as the gate structure 505.

[0097] like Figure 10 As shown, an etch stop layer 510 and another ILD layer 512 are formed above the ILD layer 504 and the gate electrode layer 508. The etch stop layer 510 may include the same material as CESL 502, and the ILD layer 512 may include the same material as ILD layer 504. Figure 11As shown, in some embodiments, a conductive feature 514 is formed in the ILD layer 512, the etch stop layer 510, the ILD layer 504, and the CESL 502, and a silicide layer 516 is formed between the conductive feature 514 and the S / D region 158. The conductive feature 514 is electrically connected to the S / D region 158. The conductive feature 514 may include any suitable conductive material. In some embodiments, the conductive feature 514 may include tungsten (W), platinum (Pt), tantalum (Ta), titanium (Ti), copper (Cu), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), or other suitable metals. The silicide layer 516 may include any suitable material, such as titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, copper silicide, or molybdenum silicide. A conductive feature 518 is formed in the ILD layer 512 and the etch stop layer 510, and the conductive feature 518 is electrically connected to the gate electrode layer 508. The conductive feature 518 may include any suitable conductive material. In some embodiments, conductive feature 518 comprises the same material as conductive feature 514. In some embodiments, conductive feature 518 and conductive feature 514 comprise different materials. Conductive features 514 and 518 may be formed simultaneously or at different times.

[0098] This disclosure provides a semiconductor device structure 100 in various embodiments, including a semiconductor layer 150, a semiconductor layer 154 disposed on the semiconductor layer 150, and a dielectric layer 156 disposed on the semiconductor layer 154. Some embodiments offer advantages. For example, the combined thickness of the semiconductor layer 154 and the dielectric layer 156 covers a substrate portion 102, which prevents current leakage in the source / drain regions.

[0099] One embodiment is a semiconductor device structure. The semiconductor device structure includes a first semiconductor layer disposed adjacent to a substrate portion and a second semiconductor layer disposed on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are different from each other. The structure further includes a dielectric layer disposed on the second semiconductor layer, source / drain regions disposed on the dielectric layer, an interlayer dielectric layer disposed above the source / drain regions, and a first conductive feature disposed through the interlayer dielectric layer. The first conductive feature is electrically connected to the source / drain regions. The structure further includes a gate structure, the gate structure including a gate dielectric layer and a spacer, the spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall facing away from the gate structure. The structure further includes a contact etch-stop layer extending along and interfaced with the second sidewall of the spacer, the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the spacer or the dielectric constant of the contact etch-stop layer.

[0100] In some embodiments, the first semiconductor layer comprises a crystalline semiconductor material, and the second semiconductor layer comprises an amorphous semiconductor material. In some embodiments, the first semiconductor layer comprises undoped crystalline silicon, and the second semiconductor layer comprises undoped amorphous silicon. In some embodiments, the semiconductor device structure further comprises one or more semiconductor layers in contact with the source / drain regions. In some embodiments, the gate structure further comprises a gate electrode layer surrounding a portion of each of the one or more semiconductor layers. In some embodiments, the semiconductor device structure further comprises a dielectric spacer disposed between the gate electrode layer and the dielectric layer. In some embodiments, the top surface of the dielectric layer is positioned above the top surface of the dielectric spacer.

[0101] Another embodiment is a semiconductor device structure. The semiconductor device structure includes a first semiconductor layer disposed in an NMOS region and a second semiconductor layer disposed in a PMOS region. The thickness of the second semiconductor layer is less than the thickness of the first semiconductor layer. The structure further includes a third semiconductor layer disposed on the second semiconductor layer in the PMOS region, a first dielectric layer disposed on the first semiconductor layer in the NMOS region, and a second dielectric layer disposed on a third conductor layer in the PMOS region. The top surface of the second dielectric layer is located at the same level as the top surface of the first dielectric layer. The structure further includes a first source / drain region disposed on the first dielectric layer in the NMOS region, a second source / drain region disposed on the second dielectric layer in the PMOS region, an interlayer dielectric layer disposed above the first source / drain region, and a first conductive feature disposed through the interlayer dielectric layer. The first conductive feature is electrically connected to the first source / drain region. The structure further includes a gate structure, the gate structure including a gate dielectric layer and a spacer, the spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall facing away from the gate structure. The structure further includes a contact etch-stop layer extending along and interfacing with the second sidewall of the spacer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the spacer or the dielectric constant of the contact etch-stop layer.

[0102] In some embodiments, the semiconductor device structure further includes a fourth semiconductor layer disposed between a first semiconductor layer and a first dielectric layer in an N-type metal-oxide-semiconductor region. In some embodiments, the top surface of the first semiconductor layer has a convex profile, and the fourth semiconductor layer is disposed on multiple edge portions of the top surface of the first semiconductor layer. In some embodiments, the top surface of the third semiconductor layer is flat. In some embodiments, the top surface of the third semiconductor layer is at the same level as the top surface of the first semiconductor layer. In some embodiments, the first and second semiconductor layers each comprise a crystalline semiconductor material, and the third semiconductor layer comprises an amorphous semiconductor material. In some embodiments, the first and second semiconductor layers each comprise undoped crystalline silicon, and the third semiconductor layer comprises undoped amorphous silicon.

[0103] A further embodiment is a method of manufacturing a semiconductor device structure. The method includes forming a stack of a first semiconductor layer and a second semiconductor layer; forming a sacrificial gate stack over a portion of the stack of the first semiconductor layer and the second semiconductor layer; removing an exposed portion of the stack of the first semiconductor layer and the second semiconductor layer to expose a substrate portion; depositing a third semiconductor layer over the substrate portion; removing a portion of the third semiconductor layer in a PMOS region; forming a fourth semiconductor layer on the third semiconductor layer in the PMOS region; depositing dielectric layers on the fourth semiconductor layer in the PMOS region and the third semiconductor layer in the NMOS region; and forming a plurality of source / drain regions over the dielectric layers in the PMOS region and the NMOS region.

[0104] In some embodiments, a fourth semiconductor layer is deposited on the third semiconductor layer within an N-type metal-oxide-semiconductor region. In some embodiments, the deposition rate of the fourth semiconductor layer in the P-type metal-oxide-semiconductor region is faster than the deposition rate of the fourth semiconductor layer in the N-type metal-oxide-semiconductor region. In some embodiments, the fourth semiconductor layer is formed in both the P-type and N-type metal-oxide-semiconductor regions using a multi-cycle deposition-etch process. In some embodiments, the multi-cycle deposition-etch process includes a plasma-enhanced chemical vapor deposition process and a plasma etching process. In some embodiments, the plasma frequency of the plasma-enhanced chemical vapor deposition process is lower than the plasma frequency of the plasma etching process.

[0105] A further embodiment provides a semiconductor device structure. The semiconductor device structure includes a first semiconductor layer disposed adjacent to a substrate portion and a second semiconductor layer disposed on the first semiconductor layer. The structure further includes a dielectric layer disposed on the second semiconductor layer, a source / drain region disposed on the dielectric layer, an interlayer dielectric layer disposed above the source / drain regions, and a first conductive feature disposed through the interlayer dielectric layer. The first conductive feature is electrically connected to the source / drain regions. The structure further includes a gate structure, the gate structure including a gate dielectric layer and a spacer, the spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall facing away from the gate structure. The structure further includes a contact etch-stop layer extending along and interfaced with the second sidewall of the spacer, the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the spacer or the dielectric constant of the contact etch-stop layer. The structure further includes one or more semiconductor layers in contact with the source / drain regions.

[0106] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, Include: A first semiconductor layer is disposed adjacent to a substrate portion; A second semiconductor layer is disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are different from each other; A dielectric layer is disposed on the second semiconductor layer; A source / drain region is disposed on this dielectric layer; An interlayer dielectric layer is disposed above the source / drain region; A first conductive feature passes through the interlayer dielectric layer, wherein the first conductive feature is electrically connected to the source / drain region; A gate structure comprising: A gate dielectric layer; and A spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall facing away from the gate structure; and A contact etch termination layer extends along the second sidewall of the spacer and interfaces with the second sidewall.

2. The semiconductor device structure as described in claim 1, characterized in that, It further includes one or more semiconductor layers in contact with the source / drain region.

3. The semiconductor device structure as described in claim 2, characterized in that, The gate structure further includes a gate electrode layer surrounding a portion of each of the one or more semiconductor layers.

4. The semiconductor device structure as described in claim 3, characterized in that, It further includes a dielectric spacer disposed between the gate electrode layer and the dielectric layer.

5. A semiconductor device structure, characterized in that, Include: A first semiconductor layer is disposed in an N-type metal-oxide-semiconductor region; A second semiconductor layer is disposed in a P-type metal-oxide-semiconductor region, wherein the thickness of the second semiconductor layer is less than the thickness of the first semiconductor layer; A third semiconductor layer is disposed on the second semiconductor layer in the P-type metal-oxide-semiconductor region; A first dielectric layer is disposed on the first semiconductor layer in the N-type metal-oxide-semiconductor region; A second dielectric layer is disposed on the third semiconductor layer in the P-type metal-oxide-semiconductor region, wherein a top surface of the second dielectric layer is located at the same level as a top surface of the first dielectric layer; A first source / drain region is disposed on the first dielectric layer in the N-type metal-oxide-semiconductor region; A second source / drain region is disposed on the second dielectric layer in the P-type metal-oxide-semiconductor region; An interlayer dielectric layer is disposed above the first source / drain region; A first conductive feature is disposed through the interlayer dielectric layer, wherein the first conductive feature is electrically connected to the first source / drain region; A gate structure comprising: A gate dielectric layer; and A spacer having a first sidewall interfaced with the gate dielectric layer and a second sidewall facing away from the gate structure; and A contact etch termination layer extends along the second sidewall of the spacer and interfaces with the second sidewall.

6. The semiconductor device structure as described in claim 5, characterized in that, It further includes a fourth semiconductor layer disposed between the first semiconductor layer and the first dielectric layer in the N-type metal-oxide-semiconductor region.

7. The semiconductor device structure as described in claim 6, characterized in that, The first semiconductor layer has a convex profile on its top surface, and the fourth semiconductor layer is disposed on a plurality of edge portions of the top surface of the first semiconductor layer.

8. The semiconductor device structure as described in claim 5, characterized in that, One of the top surfaces of the third semiconductor layer is flat.

9. The semiconductor device structure as described in claim 5, characterized in that, The top surface of the third semiconductor layer is located at the same level as the top surface of the first semiconductor layer.

10. A semiconductor device structure, characterized in that, Include: A first semiconductor layer is disposed adjacent to a substrate portion; A second semiconductor layer is disposed on the first semiconductor layer; A dielectric layer is disposed on the second semiconductor layer; A source / drain region is disposed on this dielectric layer; An interlayer dielectric layer is disposed above the source / drain region; A first conductive feature passes through the interlayer dielectric layer, wherein the first conductive feature is electrically connected to the source / drain region; A gate structure comprising: A gate dielectric layer; and A spacer having a first sidewall that interfaces with the gate dielectric layer and a second sidewall that faces away from the gate structure; A contact etch termination layer extends along and interfaces with the second sidewall of the spacer, and One or more semiconductor layers are in contact with the source / drain region.

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