Semiconductor device

Abstract

A semiconductor device includes a substrate having a (110) crystal orientation, a nanostructure stack located above the substrate, and source / drain regions located on opposite sides of the nanostructure stack. Each source / drain region includes a first semiconductor layer located on an end of a nanostructure in the nanostructure stack, where the first semiconductor layer has a triangular geometry when viewed from a cross-sectional view. Each source / drain region also includes a second semiconductor layer located on the first semiconductor layer, where the second semiconductor layer has a greater germanium concentration than the first semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to the source / drain regions of semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication of semiconductor devices typically involves depositing insulating or dielectric layers, conductive layers, and semiconductor layers sequentially on a semiconductor substrate, and using lithography to pattern the multiple material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems also arise that need to be addressed. Utility Model Content

[0004] In one embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures above the substrate, and source / drain regions on opposite sides of the nanostructure stack. Each source / drain region includes a first semiconductor layer located at the end of a nanostructure in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed in cross-section. Each source / drain region also includes a second semiconductor layer located on the first semiconductor layer, the second semiconductor layer having a greater germanium concentration than the first semiconductor layer.

[0005] In another embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures above the substrate, and source / drain regions on opposite sides of the nanostructure stack. Each source / drain region includes a first semiconductor layer located at the end of a nanostructure in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed in cross-section. The semiconductor device further includes a third semiconductor layer located at the end of a nanostructure in the lower portion of the nanostructure stack, the third semiconductor material having a quadrilateral geometry when viewed in cross-section.

[0006] In another embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures above the substrate, and p-type source / drain regions on opposite sides of the nanostructure stack. Each p-type source / drain region includes a first semiconductor layer located at the end of a nanostructure in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed in cross-section. Each p-type source / drain region also includes a second semiconductor layer located on the first semiconductor layer, the second semiconductor layer having a higher germanium concentration than the first semiconductor layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A three-dimensional view of an example nanostructure field-effect transistor (nano-FET) is illustrated according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B and Figure 18C This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments.

[0010] [Symbol Explanation]

[0011] 20: Separator line

[0012] 50:Substrate

[0013] 50N: n-type region

[0014] 50P:p-type area

[0015] 51A, 51B, 51C: First semiconductor layer

[0016] 52A, 52B, 52C: First Nanostructures

[0017] 53A, 53B, 53C: Second semiconductor layer

[0018] 54: Second Nanostructure / Nanostructure

[0019] 54A, 54B, 54C: Second nanostructures

[0020] 55: Nanostructures

[0021] 58: Trench

[0022] 64: Multi-layer stacking

[0023] 66: Fins

[0024] 68: Shallow trench isolation area

[0025] 70: Virtual gate dielectric

[0026] 71: Sacrificial Material Layer

[0027] 72: Sacrificial Materials

[0028] 76: Virtual Gate

[0029] 78: Mask

[0030] 81: Gate spacer

[0031] 83: Fin spacers

[0032] 86: First Groove

[0033] 90: Inner spacer

[0034] 92: Source / Drain Region

[0035] 94: Contact Etching Stop Layer

[0036] 96: First interlayer dielectric layer

[0037] 98: Second groove

[0038] 100: Gate dielectric layer

[0039] 102: Gate electrode / gate structure

[0040] 104: Gate Mask

[0041] 106: Second interlayer dielectric layer

[0042] 108: Third Groove

[0043] 114: Contact element

[0044] 118: Contact element

[0045] 192: First Semiconductor Material

[0046] 192′: Basement

[0047] 192a: Third Semiconductor Material

[0048] 193: Second Semiconductor Material

[0049] 194: Interface Semiconductor Materials

[0050] AA′,BB′,CC′: lines

[0051] T1, T2: Thickness

[0052] α: Vertex angle

[0053] β: Base angle Detailed Implementation

[0054] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0055] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0056] For example, the performance of p-type semiconductor devices, such as p-type field-effect transistors (including p-type nanostructure devices with a gate all-around (GAA) gate structure), can be highly correlated with hole mobility. Substrate orientation and fin orientation can also affect hole mobility and thus increase device performance. <110> The substrate orientation and fin direction of / (001) are usually greater than <110> The substrate orientation and fin orientation of (110) have lower hole mobility. In several embodiments, the methods and structures described herein are applied to the (110) substrate to provide improved charge carrier mobility and provide further advantageous performance by controlling the epitaxial deposition shape in the p-type metal-oxide-semiconductor (PMOS) source / drain regions on the (110) substrate. For example, the shape of the epitaxial deposition material in the source / drain regions can be controlled into a triangular geometry by adjusting the process conditions of the epitaxial growth process. By controlling the shape of the epitaxial material, the contact surface of the metal contacts in the source / drain regions can be maximized, thus allowing the metal contacts to be seated on the epitaxial material with a high germanium concentration. In some embodiments, a larger contact area on the high-germanium-concentration portion of the p-type epitaxial material in the source / drain regions can result in lower contact resistance.

[0057] The following embodiments are described in the specific text concerning a die including a nano-FET. However, the content herein can be applied to various embodiments, such as dies that are alternatives to or incorporate nano-FETs and include other types of transistors (e.g., transistor stacks or the like).

[0058] Figure 1 Three-dimensional views of example nano-FETs (e.g., nanowire field-effect transistors, nanosheet field-effect transistors, or similar) are illustrated according to some embodiments. For ease of illustration, in Figure 1Specific features are simplified and / or omitted. A nano-FET includes a nanostructure 54 (e.g., nanosheet, nanowire, or similar) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 54 serves as a channel region for the nano-FET. The nanostructure 54 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation regions 68 (also referred to as shallow trench isolation (STI) structures or STI regions) are disposed between adjacent fins 66, wherein the fins 66 may protrude from between adjacent shallow trench isolation regions 68 above the shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are described / drawn herein as being separated from the substrate 50, the term "substrate" may represent the semiconductor substrate itself or a combination of the semiconductor substrate and the isolation region. Furthermore, although the bottom of the fins 66 is drawn as being a single continuous material with respect to the substrate 50, the bottom of the fins 66 and / or the substrate 50 may include a single material or multiple materials. In this document, fin 66 represents the portion extending between adjacent shallow trench isolation regions 68.

[0059] A gate dielectric layer 100 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surface of the nanostructure 54. A gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 located on opposite sides of the gate dielectric layer 100 and the gate electrode 102. According to the text, the source / drain regions 92 may individually represent the source or drain, or collectively represent both the source and drain.

[0060] Figure 1 Further illustrations show the reference cross sections used in the following figures. Cross section AA′ is along the longitudinal axis of the gate electrode 102 and, for example, along the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section BB′ is perpendicular to cross section AA′, parallel to the longitudinal axis of the nano-FET fin 66, and along, for example, along the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section CC′ is parallel to cross section AA′ and extends through the epitaxial source / drain regions of the nano-FET. For clarity, these reference cross sections will be referenced in the following figures.

[0061] Some embodiments discussed herein are based on the use of a gate-last process to form nano-FETs. In other embodiments, a gate-first process may be used. Additionally, some embodiments may be considered for use with planar devices, such as planar field-effect transistors or fin field-effect transistors (FinFETs).

[0062] Figure 1 Further illustrations show the reference cross sections used in the following figures. Cross section AA′ is along the longitudinal axis of the gate electrode and, for example, along the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section BB′ is perpendicular to cross section AA′, parallel to the longitudinal axis of the nano-FET fin 66, and along, for example, along the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section CC′ is parallel to cross section AA′ and extends through the epitaxial source / drain regions of the nano-FET. For clarity, these reference cross sections will be referenced in the following figures.

[0063] According to some embodiments, Figures 2 to 18C This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET. Figures 2 to 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A Draw Figure 1 The reference section AA′ in the diagram. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 10C , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 15C , Figure 16B , Figure 17B , Figure 18B and Figure 18C Draw Figure 1 The reference section BB′ in the diagram. Figure 7C , Figure 16C and Figure 17C Draw Figure 1 The reference section CC′ in the diagram.

[0064] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide), or combinations thereof.

[0065] In some embodiments, substrate 50 may be composed of silicon (Si) with a (110) wafer crystal orientation. In some embodiments, forming the (110) silicon substrate may include a crystal orientation growth process, wherein the crystal orientation growth process includes crystal growth, orientation control, slicing, polishing / cleaning, and verification. Crystal growth may begin with the Czochralski method. In the Czochralski method, a single-crystal silicon ingot is grown from a seed crystal. The seed crystal is carefully oriented to ensure the desired (110) plane is achieved. During crystal growth, the seed crystal is aligned with the (110) plane. This alignment defines the orientation of the overall ingot. Once the ingot has grown, it can be sliced ​​into thin wafers using a diamond wire saw. For example, slicing may be performed perpendicular to the (110) plane to ensure the wafers have the correct orientation. In subsequent steps, the wafers may be polished to obtain a smooth surface and cleaned to remove any contaminants. In some embodiments, X-ray diffraction may be used to confirm the correct (110) orientation in the wafer. In some embodiments, molecular beam epitaxy (MBE) can be used to provide (110) orientation on a silicon substrate.

[0066] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor, exemplified by an n-type nano-FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, exemplified by a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (separated by dividing line 20 as shown in the figures), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown in the figures, any number of n-type regions 50N and p-type regions 50P can be provided. The process steps described in the following figures can be performed on either the n-type region 50N or the p-type region 50P, unless otherwise stated.

[0067] Furthermore, in Figure 2 In this process, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layer 53). For illustrative purposes and as discussed in detail below, the first semiconductor layer 51 in both the n-type region 50N and the p-type region 50P is removed, and the second semiconductor layer 53 is patterned to form the channel region of the nano-FET. However, in some embodiments, the second semiconductor layer 53 in both the n-type region 50N and the p-type region 50P may be removed, and the first semiconductor layer 51 may be patterned to form the channel region of the nano-FET. For example, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or other semiconductor materials) and be formed simultaneously.

[0068] In other embodiments, the first semiconductor layer 51 in the p-type region 50P can be removed, and the second semiconductor layer 53 in the p-type region 50P can be patterned to form a channel region for a nano-FET, while the second semiconductor layer 53 in the n-type region 50N can be removed, and the first semiconductor layer 51 in the n-type region 50N can be patterned to form a channel region for a nano-FET. In still other embodiments, the first semiconductor layer 51 in the n-type region 50N can be removed, and the second semiconductor layer 53 in the n-type region 50N can be patterned to form a channel region for a nano-FET, while the second semiconductor layer 53 in the p-type region 50P can be removed, and the first semiconductor layer 51 in the p-type region 50P can be patterned to form a channel region for a nano-FET. In such embodiments, the channel regions of the n-type region 50N and the p-type region 50P can have different material compositions. The first semiconductor layer 51 and the second semiconductor layer 53 can be selectively removed from the respective n-type region 50N and p-type region 50P by additional masking and etching steps. For example, the channel region of the n-type region 50N can be a silicon channel region, while the channel region of the p-type region 50P can be a silicon-germanium channel region.

[0069] For illustrative purposes, the multilayer stack 64 is illustrated as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. The layers of the multilayer stack 64 may be epitaxially grown using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy, or similar processes.

[0070] In several embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium or the like, while the second semiconductor layer 53 may be formed of a second semiconductor material such as silicon, silicon carbon, or the like. The first and second semiconductor materials may be materials with high etch selectivity relative to each other. Therefore, the first semiconductor material of the first semiconductor layer 51 can be removed without significantly removing the second semiconductor material of the second semiconductor layer 53, allowing the second semiconductor layer 53 to be patterned to form the channel region of a nano-FET.

[0071] Reference to Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, the nanostructures 55 in multilayer stack 64 and the fins 66 in substrate 50 can be formed by etching trenches 58 in multilayer stack 64 and substrate 50, respectively. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. Etching can be anisotropic. During the etching process, a hard mask can be used to define the patterning of fins 66 and nanostructures 55. The hard mask can include any suitable insulating material, such as oxides, nitrides, oxynitrides, carbon oxynitrides, or the like. In some embodiments (not specifically depicted), the hard mask can be a multilayer structure. The hard mask can be formed over nanostructures 55 using acceptable processes, such as thermal oxidation, physical vapor deposition (PVD), CVD, ALD, combinations thereof, or the like.

[0072] In some embodiments, fins 66 and nanostructures 55 may be formed on an epitaxially deposited surface on a substrate 50 having a (110) crystal orientation. Epitaxially forming fins 66 and nanostructures 55 on a substrate 50 having a (110) crystal orientation represents growing a semiconductor material on a deposition surface of semiconductor material, wherein the grown semiconductor material has substantially the same crystallization properties as the semiconductor material on the deposition surface, such as the (110) crystal orientation of the substrate 50. In some embodiments, when the chemical reactants are controlled and the system parameters are properly set, the deposited atoms arriving at the deposition surface have sufficient energy to move throughout the surface and orient themselves to the atomic crystallization configuration on the deposition surface. Thus, in some examples, the epitaxial material of the fins 66 and nanostructures 55 epitaxially deposited on the (110) crystal surface of the substrate 50 will have a (110) orientation.

[0073] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the patterned fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thus allowing the created patterns to have, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66 and nanostructures 55.

[0074] Nanostructures 55 are formed by etching multiple layers stacked 64. First nanostructures 52A to 52C (collectively referred to as first nanostructures 52) can be further defined from the first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) can be defined from the second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructures 55.

[0075] For the purpose of explanation, Figure 3 The illustrated fins 66 have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although Figure 3 The illustration shows that each fin 66 and nanostructure 55 has a uniform width, but in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls so that the width of each fin 66 and / or nanostructure 55 increases continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have different widths and may have a trapezoidal shape.

[0076] In some embodiments, the nanostructure 55 is etched to at least provide having <110> A second nanostructure 54 is oriented in the fin direction. The path of charge carriers (e.g., minority charge carriers (e.g., holes) in a p-type device) from the source region to the drain region defines the fin direction (also known as the channel direction). Nanostructure 55 has a (110) crystalline plane and is along... <110> Fin orientation.

[0077] exist Figure 4 Shallow trench isolation regions 68 are formed adjacent to the fins 66. The shallow trench isolation regions 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructures 55, and between adjacent fins 66, to fill the trenches 58. The insulating material can be, for example, an oxide of silicon oxide, a nitride, the like, or a combination thereof, and the insulating material can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55. Although the insulating material is illustrated as a single layer, some embodiments may use multiple layers. For example, in some embodiments, an inner liner (not specifically shown) can be formed first along the surfaces of the substrate 50, fins 66, and nanostructures 55. Next, a filling material, such as the one described above, can be formed on top of the liner.

[0078] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar, can be used. The planarization process exposes the nanostructure 55, so that after the planarization process is completed, the top surface of the nanostructure 55 is flush with the top surface of the insulating material.

[0079] Next, the insulating material is recessed to form shallow trench isolation regions 68. The recessed insulating material causes the upper portion of the fin 66 to protrude from between adjacent shallow trench isolation regions 68. Furthermore, the top surface of the shallow trench isolation region 68 can have a flat surface, a convex surface, a concave surface (e.g., dishing) as illustrated, or a combination thereof. The flat top surface, convex top surface, and / or concave top surface of the shallow trench isolation region 68 can be formed by appropriate etching. The recessed shallow trench isolation region 68 can be formed using an acceptable etching process, such as an etching process selective for the insulating material (e.g., etching the insulating material at a faster rate compared to the material of the fin 66 and the nanostructure 55). For example, oxides can be removed using, for example, diluted hydrofluoric acid (dHF).

[0080] In addition, Figure 4 In this process, suitable traps (not specifically shown) can be formed in the fins 66 and / or nanostructures 55. In embodiments with different trap types, photoresist or other masks (not specifically shown) can be used to achieve different placement steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity placement is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, or the like in the placement area, and the n-type impurity concentration is about 10 per cubic centimeter. 13 atoms per centimeter cubed(atm / cm 3 )) to approximately 10 per cubic centimeter 14 Within the atomic range. After implantation, the photoresist is removed using processes such as acceptable ashing.

[0081] Before or after implantation of the p-type region 50P, a photoresist or other mask (not specifically shown) is formed over the fins 66 and nanostructures 55 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like in the implantation region, with a p-type impurity concentration of approximately 10c per cubic centimeter. 13 Atoms to approximately 10 per cubic centimeter 14Within the atomic range. After implantation, the photoresist can be removed via an acceptable ashing process.

[0082] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, thus omitting the implantation step, but in-situ doping and implantation doping can also be used together.

[0083] exist Figure 5A and Figure 5B In this process, a dummy gate is formed above the nanostructure 55 and the fin 66 and along the sidewalls of the nanostructure 55 and the fin 66. To form the dummy gate, a dummy dielectric layer is first formed above the fin 66 and / or the nanostructure 55. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed above the dummy dielectric layer, and a masking layer is formed above the dummy gate layer. The dummy gate layer can be deposited above the dummy dielectric layer, followed by planarization, such as by CMP. The masking layer can be deposited above the dummy gate layer. The dummy gate layer can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer can be deposited by PVD, CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer can be made of other materials that have high etch selectivity for etch-isolated regions. The masking layer may include, for example, silicon nitride, silicon oxynitride, or the like.

[0084] Subsequently, the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gate 76 and dummy gate dielectric 70, respectively. The dummy gate 76 covers individual channel regions of fin 66. The pattern of mask 78 can be used to separate each of the dummy gates 76 from adjacent dummy gate 76 entities. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the individual fin 66. It should be noted that, for illustrative purposes only, the dummy gate dielectric 70 covering only fin 66 and nanostructure 55 is shown. In some embodiments, the dummy gate dielectric 70 may be deposited such that the dummy gate dielectric 70 covers the shallow trench isolation region 68, thus extending between the dummy gate 76 and the shallow trench isolation region 68.

[0085] exist Figure 6A and Figure 6BIn this configuration, a gate spacer 81 is formed over the nanostructure 55 and the shallow trench isolation region 68, and on the exposed sidewalls of the mask 78 (if present), the dummy gate 76, and the dummy gate dielectric 70. The gate spacer 81 can be formed by conformally forming one or more dielectric materials and subsequently etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by chemical vapor deposition, atomic layer deposition, or similar deposition processes. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, the like, or combinations thereof, can be performed to pattern the dielectric material. The etching may be anisotropic. During etching, the dielectric material leaves a portion of the material on the sidewalls of the dummy gate 76, thereby forming the gate spacer 81. As described in more detail later, during etching, dielectric material may also leave some material on the sidewalls of semiconductor fins 66 and / or nanostructures 55, thereby forming fin spacers 83 (see reference). Figure 7C After etching, the fin spacers 83 and / or the gate spacers 81 may have straight sidewalls (as shown) or curved sidewalls (not specifically shown).

[0086] Furthermore, implantation can be performed for the lightly doped source / drain (LDD) region (not specifically shown). LDD implantation can be performed before the formation of the gate spacer 81. In embodiments with different device types, similar to the previously described well implantation, a mask, such as a photoresist, can be formed over the n-type region 50N to expose the p-type region 50P, and an appropriate type (e.g., p-type) impurity can be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P to expose the n-type region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The lightly doped source / drain region can have an impurity concentration of approximately 1 × 10⁻⁶ per cubic centimeter. 15 Atoms to approximately 1 × 10¹⁰ per cubic centimeter 19 Within the atomic range, annealing can be used to repair implant damage and revitalize implant impurities.

[0087] It should be noted that the above disclosure broadly describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and / or the like. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0088] exist Figures 7A to 7C In some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions are subsequently formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54, and extend into the substrate 50. Figure 7C As illustrated, the top surface of the shallow trench isolation region 68 may be flush with the bottom surface of the first groove 86. In several embodiments, the fins 66 may be etched such that the bottom surface of the first groove 86 is located below the top surface of the shallow trench isolation region 68. The first groove 86 may be formed by etching the fins 66, nanostructures 55, and substrate 50 using an anisotropic etching process, such as reactive ion etching, neutral particle beam etching, or the like. During the etching process for forming the first groove 86, the gate spacer 81, fin spacer 83, and mask 78 shield portions of the fins 66, nanostructures 55, and substrate 50. The individual layers of the nanostructures 55 and / or fins 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first groove 86 after it has reached a desired depth.

[0089] exist Figures 8A to 9B In this process, the first nanostructure 52 is replaced by a sacrificial material 72 (also known as a disposable oxide interposer, DOI). Replacing the first nanostructure 52 may include etching it away using a suitable etching process (such as isotropic etching), which is performed via the first groove 86, as... Figures 8A to 8B As shown. The etching process can be selective in its application to the material of the first nanostructure 52, removing the first nanostructure 52 without significantly removing the second nanostructure 54 or the semiconductor fin 66. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructure 52.

[0090] Subsequently, a sacrificial material layer 71 is deposited in the first groove 86 and in the space where the first nanostructure 52 has been removed. The sacrificial material layer 71 can be deposited using a conformal deposition process, such as CVD, ALD, or the like. The sacrificial material layer may include an insulating material, such as silicon oxide (e.g., SiO2) or the like, wherein the insulating material can be selectively etched relative to the second nanostructure 54. Figures 9A to 9BNext, the sacrificial material layer 71 is etched to form the sacrificial material 72. The etching can be isotropic or anisotropic. For example, the sacrificial material layer can be etched using a wet etching process employing diluted HF or the like as the etchant. In some embodiments, etching is performed until the sidewalls of the sacrificial material 72 are recessed beyond the sidewalls of the nanostructure 54. Although the sidewalls of the sacrificial material 72 are... Figure 9B The figure is depicted as straight, but the sidewalls can be concave or convex (e.g., see reference). Figure 10C ).

[0091] Replacing the first nanostructure 52 with a sacrificial material 72 offers advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes can be performed to, for example, activate dopants in the source / drain regions. When the material of the first nanostructure 52 (e.g., SiGe) is exposed to high temperatures, germanium mixing may occur, increasing the roughness at the interface between the first nanostructure 52 and the second nanostructure 54. Such manufacturing defects can degrade the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure 54, germanium residue may remain in the channel regions of the resulting transistor device, negatively impacting the performance of the channel regions. By replacing the first nanostructure 52 with an insulating material prior to high-temperature processes (e.g., source / drain annealing), manufacturing defects can be reduced and device performance improved (e.g., increased current drive, reduced capacitance, and improved short-channel effects).

[0092] exist Figure 10A and Figure 10B In the first recess 86, an inner spacer 90 is formed on the sidewall of the sacrificial material 72. The inner spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the sacrificial material 72 will be replaced by the corresponding gate structure. The inner spacer 90 also serves to prevent subsequent etching processes (e.g., etching processes used to form the gate structure) from damaging the subsequently formed source / drain regions.

[0093] It can be done in Figure 9A and Figure 9B An inner spacer layer (not specifically shown) is deposited over the structure shown to form the inner spacer 90. The inner spacer layer can be deposited using a conformal deposition process, such as CVD, ALD, or similar. The inner spacer layer can include materials such as silicon nitride or silicon oxynitride, but any suitable material can also be used, such as a low-k material having a dielectric constant (k value) of less than about 3.5. The inner spacer 90 can then be formed by anisotropic etching. The inner spacer layer can be etched using anisotropic etching processes such as RIE, NBE, or similar.

[0094] Although the outer wall of the inner spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (e.g., see reference). Figure 10C Furthermore, although in Figure 10B The outer wall of the inner spacer 90 is shown as straight, but the outer wall of the inner spacer 90 can be concave or convex. As an example, Figure 10C An embodiment is illustrated where the sidewalls of the sacrificial material 72 are concave, the outer sidewalls of the inner spacer 90 are concave, and the inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. Other configurations are also possible. For example, Figure 10D An embodiment is illustrated in which the sidewalls of the sacrificial material 72 are concave, the outer sidewalls of the inner spacer 90 are straight, and the inner spacer 90 is flush with the sidewalls of the second nanostructure 54.

[0095] exist Figures 11A to 11G In this configuration, epitaxial source / drain regions 92 are formed in the first groove 86. In some embodiments, the source / drain regions 92 can apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance.

[0096] like Figure 11B As shown, epitaxial source / drain regions 92 are formed in the first recess 86, such that each dummy gate 76 is disposed between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the sacrificial material 72 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nano-FET.

[0097] Epitaxial source / drain regions 92 in the n-type region 50N (e.g., NMOS region) can be formed by shielding the p-type region 50P (e.g., PMOS region). Next, the epitaxial source / drain regions 92 are epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain regions 92 can include any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 in the n-type region 50N can include a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0098] Epitaxial source / drain regions 92 in the p-type region 50P (e.g., PMOS region) can be formed by shielding the n-type region 50N (e.g., NMOS region). Next, the epitaxial source / drain regions 92 are epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain regions 92 can include any acceptable material suitable for a p-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 in the p-type region 50P can include materials that apply compressive strain to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like.

[0099] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The n-type and / or p-type impurities used for the source / drain region can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain region 92 can be doped in situ during growth.

[0100] In some embodiments, the epitaxial source / drain region 92 forming the p-type region 50P may include forming three semiconductor material components, wherein the semiconductor material components may include a first semiconductor material 192, a second semiconductor material 193, and an interface semiconductor material 194 located between the first semiconductor material 192 and the second semiconductor material 193.

[0101] In some embodiments, a first semiconductor material 192 having a first germanium concentration may be epitaxially formed on the end of a nanostructure located on the sidewall of a trench, the first semiconductor material 192 having a triangular geometry when viewed from a side cross-sectional view. A first groove 86 serves as a trench, wherein the trench exposes the upper surface of a substrate having a (110) crystalline plane.

[0102] In some embodiments, the second nanostructure 54 is composed of silicon, and the first semiconductor material 192 is composed of silicon-germanium. An epitaxial deposition process can be used to form a triangular geometry of the first semiconductor material 192 located on the edge (sidewall) of the second nanostructure 54, wherein the epitaxial deposition process conditions can be adjusted to control the geometry of the deposited material. In some embodiments, by adjusting the temperature of the epitaxial deposition process, the geometry of the first semiconductor material 192 can be adjusted to a specific shape (e.g., a triangle with a three-sided cross-sectional geometry).

[0103] Epitaxially forming the first semiconductor material 192 on the edge of the second nanostructure 54 refers to growing a semiconductor material on the deposition surface of a semiconductor material, where the grown semiconductor material has substantially the same crystalline properties as the semiconductor material of the deposition surface (for example, the edge of the second nanostructure 54). In some embodiments, when chemical reactants are controlled and system parameters are properly set, deposited atoms reaching the deposition surface have sufficient energy to move around on the surface and orient themselves to the crystalline configuration of the atoms of the deposition surface. Therefore, in some examples, an epitaxial film deposited on a (110) crystalline surface will have a (110) orientation. For example, when the second nanostructure has a (110) crystal orientation, the first semiconductor material 192 may have a (110) crystal orientation.

[0104] In some embodiments, a plurality of different material sources may be used for epitaxially depositing the semiconductor material forming the first semiconductor material 192. In some embodiments, when the first semiconductor material 192 is composed of silicon germanium (SiGe), the silicon gas source for epitaxial deposition may include at least one of hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), dichlorosilane (Cl2SiH2), trichlorosilane (Cl3SiH), methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), hexamethyldisilane ((CH3)6Si2), and combinations thereof. In some embodiments, the germanium gas source for epitaxial deposition of the first semiconductor material 192 composed of silicon germanium may include at least one of germane (GeH4), digermane (Ge2H6), halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof.

[0105] In some embodiments, the germanium (Ge) concentration in the silicon germanium (SiGe) material of the first semiconductor material 192 may be selected to provide Si 1-x Ge x composition, where 0<x<0.1. The germanium (Ge) concentration of the first semiconductor material 192 may be lower than the germanium (Ge) concentration of the subsequently formed second semiconductor material 193 having a second germanium concentration, and may be lower than that of the interfacial semiconductor material 194. In some embodiments, to provide a triangular side cross-sectional geometry, the epitaxial deposition temperature for forming the first semiconductor material 192 is limited to below 600°C.

[0106] Reference Figure 11B , in some embodiments, the triangular side cross-sectional geometry includes a base angle β in the range of 35 degrees to 55 degrees. In one embodiment, the triangular side cross-sectional geometry includes a base angle β of 45 degrees, for example 45 degrees ± 10 degrees. In Figure 11B In the example shown, the base angle β is equal to 45 degrees, and the apex angle α of the triangle's lateral cross-section geometry is equal to 90 degrees.

[0107] The first semiconductor material 192, with a p-type region 50P, may be doped with a p-type dopant. For example, for Group IV semiconductors such as silicon (Si) and silicon germanium (SiGe), examples of p-type dopant may include boron, indium, and / or gallium. In some embodiments, the concentration of the p-type dopant in the first semiconductor material 192 is lower than the concentrations of the second semiconductor material 193 and the interface semiconductor material 194. In one example, the concentration of the p-type dopant in the first semiconductor material 192 may be between 1 x 10⁻⁶. 20 cm -3 Up to 3x10 20 cm -3 In some embodiments, Figure 18C The p-type dopant concentration of the third semiconductor material 192a shown in the figure can be between 1 x 10⁻⁶. 20 cm -3 Up to 3x10 20 cm -3 The second semiconductor material 193 can be between 7x10. 20 cm -3 Up to 1x10 21 cm -3 In some embodiments, the interface semiconductor material 194 may be between 3 x 10⁻⁶ and 10⁻⁶. 20 cm -3 Up to 7x10 20 cm -3 In some embodiments, the thickness T1 of the first semiconductor material 192 is measured from the edge of the second nanostructure 54 to the apex of the triangular side-section geometry of the first semiconductor material 192, and the thickness T1 can be between 2 nanometers and 10 nanometers. In one example, the thickness T1 of the first semiconductor material 192, measured from the edge of the second nanostructure 54 to the apex of the triangular side-section geometry of the first semiconductor material 192, can be between 2 nanometers and 4 nanometers.

[0108] Figure 11B The illustration shows the first semiconductor material 192 formed on the trench sidewalls provided by the first groove 86 at each end of the second nanostructure 54. The first epitaxial material substrate portion 192′ can be a trench substrate located directly on the surface of the substrate 50 having a (110) crystal orientation.

[0109] It should be noted that Figure 11BThis only shows one embodiment of the geometry of the first semiconductor material 192. When viewed from a side cross-sectional view, the semiconductor material epitaxial growth formed at the ends of the nanostructure 55 does not necessarily need to have a triangular shape. For example, Figure 11C An embodiment of a third semiconductor material 192a epitaxially formed on nanostructure 54 is illustrated, having a quadrilateral geometry (e.g., a four-sided cross-section). The quadrilateral geometry can be achieved by an epitaxial deposition process at a temperature greater than 600°C.

[0110] Reference Figure 11B The first semiconductor material is then formed, and the p-type region 50P can be processed to form the interface semiconductor material 194. The interface semiconductor material 194 can also be composed of silicon-germanium (SiGe). The interface semiconductor material 194 can be formed using an epitaxial growth process, and the interface semiconductor material 194 can have a conformal thickness, such as... Figure 11B As illustrated in the figure. Due to the use of an epitaxial deposition process, the interface semiconductor material can have a (110) crystal orientation. In some embodiments, the silicon-germanium (SiGe) material of the interface semiconductor material 194 formed by the epitaxial growth process has a germanium (Ge) content greater than the germanium (Ge) concentration of the silicon-germanium (SiGe) material of the first semiconductor material 192. For example, the silicon-germanium (SiGe) composition of the interface semiconductor material 194 can be Si 1-x Ge x , of which 0.1 <x<0.4。

[0111] The interface semiconductor material 194 of the p-type region 50P can be doped with a p-type dopant. For example, for Group IV semiconductors such as silicon (Si) and silicon germanium (SiGe), examples of p-type dopant may include boron, indium, and / or gallium. In some embodiments, the p-type dopant concentration of the interface semiconductor material 194 is higher than that of the first semiconductor material 192. However, in some embodiments, the p-type dopant concentration of the interface semiconductor material 194 is greater than that of the first semiconductor material 192. For example, the p-type dopant concentration of the interface semiconductor material 194 is equal to 7 x 10⁻⁶. 20 cm -3 Or lower.

[0112] The interface semiconductor material 194 can be a material layer with a conformal thickness. In some embodiments, the interface semiconductor material 194 can have a conformal thickness T2 ranging from 1 nanometer to 10 nanometers. In one example, the interface semiconductor material 194 has a thickness T2 ranging from 2 nanometers to 6 nanometers. However, the interface semiconductor material 194 does not necessarily need to be a conformally deposited material. For example, Figure 11D This illustration depicts an embodiment of the interface semiconductor material 194 having a non-conformal thickness. In some embodiments, this can be provided via an epitaxial deposition process. Figure 11D The non-conformal thickness of the interfacial semiconductor material 194 depicted therein, wherein the temperature of the epitaxial deposition process ranges from 600°C to 800°C. In addition, it is not necessary to use an epitaxial deposition process to form the interfacial semiconductor material 194. In some embodiments, the interfacial semiconductor material 194 may be formed by co-diffusion of elements of the first semiconductor material 192 and the second semiconductor material 193. The interfacial semiconductor material 194 is located at the interface between the first semiconductor material 192 and the second semiconductor material 193. In some embodiments, annealing may be used to facilitate the co-diffusion of elements.

[0113] Figure 11B Also depicted is the use of the second semiconductor material 193 to fill the trench provided by the first recess 86. In some embodiments, the second semiconductor material 193 is in direct contact with the interfacial semiconductor material 194. In some embodiments, the second semiconductor material 193 fills the entire trench. Similar to the first semiconductor material 192, the second semiconductor material is an epitaxially deposited (epitaxially formed) material, and the second semiconductor material may be composed of silicon germanium (SiGe). The aforementioned silicon germanium (SiGe) gas precursors for forming the first semiconductor material 192 are equally applicable to forming the second semiconductor material 193. However, the germanium concentration in the second semiconductor material 193 is greater than the germanium concentration in the first semiconductor material 192. For example, the germanium (Ge) concentration of the silicon germanium (SiGe) of the second semiconductor material 193 may be selected to provide Si 1-x Ge x , where 0.4<x<0.6. The germanium concentration of the second semiconductor material 193 is also greater than the germanium concentration of the interfacial semiconductor material 194.

[0114] The second semiconductor material 193 in the p-type region 50P may be doped with a p-type dopant. For example, for Group IV semiconductors such as silicon (Si) and silicon germanium (SiGe), examples of p-type dopants may include boron, indium and / or gallium. In some embodiments, the p-type dopant concentration of the second semiconductor material 193 is higher than the p-type dopant concentration of the first semiconductor material 192. In some embodiments, the p-type dopant concentration of the second semiconductor material 193 is also greater than the p-type dopant concentration of the interfacial semiconductor material 194. For example, the p-type dopant concentration of the second semiconductor material 193 is greater than 7x10 20 cm -3 .

[0115] The second semiconductor material 193 is epitaxially formed on the interface semiconductor material 194 and located above the first semiconductor material 192. In some embodiments, the first semiconductor material 192 is at least located at the upper part of the trench, and the interface semiconductor material 194 has a conformal thickness formed on the first semiconductor material 192. The first semiconductor material 192 has a triangular cross-sectional geometry when viewed from a side cross-section, such as... Figure 11B As illustrated in the diagram. These geometric features exist on both sides of the trench provided by the first recess 86. This results in the uppermost part of the trench having a greater width than the lower part of the trench at the apex of the triangular cross-section of the first semiconductor material 192 and the interface semiconductor material 194. The second semiconductor material 193 fills this wide upper part of the trench. In some embodiments, starting from the uppermost part of the trench, the width of the second semiconductor material 193 slopes down from the uppermost part of the trench to the trench portion at the first apex of the triangular geometry of the first semiconductor material 192 (and the interface semiconductor material 194). The width of the second semiconductor material 193 may be the narrowest at the trench portion at the first apex of the first semiconductor material 192 having the triangular cross-sectional geometry. In some embodiments, the wide portion of the second semiconductor material 193 in the upper part of the trench provides a wide landing point for subsequently formed contacts and associated metal-semiconductor alloys (e.g., silicides). Furthermore, as described later, because the second semiconductor material 193 has the highest germanium concentration and the highest p-type dopant concentration in the source / drain region of the p-type region 50p of the device, the contacts formed with the wide placement portion have lower resistance, such as low contact resistance, compared to the contacts of the contact interface semiconductor material 194 and / or the first semiconductor material 192. By providing the second semiconductor material 193 with the widest and lowest resistance portion in the uppermost part of the trench, the second semiconductor material 193 provides a low-resistance placement point for the contacts subsequently formed to the source / drain region of the p-type region 50p of the device.

[0116] Figure 11E Another embodiment of the source / drain region 92 of the p-type region 50p of the plotting device. Figure 11E In one embodiment, the upper portion of the trench includes a first semiconductor material 192 having a triangular geometry when viewed from a side cross-sectional view. However, the semiconductor material directly contacting the second nanostructure 54 does not necessarily need to have a triangular geometry. For example, a third semiconductor material 192a located in the lower portion of the trench can be epitaxially formed on the second nanostructure 54 and has a cross-section different from the triangular geometry of the first semiconductor material 192 (see example...). Figure 18CFor example, the third semiconductor material 192a located at the lower part of the trench may have a quadrilateral geometry when viewed from a side cross-section. The geometry of the semiconductor material formed on the second nanostructure 54 can be adjusted by adjusting the temperature of the epitaxial growth process that forms the first semiconductor material 192 and the third semiconductor material 192a. For example, to provide the first semiconductor material 192 located at the upper part of the trench and having a triangular geometry, the temperature of the epitaxial deposition process is limited to below 600°C. For example, to provide the third semiconductor material 192a located below the upper part of the trench and having a quadrilateral geometry, the temperature of the epitaxial deposition process can be in the range of 600°C to 800°C. In some embodiments, masking and selective etching can be used to indicate the location of the epitaxial material in the trench. For example, the first epitaxial deposition can be performed using a temperature in the range of 600°C to 800°C to provide the third semiconductor material 192a having a quadrilateral geometry when viewed from a side cross-section. To remove the quadrilateral geometry of the third semiconductor material 192a from the upper part of the trench, a mask, such as a photoresist mask, can be formed on the third semiconductor material 192a at the bottom of the trench, while exposing the quadrilateral geometry of the third semiconductor material located at the upper part of the trench. Next, the exposed portion of the quadrilateral geometry of the third semiconductor material can be removed using selective etching relative to the second nanostructure 54. Subsequently, a first semiconductor material 192 with a triangular geometry can be formed on the exposed end of the second nanostructure 54 in the upper part of the trench using low-temperature epitaxial deposition, for example, at an epitaxial deposition temperature of 600°C or lower. The mask can then be removed, and the remaining epitaxial material can then be formed to fill the trench. Figure 11E An embodiment of an epitaxial semiconductor material with a first germanium concentration is illustrated at the end of a nanostructure 54 located on the sidewall of a trench. The epitaxial semiconductor material includes a first semiconductor material 192 having a triangular geometry in the upper part of the trench, and a third semiconductor material 192a located below the upper part of the trench and having a quadrilateral geometry when viewed from a side cross-section. The first semiconductor material 192 and the third semiconductor material 192a may have the same material composition, such as silicon germanium (SiGe) with the same germanium (Ge) concentration. The first semiconductor material 192 and the third semiconductor material 192a may also be doped with dopants of the same conductivity type, such as p-type dopants, and may have the same p-type dopant composition.

[0117] exist Figures 11B to 11E The source / drain region 92 in the p-type region 50P is used as the p-type doped source / drain region. The source / drain region 92 of the n-type region 50N can be processed independently. To process the source / drain regions 92 in the p-type region 50P and the n-type region 50N independently, a masking mask can be used. (Continued...) Figure 18B and Figure 18CIn the attached diagram, the source / drain regions of both the p-type region 50P and the n-type region 50N are marked with the component symbol 92.

[0118] The epitaxial process forming the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P results in the upper surface of the epitaxial source / drain regions 92 having laterally outwardly extending crystal faces that extend beyond the sidewalls of the nanostructure 55. In some embodiments, these crystal faces cause adjacent epitaxial source / drain regions 92 in the same nano-FET to fuse, such as... Figure 11F As illustrated. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown. Figure 11G As shown in the drawing. Figure 11F and Figure 11G In the illustrated embodiment, fin spacers 83 may be formed on the top surface of the shallow trench isolation region 68 to block epitaxial growth. In some other embodiments, fin spacers 83 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 83 may be adjusted to remove spacer material, such that the epitaxial growth region extends to the surface of the shallow trench isolation region 68.

[0119] exist Figure 12A and Figure 12B In, respectively in Figure 11A and Figure 11BA first interlayer dielectric (ILD) 96 is deposited over the illustrated structure. The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced CVD (PECVD), or flow-through chemical vapor deposition. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed using any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain region 92, the mask 78, and the gate spacer 81. The contact etch stop layer 94 may include a dielectric material with a different etch rate than the material covering the first interlayer dielectric layer 96, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0120] After depositing the first interlayer dielectric layer 96, a planarization process, such as chemical mechanical polishing, can be performed to flush the top surface of the first interlayer dielectric layer 96 with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, the dummy gate 76, the gate spacer 81, and the top surface of the first interlayer dielectric layer 96 are flush within process tolerances. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric layer 96. In some embodiments, the mask 78 may be retained, wherein the planarization process flushes the top surface of the first interlayer dielectric layer 96 with the top surfaces of the mask 78 and the gate spacer 81.

[0121] exist Figure 13A and Figure 13BIn one or more etching steps, the dummy gate 76 (and, if present, the mask 78) is removed, thus forming a second recess 98. A portion of the dummy gate dielectric 70 and a portion of the protective liner in the second recess 98 may also be removed. In some embodiments, an anisotropic dry etching process is used for the dummy gate 76 and the dummy gate dielectric 70. For example, the etching process may include a dry etching process using a reactive gas, wherein the reactive gas selectively etches the dummy gate 76 at a faster rate than the first interlayer dielectric layer 96 or the gate spacer 81. Each second recess 98 exposes and / or covers portions of nanostructures 55, which serve as channel regions in the subsequently completed nano-FET. The portion of the nanostructures 55 serving as channel regions is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 70 may serve as an etch stop layer when etching the dummy gate 76. After the dummy gate 76 is removed, the dummy gate dielectric 70 may then be removed.

[0122] exist Figure 14A and Figure 14B In this process, sacrificial material 72 is removed, thereby extending the second groove 98. Removing sacrificial material 72 may include performing an isotropic etching process (e.g., wet etching or similar) using an etchant selective for the material of sacrificial material 72, while the second nanostructure 54 remains relatively unetched compared to sacrificial material 72. Sacrificial material 72 may be completely removed, or residue of sacrificial material 72 may remain on the sidewalls of the inner spacers in the second groove 98 (e.g., see reference). Figure 15C ).

[0123] In some embodiments, the shallow trench isolation region 68 can be etched while the sacrificial material 72 is being removed, but the total loss of the shallow trench isolation region 68 can be reduced by controlling the etching parameters (e.g., timing) while removing the sacrificial material 72. In other embodiments, the shallow trench isolation region 68 may include a hard mask (not specifically shown) at its top surface to protect the underlying shallow trench isolation region 68 from etching during patterning and removal of the sacrificial material 72. In such embodiments, the hard mask may include, for example, a nitride.

[0124] exist Figures 15A to 15C In the second trench 98, a gate dielectric layer 100 and a gate electrode 102 are formed as alternative gates. The gate dielectric layer 100 is conformally deposited in the second trench 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, the gate spacer 81, and the shallow trench isolation region 68.

[0125] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-enhanced chemical vapor deposition, and the like.

[0126] Multiple gate electrodes 102 are deposited above the gate dielectric layer 100 and fill the remaining portion of the second trench 98. The gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers of the above materials. For example, although... Figures 15A to 15C The diagram illustrates a single-layer gate electrode 102, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers forming the gate electrode 102 may be deposited between adjacent second nanostructures 54 in the n-type region 50N and between the second nanostructure 54A in the n-type region 50N and the substrate 50, and may be deposited between adjacent first nanostructures 54 in the p-type region 50P.

[0127] Gate dielectric layers 100 can be formed simultaneously in n-type region 50N and p-type region 50P, such that the gate dielectric layers 100 in each region are formed of the same material, and gate electrodes 102 can be formed simultaneously, such that the gate electrodes 102 in each region are formed of the same material. In some embodiments, separate processes can be used to form the gate dielectric layers 100 in each region, such that the gate dielectric layers 100 can be of different materials and / or have different numbers of layers, and / or separate processes can be used to form the gate electrodes 102 in each region, such that the gate electrodes 102 can be of different materials and / or have different numbers of layers. When using separate processes, multiple masking steps can be used to mask and expose appropriate areas.

[0128] After filling the second recess 98, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, where this excess material is located above the top surface of the first interlayer dielectric layer 96. Thus, the remaining material of the gate electrode 102 and the gate dielectric layer 100 forms the alternative gate structure of the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0129] Figure 15C Draw Figure 15B Detailed views of multiple components, including epitaxial source / drain regions 92, gate dielectric layer 100, gate electrode 102, second nanostructure 54, and inner spacers 90. In some embodiments, such as Figure 15C As illustrated, residues of sacrificial material 72 may remain on the inner spacer 90, for example, between the inner spacer 90 and the gate dielectric layer 100 / gate electrode 102. For example, sacrificial material 72 may not be completely removed, and the gate dielectric layer 100 may be formed on the remaining sacrificial material 72. Since sacrificial material 72 is an insulating material (e.g., silicon oxide), the remaining residue may not significantly affect the electrical performance of the resulting device.

[0130] exist Figures 16A to 16C In this recessed gate structure (including a gate dielectric layer 100 and a corresponding overlying gate electrode 102), a groove is formed between the gate structure directly above and the opposite portion of the gate spacer 81. The gate mask 104 includes one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, filled into the groove, and a planarization process is followed to remove excess dielectric material extending above the first interlayer dielectric layer 96. Gate contacts (e.g., gate contact 114, as described below) are then formed through the gate mask 104. Figures 18A to 18C (as described above), to contact the top surface of the recessed gate electrode 102.

[0131] like Figures 16A to 16C Further illustrated, a second interlayer dielectric layer 106 is deposited over the first interlayer dielectric layer 96 and on the gate mask 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed by flow chemical vapor deposition. In some embodiments, the second interlayer dielectric layer 106 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited using any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or the like.

[0132] exist Figures 17A to 17CIn the process, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third groove 108, wherein the third groove 108 exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. Anisotropic etching processes, such as reactive ion etching, neutral particle beam etching, or the like, can be used to form the third groove 108. In some embodiments, the third groove 108 can be etched through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96 using a first etching process, etched through the gate mask 104 using a second etching process, and then etched through the contact etch stop layer 94 using a third etching process. A mask, such as photoresist, can be formed and patterned over the second interlayer dielectric layer 106 to shield portions of the second interlayer dielectric layer 106 during the first and second etching processes. In some embodiments, the etching process can be over-etched, so that the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 can be flush with (e.g., at the same level or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure.

[0133] Figures 18A to 18CThe formation of contact 118 is illustrated. After the formation of the third trench 108, a silicide region is formed above the epitaxial source / drain region 92. For the source / drain region in the p-type region 50P, contact 118 is formed in the upper part of the trench and has the widest settling surface for contact 118. For example, a metal contact is set on an epitaxial material with the highest germanium concentration. In some embodiments, the large contact area on the high germanium concentration portion of the p-type epitaxial material of the second semiconductor material 193 for the source / drain region 92 results in low contact resistance. Contact 118 for the source / drain region 92 of the p-type region 50P does not extend into the interface semiconductor material 194, the first semiconductor material 192, or the third semiconductor material 192a, wherein each of the interface semiconductor material 194, the first semiconductor material 192, or the third semiconductor material 192a has a lower germanium (Ge) concentration and a lower p-type dopant concentration than the second semiconductor material 193. Because the first semiconductor material 192, the third semiconductor material 192a, and the interface semiconductor material 194 in the p-type region 50P have low concentrations of germanium (Ge) and p-type dopant (e.g., boron (B)), they have higher resistance than the second semiconductor material 193. Therefore, the contact 118 for the source / drain region 92 in the p-type region 50P directly contacts the second semiconductor material 193 in the uppermost portion of the trench, without extending into the first semiconductor material 192 or the interface semiconductor material 194. The contacts for the source / drain region 92 in the n-type region 50N are formed to the upper surface of the n-type doped semiconductor material in the source / drain region of the n-type region 50N.

[0134] Figure 18B Drawing formation to Figure 11B The contact 118 of the second semiconductor material 193 in the source / drain region 92. Figure 18B In the middle, the first semiconductor material 192, which has a triangular geometry when viewed from the side cross-section, is located on the edge of the nanostructure 54 in both the upper and lower parts of the trench. Figure 18C Drawing formation to Figure 11E The contact 118 of the second semiconductor material 193 in the source / drain region. Figure 18C In the middle, a first semiconductor material 192 with a triangular geometry, when viewed from a side cross-section, is located on the edge of the nanostructure 54 in the upper part of the trench. Figure 18C In the illustrated embodiment, the epitaxial semiconductor material on the nanostructure 54 located at the top of the nanostructure stack can have a triangular geometry, and the epitaxial semiconductor on the nanostructure 54 located at the bottom of the nanostructure stack can have a quadrilateral geometry. Figure 18CIn the middle, the third semiconductor material 192a located in the lower part of the trench has a quadrilateral geometry when viewed from the side cross-section.

[0135] In some embodiments, prior to forming the contact 118, a metal (not shown), such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, is deposited over the exposed portion of the epitaxial source / drain region 92. This metal can react with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region. A thermal annealing process is then performed to form the silicide region. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicides and germanides). For example, a silicon-germanide region can be formed on the contact surface of the second semiconductor material 193 in the p-type region 50P.

[0136] Next, contacts 112 and 114 (also referred to as contact plugs) are formed in the third groove 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive feature (e.g., the gate structure 102 and / or silicide region illustrated in the embodiment). Contact 114 is electrically coupled to the gate structure 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region and may be referred to as a source / drain contact. In some embodiments, the conductivity of the silicide in contact 112 is greater than the conductivity of the source / drain region. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0137] In some embodiments, the above method can produce a semiconductor device including, for example, nanostructures such as nanosheets, channel regions, and a gate-all-around gate structure, wherein the semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures 54 above the substrate 50, and a source / drain region 92 in a trench on opposite sides of the stack of nanostructures 54. The source / drain region 92 includes a first semiconductor material 192 located at the ends of the nanostructures 54 in the nanostructure stack and having a first germanium concentration. The first semiconductor material 192 has a triangular geometry when viewed from a side cross-section, and a second semiconductor material 193 on the first semiconductor material 192 has a second germanium concentration. The second semiconductor material 193 fills at least a portion of the trench. In some embodiments, the second germanium concentration of the second semiconductor material 193 is greater than the first germanium concentration of the first semiconductor material 192. In some embodiments, the first semiconductor material 192 having a triangular geometry when viewed from a side cross-section is located in both the upper and lower portions of the trench, such as... Figure 18B The diagram is shown in the figure. In some other embodiments, a first semiconductor material 192 having a triangular geometry when viewed in a side cross-sectional view is located only in the upper part of the trench, wherein the epitaxial semiconductor material on the nanostructure 54 below the upper part of the trench can have a quadrilateral geometry. For example, a third semiconductor material 192a having a quadrilateral geometry when viewed in a side cross-sectional view can be located on the nanostructure 54 in the lower part of the trench, such as... Figure 18C The diagram shows the nanostructure 54 of the p-type device in the p-type region 50P, which provides the device channel region and is composed of silicon with (110) crystal orientation. Further, the nanostructure 54 disposed between the source / drain regions is along... <110> Orientation (also known as fin orientation).

[0138] In several embodiments, the methods and structures described herein utilize a (110) substrate to provide improved minority charge carrier mobility and provide further advantageous performance by controlling the epitaxial deposition shape in the PMOS source / drain regions on the (110) substrate. For example, the shape of the epitaxial deposition material in the source / drain regions can be controlled from a rectangular geometry to a triangular geometry by adjusting the process conditions of the epitaxial growth process. By controlling the shape of the epitaxial material, the contact surface of the metal contacts in the source / drain regions can be maximized, allowing the metal contacts to be situated on the epitaxial material with the highest germanium concentration. In some embodiments, the larger contact area on the high-germanium-concentration portion of the p-type epitaxial material in the source / drain regions results in low contact resistance.

[0139] In some embodiments, a method of forming a semiconductor device includes the following steps: Forming a trench through a stack of nanostructures above an orientation substrate (110), the nanostructure stack including a plurality of first nanostructures. Epitaxially forming a first semiconductor material having a first germanium concentration on the sidewalls of the first nanostructures in the trench, wherein the first semiconductor material has a triangular geometry in a cross-sectional view. Epitaxially forming a second semiconductor material having a second germanium concentration on the first semiconductor material, the second semiconductor material having a width that tapers slopingly from the uppermost portion of the trench, wherein the second germanium concentration is greater than the first germanium concentration. Forming a contact to the second semiconductor material. In one embodiment, the method may further include forming an interface semiconductor material that directly contacts the first semiconductor material and the second semiconductor material, wherein the interface germanium concentration of the interface semiconductor material is between the first germanium concentration and the second germanium concentration. In some embodiments, the contact to the second semiconductor material does not extend beyond the second semiconductor material having the second germanium concentration. In some embodiments, the first semiconductor material and the second semiconductor material are doped with p-type dopants. In some embodiments, a first concentration of p-type dopants in the first semiconductor material is lower than a second concentration of p-type dopants in the second semiconductor material. In some embodiments, the triangular geometry has base angles in the range of 35 degrees to 55 degrees. For example, a triangular geometry can have a base angle of approximately 45 degrees, such as 45 degrees ± 10 degrees.

[0140] In another embodiment, a method of forming a semiconductor device includes the following steps: Forming a trench through a stack of nanostructures above an orientation substrate (110), the nanostructure stack including a plurality of first nanostructures. Epitaxially forming a first semiconductor material having a first germanium concentration on the sidewalls of the first nanostructures in the trench, wherein the epitaxial growth temperature of the first semiconductor material is limited to a maximum of 600°C, and the first semiconductor material has a triangular geometry in a cross-sectional view. Epitaxially forming a second semiconductor material having a second germanium concentration on the first semiconductor material to fill at least a portion of the trench. Forming contacts to the second semiconductor material, wherein the contacts do not extend into the first semiconductor material. In one embodiment, an interface semiconductor material directly contacts the first and second semiconductor materials, wherein the interface germanium concentration of the interface semiconductor material is between the first and second germanium concentrations. In one embodiment, the contacts to the second semiconductor material do not extend beyond the second semiconductor material. In one embodiment, the triangular geometry has base angles in the range of 35 degrees to 55 degrees. In one embodiment, the method further includes forming a third semiconductor material on a first nanostructure in the lower portion of the trench, the third semiconductor material having a quadrilateral geometry in a cross-sectional view, wherein the first semiconductor material is formed in the upper portion of the trench after the formation of the third semiconductor material. In one embodiment, the quadrilateral geometry of the third semiconductor material is formed using an epitaxial deposition process at a temperature greater than 600°C.

[0141] In another embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a nanostructure stack located above the substrate, and source / drain regions located on opposite sides of the nanostructure stack. In some embodiments, each source / drain region includes a first semiconductor material located at the end of a nanostructure in the nanostructure stack and having a first germanium concentration, wherein the first semiconductor material has a triangular geometry when viewed in cross-section. Each source / drain region also includes a second semiconductor material located on the first semiconductor material and having a second germanium concentration greater than the first germanium concentration. In some embodiments, the source / drain regions are doped to a p-type conductivity type. In some embodiments, the nanostructure stack is configured to provide along... <110> p-type charge carriers traveling in a specific direction. In some embodiments, the semiconductor device further includes an interface semiconductor material that directly contacts the first semiconductor material and the second semiconductor material, wherein the interface germanium concentration of the interface semiconductor material is between the first germanium concentration and the second germanium concentration. In some embodiments, the semiconductor device further includes a contact to the second semiconductor material, wherein the contact to the second semiconductor material does not extend beyond the second semiconductor material. In some embodiments, the first semiconductor material and the second semiconductor material are doped with a p-type dopant, wherein a first concentration of the p-type dopant in the first semiconductor material is lower than a second concentration of the p-type dopant in the second semiconductor material. In some embodiments, the triangular geometry has a base angle in the range of 35 degrees to 55 degrees. In some embodiments, the first semiconductor material having a first germanium concentration is located at the end of a nanostructure in the upper part of the nanostructure stack, wherein the third semiconductor material having a first germanium concentration is located at the end of a nanostructure in the lower part of the nanostructure stack, and the third semiconductor material has a quadrilateral geometry when viewed in cross-section.

[0142] In another embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures above the substrate, and source / drain regions on opposite sides of the nanostructure stack. Each source / drain region includes a first semiconductor layer located at the end of a nanostructure in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed in cross-section. Each source / drain region also includes a second semiconductor layer located on the first semiconductor layer, the second semiconductor layer having a greater germanium concentration than the first semiconductor layer. In some embodiments, the semiconductor device further includes an interface semiconductor layer directly contacting the first and second semiconductor layers, wherein the interface germanium concentration of the interface semiconductor layer is between that of the first and second semiconductor layers. In some embodiments, the semiconductor device further includes a contact to the second semiconductor layer, wherein the contact to the second semiconductor layer does not extend beyond the second semiconductor layer. In some embodiments, the triangular geometry has a base angle in the range of 35 degrees to 55 degrees. In some embodiments, the first semiconductor layer is located at the end of a nanostructure in the upper portion of the nanostructure stack.

[0143] In another embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures above the substrate, and source / drain regions on opposite sides of the nanostructure stack. Each source / drain region includes a first semiconductor layer located at the end of a nanostructure in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed in cross-section. The semiconductor device further includes a third semiconductor layer located at the end of a nanostructure in the lower portion of the nanostructure stack, the third semiconductor material having a quadrilateral geometry when viewed in cross-section. In some embodiments, the semiconductor device further includes a second semiconductor layer located at multiple ends of multiple nanostructures in the middle portion of the nanostructure stack. In some embodiments, the triangular geometry has a base angle in the range of 35 degrees to 55 degrees.

[0144] In another embodiment, a semiconductor device includes a substrate having a (110) crystal orientation, a stack of nanostructures above the substrate, and p-type source / drain regions on opposite sides of the nanostructure stack. Each p-type source / drain region includes a first semiconductor layer located at the end of a nanostructure in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed in cross-section. Each p-type source / drain region also includes a second semiconductor layer located on the first semiconductor layer, the second semiconductor layer having a higher germanium concentration than the first semiconductor layer. In some embodiments, the nanostructure stack is configured to provide along... <110> p-type charge carriers traveling in a certain direction.

[0145] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a (110) crystal orientation; A stack of nanostructures is located on top of the substrate; and Multiple source / drain regions are located on opposite sides of the nanostructure stack, wherein each of the multiple source / drain regions includes: A first semiconductor layer is located at multiple ends of multiple nanostructures in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed from a cross-sectional view; and A second semiconductor layer is located on the first semiconductor layer, and the germanium concentration of the second semiconductor layer is greater than that of the first semiconductor layer.

2. The semiconductor device as claimed in claim 1, characterized in that, It further includes an interface semiconductor layer that directly contacts the first semiconductor layer and the second semiconductor layer, wherein the germanium concentration of the interface semiconductor layer is between that of the first semiconductor layer and the second semiconductor layer.

3. The semiconductor device as claimed in claim 1, characterized in that, It further includes a contact to the second semiconductor layer, wherein the contact to the second semiconductor layer does not extend beyond the second semiconductor layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The triangle's geometry has base angles ranging from 35 to 55 degrees.

5. The semiconductor device as claimed in claim 1, characterized in that, The first semiconductor layer is located on the plurality of ends of the plurality of nanostructures in an upper part of the nanostructure stack.

6. A semiconductor device, characterized in that, include: A substrate having a (110) crystal orientation; A stack of nanostructures is located on top of the substrate; and Multiple source / drain regions are located on opposite sides of the nanostructure stack, wherein each of the multiple source / drain regions includes: A first semiconductor layer is located on multiple ends of multiple nanostructures in an upper part of a plurality of nanostructures in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed from a cross-sectional view; and A third semiconductor layer is located at multiple ends of multiple nanostructures in the lower part of the nanostructure stack, wherein the third semiconductor layer has a quadrilateral geometry when viewed from the cross-sectional view.

7. The semiconductor device as claimed in claim 6, characterized in that, It further includes a second semiconductor layer located at multiple ends of multiple nanostructures in a middle portion of the nanostructure stack.

8. The semiconductor device as claimed in claim 6, characterized in that, The triangle's geometry has base angles ranging from 35 to 55 degrees.

9. A semiconductor device, characterized in that, include: A substrate having a (110) crystal orientation; A stack of nanostructures is located on top of the substrate; and Multiple p-type source / drain regions are located on opposite sides of the nanostructure stack, wherein each of the multiple p-type source / drain regions includes: A first semiconductor layer is located at multiple ends of multiple nanostructures in the nanostructure stack, wherein the first semiconductor layer has a triangular geometry when viewed from a cross-sectional view; and A second semiconductor layer is located on the first semiconductor layer, and the germanium concentration of the second semiconductor layer is greater than that of the first semiconductor layer.

10. The semiconductor device as claimed in claim 9, characterized in that, The nanostructure stack is configured to provide along <110> p-type charge carriers traveling in a certain direction.

Images