Semiconductor device

Abstract

A semiconductor device includes a substrate, a source / drain region, a composite layer, and a backside via. The source / drain region is on the substrate and has a first surface with a recess. The composite layer is on the first surface of the source / drain region, wherein the composite layer includes a plurality of first heavily doped sub-layers and a plurality of second lightly doped sub-layers arranged alternately, and the composite layer has a second surface recessed toward the substrate. The backside via is on the second surface of the composite layer and electrically connected to the source / drain region through the composite layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and by using photolithography to pattern the various material layers to form circuit components and elements.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a substrate, source / drain regions located on the substrate, wherein the source / drain regions have a first surface with a recess. A composite layer is located on the first surface of the source / drain regions, wherein the composite layer includes alternating first heavily doped sublayers and multiple second lightly doped sublayers, and the composite layer has a second surface recessed toward the substrate. A back-side via is located on the second surface of the composite layer and is electrically connected to the source / drain regions through the composite layer.

[0005] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a substrate, source / drain regions, a composite layer, a back via, and spacers. The source / drain regions are located on the substrate, wherein the source / drain regions have a first surface. The composite layer is located on the first surface of the source / drain regions, wherein the composite layer includes alternating first heavily doped sublayers and multiple second lightly doped sublayers. The back via is located on the composite layer and is electrically connected to the source / drain regions through the composite layer. The spacers surround the back vias, wherein the bottom surface of the spacers is in direct contact with the first surface of the composite layer.

[0006] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a substrate and a transistor. The transistor is disposed on the substrate. The transistor includes a fin, a nanostructure, a gate dielectric layer, a gate electrode, a source / drain region, and a composite layer. The fin protrudes from the substrate. The nanostructure is located on the fin. The gate dielectric layer is located above the top surface of the fin and extends along the top surface, sidewalls, and bottom surface of the nanostructure. The gate electrode is located above the gate dielectric layer. The source / drain region is disposed on the fin on the opposite side of the gate dielectric layer and the gate electrode, wherein the source / drain region has a first surface with a recess. The composite layer is located on the first surface of the source / drain region and extends conformally along the recess, wherein the composite layer includes a plurality of alternating first n-type heavily doped sublayers and a plurality of second n-type lightly doped sublayers, wherein the composite layer has a second surface recessed toward the substrate. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a three-dimensional view of an example of a nanostructure field-effect transistor (nano-FET) according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A, Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 24C , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 27C and Figure 27D This is a cross-sectional view illustrating intermediate steps in the fabrication of a semiconductor device including a nanoFET, according to some embodiments.

[0010] Figure 28A , Figure 28B and Figure 28C It is a graph showing the concentrations of various components in a semiconductor device (including a nanoFET) according to some embodiments;

[0011] Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C , Figure 31D , Figure 32A , Figure 32B , Figure 32C , Figure 33A , Figure 33B , Figure 33C , Figure 34A , Figure 34B and Figure 34C This is a cross-sectional view illustrating intermediate steps in the fabrication of a semiconductor device including a nanoFET, according to some embodiments.

[0012] Figure 35A , Figure 35B , Figure 35C , Figure 36A , Figure 36B and Figure 36C This is a cross-sectional view of a semiconductor device including a nanoFET according to some embodiments.

[0013] [Symbol Explanation]

[0014] 20: Divider

[0015] 50:Substrate

[0016] 50N: n-type region

[0017] 50P:p-type area

[0018] 51, 51A, 51B, 51C: First semiconductor layer

[0019] 52, 52A, 52B, 52C: First nanostructure

[0020] 53, 53A, 53B, 53C: Second semiconductor layer

[0021] 54, 54A, 54B, 54C: Second nanostructures

[0022] 55: Nanostructures

[0023] 56: Stacking

[0024] 60: Dummy gate dielectric

[0025] 64: Stacking

[0026] 66: Fins

[0027] 68: Shallow trench isolation area, STI area

[0028] 70: Dummy Dielectric Layer

[0029] 71: Dummy gate dielectric

[0030] 72: Dummy gate layer

[0031] 74: Masking layer

[0032] 76: Dummy gate

[0033] 78: Mask

[0034] 80: First Spacing Layer

[0035] 81: First spacer

[0036] 82: Second spacer layer

[0037] 83: Second spacer

[0038] 86: First Groove

[0039] 87: Second groove

[0040] 88: Side wall depression

[0041] 90: First internal spacer

[0042] 91: Semiconductor layer

[0043] 92: Source / Drain Region

[0044] 92A: First semiconductor material layer

[0045] 92B: Second semiconductor material layer

[0046] 92C: Third semiconductor material layer

[0047] 94: Contact Etching Stop Layer, CESL

[0048] 96: First interlayer dielectric, first ILD

[0049] 98: Third Groove

[0050] 100: Gate dielectric layer

[0051] 102: Gate electrode

[0052] 104: Gate Mask

[0053] 106: Second ILD

[0054] 108: Fourth Groove

[0055] 109: Transistor Structure

[0056] 110: First silicide region

[0057] 112: Source / Drain Contact

[0058] 114: Gate contact

[0059] 120: Front-side interconnect structure

[0060] 122: First electrical conductivity characteristic

[0061] 123: Second dielectric layer

[0062] 124: First dielectric layer

[0063] 125: Fifth Groove

[0064] 126: Third spacer

[0065] 127: Composite layer

[0066] 127A: First Sublayer

[0067] 127B: Second Sublayer

[0068] 128: Area

[0069] 129: Second silicide region

[0070] 130: Through hole on the back

[0071] 132: Third dielectric layer

[0072] 134: Conductive wire

[0073] 136: Backside interconnect structure

[0074] 138: Fourth dielectric layer

[0075] 140: Second conductivity characteristic

[0076] 140C: Topmost wire

[0077] 144: Passivation layer

[0078] 146:UBM

[0079] 148: External Connector

[0080] 150: Carrier substrate

[0081] 152: Bonding layer

[0082] 152A: First bonding layer

[0083] 152B: Second bonding layer

[0084] 200: Semiconductor devices

[0085] A-A': Cross-section

[0086] B-B': Cross section

[0087] C-C': Cross section

[0088] D1: Depth

[0089] D2: Depth

[0090] T1: Thickness

[0091] T2: Thickness

[0092] T3: Thickness

[0093] T4: Thickness

[0094] W1: Width

[0095] W2: Width

[0096] X: axis

[0097] Y: axis

[0098] Z: Axis Detailed Implementation

[0099] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the content of this disclosure, specific elements and layout examples will be described below. Of course, these are merely examples and are not intended to be limiting. For example, the first feature described below may be located on or overlaying a second feature; this may include embodiments where the first and second features are in direct contact, or embodiments where another feature is formed between the first and second features, such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplification and clarity and does not imply any specific association between the embodiments and / or configurations.

[0100] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “lower,” “lower,” “above,” and “higher” to describe the relationship between one element or feature and another, as shown in the accompanying drawings. The use of these spatial relative terms is intended to cover different orientations of the device during use or operation, and is not limited to those shown in the accompanying drawings. The device may also have other orientations (e.g., rotation of 90 degrees or other angles), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0101] Various embodiments disclosed herein provide a semiconductor device and a method for forming the same, having a composite layer between the epitaxial source / drain regions and conductive contacts. The composite layer may be a semiconductor layer with a modulated doping profile, comprising a series of highly doped sublayers and a series of lightly doped sublayers arranged in an alternating pattern. The composite layer can have a high average dopant concentration and a high average carrier concentration, which can reduce the contact resistance between the epitaxial source / drain regions and the conductive contacts. Therefore, the performance of the semiconductor device can be improved.

[0102] Some of the embodiments discussed herein are described in the context of semiconductor devices, such as superpower rail (SPR) devices including nanoFETs. However, various embodiments can be applied to devices that include other types of transistors (e.g., fin field-effect transistors, vertical field-effect transistors, complementary field-effect transistors, planar transistors, etc.) that replace or are combined with nanoFETs.

[0103] Figure 1 This is a three-dimensional view illustrating an example of a nanoFET (e.g., nanowire FET, nanosheet FET, etc.). The nanoFET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may be above and protrude between adjacent STI regions 68. Although the STI regions 68 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an STI region. Additionally, although the bottom of the fins 66 is shown as being a single, continuous material with the substrate 50, the bottom portion of the fins 66 and / or the substrate 50 may include a single material or multiple materials. In this document, fins 66 refer to the portion extending between adjacent STI regions 68.

[0104] The gate dielectric layer 100 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0105] Figure 1The reference cross-sections used in the following figures are further illustrated. Cross-section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross-section B-B' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions 92 of the multiple nanoFETs. Cross-section C-C' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fins 66 of the nanoFET and in a direction, for example, current flow between the epitaxial source / drain regions 92 of the nanoFET. For clarity, the following figures refer to these reference cross-sections. Some embodiments discussed herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Moreover, some embodiments contemplate use in planar devices, such as planar FETs or FinFETs.

[0106] Figures 2 to 34C This is a cross-sectional view illustrating intermediate steps in the fabrication of a semiconductor device including a nanoFET, according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A and Figure 34A Show along Figure 1 The cross-sectional view of reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B and Figure 34B Show along Figure 1 The cross-sectional view of reference section B-B' is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C , Figure 24C , Figure 25C , Figure 26C , Figure 27C , Figure 29C , Figure 30C , Figure 31C , Figure 32C , Figure 33C and Figure 34C Show along Figure 1 The cross-sectional view of reference section C-C' is shown.

[0107] exist Figure 2The diagram provides a substrate 50. The substrate 50 can be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0108] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, or n-type nano-FETs, and the p-type region 50P can be used to form p-type devices, such as PMOS transistors, or p-type nano-FETs. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active elements, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0109] Further in Figure 2In this embodiment, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor layer 51A, a first semiconductor layer 51B, a first semiconductor layer 51C (collectively referred to as the first semiconductor layer 51) and a second semiconductor layer 53A, a second semiconductor layer 53B, and a second semiconductor layer 53C (collectively referred to as the second semiconductor layer 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form channel regions for the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions for the nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions for the nanoFET in the n-type region 50N. In some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the n-type region 50N. In some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P.

[0110] For illustrative purposes, the multilayer stack 64 is shown as three layers, each including a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be used by methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or others. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon or germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material, such as silicon or carbon-doped silicon.

[0111] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material.

[0112] exist Figure 3 In the process, fins 66 (e.g., protrusions or base portions) are formed. In some embodiments, nanostructures 55 and fins 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. Forming nanostructures 55 by etching the multilayer stack 64 can also define first nanostructures 52A, 52B, and 52C (collectively referred to as first nanostructures 52) and second nanostructures 54A, 54B, and 54C (collectively referred to as second nanostructures 54) from the first semiconductor layer 51. The first nanostructures 52 and the second nanostructures 54 can be collectively referred to as nanostructures 55.

[0113] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more lithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins 66 and nanostructures 55. Generally, dual-patterning or multi-patterning processes combine lithography with self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0114] For the purpose of explanation, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be thicker or thinner than the width of the fins 66 in the p-type region 50P. Furthermore, while each fin 66 and nanostructure 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructure 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0115] exist Figure 4 In the substrate 50, adjacent fins 66 form shallow trench isolation (STI) regions 68. The STI regions 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, or combinations thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed via an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material can be formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments can be formed as multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 66, and nanostructure 55. A filler material, as discussed above, can then be formed over the liner.

[0116] Next, a removal process is performed on the insulating material to remove excess insulating material from the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etching back, or combinations thereof can be used. The planarization process exposes the nanostructure 55 so that the top surfaces of the nanostructure 55 and the insulating material are horizontal after the planarization process is completed.

[0117] The insulating material is then recessed to form the STI region 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, such as a material-selective etching process for the insulating material (e.g., etching the insulating material at a faster rate than the materials of the fins 66 and nanostructures 55). For example, an oxide such as dilute hydrofluoric acid (dHF) can be used for removal.

[0118] The above reference Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the substrate 50 underneath. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures can include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. Although in-situ doping and implantation doping can be used together, in some embodiments where epitaxial structures are epitaxially grown, the material for epitaxial growth can be doped in-situ during growth to avoid performing previous and / or subsequent implantation doping.

[0119] Furthermore, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in different orders in the p-type region 50P and the n-type region 50N.

[0120] In addition, Figure 4In this process, suitable well regions (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well region types, different implantation steps for n-type regions 50N and p-type regions 50P can be achieved using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted in the regions at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0121] After or before implantation into the p-type region 50P, a photoresist (not shown separately) is formed over the fins 66 and STI region 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in the region at a concentration of approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0122] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and reactivate the implanted p-type and / or n-type impurities. Although in-situ doping and implantation doping can be used together, in some embodiments, the growth material of the epitaxial fins can be doped in-situ during growth to avoid performing the implantation process.

[0123] exist Figure 5In this configuration, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The masking layer 74 can be deposited over the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity for etching the isolation region. The masking layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single masking layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0124] Figures 6A to 20C Additional steps in the fabrication process of a semiconductor device containing a nanoFET are shown. Figures 6A to 20C The intermediate steps described can be applied to both the n-type region 50N and the p-type region 50P. Figures 6A to 6C In this process, acceptable lithography and etching techniques can be used to mask layer 74 (see...). Figure 5 The pattern is then patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0125] exist Figures 7A to 7C In the middle, the first spacer layer 80 and the second spacer layer 82 are formed in Figures 6A to 6C Above the structure shown. Then, the first spacer layer 80 and the second spacer layer 82 are patterned as spacers for forming self-aligned source / drain regions. Figures 7A to 7CIn this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the nanostructure 55; on the mask 78; and on the sidewalls of the fin 66, the dummy gate 76, and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0126] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation of lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, similar to the above description... Figure 4 The implantation discussed earlier can involve forming a mask, such as a photoresist, over the n-type region 50N, while simultaneously exposing the p-type region 50P. An appropriate type of impurity (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 within the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed earlier, and the p-type impurity can be any of the p-type impurities discussed earlier. The lightly doped source / drain regions can have a density of approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 Impurity concentration within a specified range. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0127] exist Figures 8A to 8CIn this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using suitable etching processes, such as isotropic etching processes (e.g., wet etching processes) and anisotropic etching processes (e.g., dry etching processes). In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, anisotropic etching processes can be used to etch the second spacer layer 82, wherein the first spacer layer 80 acts as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, as... Figure 8B As shown. Subsequently, the second spacer 83 acts as a mask while the exposed portion of the first spacer layer 80 is etched, thereby forming the first spacer 81, as... Figure 8B and Figure 8C As shown.

[0128] like Figure 8B As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8C As shown, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, where the first spacer layer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0129] It should be noted that the above disclosure provides a general description of the process for forming the spacers and LDD regions. Other processes and step sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers can be formed and removed, and / or similar methods can be employed. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0130] exist Figures 9A to 9CIn some embodiments, a first groove 86 and a second groove 87 are formed in the fin 66, the nanostructure 55, and the substrate 50. Epitaxial source / drain regions are then formed in the first groove 86 and the semiconductor layer (e.g., a sacrificial material), and subsequently, epitaxial source / drain regions are formed in the second groove 87. The first groove 86 and the second groove 87 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Figure 9B As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 can be etched such that the bottom surface of the first groove 86 is positioned below the top surface of the STI region 68, etc. The bottom surface of the second groove 87 can be positioned below the bottom surface of the first groove 86 and the top surface of the STI region 68. The first groove 86 and the second groove 87 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using anisotropic etching processes such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask a portion of the fin 66, the nanostructure 55, and the substrate 50 during the etching process used to form the first groove 86 and the second groove 87. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching after the first groove 86 and the second groove 87 have reached the desired depth. The second groove 87 can be etched using the same process used to etch the first groove 86, as well as additional etching processes before or after etching the first groove 86. In some embodiments, the area corresponding to the first groove 86 may be masked while performing an additional etching process for etching the second groove 87.

[0131] exist Figures 10A to 10C In the process, the exposed sidewalls of the nanostructure 55 (e.g., the first nanostructure 52) formed of the first semiconductor material, via the first groove 86 and the second groove 87, are etched to form sidewall recesses 88. Although the sidewalls of the first nanostructure 52 adjacent to the sidewall recesses 88 are... Figure 10C The sidewalls are shown as straight, but they can be concave or convex. An isotropic etching process, such as wet etching, can be used to etch the sidewalls. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52.

[0132] exist Figures 11A to 11D In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figures 10A to 10CAn internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation component between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions and epitaxial material will be formed in the first recess 86 and the second recess 87, while the first nanostructure 52 will be replaced by the corresponding gate structure. The internal spacer layer can be deposited by a conformal deposition process, such as CVD, ALD, etc. The internal spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer wall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the first internal spacer 90 may extend beyond or recess from the sidewall of the second nanostructure 54.

[0133] Furthermore, although the outer wall of the first internal spacer 90 is in Figure 11C The central part is shown as straight, but the outer wall of the first internal spacer 90 can be concave or convex. As an example, Figure 11D One embodiment is shown in which the sidewalls of the first nanostructure 52 are recessed, the outer sidewalls of the first internal spacer 90 are recessed, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54. The internal spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent the formation of subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, hereinafter referred to as...). Figures 12A to 12D (Discussion) Damage caused by subsequent etching processes (e.g., etching processes used to form gate structures).

[0134] exist Figures 12A to 12D In this configuration, a semiconductor layer 91 is formed in a second recess 87, and epitaxial source / drain regions 92 are formed in a first recess 86 and a second recess 87. In some embodiments, the semiconductor layer 91 may be a sacrificial material that is subsequently removed to form a back-side via (such as back-side via 130, referred to below). Figures 26A to 26C(Discussion). A semiconductor layer 91 can be epitaxially grown in the second recess 87 using processes such as CVD, ALD, VPE, MBE, etc. The semiconductor layer 91 can comprise any acceptable material, such as silicon-germanium. The semiconductor layer 91 can be formed of a material with high etch selectivity relative to the materials of the epitaxial source / drain regions 92, the substrate 50, and the dielectric layer (such as STI region 6). In this way, the semiconductor layer 91 can be removed and replaced with a back-side via without significantly removing the epitaxial source / drain regions 92 and the dielectric layer. In embodiments where both the semiconductor layer 91 and the epitaxial source / drain regions 92 comprise silicon-germanium, the germanium percentage of the semiconductor layer 91 can differ from the germanium percentage of the epitaxial source / drain regions, thereby achieving etch selectivity. For example, the semiconductor layer 91 can be selectively grown in the first recess 86 by shielding the second recess 87 while growing the semiconductor layer 91.

[0135] Then, epitaxial source / drain regions 92 are formed over the semiconductor layer 91 in the first groove 86 and the second groove 87. In some embodiments, the epitaxial source / drain regions 92 can apply stress to the second nanostructure 54, thereby improving performance. Figure 12C As shown, epitaxial source / drain regions 92 are formed in the first groove 86 and the second groove 87, such that each dummy gate 76 is positioned between each pair of adjacent epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate of the subsequently formed nanoFET.

[0136] Epitaxial source / drain regions 92 in the n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first groove 86 and the second groove 87 in the n-type region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 92 can have surfaces protruding from the corresponding upper surface of the nanostructure 55 and can have facets.

[0137] Epitaxial source / drain regions 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first groove 86 and the second groove 87 in the p-type region 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain regions 92 can comprise materials that apply compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain regions 92 can also have surfaces protruding from corresponding surfaces of the multilayer stack 56 and can have facets.

[0138] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as... Figure 12B As shown. In other embodiments, such as Figure 12D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Figure 12B and Figure 12D In the illustrated embodiment, the first spacer 81 may be formed to the top surface of the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0139] The epitaxial source / drain region 92 may include one or more layers of semiconductor material. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. The first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0140] exist Figures 13A to 13C In the middle, the first interlayer dielectric (ILD) 96 is deposited on Figures 12A to 12C Above the structure shown. The first ILD96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)94 is disposed between the first ILD96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. CESL94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from that of the material covering the first ILD96.

[0141] exist Figures 14A to 14C In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the dummy gate 76, the first spacer 81, and the top surface of the first ILD96 are horizontal within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0142] exist Figures 15A to 15CIn one or more etching steps, the dummy gate 76 and the mask 78 (if present) are removed to form a third recess 98. A portion of the dummy gate dielectric 60 in the third recess 98 is removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each third recess 98 exposes and / or covers a portion of a nanostructure 55, which serves as a channel region in the subsequently completed nanoFET. The nanostructure 55, as part of the channel region, is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 60 can be used as an etch stop layer while etching the dummy gate 76. The dummy gate dielectric 60 can then be removed after the dummy gate 76 has been removed.

[0143] exist Figures 16A to 16C In the process, the first nanostructure 52 is removed, and the third groove 98 is extended. The first nanostructure 52 can be removed by an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A to 54C comprise, for example, Si or SiC, the first nanostructure 52 can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0144] exist Figures 17A to 17C In this process, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the third groove 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68, as well as on the sidewalls of the first spacer 81 and the first internal spacer 90.

[0145] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric layer may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0146] Gate electrodes 102 are deposited above the gate dielectric layer 100 and fill the remaining portion of the third trench 98. Gate electrodes 102 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although... Figure 17A and Figure 17C The diagram shows a single-layer gate electrode 102, but the gate electrode 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and in the n-type region 50N between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0147] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material. Similarly, the formation of the gate electrode 102 can be performed simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed using different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed using different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0148] After filling the third recess 98, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100 and material of the gate electrode 102, which lie above the top surface of the gate dielectric layer 100. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus forms the alternative gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0149] exist Figures 18A to 18C In this design, the gate structure (including the gate dielectric layer 100 and the corresponding covering gate electrode 102) is recessed, such that a groove is formed directly above the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the groove, followed by a planarization process to remove excess dielectric material extending above the first ILD 96. The gate contact (e.g., gate contact 114, hereinafter referred to) is then formed. Figures 20A to 20C (Discussion) Penetrates the gate shield 104 to contact the recessed top surface of the gate electrode 102.

[0150] like Figures 18A to 18C As further shown, the second ILD106 is deposited over the first ILD96 and over the gate mask 104. In some embodiments, the second ILD106 is a flowable film formed via FCVD. In some embodiments, the second ILD106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0151] exist Figures 19A to 19CIn this process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a fourth recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The fourth recess 108 can be formed by etching using anisotropic etching processes such as RIE or NBE. In some embodiments, the fourth recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the gate mask 104 can be etched through using a second etching process; and then the CESL 94 can be etched through using a third etching process. A mask such as a photoresist can be formed and patterned over the second ILD 106 to shield portions of the second ILD 106 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch; therefore, the fourth groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the fourth groove 108 may be with (e.g., on the same horizontal plane, or at the same distance from the substrate 50) or below (e.g., closer to the substrate 50) the epitaxial source / drain region 92 and / or gate structure. Although Figure 19C The fourth groove 108 is shown to expose the epitaxial source / drain region 92 and the gate structure in the same cross section. In various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short circuits in the subsequently formed contacts.

[0152] After the fourth groove 108 is formed, a first silicide region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal layer (not shown separately) on the exposed portion of the epitaxial source / drain region 92. The material of the metal layer includes, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal layer may react with the underlying semiconductor material of the epitaxial source / drain region 92 (e.g., silicon, silicon-germanium, germanium) to form a silicide or germanide material. A thermal annealing process can then be performed to transform the portion of the epitaxial source / drain region 92 in contact with the metal layer and the portion of the metal layer in contact with the epitaxial source / drain region 92 into the first silicide region 110. The remaining portion of the metal layer can then be removed by a suitable etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region including both silicide and germanide).

[0153] exist Figures 20A to 20CIn this configuration, source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in a fourth recess 108. Source / drain contacts 112 and gate contacts 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, source / drain contacts 112 and gate contacts 114 each comprise a barrier layer and a conductive material, and are each electrically connected to an underlying conductive component (e.g., gate electrode 102 and / or a first conductive component). Gate contact 114 is electrically connected to gate electrode 102, and source / drain contacts 112 are electrically connected to a first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The epitaxial source / drain region 92, the second nanostructure 54 (e.g., a channel region), and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) can be collectively referred to as transistor structure 109. Transistor structure 109 can be commonly disposed in a device layer, wherein the first interconnect structure (e.g., front interconnect structure 120, hereinafter referred to) Figures 21A to 21C (Discussion), formed on the front side of transistor structure 109, a second interconnect structure (e.g., back side interconnect structure 136, hereinafter referred to) Figures 27A to 27C (Discussion) is formed above the back side of transistor structure 109. Although the device layer is described as having a nano-FET, other embodiments may include a device layer having different types of transistors (e.g., planar FET, finFET, thin film transistors (TFT), etc.).

[0154] although Figures 20A to 20C Source / drain contacts 112 extending to each epitaxial source / drain region 92 are shown. These source / drain contacts 112 may be omitted from some epitaxial source / drain regions 92. For example, as explained in more detail below, conductive features (e.g., back vias or power rails) may subsequently be attached through the back of one or more epitaxial source / drain regions 92. For these specific epitaxial source / drain regions 92, the source / drain contacts 112 may be omitted or may be dummy contacts not electrically connected to any overlay wires (such as those referenced below). Figures 21A to 21C The first conductive characteristic discussed is 122).

[0155] Figures 21A to 34C This illustrates intermediate steps in forming a front interconnect structure and a back interconnect structure on transistor structure 109. Both the front and back interconnect structures may include conductive components electrically connected to nanoFETs formed on substrate 50 to provide functional circuitry. Unless otherwise stated, Figures 21A to 34CThe intermediate steps described herein can be applied to both the n-type region 50N and the p-type region 50P. As described above, back-side conductive features (e.g., back-side vias or power rails) can be connected to one or more epitaxial source / drain regions 92. In this way, the source / drain contacts 112 can be selectively omitted from these epitaxial source / drain regions 92.

[0156] exist Figures 21A to 21C In this configuration, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 may be referred to as a front-side interconnect structure because it is formed on the front side of the transistor structure 109 (e.g., on one side of the transistor structure 109 on which active devices are formed). The front-side interconnect structure 120 may include one or more first conductive features 122 formed in one or more stacked first dielectric layers 124. Each stacked first dielectric layer 124 may include a dielectric material, such as a low-k dielectric material, an extra-low-k (ELK) dielectric material, etc. The first dielectric layers 124 may be deposited using appropriate processes, such as CVD, ALD, PVD, PECVD, etc. The first conductive features 122 may include conductive lines and conductive vias interconnecting conductive line layers. Conductive vias may extend through the respective first dielectric layers 124 to provide vertical connections between the conductive lines. The first conductive features 122 may be formed using any acceptable process, such as a damascene process, a dual damascene process, etc.

[0157] In some embodiments, the first conductive feature 122 may be formed using an damascene process, wherein a combination of lithography and etching techniques is used to pattern the corresponding first dielectric layer 124 to form trenches corresponding to a desired pattern for the first conductive feature 122. Optional diffusion barrier layers and / or optional adhesion layers may be deposited, and the trenches may then be filled with a conductive material. Suitable materials for the barrier layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, etc., and suitable materials for the conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, etc. In an embodiment, the first conductive feature 122 may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. Chemical mechanical planarization (CMP) processes may be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124 and planarize the surfaces of the first dielectric layer 124 and the first conductive feature 122 for subsequent processing.

[0158] Figures 21A to 21CThe diagram illustrates five layers of first conductive features 122 and a first dielectric layer 124 in a front-side interconnect structure 120. However, it should be understood that the front-side interconnect structure 120 may include any number of first conductive features 122 disposed in any number of first dielectric layers 124. The front-side interconnect structure 120 may be electrically connected to gate contacts 114 and source / drain contacts 112 to form functional circuitry. In some embodiments, the functional circuitry formed by the front-side interconnect structure 120 may include logic circuitry, memory circuitry, image sensor circuitry, etc.

[0159] Also Figures 21A to 21C As shown, the first bonding layer 152A can be deposited over the front interconnect structure 120. The first bonding layer 152A can facilitate bonding of the carrier substrate in subsequent processes (see...). Figures 22A to 22C The first bonding layer 152A transfers heat generated by the transistor structure 109 to the carrier substrate during operation, as discussed in more detail below. The first bonding layer 152A may include a material suitable for the subsequent dielectric-to-dielectric bonding process and may have high thermal conductivity, such as a metal oxide. Example materials for the first bonding layer 152A may include titanium oxide, aluminum oxide, nickel oxide, zinc oxide, etc. The first bonding layer 152A can be deposited by any suitable method, such as PVD, CVD, ALD, etc. Excess material can then be removed from the surface of the first bonding layer 152A using a planarization process such as CMP, and the surface of the first bonding layer 152A can be planarized for subsequent processing.

[0160] exist Figures 22A to 22C In this process, the carrier substrate 150 is bonded to the front-side interconnect structure 120 by bonding a first bonding layer 152A and a second bonding layer 152B onto the carrier substrate 150. The carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 150 can provide structural support during subsequent processes and in the completed device. The second bonding layer 152B may include a material suitable for dielectric-to-dielectric bonding processes and may have high thermal conductivity, such as a metal oxide. Exemplary materials for the second bonding layer 152B may include titanium oxide, aluminum oxide, nickel oxide, zinc oxide, etc. In some embodiments, the first bonding layer 152A and the second bonding layer 152B may include the same material. The second bonding layer 152B can be deposited using a method similar to that described with respect to the first bonding layer 152A. Excess material can then be removed from the surface of the second bonding layer 152B using a planarization process such as CMP, and the surface of the second bonding layer 152B can be planarized for subsequent processing.

[0161] The dielectric-to-dielectric bonding process may include applying a surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more bonding layers 152. Next, the carrier substrate 150 is aligned with the front interconnect structure 120 and the two are pressed together to initiate pre-bonding of the carrier substrate 150 and the front interconnect structure 120. Pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). After pre-bonding, an annealing process may be applied, for example, by heating the front interconnect structure 120 and the carrier substrate 150 to a temperature in the range of 150°C to 500°C. The annealing process promotes the formation of covalent bonds between the first bonding layer 152A and the second bonding layer 152B. Other bonding processes, such as ambient bonding, vacuum bonding, etc., may be used in other embodiments. After bonding, the first bonding layer 152A and the second bonding layer 152B can be collectively referred to as bonding layer 152.

[0162] In addition, Figures 22A to 22C In this process, after the carrier substrate 150 is bonded to the front interconnect structure 120, the device can be flipped so that the back side of the transistor structure 109 faces upward. The back side of the transistor structure 109 can refer to the side opposite to the front side of the transistor structure 109 on which active elements are formed.

[0163] exist Figures 23A to 23C In this process, a thinning process can be applied to the back side of the substrate 50. The thinning process can include planarization processes (e.g., mechanical polishing, CMP, etc.), etch-back processes, and combinations thereof. The thinning process can expose the surface of the semiconductor layer 91 opposite to the front interconnect structure 120. Furthermore, after the thinning process, a portion of the fin 66 can remain above the gate structure (e.g., gate electrode 102 and gate dielectric layer 100) and the nanostructure 55. Figures 23A to 23C As shown, after the thinning process, the back surfaces of the semiconductor layer 91, the STI region 68, and the fin 66 can be flush with each other.

[0164] exist Figures 24A to 24CIn this process, a second dielectric layer 123 is formed on the back surface of the fin 66 and the STI region 68. After the formation of the second dielectric layer 123, the exposed semiconductor layer 91 can remain. The second dielectric layer 123 can be used to protect the fin 66 in subsequent processes. The second dielectric layer 123 may include a dielectric material such as silicon oxide. The second dielectric layer 123 can be formed by depositing a dielectric layer covering the fin 66, the STI region 68, and the back surface of the semiconductor layer 91 using a suitable deposition process (such as CVD, ALD, etc.). The dielectric layer is then patterned using a suitable lithography process to expose the semiconductor layer 91.

[0165] exist Figures 25A to 25C In this embodiment, a fifth groove 125 is formed by removing the semiconductor layer 91 to expose the back surface of the epitaxial source / drain region 92. The fifth groove 125 also exposes the fin 66, the STI region 68, the first spacer 81, the first internal spacer 90, and the sidewalls of the second dielectric layer 123. The semiconductor layer 91 can be removed by a suitable etching process, which can be an isotropic etching process. In some embodiments, the etching process is a dry etching process using a halogen-based etchant. The etching process can have high etch selectivity for the material of the semiconductor layer 91. Thus, the semiconductor layer 91 can be removed without significantly removing the material of the second dielectric layer 123, the STI region 68, the first spacer 81, the first internal spacer 90, or the epitaxial source / drain region 92. In embodiments where both the semiconductor layer 91 and the epitaxial source / drain region 92 comprise silicon and germanium, the germanium concentration in the semiconductor layer 91 and the epitaxial source / drain region 92 can be varied and selected to achieve this etch selectivity.

[0166] exist Figures 26A to 26C In this process, a third spacer 126, a second dielectric layer 123, a first internal spacer 90, an STI region 68, a first spacer 81, and an epitaxial source / drain region 92 are formed on the sidewalls of the fin 66. The third spacer 126 may include a dielectric material such as silicon nitride. The third spacer 126 can be formed by depositing a dielectric layer covering the back surface and sidewalls of the second dielectric layer 123 and the epitaxial source / drain region 92. The third spacer 126 can achieve the various features described above through a suitable deposition process, such as CVD, ALD, etc. The dielectric layer is then etched using a suitable etching process to remove a portion of the dielectric layer covering the second dielectric layer 123 and the epitaxial source / drain region 92. During the etching process, a portion of the epitaxial source / drain region 92 may also be removed, which may result in a recess on the back surface of the epitaxial source / drain region 92. After the etching process, the bottom surface of the third spacer 126 may also be exposed. In some embodiments, the etching process is a dry etching process using a fluorine-based etchant.

[0167] exist Figures 27A to 27CIn the middle, the composite layer 127 is formed on the back surface of the epitaxial source / drain region 92. Figure 27D Show Figure 27C Region 128 shown has further structural details of composite layer 127. Composite layer 127 can have a high average carrier concentration, which can reduce the contact resistance between epitaxial source / drain region 92 and the conductive contacts (e.g., back vias) subsequently formed over epitaxial source / drain region 92. Composite layer 127 can be a semiconductor layer with a modulated doping distribution. Composite layer 127 can include a series of first sublayers 127A and a series of second sublayers 127B arranged in an alternating pattern, wherein one of the first sublayers 127A can contact the back surface of epitaxial source / drain region 92. Composite layer 127 can contact the bottom surface of third spacer 126. Figure 27D Five first sublayers 127A and five second sublayers 127B in composite layer 127 are shown as examples, and other numbers of first sublayers 127A and second sublayers 127B can be envisioned.

[0168] In the n-type region 50N of the semiconductor device, the epitaxial source / drain region 92 may include silicon and may be doped with n-type dopants, such as phosphorus, arsenic, antimony, etc. The first sublayer 127A and the second sublayer 127B of the composite layer 127 may include the same material and the same dopants as the epitaxial source / drain region 92, such as silicon doped with phosphorus, arsenic, antimony, etc. The epitaxial source / drain region 92 may have a density of approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 The dopant concentration between [variable values]. The first sublayer 127A can be highly doped and can have a dopant concentration of approximately 1 × 10⁻⁶. 21 atoms / cm 3 and approximately 1×10 22 atoms / cm 3 The dopant concentration between [a certain value]. The second sublayer 127B can be lightly doped and can have a dopant concentration of approximately 1 × 10 [units]. 15 atoms / cm 3 and approximately 1×10 21 atoms / cm 3 The dopant concentrations in the first sublayer 127A and the second sublayer 127B can be greater. The dopant concentration in the epitaxial source / drain region 92 can be less than that in the first sublayer 127A and greater than that in the second sublayer 127B. Due to the high dopant concentration in the first sublayer 127A, the composite layer 127 can have a high average dopant concentration, which can be higher than that in the epitaxial source / drain region 92. Therefore, the composite layer 127 can have a high average carrier concentration.

[0169] The composite layer 127 can be formed by repeating cycles of deposition and etching, which may include depositing a first sublayer 127A, depositing a second sublayer 127B, and removing portions of the first sublayer 127A and the second sublayer 127B by an etching process. In some embodiments, the deposition and etching cycles are repeated five to twenty times to form the composite layer 127. During the first cycle of deposition and etching, when the first sublayer 127A is initially deposited, the first sublayer 127A may include an upper portion and a lower portion, the upper portion of which may cover the second dielectric layer 123 and the third spacer 126, and the lower portion of which may cover the epitaxial source / drain region 92. The upper portion of the first sublayer 127A may be amorphous, which may be due to deposition on a dielectric material such as the second dielectric layer 123 and the third spacer 126. The lower portion of the first sublayer 127A may be crystalline, which may be due to deposition on a crystalline semiconductor material such as the epitaxial source / drain region 92. When the second sublayer 127B is initially deposited, the second sublayer 127B may include an upper portion and a lower portion. The upper portion may cover the upper portion of the first sublayer 127A (e.g., an amorphous portion), and the lower portion may cover the lower portion of the first sublayer 127A (e.g., a crystalline portion). The upper portion of the second sublayer 127B may be amorphous, and the lower portion of the second sublayer 127B may be crystalline.

[0170] Next, an etching process is performed to selectively remove the upper portions (e.g., amorphous portions) of the first sublayer 127A and the second sublayer 127B, while the lower portions (e.g., crystalline portions) of the first sublayer 127A and the second sublayer 127B remain substantially intact. Because the second sublayer 127B has a lower dopant concentration than the first sublayer 127A, the etching selectivity between the crystalline and amorphous portions of the second sublayer 127B can be greater than the etching selectivity between the crystalline and amorphous portions of the first sublayer 127A. Therefore, the lower portion (e.g., crystalline portion) of the second sublayer 127B can protect the lower portion (e.g., crystalline portion) of the first sublayer 127A, while the upper portions (e.g., amorphous portions) of the first sublayer 127A and the second sublayer 127B can be removed during the etching process. The deposition and etching cycle is then repeated. During subsequent deposition and etching cycles, the upper portions of the first sublayer 127A and the second sublayer 127B may be amorphous after the deposition process and are removed after the etching process, while the lower portions of the first sublayer 127A and the second sublayer 127B may be crystalline after the deposition process and remain substantially intact after the etching process.

[0171] The first sublayer 127A and the second sublayer 127B can be formed in the n-type region 50N of the semiconductor device and simultaneously in the p-type region 50P of the semiconductor device by appropriate deposition and doping processes (such as CVD with in-situ doping). The process temperature of the deposition and doping process can be below about 450°C. Silane, dichlorosilane, dichlorosilane, hydrogen chloride, chlorine, etc. can be used as precursors for forming the first sublayer 127A and the second sublayer 127B. Phosphine, arsenic, antimony, monomethylsilane, etc. can be used as precursors for forming dopants. The etching process can be a dry etching process using hydrogen chloride, chlorine, etc. as etchants. After completing the deposition and etching cycle, the composite layer 127 can have a density of about 1 × 10⁻⁶. 14 atoms / cm 3 1×10 18 atoms / cm 3 The chlorine concentration between.

[0172] In the p-type region 50P of the semiconductor device, the epitaxial source / drain region 92 may include silicon germanium and may be doped with p-type dopants, such as boron, gallium, etc. The first sublayer 127A and the second sublayer 127B of the composite layer 127 may include the same material and the same dopants as the epitaxial source / drain region 92. Alternatively, the first sublayer 127A and the second sublayer 127B of the composite layer 127 may include materials different from the epitaxial source / drain region 92 and the same dopants as the epitaxial source / drain region 92. In some embodiments, the first sublayer 127A and the second sublayer 127B include silicon germanium doped with p-type dopants (e.g., boron, gallium, etc.). In some embodiments, the first sublayer 127A includes germanium doped with p-type dopants such as boron, gallium, etc., and the second sublayer 127B includes silicon germanium doped with p-type dopants such as boron, gallium, etc. In some embodiments, the first sublayer 127A comprises silicon germanium doped with p-type dopants such as boron, gallium, etc., and the second sublayer 127B comprises silicon doped with p-type dopants such as boron, gallium, or the like.

[0173] The epitaxial source / drain region 92 may have a germanium atom percentage between about 30% and about 50%. The first sublayer 127A may have a germanium atom percentage between about 50% and about 100%. The second sublayer 127B may have a germanium atom percentage between about 0% and about 50%. The germanium atom percentage of the first sublayer 127A may be greater than that of the second sublayer 127B. The germanium atom percentage of the epitaxial source / drain region 92 may be less than that of the first sublayer 127A but greater than that of the second sublayer 127B.

[0174] The epitaxial source / drain region 92 can have approximately 1×10 19 atoms / cm 3 1×10 21atoms / cm 3 The dopant concentration between [a certain value]. The first sublayer 127A can be lightly doped and can have a dopant concentration of approximately 1 × 10 [units]. 15 atoms / cm 3 and approximately 1×10 21 atoms / cm 3 The dopant concentration between [a certain value]. The second sublayer 127B can be highly doped and can have a dopant concentration of approximately 1 × 10 [units]. 21 atoms / cm 3 1×10 22 atoms / cm 3 The dopant concentrations in the first sublayer 127A and the second sublayer 127B can be different. The dopant concentration in the epitaxial source / drain region 92 can be higher than that in the first sublayer 127A and lower than that in the second sublayer 127B. Due to the high dopant concentration in the second sublayer 127B, the composite layer 127 can have a high average dopant concentration, which can be higher than that in the epitaxial source / drain region 92. As a result, the composite layer 127 can have a high average carrier concentration.

[0175] The composite layer 127 can be formed by repeating a cycle of deposition and etching, which may include depositing a first sublayer 127A, depositing a second sublayer 127B, and removing portions of the first sublayer 127A and the second sublayer 127B by an etching process. In some embodiments, the deposition and etching cycle is repeated five to twenty times to form the composite layer 127. During the first deposition and etching cycle, when the first sublayer 127A is initially deposited, the first sublayer 127A may include an upper portion that may cover the second dielectric layer 123 and the third spacer 126 and a lower portion that may cover the second dielectric layer 123 and the third spacer 126. The upper portion of the first sublayer 127A may be amorphous, which may be due to deposition on a dielectric material such as the second dielectric layer 123 and the third spacer 126. The lower portion of the first sublayer 127A may be crystalline, which may be due to deposition on a crystalline semiconductor material such as the epitaxial source / drain region 92. When the second sublayer 127B is initially deposited, the second sublayer 127B may include an upper part and a lower part, the upper part of the second sublayer 127B may cover the upper part of the first sublayer 127A (e.g., the amorphous portion), and the lower part of the second sublayer 127B may cover the lower part of the first sublayer 127A (e.g., the crystalline portion).

[0176] Next, an etching process is performed to selectively remove the upper portions (e.g., amorphous portions) of the first sublayer 127A and the second sublayer 127B, while substantially preserving the lower portions (e.g., crystalline portions) of the first sublayer 127A and the second sublayer 127B. Since the second sublayer 127B has a lower percentage of germanium atoms than the first sublayer 127A, the etching selectivity between the crystalline and amorphous portions of the second sublayer 127B can be greater than that between the crystalline and amorphous portions of the first sublayer 127A. As a result, the lower portion (e.g., crystalline portion) of the second sublayer 127B can protect the lower portion (e.g., crystalline portion) of the first sublayer 127A, while the upper portion (e.g., amorphous portion) of the first sublayer 127A can protect the lower portion (e.g., crystalline portion) of the first sublayer 127A. The deposition and etching cycle is then repeated. In subsequent deposition and etching cycles, the upper portions of the first sublayer 127A and the second sublayer 127B may be amorphous after the deposition process and may be removed after the etching process, while the lower portions of the first sublayer 127A and the second sublayer 127B may be crystalline after the deposition process and remain substantially intact after the etching process.

[0177] The first sublayer 127A and the second sublayer 127B can be formed in the p-type region 50P of the semiconductor device by appropriate deposition and doping processes (such as CVD with in-situ doping), while the n-type region 50N of the semiconductor device can be protected by a mask. During deposition and doping, an increase in the percentage of germanium atoms may lead to a decrease in the dopant concentration. The process temperature for deposition and doping can be below approximately 450°C. Silane, disilane, dichlorosilane, germanane, germanium tetrachloride, hydrogen chloride, chlorine, etc., can be used as precursors for forming the first sublayer 127A and the second sublayer 127B. Diborane, boron trichloride, trimethylgallium, etc., can be used as precursors for forming the dopant. The etching process can be a dry etching process using hydrogen chloride, chlorine, etc., as etchants. After completing the deposition and etching cycle, the composite layer 127 can have a density of approximately 1 × 10⁻⁶. 14 atoms / cm 3 1×10 18 atoms / cm 3 The chlorine concentration between.

[0178] exist Figure 28A The diagram shows the position of the dopant concentration relative to the position of the composite layer 127 in the n-type region 50N of the semiconductor device, which demonstrates the modulated doping distribution of the composite layer 127. The position measurements in this diagram can be performed along... Figure 27DThe composite layer 127 shown is oriented along either the Y-axis or the Z-axis, and the diagram described below can be applied to cross-sections along both the Y-axis and Z-axis. A representative first sublayer 127A and a representative second sublayer 127B are indicated by dashed lines on the position axes in the diagram. The first sublayer 127A may have a thickness T1 of less than about 7.5 nm, and the second sublayer 127B may have a thickness T2 of less than about 7.5 nm. In some embodiments, in the n-type region 50N, the thickness T1 is greater than the thickness T2. The peaks in the diagram, and the corresponding ramps before and after the peaks, can represent the first sublayer 127A. The peaks may represent the core portion of the first sublayer 127A with a high dopant concentration. The peaks may have a thickness T3 of less than about 5 nm. The valleys, and the corresponding ramps before and after the valleys, can represent the second sublayer 127B. The valleys may represent the core portion of the second sublayer 127B with a low dopant concentration. The valleys may have a thickness T4 of less than about 5 nm. The starting point on the position axis in the figure can represent the interface between the epitaxial source / drain region 92 and the first sublayer 127A of the composite layer 127. The other end on the position axis in the figure can represent the top surface of the composite layer 127, where the composite layer 127 can be the second sublayer 127B.

[0179] exist Figure 28B The diagram shows the position of the dopant concentration relative to the position of the composite layer 127 in the p-type region 50P of the semiconductor device, which demonstrates the modulated doping distribution of the composite layer 127. The position measurements in this diagram can be performed along... Figure 27D The composite layer 127 shown is oriented along either the Y-axis or the Z-axis, and the diagram described below can be applied to cross-sections along both the Y-axis and Z-axis. A representative first sublayer 127A and a representative second sublayer 127B are indicated by dashed lines on the position axes in the diagram. The first sublayer 127A may have a thickness T1 of less than about 7.5 nm, and the second sublayer 127B may have a thickness T2 of less than about 7.5 nm. In some embodiments, in the p-type region 50P, the thickness T2 is greater than the thickness T1. Valleys and corresponding ramps before and after valleys can represent the first sublayer 127A. Valleys may represent the core portion of the first sublayer 127A with a low dopant concentration. Valleys may have a thickness T3 of less than about 5 nm. Peaks in the diagram and corresponding ramps before and after peaks can represent the second sublayer 127B. Peaks may represent the core portion of the second sublayer 127B with a high dopant concentration. Peaks may have a thickness T4 of less than about 5 nm. The starting point on the position axis in the figure can represent the interface between the epitaxial source / drain region 92 and the first sublayer 127A of the composite layer 127. The other end on the position axis in the figure can represent the top surface of the composite layer 127, where the composite layer 127 can be the second sublayer 127B.

[0180] Figure 28A and Figure 28BThe graph in the image shows a generally flat peak and valley as an example. In some embodiments, the peaks and valleys may be sloping, with a slope greater than 10 nm / decade, corresponding to an increase or decrease in dopant concentration. As an example, Figure 28A and Figure 28B The graph shows dopant concentrations at substantially the same peak and substantially the same valley. In some embodiments, the dopant concentrations at the peak and valley gradually increase from the beginning to the end of the position axis in the graph. In some embodiments, the dopant concentrations at the peak and valley gradually decrease from the beginning to the end of the position axis in the graph.

[0181] exist Figure 28C The diagram shows the percentage of germanium atoms relative to the position of composite layer 127 in the p-type region 50P of the semiconductor device. The percentage of germanium atoms in the first sublayer 127A and the second sublayer 127B can be inversely proportional to the dopant concentration in the same first sublayer 127A and the second sublayer 127B. The position measurements in this diagram can be taken along... Figure 27D The composite layer 127 is shown along either the Y-axis or the Z-axis, and the diagram described below can be applied to cross-sections along both the Y-axis and Z-axis. A representative first sublayer 127A and a representative second sublayer 127B are shown by dashed lines on the position axis in the diagram. The first sublayer 127A may have a thickness T1 of less than about 7.5 nm, and the second sublayer 127B may have a thickness T2 of less than about 7.5 nm. The peaks in the diagram, and the corresponding ramps before and after the peaks, can represent the first sublayer 127A. The peaks can represent the core portion of the first sublayer 127A with a high dopant concentration. The peaks can have a thickness T3 of less than about 5 nm. The valleys, and the corresponding ramps before and after the valleys, can represent the second sublayer 127B. The valleys can represent the core portion of the second sublayer 127B with a low dopant concentration. The valleys can have a thickness T4 of less than about 5 nm. The starting point on the position axis in the diagram can represent the interface between the epitaxial source / drain region 92 and the first sublayer 127A of the composite layer 127. The other end of the position axis in the figure can represent the top surface of composite layer 127, where composite layer 127 can be the second sublayer 127B.

[0182] exist Figures 29A to 29CIn this process, the upper portion of the composite layer 127 is recessed to form a concave upper surface, thereby improving the overall film quality and increasing the contact area with the subsequently formed silicide regions. Removal of the upper portion of the composite layer can be accomplished by a suitable etching process, such as a dry etching process using a fluorine-based etchant. During the etching process, the upper portion of the composite layer 127 can be removed without significantly removing the second dielectric layer 123 and the third spacer 126. After the etching process, the remaining portion of the top surface of the composite layer 127, which may contact the third spacer 126, can be completely covered by the third spacer 126, and the composite layer 127 may have a concave upper surface disposed below the top surface.

[0183] exist Figures 30A to 30C In the middle, a second silicide region 129 is formed on the composite layer 127 in the fifth groove 125. The second silicide region 129 can be formed by referring to the above reference. Figures 19A to 19C The first silicide region 110 is formed from the same or similar material and through the same or similar process. The thermal annealing process for forming the second silicide region 129 can utilize a lower temperature than the thermal annealing process for forming the first silicide region 110. The portion of the composite layer 127 near the upper surface can be transformed into the second silicide region 129, which can have a recessed upper surface.

[0184] exist Figures 31A to 31D In the middle, the back through hole 130 is formed in the fifth groove 125. Figure 31D Show Figure 31C Further structural details of region 128 and composite layer 127 are shown. A back via 130 can extend on the inner sidewall of the third spacer 126. The back via 130 can extend through fin 66 and STI region 68, and can be electrically connected to epitaxial source / drain region 92 via second silicide region 129 and composite layer 127. Due to the high average doping concentration and average carrier concentration of composite layer 127, the contact resistance between epitaxial source / drain region 92 and back via 130 can be reduced, thereby improving the performance of the semiconductor device.

[0185] The composite layer 127 may have a width W1 between about 5 nm and about 50 nm. The back via 130 may have a width W2 between about 5 nm and about 40 nm. The width W2 may be smaller than the width W1. The composite layer 127 may have a depth D1 between about 5 nm and about 40 nm. The depth D1 may be along... Figure 31D The Z-direction shown is the vertical distance between the bottom surface of the third spacer 126 and the bottom surface of the composite layer 127. The back-side via 130 can have a depth D2 of less than approximately 10 nm. The depth D2 can be along... Figure 31DThe Z-direction shown is the vertical distance between the bottom surface of the third spacer 126 and the bottom surface of the back through-hole 130. Depth D2 can be less than depth D1. The back through-hole 130 can be formed by referring to the upper reference... Figures 20A to 20C The source / drain contacts 112 described are formed of the same or similar materials and by the same or similar processes.

[0186] The above description discloses an embodiment where a composite layer 127 is formed between an epitaxial source / drain region 92 and a back via 130 on the back side of the transistor structure 109 as an example. In some embodiments, the composite layer 127 is formed between more than one epitaxial source / drain region 92 and a corresponding back via 130 on the back side of the transistor structure 109. In some embodiments, the composite layer 127 is formed between one or more epitaxial source / drain regions 92 on the front side of the transistor structure 109 and a corresponding source / drain contact 112. In some embodiments, the composite layer 127 is formed between one or more epitaxial source / drain regions 92 and a corresponding back via 130 on the back side of the transistor structure 109, and the composite layer 127 is formed between one or more epitaxial source / drain regions 92 and a corresponding source / drain contact 112 on the front side of the transistor structure 109. In such embodiments, a first silicide region 110 may be disposed between the composite layer 127 and the source / drain contact 112.

[0187] exist Figures 32A to 32C In this configuration, a third dielectric layer 132 and conductive lines 134 are formed above the second dielectric layer 123, the third spacer 126, and the back via 130. The third dielectric layer 132 can be formed from dielectric materials such as PSG, BSG, BPSG, and USG, and can be formed by suitable deposition methods such as CVD and ALD.

[0188] Conductive lines 134 are formed in a third dielectric layer 132. Forming conductive lines 134 may include, for example, patterning grooves in the third dielectric layer 132 using a combination of lithography and etching processes. The pattern of the grooves in the third dielectric layer 132 may correspond to the pattern of the conductive lines 134. The conductive lines 134 are then formed by depositing conductive material in the grooves. In some embodiments, the conductive lines 134 include a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the conductive lines 134 include copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. An optional diffusion barrier layer and / or an optional adhesive layer may be deposited before filling the grooves with conductive material. Suitable materials for the barrier layer / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, etc. The conductive lines 134 may be formed using, for example, CVD, ALD, PVD, electroplating, etc. The conductive lines 134 are physically and electrically connected to the epitaxial source / drain region 92 via a back via 130 and a second silicide region 129. A planarization process (e.g., CMP, polishing, etch-back, etc.) can be performed to remove excess portions of the conductive lines 134 formed above the third dielectric layer 132.

[0189] In some embodiments, the conductive line 134 is a power rail, which is a wire electrically connecting the epitaxial source / drain region 92 to a reference voltage, a power supply voltage, etc. Placing the power rail on the back side of the resulting semiconductor device, rather than on the front side, offers several advantages. For example, it can increase the gate density of the nanoFET and / or the interconnect density of the front-side interconnect structure 120. Furthermore, the back side of the semiconductor device can accommodate a wider power rail, thereby reducing resistance and improving power transfer efficiency to the nanoFET.

[0190] exist Figures 33A to 33C In this configuration, a fourth dielectric layer 138 and a second conductive feature 140 are formed on the third dielectric layer 132 and the conductive line 134. The second conductive feature 140 may include routing lines in the fourth dielectric layer 138 (e.g., routing for subsequently formed contact pads and external connectors). The fourth dielectric layer 138 may be formed from similar materials using a process similar to that used for the first dielectric layer 124, while the second conductive feature 140 may be formed from similar materials using a process similar to that used for the first conductive feature 122. The second conductive feature 140 may also be patterned to include one or more embedded passive elements, such as resistors, capacitors, inductors, etc. The embedded passive elements may be integrated with the conductive line 134 (e.g., a power rail) to provide circuitry (e.g., power circuitry) on the back side of the nanoFET. The third dielectric layer 132, the conductive line 134, the fourth dielectric layer 138, and the second conductive feature 140 may be collectively referred to as a back-side interconnect structure 136, which may be located on the back side of the device layer in which the transistor structure 109 is disposed (e.g., on one side of the transistor structure opposite the gate electrode 102).

[0191] exist Figures 34A to 34C In this structure, passivation layer 144, UBM 146 and external connector 148 are formed on top of back interconnect structure 136. Figures 34A to 34C The structure shown, including a front interconnect structure 120, a device layer including a transistor structure 109, and a back interconnect structure 136, can be referred to as a semiconductor device 200. The semiconductor device 200 can be referred to as an SPR device. The passivation layer 144 can include polymers such as PBO, polyimide, BCB, etc. Alternatively, the passivation layer 144 can include inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. The passivation layer 144 can be deposited by, for example, CVD, PVD, ALD, etc.

[0192] UBM146 forms a second conductive feature 140 in the back-side interconnect structure 136 through passivation layer 144, and an external connector 148 is formed on UBM146. UBM146 may include one or more layers of copper, nickel, gold, etc., and may be formed by electroplating processes, etc. External connector 148 (e.g., solder balls) is formed on UBM146. Forming external connector 148 may include placing solder balls on exposed portions of UBM146 and reflowing the solder balls. In some embodiments, forming external connector 148 includes performing an electroplating step to form a solder region above the topmost conductor 140C, and then reflowing the solder region. UBM146 and external connector 148 may be used to provide input / output connections to other electrical features, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc. UBM146 and external connector 148 may also be referred to as back-side input / output pads and may provide signal, power supply voltage, and / or ground connections to the aforementioned nanoFETs.

[0193] Figures 35A to 36C Showing with Figures 34A to 34C The embodiments shown are similar to those of semiconductor device 200, wherein the same symbols represent the same features formed by the same process. Figure 35A and Figure 36A Show along Figure 1 The cross-sectional view of reference section A-A' is shown. Figure 35B and Figure 36B Show along Figure 1 The cross-sectional view of reference section B-B' is shown. Figure 35C and Figure 36C Show along Figure 1 The cross-sectional view shown is a reference section C-C'. Figures 35A to 35CIn the illustrated embodiment, a composite layer 127 is formed between the epitaxial source / drain region 92 and the source / drain contact 112 on the front side of the transistor structure 109. A first silicide region 110 may be disposed between the composite layer 127 and the source / drain contact 112. A second silicide region 129 may contact the epitaxial source / drain region 92 on the back side of the transistor structure 109. Figures 36A to 36C In the illustrated embodiment, a composite layer 127 is formed between the epitaxial source / drain region 92 and the back via 130 on the back side of the transistor structure 109, and the composite layer 127 is formed between the epitaxial source / drain region 92 and the source / drain contact 112 on the front side of the transistor structure 109. A first silicide region 110 may be disposed between the composite layer 127 and the source / drain contact 112.

[0194] The embodiments disclosed herein have several advantageous features. By utilizing the above-described deposition and doping methods to form a composite layer 127 with a modulated doping distribution, the composite layer 127 can have a high average dopant concentration and a high average carrier concentration in both the n-type region 50N and the p-type region 50P of the semiconductor device 200. This reduces the contact resistance between the epitaxial source / drain region 92 and the back via 130 and / or the source / drain contact 112. As a result, the performance of the semiconductor device 200 can be improved.

[0195] In some embodiments, the semiconductor device includes a source / drain region; a composite layer on the source / drain region, wherein the composite layer has a modulated doping distribution, and wherein the composite layer includes: a first sublayer on the source / drain region, wherein the first sublayer includes a first semiconductor material and a first dopant having a first dopant concentration; a second sublayer, wherein the first sublayer is located between the second sublayer and the source / drain region, wherein the second sublayer includes a second semiconductor material and a second dopant having a second doping concentration, wherein the second dopant is the same as the first dopant, and wherein the second dopant concentration is different from the first dopant concentration; and a conductive contact above the composite layer, wherein the conductive contact is electrically connected to the source / drain region through the composite layer. In some embodiments, the second semiconductor material is the same as the first semiconductor material. In some embodiments, the source / drain region includes a third semiconductor material and a third dopant having a third doping concentration, wherein the third semiconductor material is the same as the first semiconductor material and a second semiconductor material, wherein the third dopant is the same as the first dopant and the second dopant, and wherein the third dopant concentration is between the first dopant concentration and the second dopant concentration. In some embodiments, the first dopant and the second dopant are the same n-type dopant as the first semiconductor material and the second semiconductor material, wherein the concentration of the first dopant is greater than the concentration of the second dopant. In some embodiments, the first dopant and the second dopant are the same p-type dopant as the first semiconductor material and the second semiconductor material, wherein the concentration of the first dopant is less than the concentration of the second dopant. In some embodiments, the first semiconductor material is silicon-germanium having a first percentage of germanium atoms, wherein the second semiconductor material is silicon-germanium having a second percentage of germanium atoms, wherein the first percentage of germanium atoms is greater than the second percentage of germanium atoms. In some embodiments, the first semiconductor material is silicon-germanium having a first percentage of germanium atoms, wherein the second semiconductor material is silicon-germanium having a second percentage of germanium atoms, wherein the first percentage of germanium atoms is greater than the second percentage of germanium atoms. In some embodiments, the composite layer includes a third sublayer, wherein a second sublayer is located between the first sublayer and the third sublayer, wherein the third sublayer includes a first semiconductor material and a first dopant having a third dopant concentration, and wherein the third dopant concentration is different from the second dopant concentration; and a fourth sublayer, wherein the third sublayer is located between the second sublayer and the fourth sublayer, wherein the fourth sublayer includes a second semiconductor material and a second dopant having a fourth dopant concentration, and wherein the fourth dopant concentration is different from the third dopant concentration.

[0196] In some embodiments, the semiconductor device includes source / drain regions; a composite layer on the source / drain regions, wherein the composite layer includes alternating heavily doped and lightly doped layers, wherein the heavily doped layer includes a first sublayer, wherein the first sublayer includes a first semiconductor material and a first dopant having a first dopant concentration, wherein the lightly doped layer includes a second sublayer located above the first sublayer, wherein the second sublayer includes a second semiconductor material and a second dopant having a second dopant concentration, wherein the second dopant is the same as the first dopant, and wherein the second dopant concentration is less than the first dopant concentration; and conductive contacts are located above the composite layer, wherein the conductive contacts are electrically connected to the source / drain regions through the composite layer. In some embodiments, the first and second dopants are the same n-type dopant as the first and second semiconductor materials, and wherein the first sublayer contacts the source / drain regions. In some embodiments, the first and second dopants are the same p-type dopant as the first and second semiconductor materials, and wherein the second sublayer contacts the source / drain regions. In some embodiments, the source / drain regions include a third dopant having a third dopant concentration, wherein the third dopant is the same as the first and second dopant, and wherein the concentration of the third dopant is greater than the concentration of the second dopant but less than the concentration of the first dopant. In some embodiments, the composite layer includes a higher chlorine concentration than the source / drain regions. In some embodiments, the device further includes a silicide layer disposed between the composite layer and the conductive contacts.

[0197] In some embodiments, a method of forming a semiconductor device includes the following steps: forming a source / drain region; forming a dielectric layer over the source / drain region; and forming a composite layer on the surface of the source / drain region, wherein the composite layer has a modulated doping distribution. The formation of the composite layer includes: forming a first semiconductor layer, wherein an upper portion of the first semiconductor layer is formed on the sidewall of the dielectric layer, and a lower portion of the first semiconductor layer is formed on the surface of the source / drain region, and wherein the first semiconductor layer comprises a first semiconductor material and a first dopant having a first dopant concentration; forming a second semiconductor layer, wherein an upper portion of the second semiconductor layer is formed on the upper portion of the first semiconductor layer, and a lower portion of the second semiconductor layer is formed on the lower portion of the first semiconductor layer, wherein the second semiconductor layer comprises a second semiconductor material and a second dopant having a second dopant concentration, wherein the second dopant is the same as the first dopant, and wherein the concentration of the second dopant is different from the concentration of the first dopant; selectively removing the upper portion of the first semiconductor layer and the upper portion of the second semiconductor layer by a first etching process, wherein the lower portion of the first semiconductor layer and the lower portion of the second semiconductor layer remain on the surface of the source / drain region after the first etching process; and forming a conductive contact above the composite layer, wherein the conductive contact contacts the sidewall of the dielectric layer. In some embodiments, the upper portion of the first semiconductor layer and the upper portion of the second semiconductor layer are amorphous, and wherein the lower portion of the first semiconductor layer and the lower portion of the second semiconductor layer are crystalline. In some embodiments, the first etching process uses a chlorine-based etchant. In some embodiments, the first and second dopants are the same n-type dopants as the first and second semiconductor materials, wherein the concentration of the first dopant is greater than the concentration of the second dopant. In some embodiments, the first and second dopants are the same p-type dopants as the first and second semiconductor materials, wherein the concentration of the first dopant is less than the concentration of the second dopant. In some embodiments, the first semiconductor material is silicon-germanium having a first composition, wherein the second semiconductor material is silicon-germanium having a second composition, wherein the first composition includes more germanium than the second composition. In some embodiments, the composite layer has a modulated percentage distribution of germanium atoms.

[0198] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a substrate, source / drain regions located on the substrate, wherein the source / drain regions have a first surface with a recess. A composite layer is located on the first surface of the source / drain regions, wherein the composite layer includes alternating first heavily doped sublayers and multiple second lightly doped sublayers, and the composite layer has a second surface recessed toward the substrate. A back via is located on the second surface of the composite layer and electrically connected to the source / drain regions through the composite layer. In some embodiments, the composite layer has a first width, and the back via has a second width, the first width being greater than the second width. In some embodiments, the semiconductor device further includes a silicide layer located between the back via and the composite layer. In some embodiments, the recess of the source / drain regions has a depth between 5 nm and 40 nm.

[0199] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a substrate, source / drain regions, a composite layer, a back via, and spacers. The source / drain regions are located on the substrate, wherein the source / drain regions have a first surface. The composite layer is located on the first surface of the source / drain regions, wherein the composite layer includes alternating first heavily doped sublayers and multiple second lightly doped sublayers. The back via is located on the composite layer and is electrically connected to the source / drain regions through the composite layer. The spacers surround the back vias, wherein the bottom surface of the spacers is in direct contact with the first surface of the composite layer. In some embodiments, the semiconductor device further includes conductive lines electrically connected to the back vias. In some embodiments, the semiconductor device further includes source / drain contacts electrically connected to the source / drain regions.

[0200] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a substrate and a transistor. The transistor is disposed on the substrate. The transistor includes a fin, a nanostructure, a gate dielectric layer, a gate electrode, source / drain regions, and a composite layer. The fin protrudes from the substrate. The nanostructure is located on the fin. The gate dielectric layer is located above the top surface of the fin and extends along the top surface, sidewalls, and bottom surface of the nanostructure. The gate electrode is located above the gate dielectric layer. The source / drain regions are disposed on the fin on opposite sides of the gate dielectric layer and the gate electrode, wherein the source / drain regions have a first surface with a recess. The composite layer is located on the first surface of the source / drain regions and extends conformally along the recess, wherein the composite layer includes a plurality of alternating first n-type heavily doped sublayers and a plurality of second n-type lightly doped sublayers, wherein the composite layer has a second surface recessed toward the substrate. In some embodiments, the semiconductor device further includes a back via located on the composite layer and electrically connected to the source / drain regions through the composite layer. In some embodiments, the semiconductor device further includes a silicide layer located between the back via and the composite layer.

[0201] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A source / drain region is located on the substrate, wherein the source / drain region has a first surface and the first surface has a recess; A composite layer is located on the first surface of the source / drain region, wherein the composite layer includes a plurality of alternating first heavily doped sublayers and a plurality of second lightly doped sublayers, and the composite layer has a second surface that is recessed toward the substrate; and A back-side via is located on the second surface of the composite layer and is electrically connected to the source / drain region through the composite layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The composite layer has a first width, and the back through-hole has a second width, the first width being greater than the second width.

3. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A silicide layer is located between the back via and the composite layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The recess in the source / drain region has a depth between 5 nm and 40 nm.

5. A semiconductor device, characterized in that, include: One substrate; A source / drain region is located on the substrate, wherein the source / drain region has a first surface; A composite layer is located on the first surface of the source / drain region, wherein the composite layer includes a plurality of alternating first heavily doped sublayers and a plurality of second lightly doped sublayers; A back-side via is located on the composite layer and is electrically connected to the source / drain region through the composite layer. and A spacer surrounds the back through-hole, wherein a bottom surface of the spacer is in direct contact with the first surface of the composite layer.

6. The semiconductor device as claimed in claim 5, characterized in that, Further includes: A conductive wire is electrically connected to the through hole on the back side.

7. The semiconductor device as claimed in claim 5, characterized in that, Further includes: A source / drain contact is electrically connected to the source / drain region.

8. A semiconductor device, characterized in that, include: One substrate; and A transistor, disposed on the substrate, includes: A fin protrudes from the substrate; A nanostructure is located on the fin; A gate dielectric layer is located on a top surface of the fin and extends along a top surface, a sidewall, and a bottom surface of the nanostructure; A gate electrode is located above the gate dielectric layer; A source / drain region is disposed on the fin on the opposite side of the gate dielectric layer and the gate electrode, wherein the source / drain region has a first surface with a recess; and A composite layer is located on the first surface of the source / drain region and extends conformally along the recess, wherein the composite layer includes a plurality of alternating first n-type heavily doped sublayers and a plurality of second n-type lightly doped sublayers, wherein the composite layer has a second surface that is recessed toward the substrate.

9. The semiconductor device as claimed in claim 8, characterized in that, Further includes: A back-side via is located on the composite layer and is electrically connected to the source / drain region through the composite layer.

10. The semiconductor device as claimed in claim 9, characterized in that, Further includes: A silicide layer is located between the back via and the composite layer.

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