Semiconductor structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure including a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a base structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. The semiconductor structure includes an interface layer around the first, second, and third nanosheets. The semiconductor structure includes a high-k dielectric layer around at least a portion of the first, second, and third nanosheets. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-k dielectric layer on the interface layer around the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-k dielectric layer on the interface layer around the third nanosheet.

Description

Technical Field

[0001] This disclosure pertains to semiconductor structures. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] According to some embodiments of this disclosure, a semiconductor structure includes a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. The semiconductor structure includes an interface layer surrounding the first, second, and third nanosheets. The semiconductor structure includes a high-dielectric-constant dielectric layer surrounding at least a portion of the first, second, and third nanosheets. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet.

[0005] According to some embodiments of this disclosure, a semiconductor structure includes a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. A defect angle is defined between the top surface of the substrate structure of the channel region and a tangent portion, and the defect angle is between 40° and 90°. The semiconductor structure includes an interface layer surrounding the first nanosheet, the second nanosheet, and the third nanosheet. The semiconductor structure includes a high-dielectric-constant dielectric layer disposed around at least a portion of the first nanosheet, at least a portion of the second nanosheet, and at least a portion of the third nanosheet. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet.

[0006] According to some embodiments of this disclosure, a semiconductor structure includes a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. The semiconductor structure includes an interface layer surrounding the first, second, and third nanosheets. The semiconductor structure includes a high-dielectric-constant dielectric layer surrounding at least a portion of the first, second, and third nanosheets. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, wherein the third nanosheet has a length between 5 nm and 12 nm along its bottom surface in the uncovered segment. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating an example method of semiconductor manufacturing, including the manufacture of a multi-gate device, is shown according to some embodiments;

[0009] Figures 2 to 3 , Figures 4A to 4C , Figure 5 , Figures 6A to 6B and Figures 7 to 16 This is a schematic diagram of a semiconductor structure at multiple manufacturing stages according to some embodiments;

[0010] Figure 17 This is a flowchart of an example method for forming a high-dielectric-constant metal gate structure in a semiconductor structure having p-type and p-type regions, according to some embodiments;

[0011] Figures 18A to 18B , Figures 19A to 19B , Figures 20A to 20B , Figures 21A to 21B , Figures 22A to 22B , Figures 23A to 23B , Figures 24A to 24B , Figures 25A to 25B , Figures 26A to 26B , Figures 27A to 27B , Figures 28A to 28B and Figures 29A to 29B This is a schematic diagram of a semiconductor structure at multiple manufacturing stages according to some embodiments;

[0012] Figures 30 to 31 Cross-sectional schematic diagrams of a semiconductor structure at multiple manufacturing stages are illustrated according to some embodiments;

[0013] Figures 32 to 33 Cross-sectional schematic diagrams of sample semiconductor structures at multiple stages of batch testing of metal gates are illustrated according to some embodiments;

[0014] Figures 34 to 37 A schematic cross-sectional view of a sample semiconductor structure undergoing example measurements during batch testing is illustrated according to some embodiments;

[0015] Figures 38 to 41 A cross-sectional schematic diagram of a sample semiconductor structure undergoing example angle measurements during batch testing is illustrated according to some embodiments.

[0016] [Symbol Explanation]

[0017] 100: Method

[0018] 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132: Squares

[0019] 200: Device

[0020] 202:Substrate

[0021] 212: Epitaxial Stacking

[0022] 214: Sacrificial epitaxial layer / epitaxy layer

[0023] 216: Channel epitaxial layer / epitaxy layer / nanofacial sheet

[0024] 220: Fins

[0025] 222: Top layer

[0026] 224: Sacrificial gate structure

[0027] 228: Sacrificial gate electrode layer

[0028] 232: Gate sidewall spacer

[0029] 234: Groove

[0030] 235: Sacrificial epitaxial layer groove

[0031] 238: Inner spacer layer

[0032] 240: Source / Drain Characteristics

[0033] 242: Contact Etching Stop Layer

[0034] 244: Interlayer dielectric layer

[0035] 254: Gate Trench

[0036] 260: Gate structure

[0037] 1700: Method

[0038] 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, 1718, 1720, 1722, 1724, 1726, 1728, 1730, 1732, 1734, 1736: Squares

[0039] 1800: Semiconductor Structure

[0040] 1802:Substrate

[0041] 1804: n-type region / NFET region

[0042] 1806: p-type region / PFET region

[0043] 1808: Source / Drain Characteristics

[0044] 1810: Source / Drain Terminal

[0045] 1812: Spacer layer

[0046] 1813: Inner spacer

[0047] 1814: Interlayer dielectric layer

[0048] 1816:n-type nanostructure

[0049] 1818: p-type nanostructure

[0050] 1820: n-type base structure

[0051] 1822: p-type base structure

[0052] 1824: Gate dielectric layer

[0053] 1826: Virtual Materials

[0054] 1827, 1829: Gate trench

[0055] 1828: Patterned Mask Layer

[0056] 1830: Gap

[0057] 1832: First work function layer

[0058] 1834, 1836: Sidewall Structure

[0059] 1838, 1840: Topmost surface

[0060] 1842: Patterned Mask Layer

[0061] 1844: Second work function layer

[0062] 1846: Merge Layer

[0063] 1848: Adhesive layer

[0064] 3000: Semiconductor Structure

[0065] 3002: n-type nanostructure

[0066] 3004: n-type region

[0067] 3006: p-type nanostructure

[0068] 3008: P-type region

[0069] 3010: First work function layer

[0070] 3012: Virtual Materials

[0071] 3014: Patterned Mask Layer

[0072] 3016: Defect Area

[0073] 3018: High dielectric constant dielectric layer

[0074] 3020: Interface Layer

[0075] 3400, 3500, 3600, 3700, 3800, 3900, 4000, 4100, 4150: p-type nanostructures / nanostructures

[0076] 3802, 3902, 4002, 4102, 4152: Defect Angles

[0077] HAADF: High-angle annular dark field

[0078] NFET: n-type field-effect transistor

[0079] PFET: p-type field-effect transistor

[0080] S1: First Nanosheet

[0081] S2: Second nanosheet

[0082] S3: Third Nanosheet

[0083] X, Y, Z: Direction

[0084] X1-X1′: Cutoff line Detailed Implementation

[0085] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0086] For simplicity, this document may not describe in detail the known techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in semiconductor device manufacture are well-known; therefore, for simplicity, this document will only briefly mention many known processes, or omit them entirely without providing well-known process details. After a full reading of this disclosure, those skilled in the art will readily understand that the structures disclosed herein can be employed with a variety of techniques and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the illustrations may represent multiple components.

[0087] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings of this document.

[0088] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “on top,” “upper,” “top,” “below,” “submerged,” “under,” “lower,” “bottom,” and the like are used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. When spatial relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on the other element, or there may be an intermediate element or layer present.

[0089] Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0090] It should be noted that references such as "an embodiment," "an example embodiment," "exemplary embodiment," "exemplary," and "example" in the specification indicate that the embodiment may include specific features, structures, or characteristics, but each embodiment does not necessarily include specific features, structures, or characteristics. Furthermore, such terms do not necessarily represent the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments falls within the knowledge of those skilled in the art.

[0091] In specific embodiments herein, a "material layer" is a layer comprising at least 50 wt.% of a quality material, such as at least 60 wt.% of a quality material, at least 75 wt.% of a quality material, at least 90 wt.% of a quality material, at least 95 wt.% of a quality material, or at least 99 wt.% of a quality material, while a "material" layer comprises at least 50 wt.% of a quality material, such as at least 60 wt.% of a quality material, at least 75 wt.% of a quality material, at least 90 wt.% of a quality material, at least 95 wt.% of a quality material, or at least 99 wt.% of a quality material. For example, in specific embodiments, an aluminum layer and a layer of aluminum are each a layer of aluminum comprising at least 50 wt.% of, at least 60 wt.% of, at least 75 wt.% of, at least 90 wt.% of, at least 95 wt.% of, or at least 99 wt.% of aluminum.

[0092] It should be understood that the phrases or terms used herein are for descriptive rather than limiting purposes, and therefore the terms or phrases in this specification will be interpreted by those skilled in the art based on the teachings herein.

[0093] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Throughout the description herein, unless otherwise stated, the same reference numerals in different figures refer to the same or similar components formed using the same or similar materials(s) by the same or similar methods.

[0094] Although several embodiments of the semiconductor device are illustrated in the accompanying drawings, additional features may be added to the semiconductor device illustrated in the drawings, and other embodiments of the semiconductor device may replace, modify or delete some of the features described below.

[0095] Additional operations may be provided before, during, and / or after the stages described in these embodiments. Different embodiments may replace or omit some of the stages described below. Additional features may be added to the semiconductor device structure. Different embodiments may replace or omit some of the features described below. Although some embodiments are described as performing operations in a specific order, these operations may be performed in other logical orders.

[0096] As used herein, a “layer” is a region, such as a region including virtual boundaries, and does not need to include uniform thickness. For example, a layer can be a region that includes at least some thickness variations.

[0097] This disclosure generally relates to semiconductor devices and their fabrication processes, and some examples relate to multi-gate devices. Multi-gate devices include transistors with gate structures formed on at least two sides of a channel region. These multi-gate devices can include n-type metal-oxide-semiconductor devices or p-type metal-oxide-semiconductor multi-gate devices. Specific examples herein may be presented as a type of multi-gate transistor, referred to as a gate-all-around (GAA) device. A GAA device includes any device with gate structures or portions of gate structures formed on all four sides of a channel region (e.g., surrounding a portion of the channel region). Devices presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, rod channels, and / or other suitable channel configurations. Device embodiments presented herein may have a single continuous gate structure associated with one or more channel regions (e.g., nanosheets). Those skilled in the art will recognize that other examples of semiconductor devices may benefit from the morphology of this disclosure.

[0098] Figure 1 Flowcharts illustrating an example semiconductor manufacturing method 100 including the fabrication of a multi-gate device are provided according to various embodiments of this disclosure. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device may be referred to as a GAA device having gate material disposed on four sides of at least one channel member of the device. The channel member may be referred to as a "nanostructure" or "nanosheet," and herein, "nanostructure" or "nanosheet" refers to any material portion having a nanoscale or even microscale, and having an extended shape regardless of its cross-sectional shape. Thus, as used herein, the terms "nanostructure" or "nanosheet" refer to both extended material portions with circular and substantially circular cross-sections, and include bundled or rod-shaped material portions, such as those with cylindrical or substantially rectangular cross-sections.

[0099] The following will combine Figures 2 to 3 , Figures 4A to 4C , Figure 5 , Figures 6A to 6B and Figures 7 to 16 describe Figure 1 ,in Figures 2 to 3 , Figures 4A to 4C , Figure 5 , Figures 6A to 6B and Figures 7 to 16 Semiconductor device 200 or structure at multiple manufacturing stages is illustrated according to some embodiments. Method 100 is merely an example and is not intended to limit this disclosure to the specific content described in the claims. Additional steps may be provided before, during, and after method 100, and other embodiments of method 100 may move, replace, or omit some of the steps described below. The semiconductor device 200 illustrated in the figures may have additional features added, and in other embodiments, some features described below may be replaced, modified, or omitted.

[0100] Along with the other method embodiments and example apparatuses described herein, it should be understood that portions of the semiconductor device can be manufactured using semiconductor technology process flows; therefore, only some processes are briefly described herein. Furthermore, the example semiconductor device may include a variety of other devices and features, such as other types of devices including additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but these are simplified for a better understanding of the concepts of this disclosure. In some embodiments, the example apparatus includes multiple interconnectable semiconductor devices (e.g., transistors), including p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), etc. Additionally, it should be noted that the process steps of method 100 and the remaining methods and example drawings provided by the embodiments of this disclosure, including any descriptions with reference to the accompanying drawings, are merely illustrative and not intended to limit the specific content of the claims.

[0101] Figures 2 to 3 , Figures 4A to 4C , Figure 5 , Figures 6A to 6B and Figures 7 to 16 These are schematic diagrams based on some embodiments, illustrating example semiconductor device structures at various manufacturing stages. In some figures, for ease of illustration, some reference numerals for components or features may be omitted to avoid obscuring other components or features.

[0102] In block 102, example method 100 includes providing a substrate. (Reference) Figure 2For example, in one embodiment of block 102, a substrate 202 for forming a semiconductor device 200 is provided. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, the substrate 202 includes a single-crystal semiconductor layer at least on its surface portion. The substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 202 may include compound semiconductors and / or alloy semiconductors. The substrate 202 may include multiple layers, including conductive or insulating layers formed on the semiconductor substrate. Depending on design requirements, the substrate 202 may include multiple doping configurations. For example, different doping profiles (e.g., n-wells, p-wells) may be formed in regions on the substrate 202 for different device types (e.g., n-type field-effect transistors, p-type field-effect transistors). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 has isolation features (e.g., shallow trench isolation (STI) features) that intervene in regions of different device types. Furthermore, the substrate 202 may be strained to enhance performance, the substrate 202 may include a silicon-on-insulator (SOI) structure, and / or the substrate 202 may have other suitable enhancement features.

[0103] In block 104, example method 100 then includes forming an epitaxial stack comprising multiple epitaxial layers over a substrate. (Reference) Figure 3 For example, in one embodiment of block 104, an epitaxial stack 212 is formed over substrate 202. The epitaxial stack 212 includes a sacrificial epitaxial layer 214 of a first component inserted into a channel epitaxial layer 216 of a second component. The first and second components can be different. In one embodiment, the sacrificial epitaxial layer 214 is formed of SiGe, and the channel epitaxial layer 216 is formed of silicon (Si). However, other embodiments may also include first and second components with different oxidation rates and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 comprises SiGe, and the channel epitaxial layer 216 comprises silicon (Si). However, other embodiments may also include first and second components with different oxidation rates and / or etch selectivity. In some embodiments where the sacrificial epitaxial layer 214 comprises SiGe and the channel epitaxial layer 216 comprises Si, the Si oxidation rate of the channel epitaxial layer 216 is lower than the SiGe oxidation rate of the sacrificial epitaxial layer 214. It should be noted that... Figure 3The illustration depicts three sacrificial epitaxial layers 214 and three channel epitaxial layers 216, but is for illustrative purposes only and is not intended to limit the scope of the claims. In various embodiments, any number of epitaxial layers can be formed in the epitaxial stack 212, depending on the desired number of channel regions for the device 200. In some embodiments, the number of channel epitaxial layers 216 is between 2 and 10, such as 3, 4, or 5.

[0104] In some embodiments, the sacrificial epitaxial layer 214 has a thickness of about 4 nanometers to about 12 nanometers. The sacrificial epitaxial layer 214 may have a substantially uniform thickness. In some embodiments, the channel epitaxial layer 216 has a thickness of about 3 nanometers to about 6 nanometers. In some embodiments, the stacked channel epitaxial layers 216 have a substantially uniform thickness.

[0105] As described in more detail below, the channel epitaxial layer 216 can serve as a channel region for a subsequently formed multi-gate device, and the thickness of the channel epitaxial layer 216 is selected based on device performance considerations. The sacrificial epitaxial layer 214 can serve as a space (or gap) reserved between adjacent channel regions of a subsequently formed multi-gate device, and the thickness of the sacrificial epitaxial layer 214 is selected based on device performance considerations.

[0106] As an example, the epitaxial growth of the epitaxial stack 212 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer of, for example, the channel epitaxial layer 216 comprises the same material as the substrate 202, such as silicon (Si). In some embodiments, epitaxial layers 214 and 216 comprise materials different from those of the substrate 202. As described above, in at least some examples, the sacrificial epitaxial layer 214 comprises epitaxially grown Si. 1-x Ge xThe sacrificial epitaxial layer 214 (e.g., x is about 25% to 55%) and the channel epitaxial layer 216 comprises an epitaxially grown Si layer. Alternatively, in some embodiments, either the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), or combinations thereof. As discussed herein, the materials of the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may be selected based on differences in properties providing oxidation and etch selectivity. In several embodiments, the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 are substantially free of dopants (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 (External dopant concentration), for example, no intentional doping during the epitaxial growth process.

[0107] In block 106, example method 100 includes patterning epitaxial stacks to form semiconductor fins (also known as fins). Reference Figure 4A , Figure 4B and Figure 4C For example, in one embodiment of block 106, a plurality of fins 220 are formed extending from substrate 202. In various embodiments, each fin 220 includes an upper portion of staggered sacrificial epitaxial layers 214 and channel epitaxial layers 216, and a bottom portion protruding from substrate 202.

[0108] The fins 220 can be fabricated using suitable processes, including photolithography and etching. The photolithography process may include forming a photoresist layer over the substrate 202 (e.g., over the epitaxial stack 212), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element including the photoresist. In some embodiments, the photoresist may be patterned using an electron beam lithography process to form the mask element. The mask element can then be used to protect areas of the substrate 202 and the epitaxial stack 212 formed on those areas, while the etching process forms trenches in the unprotected areas through the mask layer (e.g., a hard mask), leaving multiple extended fins. The trenches may be etched using dry etching (e.g., reactive ion etching, RIE), wet etching, and / or other suitable processes. The trenches may be filled with a dielectric material to form, for example, shallow trench isolation features intervening between the fins.

[0109] In block 108, example method 100 includes forming one or more sacrificial layers / features over a substrate. (Reference) Figure 5For example, in one embodiment of block 108, a sacrificial gate dielectric layer (not shown) is blanket-deposited over a top layer 222 above fin 220, wherein fin 220 is formed over substrate 202. A sacrificial gate electrode layer 228 is then blanket-deposited over the sacrificial gate dielectric layer and over substrate 202. The sacrificial gate electrode layer 228 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer 228 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, including low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD).

[0110] In block 110, example method 100 includes patterning one or more sacrificial layers / features to form a virtual gate structure on the channel region of the fin. (Reference) Figure 6A and Figure 6B In one embodiment of block 110, a sacrificial gate structure 224 is formed over a fin 220 that will serve as a portion of the channel region. The sacrificial gate structure 224 defines the channel region of the GAA device. The sacrificial gate structure 224 includes a sacrificial gate dielectric layer and a sacrificial gate electrode layer 228. The sacrificial gate structure 224 is formed by forming a mask layer over the sacrificial gate electrode layer. The mask layer may include a pad silicon oxide layer and a silicon nitride mask layer. Subsequently, a patterning operation is performed on the mask layer, and the sacrificial gate dielectric and electrode layer are patterned into the sacrificial gate structure 224. By patterning the sacrificial gate structure 224, the fin 220 is partially exposed on opposite sides of the sacrificial gate structure 224, thereby defining a source / drain (S / D) region. In embodiments of this disclosure, the source and drain may be used alternately, and their structures are substantially identical.

[0111] Referring to block 132 of method 100, the sacrificial gate structure 224 is then removed, and the sacrificial gate structure 224 is replaced by the final gate stack in a subsequent process stage of device 200. Specifically, the sacrificial gate structure 224 is replaced in a later process stage by a high-K dielectric layer (HK) and a metal gate electrode (MG).

[0112] In block 112, example method 100 includes forming gate sidewall spacers on the sidewalls of the sacrificial gate structure. (See reference...) Figure 7 For example, in one embodiment of block 112, gate sidewall spacers 232 are formed on the sidewalls of the sacrificial gate structure 224. In various embodiments, the gate sidewall spacers 232 may include a dielectric material, such as silicon oxide (SiO2). x Silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), SiCN film, silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOCN) film, and / or combinations thereof. In some embodiments, the gate sidewall spacer 232 comprises multiple layers, such as a main spacer wall, an inner liner, and the like. As an example, the gate sidewall spacer 232 can be formed by depositing a dielectric material layer over the sacrificial gate structure 224 using processes such as chemical vapor deposition, sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), atomic layer deposition, physical vapor deposition, or other suitable processes. In some embodiments, after depositing the dielectric material layer, a subsequent etch-back (e.g., anisotropic) process is performed to expose the fins 220 (e.g., source / drain regions) adjacent to and not covered by the sacrificial gate structure 224. A dielectric material layer may be retained on the sidewalls of the sacrificial gate structure 224 as a gate sidewall spacer 232. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The gate sidewall spacer 232 may have a thickness of about 5 nanometers to about 20 nanometers.

[0113] In block 114, example method 100 includes fins in the recessed source / drain regions. (Reference) Figure 8For example, in one embodiment of block 114, fins 220 are recessed in the source / drain region. Stacked epitaxial layers 214 and 216 are etched down into the source / drain region to form a recess 234. In various embodiments, the recess is performed using a suitable etching process, such as a dry etching process, a wet etching process, or a reactive ion etching process. Dry etching can use etchants including bromine-containing gases (e.g., HBr and / or CHBR3), fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), other suitable gases, or combinations thereof.

[0114] In block 116, example method 100 includes grooves in the sacrificial epitaxial layer (e.g., SiGe) forming the epitaxial stack. Reference Figure 9 For example, in one embodiment of block 116, the sacrificial epitaxial layer 214 is etched back to form a sacrificial epitaxial layer groove 235, wherein the top and bottom of the sacrificial epitaxial layer groove 235 are bounded by the channel epitaxial layer 216 and laterally by the recessed sacrificial epitaxial layer 214. The sacrificial epitaxial layer 214 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Alternatively, in block 118, the lateral ends of the sacrificial epitaxial layer 214 exposed in the sacrificial epitaxial layer groove 234 can be selectively oxidized to increase the etch selectivity between the epitaxial layer 214 and the epitaxial layer 216. In some examples, the oxidation process can be performed by exposing the apparatus 200 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0115] In block 118, example method 100 includes forming an inner spacer layer in a sacrificial epitaxial layer groove. Forming the inner spacer layer may include depositing inner spacer material. (Reference) Figure 10 For example, in one embodiment of block 118, an inner spacer layer 238 is formed in the sacrificial epitaxial layer groove 235. The inner spacer layer 238 may include a dielectric material, such as silicon oxide (SiO2). x The inner spacer layer 238 may be composed of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), SiCN, silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOCN), and / or combinations thereof. In some embodiments, the inner spacer layer 238 comprises multiple layers and / or other suitable dielectric materials. In some embodiments, the inner spacer layer 238 is deposited as a conformal layer. The inner spacer layer 238 may be formed by atomic layer deposition or any other suitable method.

[0116] In block 120, example method 100 includes forming source / drain characteristics. (Reference) Figure 11 For example, in one embodiment of block 120, an epitaxial source / drain feature 240 is formed in a recess 234. In some embodiments, the epitaxial source / drain feature 240 includes silicon for an NFET and SiGe for a PFET. In some embodiments, the epitaxial source / drain feature 240 is formed using an epitaxial growth method such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The formed epitaxial source / drain feature 240 contacts a channel epitaxial layer 216, and an inner spacer layer 238 separates the epitaxial source / drain feature 240 from the sacrificial epitaxial layer 214.

[0117] In block 122, example method 100 includes forming a contact etch stop layer (CESL). Reference Figure 12 For example, in one embodiment of block 122, a contact etch stop layer 242 is formed over the source / drain feature 240. The contact etch stop layer 242 may comprise silicon nitride, silicon oxynitride, silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials, and may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. In several embodiments, the contact etch stop layer 242 is formed of SiN.

[0118] In block 124, example method 100 includes forming an interlayer dielectric (ILD) layer. (See reference) Figure 13 For example, in one embodiment of block 124, an interlayer dielectric layer 244 is formed over the contact etch stop layer 242. The interlayer dielectric layer 244 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials. The interlayer dielectric layer 244 may be formed by plasma-enhanced chemical vapor deposition, flow-through chemical vapor deposition, or other suitable methods. In some embodiments, forming the interlayer dielectric layer 244 further includes performing a chemical mechanical planarization (CMP) process to planarize the top surface of the device 200, thereby exposing the top surface of the sacrificial gate structure 224.

[0119] In block 126, example method 100 includes removing the dummy gate stack to form a gate trench. (Reference) Figure 14 In one embodiment of block 126, for example, the sacrificial gate structure 224 is removed to form a gate trench 254. The gate trench 254 exposes the fins 220 in the channel region. During the removal of the sacrificial gate structure 224, an interlayer dielectric layer 244 and a contact etch stop layer 242 protect the epitaxial source / drain features 240. The sacrificial gate structure 224 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the interlayer dielectric layer 244 is oxide, the sacrificial gate electrode layer can be selectively removed using a wet etchant such as a TMAH solution. After the sacrificial gate electrode layer is removed, the sacrificial gate dielectric layer is removed using plasma dry etching and / or wet etching.

[0120] In block 128, example method 100 includes removing the sacrificial epitaxial layer to form nanosheets. (Reference) Figure 15 For example, in one embodiment of block 128, the sacrificial epitaxial layer 214 is removed to release the channel member from the channel region of the GAA device. In the illustrated embodiment, the channel member is a nanosheet-type channel epitaxial layer 216. In several embodiments, the channel epitaxial layer 216 comprises silicon, and the sacrificial epitaxial layer 214 comprises silicon germanium. In several embodiments, multiple sacrificial epitaxial layers 214 are selectively removed by a selective removal process, wherein the selective removal process includes oxidizing the multiple sacrificial epitaxial layers 214 with a suitable oxidant, such as ozone. Thereafter, the oxidized sacrificial epitaxial layers 214 are selectively removed by a dry etching process, for example, by applying HCl gas at a temperature of about 500°C to about 700°C or by applying a mixture of CF4, SF6, and CHF3.

[0121] In block 130, example method 100 includes forming a high-dielectric-constant metal gate structure surrounding and situated above a nanostructure. In various embodiments, the gate structure is a multilayer structure. Each gate structure may include an interfacial layer (IL), a gate dielectric layer, a work function layer, and a gate electrode layer. Reference Figure 16For example, in one embodiment of block 130, a gate structure 260 is formed. In several embodiments, the gate structure 260 is the gate of a multi-gate transistor. In several embodiments, the gate structure 260 is a high-dielectric-constant metal gate stack; however, other compositions are also possible. In several embodiments, the high-dielectric-constant metal gate stack includes a gate dielectric layer, wherein the gate dielectric layer includes an interface layer and a high-dielectric-constant dielectric layer. The high-dielectric-constant dielectric layer surrounds the respective nanosheets 216, and the interface layer intervenes between the high-dielectric-constant dielectric layer and the nanosheets 216. The interface layer may include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The high dielectric constant dielectric layer may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), other suitable high dielectric constant dielectric materials, and / or combinations thereof. The high dielectric constant material may be further selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable materials, and / or combinations thereof. High-dielectric-constant dielectric layers can be formed using any suitable process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, remote plasma chemical vapor deposition (RPCVD), plasma-enhanced chemical vapor deposition, metal-organic chemical vapor deposition, sputtering, electroplating, other suitable processes, and / or combinations thereof. In one embodiment, to ensure the formation of a gate dielectric layer with a uniform thickness around the respective channel layers, a highly conformal deposition process, such as atomic layer deposition, is used to form the gate dielectric layer. The high-dielectric-constant metal gate structure may include additional material layers.

[0122] In several embodiments, multiple wafers are formed in a batch. One or more wafers in a wafer batch can be used as test wafers to determine whether defects were generated in the PFETs within the batch during the formation of the high-dielectric-constant metal gate structure. In the test wafer, a chemical wash is performed after the p-type work function metal is formed around the PFET and NFET, and after the p-type work function metal is removed from around the NFET. Chemical washing makes defects in the PFETs more clearly visible during scanning, such as in a scanning electron microscope (SEM). The scan of the test wafer can reveal the extent of defects in the PFETs, and when the defects are within certain limits, it can be inferred that the PFETs in non-test wafers may have similar defects, but these wafers can still be used without being scrapped. When the PFET defects in the test wafer are not within certain limits, it can be inferred that the non-test wafers may have defects that render the non-test wafers unusable. Chemical cleaning applied to a test wafer can provide insight into the health of the PFETs in a batch of wafers and can increase wafer yield by allowing PFETs with defects within certain limits to be used. This is particularly useful for wafers that use a large number of PFETs simultaneously, such as wafers in memory arrays. Anomalies in a few PFETs in a memory array will not determine the use of the memory array.

[0123] In block 132, example method 100 includes performing further fabrication on a non-test wafer. The semiconductor device can be further fabricated to form multiple features and regions known in the art. For example, subsequent process steps can form contact openings, contact metals, and multiple contacts / vias / wires and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, and configure the multiple features to connect to form a functional circuit that may include one or more multi-gate devices. In a further example, the multilayer interconnect may include, for example, vertical interconnects of vias or contacts and horizontal interconnects of, for example, metal lines. The multiple interconnect features can utilize a variety of conductive materials, including copper, tungsten, and / or silicides. In one example, a copper-associated multilayer interconnect structure is formed using damascene and / or dual damascene processes. Additionally, extra process steps may be performed before, during, and after method 100, and various embodiments of method 100 may replace or omit some of the process steps described above.

[0124] Figure 17 A flowchart of an example method 1700 is illustrated according to some embodiments, wherein example method 1700 is used to form a high-dielectric-constant metal gate structure in a semiconductor structure having p-type and n-type regions. The following will be combined with... Figures 18A to 18B , Figures 19A to 19B , Figures 20A to 20B , Figures 21A to 21B, Figures 22A to 22B , Figures 23A to 23B , Figures 24A to 24B , Figures 25A to 25B , Figures 26A to 26B , Figures 27A to 27B , Figures 28A to 28B and Figures 29A to 29B describe Figure 17 The accompanying drawings illustrate a semiconductor structure 1800 at multiple manufacturing stages according to some embodiments. Method 1700 is merely an example and is not intended to limit this disclosure to the specific content described in the claims. Additional steps may be provided before, during, and after method 1700. Together with the other method embodiments described herein, it should be understood that portions of the semiconductor device can be manufactured using semiconductor technology process flows; therefore, only some processes are briefly described herein.

[0125] Example method 1700 begins at block 1702 and provides a semiconductor structure 1800 including a substrate, wherein the substrate has n-type and p-type regions. Reference Figure 18A and Figure 18B An example is provided of a substrate 1802 having an n-type region 1804 and a p-type region 1806. An n-type field-effect transistor is formed in the n-type region 1804, and a p-type field-effect transistor is formed in the p-type region 1806. The substrate 1802 includes source / drain features 1808, source / drain terminals 1810, a spacer layer 1812, an inner spacer 1813, and an interlayer dielectric layer 1814. The substrate 1802 further includes an n-type nanostructure 1816, a p-type nanostructure 1818, an n-type substrate structure 1820, and a p-type substrate structure 1822.

[0126] In block 1704, example method 1700 includes forming an interface layer around the nanostructure and on exposed portions of the substrate fin structure. The interface layer may be formed of silicon oxide and may be formed by thermal oxidation. In some embodiments, the interface layer has a thickness ranging from about 0.5 nanometers to about 1.5 nanometers.

[0127] In block 1706, example method 1700 includes forming a gate dielectric layer over the interface layer such that the gate dielectric layer surrounds (e.g., wraps) the nanostructure. Reference Figure 19A and Figure 19BIn one example, a gate dielectric layer 1824 is formed over an interface layer, wherein the gate dielectric layer surrounds an n-type nanostructure 1816 and a p-type nanostructure 1818. Additionally, the gate dielectric layer 1824 also covers the sidewalls of the spacer layer 1812 and the inner spacer 1813. The gate dielectric layer 1824 can be formed from one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other applicable high-dielectric-constant dielectric materials, or combinations thereof. The gate dielectric layer 1824 can be formed using chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof. In some embodiments, the gate dielectric layer has a thickness ranging from about 0.5 nanometers to about 3 nanometers.

[0128] In block 1708, example method 1700 involves forming virtual materials above and between the nanostructures. (Reference) Figure 20A and Figure 20B For example, virtual material 1826 is formed above n-type nanostructure 1816 and p-type nanostructure 1818, and virtual material 1826 is formed between n-type nanostructure 1816 and p-type nanostructure 1818. Virtual material 1826 may be made of a metal oxide (e.g., AlO) different from that of the gate dielectric layer. x GaO x TiO x ZnO, NiO x The virtual material 1826 can be formed using chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof, where x can be a positive integer, or a metal (e.g., TiN, TiAl, TiAlN), similar materials, or combinations thereof.

[0129] By forming a virtual material 1826 between the n-type nanostructures 1816 and the p-type nanostructures 1818, the subsequently formed metal gate layer does not need to be formed between the nanostructures, and in the subsequent etching process, the virtual material 1826 between the n-type nanostructures 1816 and the p-type nanostructures 1818 is easier to remove than the subsequently formed metal gate layer.

[0130] In block 1710, example method 1700 includes removing virtual material above the nanostructures, where the virtual material remains between the nanostructures. (Reference) Figure 21A and Figure 21BFor example, dummy material 1826 is removed from above the n-type nanostructure 1816 and the p-type nanostructure 1818, and also removed from the NFET gate trench 1827 and the PFET gate trench 1829. The dummy material 1826 remains between the n-type nanostructure 1816 and the p-type nanostructure 1818. The dummy material 1826 can be removed by an etching process. The etching process can include a dry etching process or a wet etching process.

[0131] In block 1712, example method 1700 involves forming a patterned mask layer over an n-type region while exposing a p-type region. (See reference) Figure 22A and Figure 22B For example, a patterned mask layer 1828 is formed over the NFET region 1804, while exposing the PFET region 1806. The patterned mask layer fills the NFET gate trench 1827. In several embodiments, the patterned mask layer is a patterned bottom anti-reflective coating (BARC) layer. The patterning process for forming the patterned BARC layer may include photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include dry etching or wet etching.

[0132] In block 1714, example method 1700 involves removing virtual material between p-type nanostructures. (Reference) Figure 22A and Figure 22B For example, dummy material 1826 is removed between p-type nanostructures 1818. The dummy material 1826 can be removed by an etching process. The etching process can include a dry etching process or a wet etching process. After the dummy material 1826 is removed from the PFET region 1806, voids 1830 reappear between the p-type nanostructures 1818 of the adjacent channel.

[0133] In block 1716, example method 1700 includes removing a patterned mask layer over an n-type metal gate layer. (Reference) Figure 23A and Figure 23B For example, the patterned mask layer 1828 is removed from the n-type region 1804 using a suitable etching process. In several embodiments, the patterned mask layer 1828 can be removed by an ashing process using N2 and H2.

[0134] In block 1718, example method 1700 includes forming a first work function layer (p-type) over the n-type nanostructure and the p-type nanostructure. (See reference) Figure 24A and Figure 24BFor example, a first work function layer 1832 (p-type) is formed over n-type nanostructures 1816 and p-type nanostructures 1818. The first work function layer 1832 is conformally formed over n-type nanostructures 1816, p-type nanostructures 1818, sidewall structures 1834 in n-type region 1804, sidewall structures 1836 in p-type region 1806, the top surface 1838 in n-type region 1804, and the top surface 1840 in p-type region 1806. The first work function layer 1832 is also conformally formed to surround (enclose) each p-type nanostructure 1818, but does not surround the n-type nanostructure 1816. The first work function layer 1832 is fused in the voids 1830 between adjacent p-type nanostructures 1818. In several embodiments, the first work function layer comprises a p-type work function metal. In several embodiments, the p-type work function metal includes Ti, Al, Zn, W, Nb, Co, or others. The first work function layer can be a multi-layered structure.

[0135] In several embodiments, the first work function layer 1832 is formed of a metallic material. In several embodiments, the first work function layer 1832 includes titanium nitride (TiN), tungsten (W), molybdenum (Mo), tungsten nitride (WN), tungsten carbonitride (WCN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), ruthenium (Ru), or combinations thereof. The first work function layer 1832 can be formed by a conformal deposition process, such as chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof. In some embodiments, the first work function layer 1832 has a thickness of about 1.0 nanometer to about 3.5 nanometers.

[0136] In block 1720, example method 1700 includes forming a patterned masking layer over the p-type metal gate layer to cover a portion of the p-type metal gate layer in the PFET region, while exposing the n-type metal gate layer in the NFET region. Reference Figure 25A and Figure 25B For example, a patterned mask layer 1842 is formed over the PFET region 1806 while exposing the NFET region 1804. The patterned mask layer fills the PFET gate trench 1829. In several embodiments, the patterned mask layer 1842 is a patterned BARC layer. The patterning process for forming the patterned BARC layer may include photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include dry etching or wet etching.

[0137] In block 1722, example method 1700 involves removing the first work function layer from above the n-type region. (See reference) Figure 25A and Figure 25BFor example, the first work function layer 1832 is removed from above the n-type region 1804. The first work function layer 1832 is removed from the n-type region 1804, while the p-type region 1806 remains masked by the patterned masking layer 1842. In several embodiments, a wet etching process is performed to remove the first work function layer 1832 exposed in the n-type region 1804 by the patterned masking layer 1842. In several embodiments, the wet etching process is performed using an etchant solution, such as an acidic HCl solution, NH4OH, or H2SO4 mixed with H2O2 as an oxidant. The etching amount of the wet etching process can be adjusted by changing the etching time and temperature.

[0138] The patterned masking layer 1842 may be defective and expose portions of the first work function layer 1832 surrounding the p-type nanostructure 1818. Removing the first work function layer 1832 above the n-type nanostructure 1816 may remove some of the first work function layer 1832 around and between the p-type nanostructure 1818.

[0139] In block 1724, example method 1700 involves removing virtual material between n-type nanostructures in the n-type region. (Reference) Figure 25A and Figure 25B For example, virtual material 1826 is removed between n-type nanostructures 1816 in n-type region 1804.

[0140] The patterned masking layer 1842 may have defects and expose portions of the first work function layer 1832 surrounding the p-type nanostructure 1818. Removing the virtual material 1826 between the n-type nanostructures 1816 may remove some of the first work function layer 1832 around and between the p-type nanostructures 1818.

[0141] In several embodiments, multiple wafers are formed in a batch. One or more wafers in the batch can be used as test wafers to determine whether defects were generated in the PFETs within the batch during the formation of the high-dielectric-constant metal gate structure.

[0142] In block 1726, example method 1700 includes treating the nanostructure in the test wafer with a chemical cleaner, such as HF, wherein the chemical cleaner removes a high-dielectric-constant dielectric layer (e.g., HfO2) from the location surrounding the p-type nanostructure 1818 and where the first work function layer 1832 has been removed. Using HF for treatment makes defects in the PFET more readily apparent during scanning, thus allowing assessment of defect severity and determination of whether the defect is so severe that scrapping the wafer batch is not necessary.

[0143] In block 1728, example method 1700 includes removing the patterned mask layer 1842 above the p-shaped region 1806. (See reference) Figure 26A and Figure 26B For example, the patterned mask layer 1842 is removed from the p-type region 1806 using a suitable etching process. In several embodiments, the patterned mask layer 1842 can be removed by an ashing process using N2 and H2.

[0144] In block 1730, example method 1700 involves forming a second work function layer on top of the nanostructure. (Reference) Figure 27A and Figure 27B For example, the second work function layer 1844 is conformally formed above the first work function layer 1832 above the n-type nanostructure 1816, around the n-type nanostructure 1816, and above the p-type nanostructure 1818.

[0145] In several embodiments, the second work function layer 1844 comprises an n-type work function metal. In several embodiments, the n-type work function metal may include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium-aluminum alloy (TiAl), titanium-aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), silicon-tantalum nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. The second work function layer may be formed using chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof. In some embodiments, the second work function layer has approximately 28 angstroms (Å) in the x-direction. The thickness is approximately 40 angstroms.

[0146] In block 1732, example method 1700 includes forming a fusion layer over the p-shaped region. (See reference) Figure 28A and Figure 28B For example, a fusion layer 1846 is formed over the p-type region 1806. In several embodiments, the fusion layer 1846 is formed of a metallic material, such as TiN or tungsten (W).

[0147] In block 1734, example method 1700 includes forming an adhesive layer above the second work function layer and above the fusion layer above the n-type region. (Reference) Figure 29A and Figure 29BFor example, an adhesive layer 1848 is formed over a second work function layer 1844 and a fusion layer 1846 above an n-type region 1804. In various embodiments, the adhesive layer 1848 is formed of TiN, Ti, TaN, MoN, WN, other applicable materials, or combinations thereof. In various embodiments, the adhesive layer 1848 is formed by depositing a conductive material of the adhesive layer using a chemical vapor deposition process, a physical vapor deposition process (e.g., evaporation or sputtering), an atomic layer deposition process, an electroplating process, other suitable processes, or combinations thereof. A planarization process or an etch-back process is then performed to remove excess conductive material. In some embodiments, after the planarization process, the top surface of the adhesive layer is substantially flush with the top surface of the second work function layer.

[0148] In block 1736, example method 1700 includes forming a metal gate fill material layer over an n-type region and a metal gate fill material layer over a p-type region. In various embodiments, the metal gate fill material layer may include tungsten (W) or cobalt (Co), and may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Thus, an n-type GAA device is formed in n-type region 1804, and a p-type GAA device is formed in p-type region 1806.

[0149] Figure 30 This is a schematic diagram based on some embodiments, illustrating a cross-sectional view of a semiconductor structure 3000 at a manufacturing stage of a metal gate. The example semiconductor structure 3000 includes an n-type nanostructure 3002 in an n-type region 3004 and a p-type nanostructure 3006 in a p-type region 3008. A first work function layer 3010 (p-type) is formed over the n-type nanostructure 3002 and over and between the p-type nanostructure 3006. In several embodiments, the first work function layer 3010 is conformally formed over the n-type nanostructure 3002 and conformally formed over and around the p-type nanostructure 3006. Because a dummy material 3012 is disposed around the n-type nanostructure 3002, the first work function layer 3010 does not surround the n-type nanostructure 3002. A patterned mask layer 3014, including a patterned BARC layer, is formed over the p-type region 3008 to protect the p-type region 3008 during subsequent manufacturing operations. In this example, the patterned mask layer 3014 has a defect region 3016 in the patterned mask layer 3014, wherein the defect region 3016 exposes a portion of the first work function layer 3010.

[0150] Figure 31This is a schematic diagram based on some embodiments, illustrating a cross-sectional view of the semiconductor structure 3000 at another manufacturing stage of the metal gate. In this manufacturing stage, the first work function layer 3010 is removed from the n-type region 3004, while the p-type region 3008 remains masked by the patterned masking layer 3014. Furthermore, dummy material 3012 is removed between the n-type nanostructures 3002 in the n-type region 3004. During the removal of the first work function layer 3010 around the n-type nanostructures 3002 and / or the removal of the dummy material 3012 around the n-type nanostructures 3002, the exposed portion of the first work function layer 3010 around the p-type nanostructure 3006 is also removed due to the presence of defect regions 3016 in the patterned masking layer 3014.

[0151] Figure 32 This is a schematic diagram according to some embodiments, illustrating a cross-sectional view of a stage of the metal gate of the semiconductor structure 3000 on a test wafer in a test wafer batch. In this stage, chemical cleaning is performed on the semiconductor structure 3000. The chemical cleaning removes a high-dielectric-constant dielectric layer 3018 (e.g., HfO2, ZrO2, SiO2) from around the n-type nanostructure 3002 and around the p-type nanostructure 3006 in the defect region 3016, leaving an interface layer 3020 around the n-type nanostructure 3002 and around the p-type nanostructure 3006. In several embodiments, the chemical cleaning includes concentrations ranging from about 0.1 ppm to about 10 ppm. 7 Acidic chemicals in ppm, such as HF, HCl, H2SO4, CO2 in water, and HBr.

[0152] Figure 33 This is a schematic diagram based on some embodiments, illustrating a cross-sectional view of the metal gate of the semiconductor structure 3000 on a test wafer in a test wafer batch at another stage. In this fabrication stage, the patterned masking layer 3014 is removed from the p-type region 3008. The high-dielectric-constant dielectric layer 3018 on the portion of the p-type nanostructure 3006 not covered by the first work function layer 3010 has been removed. Further fabrication can be performed on the semiconductor structure 3000 on non-test wafers in the wafer batch, and if the PFET conforms to the specific physical properties associated with the p-type nanostructure 3006, the PFET formed in the p-type region 3008 of the non-test wafer in this configuration can be used, as described in more detail below.

[0153] Figure 34This is a schematic diagram according to some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. A second work function layer is formed in the defect regions. The figures illustrate a p-type nanostructure 3400 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 19 nanometers. In various embodiments, the sheet widths of the nanosheets are between about 8 nanometers and about 70 nanometers. In the illustrated example, nanostructure 3400 has damaged regions with a horizontal length of 5.2 nm on the bottom surface of the first nanosheet S1 not covered by the p-type work function metal, a horizontal length of 6.9 nm on the bottom surface of the second nanosheet S2 not covered by the p-type work function metal, and a horizontal length of 10.4 nm on the bottom surface of the third nanosheet S3 not covered by the p-type work function metal. In this example, the damaged regions are chemically cleaned, where the high-dielectric-constant dielectric layer is removed from portions of the first nanosheet S1, second nanosheet S2, and third nanosheet S3 within the damaged regions. Chemical cleaning allows the damaged regions to be revealed for assessment of the degree of damage. PFETs can still be used when the damage is below a certain limit.

[0154] In several embodiments, the PFET is available when the horizontal length of the first nanosheet in the damaged region is less than about 6 nanometers, the horizontal length of the second nanosheet in the damaged region is less than about 8 nanometers, and the horizontal length of the third nanosheet in the damaged region is less than about 12 nanometers.

[0155] In several embodiments, a PFET is available when the horizontal length of the first nanosheet in the damaged region is between 0 nanometers and about 6 nanometers, the horizontal length of the second nanosheet in the damaged region is between about 3 nanometers and about 8 nanometers, and the horizontal length of the third nanosheet in the damaged region is between about 5 nanometers and about 12 nanometers.

[0156] Figure 35This is a schematic diagram according to some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. A second work function layer is formed in the defect regions. The figures illustrate a p-type nanostructure 3500 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 19 nanometers. In various embodiments, the sheet widths of the nanosheets are between about 8 nanometers and about 70 nanometers. In the illustrated example, the nanostructure 3500 has damaged regions, wherein the damaged regions have a horizontal length of 0 nm on the bottom surface of the first nanosheet S1 not covered by the p-type work function metal, a horizontal length of 5.7 nm on the bottom surface of the second nanosheet S2 not covered by the p-type work function metal, and a horizontal length of 9.5 nm on the bottom surface of the third nanosheet S3 not covered by the p-type work function metal. In this example, the damaged regions are chemically cleaned, wherein the chemical cleaning removes the high-dielectric-constant dielectric layer from portions of the first nanosheet S1, second nanosheet S2, and third nanosheet S3 in the damaged regions. The chemical cleaning process allows the damaged regions to be exposed for assessment of the degree of damage. Since the damage is below a certain limit, the PFET is usable. In several embodiments, the PFET is usable when the horizontal length of the first nanosheet in the damaged region is between 0 nm and approximately 6 nm, the horizontal length of the second nanosheet in the damaged region is between approximately 3 nm and approximately 8 nm, and the horizontal length of the third nanosheet in the damaged region is between approximately 5 nm and approximately 12 nm.

[0157] Figure 36This is a schematic diagram according to some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. A second work function layer is formed in the defect regions. The figures illustrate a p-type nanostructure 3600 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 11 nanometers. In various embodiments, the sheet widths of the nanosheets are between about 8 nanometers and about 70 nanometers. In the illustrated example, the nanostructure 3600 has damaged regions with a horizontal length of 0 nm on the bottom surface of the first nanosheet S1 not covered by the p-type work function metal, a horizontal length of 4.7 nm on the bottom surface of the second nanosheet S2 not covered by the p-type work function metal, and a horizontal length of 6.3 nm on the bottom surface of the third nanosheet S3 not covered by the p-type work function metal. In this example, the damaged regions are chemically cleaned, where the high-dielectric-constant dielectric layer is removed from portions of the first nanosheet S1, second nanosheet S2, and third nanosheet S3 within the damaged regions. This chemical cleaning process allows the PFET formed from the p-type nanostructure 3600 to be used instead of being discarded.

[0158] Figure 37This is a schematic diagram based on some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. The figures illustrate a p-type nanostructure 3700 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 11 nanometers. In various embodiments, the sheet widths of the nanosheets are between approximately 8 nanometers and approximately 70 nanometers. In the illustrated example, the nanostructure 3700 has damaged regions having a horizontal length of 0 nm on the bottom surface of the first nanosheet S1 not covered by the p-type work function metal, a horizontal length of 4.4 nm on the bottom surface of the second nanosheet S2 not covered by the p-type work function metal, and a horizontal length of 6.3 nm on the bottom surface of the third nanosheet S3 not covered by the p-type work function metal. In this example, the damaged regions are chemically cleaned, wherein the chemical cleaning removes the high-dielectric-constant dielectric layer from portions of the first nanosheet S1, second nanosheet S2, and third nanosheet S3 in the damaged regions. The chemical cleaning process allows the damaged regions to be exposed for assessment of the degree of damage. Since the damage is below a certain limit, the PFET is usable. In several embodiments, the PFET is usable when the horizontal length of the first nanosheet in the damaged region is between 0 nm and approximately 6 nm, the horizontal length of the second nanosheet in the damaged region is between approximately 3 nm and approximately 8 nm, and the horizontal length of the third nanosheet in the damaged region is between approximately 5 nm and approximately 12 nm.

[0159] Figure 38The figures are schematic diagrams according to some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. The figures illustrate a p-type nanostructure 3800 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 19 nanometers. In various embodiments, the sheet widths of the nanosheets are between approximately 8 nanometers and approximately 70 nanometers. In the illustrated example, nanostructure 3800 has a damaged region with a defect angle 3802 between the top surface of the p-type substrate structure and a tangential portion. The tangential portion begins at an endpoint on the top surface of the topmost nanosheet (e.g., the first nanosheet S1) not covered by the p-type work function metal, extends through an endpoint on the bottom surface of the bottommost nanosheet (e.g., the third nanosheet S3) not covered by the p-type work function metal, and intersects with an extension of the top surface of the p-type substrate structure. In this example, the defect angle 3802 is 50.1°. Chemical cleaning can expose the damaged region to assess the degree of damage. Since the damage is below a certain limit, the PFET is usable. In several embodiments, the PFET is usable when the defect angle is between approximately 40° and 90°.

[0160] Figure 39The figures are schematic diagrams according to some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. The figures illustrate a p-type nanostructure 3900 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 19 nanometers. In various embodiments, the sheet widths of the nanosheets are between approximately 8 nanometers and approximately 70 nanometers. In the illustrated example, nanostructure 3900 has a damaged region with a defect angle 3902 between the top surface of the p-type substrate structure and a tangential portion. The tangential portion begins at an endpoint on the top surface of the topmost nanosheet (e.g., the second nanosheet S2) not covered by the p-type work function metal, extends through an endpoint on the bottom surface of the bottommost nanosheet (e.g., the third nanosheet S3) not covered by the p-type work function metal, and intersects with an extension of the top surface of the p-type substrate structure. In this example, the defect angle 3902 is 47.5°. Chemical cleaning can expose the damaged region to assess the degree of damage. Since the damage is below a certain limit, the PFET is usable. In several embodiments, the PFET is usable when the defect angle is between approximately 40° and 90°.

[0161] Figure 40 This is a schematic diagram based on some embodiments, illustrating a cross-sectional view of a semiconductor structure at a stage where a first work function layer around the n-type region has been removed and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. The figures illustrate a p-type nanostructure 4000 including a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3. In this example, the sheet widths of the first nanosheet S1, the second nanosheet S2, and the third nanosheet S3 are 11 nanometers. In various embodiments, the sheet widths of the nanosheets are between approximately 8 nanometers and approximately 70 nanometers.

[0162] In the illustrated example, nanostructure 4000 has a damaged region with a defect angle 4002 between the top surface of the p-type substrate structure and a tangential portion. The tangential portion begins at an endpoint on the top surface of the topmost nanosheet (e.g., the second nanosheet S2) not covered by the p-type work function metal, extends through an endpoint on the bottom surface of the bottommost nanosheet (e.g., the third nanosheet S3) not covered by the p-type work function metal, and intersects with an extension of the top surface of the p-type substrate structure. In this example, the defect angle 4002 is 72.6°. Chemical cleaning can reveal the damaged region to assess the degree of damage. Since the damage is below a certain limit, the PFET is usable. In several embodiments, the PFET is usable when the defect angle is between approximately 40° and 90°.

[0163] Figure 41 The figures are schematic diagrams according to some embodiments, illustrating a cross-sectional view of a semiconductor structure during a stage where a first work function layer around an n-type region has been removed, and dummy material between the n-type nanostructures in the n-type region has been removed, while the p-type region remains masked by a patterned masking layer. During the removal of the first work function layer around the n-type nanostructures and / or the removal of the dummy material around the n-type nanostructures, the exposed portion of the first work function layer around the p-type nanostructures is also removed due to defect regions in the patterned masking layer. The figures illustrate a p-type nanostructure 4100 comprising a first nanosheet S1, a second nanosheet S2, and a third nanosheet S3, and a p-type nanostructure 4150 comprising the same three nanosheets. In this example, the sheet widths of the first nanosheets S1, second nanosheet S2, and third nanosheet S3 in both p-type nanostructures 4100 and 4150 are 11 nanometers. In various embodiments, the sheet widths of the nanosheets are between approximately 8 nanometers and approximately 70 nanometers.

[0164] In the illustrated example, nanostructure 4100 has a damaged region with a defect angle 4102 between the top surface of the p-type substrate structure and a tangential portion. The tangential portion begins at an endpoint on the top surface of the topmost nanosheet (e.g., the second nanosheet S2) not covered by the p-type work function metal, extends through an endpoint on the bottom surface of the bottommost nanosheet (e.g., the third nanosheet S3) not covered by the p-type work function metal, and intersects with an extension of the top surface of the p-type substrate structure. In this example, the defect angle 4102 is 75.3°. Chemical cleaning can reveal the damaged region to assess the degree of damage. Since the damage is below a certain limit, the PFET is usable. In several embodiments, the PFET is usable when the defect angle is between approximately 40° and 90°.

[0165] In the illustrated example, nanostructure 4150 does not have a damaged area, and defect angle 4152 is located between the top surface of the p-type substrate structure and the tangent portion, which begins at the endpoint of the top surface of the topmost nanosheet (e.g., the first nanosheet S1), extends through the endpoint of the bottommost nanosheet (e.g., the third nanosheet S3), and intersects with the extension of the top surface of the p-type substrate structure. In this example, defect angle 4152 is 90°.

[0166] In some embodiments, the technology described herein relates to a method of fabricating a semiconductor structure, comprising the following steps: providing a first nanostructure of a first type and dummy material between nanosheets of the first nanostructure, and providing a second nanostructure of a second type. Forming a first work function metal layer around the first nanostructure and the second nanostructure, wherein the first work function metal layer is formed between the nanosheets of the second nanostructure, but not between the nanosheets of the first nanostructure. Forming a masking layer over the second nanostructure, wherein the masking layer has defects in the exposed portions of the second nanostructure. Removing the first work function metal layer from around the first nanostructure and the exposed portions of the second nanostructure, and removing the dummy material between the nanosheets of the first nanostructure. Removing the masking layer. Treating the exposed portions of the first nanostructure and the second nanostructure with an acidic chemical agent, wherein the acidic chemical agent removes a high dielectric constant dielectric layer from the exposed portions of the first nanostructure and the second nanostructure. Measuring how much of the first work function metal layer was removed from the nanosheets of the second nanostructure and the nanosheets of the second nanostructure.

[0167] In some cases, the techniques described herein relate to a method for manufacturing a semiconductor structure in which the acidic chemical agents include one or more of HF, HCl, H2SO4, CO2 in water, or HBr.

[0168] In some cases, the technique described herein relates to a method for manufacturing a semiconductor structure, wherein the acidic chemical in water has a concentration between about 0.1 ppm and 10 ppm. 7 Concentrations in ppm.

[0169] In some cases, the techniques described herein relate to a method for manufacturing a semiconductor structure, wherein the first nanostructure comprises an n-type nanostructure and the second nanostructure comprises a p-type nanostructure.

[0170] In some embodiments, the technology described herein relates to a method of fabricating a semiconductor structure, wherein the second nanostructure comprises a plurality of vertically stacked nanosheets, the vertically stacked nanosheets comprising a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. The third nanosheet comprises a covered segment and an uncovered segment, the covered segment having a high-dielectric-constant dielectric layer disposed around the third nanosheet, and the uncovered segment not having a high-dielectric-constant dielectric layer disposed around the third nanosheet.

[0171] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor structure, wherein a second nanosheet includes a covered segment and an uncovered segment, the covered segment having a high-dielectric-constant dielectric layer disposed around the second nanosheet, and the uncovered segment not having a high-dielectric-constant dielectric layer disposed around the second nanosheet.

[0172] In some embodiments, the technique described herein relates to a method of fabricating a semiconductor structure in which a defect angle is defined between the top surface of a substrate structure in a channel region and a tangent portion extending from an endpoint on the top surface of the topmost nanosheet having an uncovered region in a second nanostructure and through an endpoint on the bottom surface of the uncovered region of the bottommost nanosheet of the second nanostructure, and the defect angle is between approximately 40° and 90°.

[0173] In some embodiments, the technology described herein relates to a semiconductor structure. The semiconductor structure includes a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. The semiconductor structure includes an interface layer surrounding the first, second, and third nanosheets. The semiconductor structure includes a high-dielectric-constant dielectric layer disposed around at least a portion of the first, second, and third nanosheets. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet.

[0174] In some cases, the technology described herein relates to a semiconductor structure in which a third nanosheet has a length between about 5 nanometers and about 12 nanometers along the bottom surface of the third nanosheet in an uncovered segment.

[0175] In some embodiments, the technology described herein relates to a semiconductor structure in which a second nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above a high-dielectric-constant dielectric layer on an interface layer surrounding the second nanosheet, and the uncovered segment does not have a first work function metal layer and a high-dielectric-constant dielectric layer on an interface layer surrounding the second nanosheet.

[0176] In some cases, the technology described herein relates to a semiconductor structure in which a second nanosheet has a length between about 3 nanometers and about 8 nanometers along the bottom surface of the second nanosheet in an uncovered segment.

[0177] In some embodiments, the technology described herein relates to a semiconductor structure in which a first nanosheet includes a covered segment and does not include an uncovered segment, wherein the covered segment has a first work function metal layer above a high-dielectric-constant dielectric layer on an interface layer surrounding the first nanosheet, and the uncovered segment does not have a first work function metal layer above a high-dielectric-constant dielectric layer on an interface layer surrounding the first nanosheet.

[0178] In some cases, the technique described herein relates to a semiconductor structure in which a defect angle is defined between the top surface of the substrate structure of the channel region and a tangential portion extending from an endpoint on the top surface of the topmost nanosheet having an uncovered region through an endpoint on the bottom surface of the bottommost nanosheet with an uncovered region, and the defect angle is between approximately 40° and 90°.

[0179] In some cases, the technique described herein relates to a semiconductor structure in which a second nanosheet is the topmost nanosheet and a third nanosheet is the bottommost nanosheet.

[0180] In some cases, the technology described herein relates to a semiconductor structure in which a first nanosheet is the topmost nanosheet and a third nanosheet is the bottommost nanosheet.

[0181] In some embodiments, the technology described herein relates to a method for fabricating a semiconductor structure, comprising the following steps: A masking layer is formed over a nanostructure having multiple vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet, wherein the masking layer has defects in the exposed portions of the nanostructure. A first work function metal layer is removed from around the exposed portions of the nanostructure. The masking layer is removed. The exposed portions of the nanostructure are treated with an acidic chemical agent, wherein the acidic chemical agent removes a high-dielectric-constant dielectric layer from the exposed portions of the nanostructure.

[0182] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor structure, wherein a third nanosheet includes a covered segment and an uncovered segment, the covered segment having a high-dielectric-constant dielectric layer disposed around the third nanosheet, and the uncovered segment not having a high-dielectric-constant dielectric layer disposed around the third nanosheet.

[0183] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor structure, wherein a second nanosheet includes a covered segment and an uncovered segment, the covered segment having a high-dielectric-constant dielectric layer disposed around the second nanosheet, and the uncovered segment not having a high-dielectric-constant dielectric layer disposed around the second nanosheet.

[0184] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor structure, wherein a first nanosheet includes a covered section and does not include an uncovered section, the covered section having a high-dielectric-constant dielectric layer disposed around the first nanosheet, and the uncovered section not having a high-dielectric-constant dielectric layer disposed around the first nanosheet.

[0185] In some embodiments, the technique described herein relates to a method of fabricating a semiconductor structure in which a defect angle is defined between the top surface of a substrate structure in a channel region and a tangent portion extending from an endpoint on the top surface of the topmost nanosheet having an uncovered region in the nanostructure and through an endpoint on the bottom surface of the uncovered region of the bottommost nanosheet in the nanostructure, and the defect angle is between approximately 40° and 90°.

[0186] In some embodiments, the technology described herein relates to a semiconductor structure. The semiconductor structure includes a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. A defect angle is defined between the top surface of the substrate structure of the channel region and a tangential portion, and the defect angle is between 40° and 90°. The semiconductor structure includes an interface layer surrounding the first, second, and third nanosheets. The semiconductor structure includes a high-dielectric-constant dielectric layer disposed around at least a portion of the first, second, and third nanosheets. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet.

[0187] In some cases, the technique described herein relates to a semiconductor structure. A third nanosheet has a length between 5 and 12 nanometers along the bottom surface of the third nanosheet in an uncovered segment.

[0188] In some embodiments, the technology described herein relates to a semiconductor structure. The semiconductor structure includes a plurality of vertically stacked nanosheets, wherein the vertically stacked nanosheets include a first nanosheet above a substrate structure of a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet. A defect angle is defined between the top surface of the substrate structure of the channel region and a tangential portion, and the defect angle is between 40° and 90°. The semiconductor structure includes an interface layer surrounding the first, second, and third nanosheets. The semiconductor structure includes a high-dielectric-constant dielectric layer disposed around at least a portion of the first, second, and third nanosheets. The third nanosheet includes a covered segment and an uncovered segment, wherein the covered segment has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, and the uncovered segment does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet, wherein the third nanosheet has a length between 5 nm and 12 nm along the bottom surface of the third nanosheet in the uncovered segment.

[0189] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist in the embodiments. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with convenient planning for implementing exemplary embodiments of this disclosure. It should be understood that various changes may be made to the function and configuration of the components described in the exemplary embodiments without departing from the scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple vertically stacked nanosheets, including a first nanosheet above a substrate structure in a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet; An interface layer is located around the first nanosheet, the second nanosheet, and the third nanosheet; and A high dielectric constant dielectric layer is located around at least a portion of the first nanosheet, at least a portion of the second nanosheet, and at least a portion of the third nanosheet; The third nanosheet includes a covered section and an uncovered section. The covered section has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet. The uncovered section does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet.

2. The semiconductor structure as described in claim 1, characterized in that, The second nanosheet includes a covered section and an uncovered section. The covered section has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the second nanosheet. The uncovered section does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the second nanosheet.

3. The semiconductor structure as described in claim 2, characterized in that, The second nanosheet has a length between 3 nanometers and 8 nanometers along one bottom surface of the uncovered section.

4. The semiconductor structure as described in claim 1, characterized in that, The first nanosheet includes a covered section and does not include an uncovered section. The covered section has a first work function metal layer above the high dielectric constant dielectric layer on the interface layer surrounding the first nanosheet. The uncovered section does not have the first work function metal layer above the high dielectric constant dielectric layer on the interface layer surrounding the first nanosheet.

5. The semiconductor structure as described in claim 1, characterized in that, A defect angle is defined between a top surface of the substrate structure in the channel region and a tangential portion extending from an end point on a top surface of a top nanosheet having an uncovered region and through an end point on a bottom surface of an uncovered region of a bottom nanosheet, and the defect angle is between 40° and 90°.

6. The semiconductor structure as described in claim 5, characterized in that, The second nanosheet is the topmost nanosheet, and the third nanosheet is the bottommost nanosheet.

7. The semiconductor structure as described in claim 5, characterized in that, The first nanosheet is the topmost nanosheet, and the third nanosheet is the bottommost nanosheet.

8. A semiconductor structure, characterized in that, include: Multiple vertically stacked nanosheets, including a first nanosheet above a substrate structure in a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet, wherein a defect angle is defined between a top surface of the substrate structure in the channel region and a tangent portion, and the defect angle is between 40° and 90°. An interface layer is located around the first nanosheet, the second nanosheet, and the third nanosheet; and A high dielectric constant dielectric layer is located around at least a portion of the first nanosheet, at least a portion of the second nanosheet, and at least a portion of the third nanosheet; The third nanosheet includes a covered section and an uncovered section. The covered section has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet. The uncovered section does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet.

9. The semiconductor structure as described in claim 8, characterized in that, The third nanosheet has a length between 5 nanometers and 12 nanometers along one bottom surface of the uncovered section.

10. A semiconductor structure, characterized in that, include: Multiple vertically stacked nanosheets, including a first nanosheet above a substrate structure in a channel region, a second nanosheet below the first nanosheet, and a third nanosheet below the second nanosheet; An interface layer is located around the first nanosheet, the second nanosheet, and the third nanosheet; and A high dielectric constant dielectric layer is located around at least a portion of the first nanosheet, at least a portion of the second nanosheet, and at least a portion of the third nanosheet; The third nanosheet includes a covered section and an uncovered section. The covered section has a first work function metal layer above the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet. The uncovered section does not have the first work function metal layer and the high-dielectric-constant dielectric layer on the interface layer surrounding the third nanosheet. The third nanosheet has a length between 5 nanometers and 12 nanometers along a bottom surface of the third nanosheet in the uncovered section.

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