Integrated circuit structure

Abstract

Embodiments of the present application provide an integrated circuit structure including a semiconductor substrate, an epitaxial layer on the semiconductor substrate, a first device region including a first transistor device in a first well of doped semiconductor material in the epitaxial layer, a second device region in the epitaxial layer, and a deep trench isolation structure interposed between the first device region and the second device region, wherein the deep trench isolation structure extends through the epitaxial layer and includes a doped semiconductor fill. The deep trench isolation structure can reduce charge carrier flow in undesired paths.

Description

Technical Field

[0001] Embodiments of this utility model relate to an integrated circuit structure, and more particularly to an integrated circuit structure including an isolation structure for suppressing charge flow. Background Technology

[0002] Many integrated circuits (ICs) consist of multiple transistor devices fabricated in different doped regions of a semiconductor die. A field-effect transistor (FET) uses a gate to control an electric field, regulating the flow of charge carriers in the channel region between the source and drain regions of the FET. In some cases, charge carriers in the semiconductor die may flow down unwanted paths and trigger circuit failures. Utility Model Content

[0003] An embodiment of the present invention provides an integrated circuit structure including a semiconductor substrate, an epitaxial layer on the semiconductor substrate, a first device region of a first transistor device in a first well including a doped semiconductor material in the epitaxial layer, a second device region in the epitaxial layer, and a deep trench isolation structure interposed between the first device region and the second device region, wherein the deep trench isolation structure extends through the epitaxial layer and includes a doped semiconductor filler.

[0004] An embodiment of this utility model provides an integrated circuit structure including a P-type semiconductor substrate, a substantially P-type doped epitaxial layer on the P-type semiconductor substrate, a first device region of a first transistor device included in a well of P-type doped semiconductor material in the epitaxial layer, a second region in the epitaxial layer, and a deep trench isolation structure interposed between the first device region and the second region, wherein the deep trench isolation structure extends through the epitaxial layer and includes sidewalls and an N-type doped semiconductor filler electrically connected to the P-type semiconductor substrate, the sidewalls comprising a dielectric material.

[0005] Based on the above, the doped semiconductor filler in the integrated circuit structure of the embodiments of the present invention is configured to capture charge carriers near the bottom of the deep trench isolation structure, thereby preventing charge carriers from moving along unwanted paths and thus improving the isolation between the first device region and the second device region. The doped semiconductor filler may have a doping type complementary to the semiconductor substrate, thereby enhancing the isolation between the first device region and the second device region and significantly reducing current injection (e.g., by more than an order of magnitude).

[0006] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1A A simplified schematic top view of a portion of an example integrated circuit according to this disclosure is shown.

[0008] Figure 1B It shows Figure 1A The portion along Figure 1A An example of a simplified sectional view of the cutting lines.

[0009] Figure 1C It shows Figure 1B An additional embodiment of a simplified cross-sectional view of the portion thereof, wherein some IC interconnect components are formed on the portion.

[0010] Figure 1D It shows Figure 1A and Figure 1B An embodiment of a simplified cross-sectional view of an alternative implementation of the aforementioned portion.

[0011] Figure 1E Embodiments according to this disclosure are shown and related Figure 1B A simplified cross-sectional view of a portion of the integrated circuit associated with the aforementioned part.

[0012] Figure 1F A simplified cross-sectional view of a portion of an integrated circuit according to an alternative embodiment of this disclosure is shown.

[0013] Figure 1G A simplified cross-sectional view of a portion of an integrated circuit according to an alternative embodiment of this disclosure is shown.

[0014] Figure 1H A simplified cross-sectional view of a portion of an integrated circuit according to an alternative embodiment of this disclosure is shown.

[0015] Figure 1I A simplified cross-sectional view of a portion of an integrated circuit according to an alternative embodiment of this disclosure is shown.

[0016] Figure 1J A simplified cross-sectional view of a portion of an integrated circuit according to an alternative embodiment of this disclosure is shown.

[0017] Figure 2-9 Simplified cross-sectional views are shown of various example stages of the fabrication of a deep trench isolation (DTI) structure according to some embodiments of this disclosure.

[0018] Figure 10 This is a flowchart illustrating a method for forming a DTI structure according to some embodiments of the present disclosure. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0020] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0021] A field-effect transistor (FET) uses a voltage level at the gate to control an electric field, thereby regulating the flow of charge carriers in the channel region between the source and drain regions of the FET. One or more source / drain regions may refer to the source or drain individually or collectively, depending on the context. It should be noted that the source and drain of an FET may be collectively referred to as the current-carrying terminals of the FET, to distinguish them from the gate terminals. Current-carrying terminals may also be referred to as charge-carrying terminals. In some cases, such as during the operation of high-power devices carrying relatively large currents, especially when they are adjacent to other devices, charge carriers in the semiconductor die, including those of high-power devices, may be triggered to flow through the die via unintended paths. Charge carriers flowing in unintended paths may thus form parasitic transistor devices in the semiconductor die and cause latch-up or similar failures involving high-power devices. Latch-up can be triggered by, for example, voltage spikes, transient currents, ionizing radiation, or high temperatures. Latch-up then leads to potentially excessive and uncontrolled current, resulting in IC overheating and / or permanent IC damage. In an IC, a specific IC structure adjacent to a latch-up-prone device can electrically isolate the latch-up-prone device from other components of the IC by reducing the flow of charge carriers in unwanted paths, and can significantly reduce the likelihood of latch-up occurring in the IC.

[0022] This disclosure relates to an integrated chip structure including a deep trench isolation (DTI) structure that reduces charge carrier flow in unwanted paths. In some embodiments, the IC structure includes an epitaxial layer on a semiconductor substrate. The epitaxial layer includes a first device region and a second device region. The first device region includes a first transistor device in a first well disposed in the epitaxial layer of a doped semiconductor material. The DTI structure is interposed between the first and second device regions. The DTI structure extends through the epitaxial layer and has a doped semiconductor filler disposed along the bottom surface of the DTI structure. The doped semiconductor filler is configured to trap charge carriers near the bottom of the DTI structure, thereby preventing charge carriers from moving along unwanted paths and thus improving isolation between the first and second device regions. In some embodiments, the doped semiconductor filler may have a doping type complementary to the semiconductor substrate, thereby enhancing isolation between the first and second device regions and significantly reducing current injection (e.g., by more than an order of magnitude).

[0023] Figure 1A A simplified schematic top view of portion 100 of an example integrated circuit according to this disclosure is shown. Note that in Figure 1A In the following diagrams, the different fill patterns of the components are intended to help visually distinguish different types of components. Therefore, unless otherwise stated, different components drawn using the same fill pattern can generally be considered to have similar characteristics. Part 100 includes a first device region 101, which includes a first transistor device 102 (1) and a second transistor device 102 (2). Part 100 also includes a second device region 104 separated from the first device region 101 by a deep trench isolation (DTI) structure 105. The deep trench isolation (DTI) structure 105 can form a trench laterally surrounding the first device region 101.

[0024] The first transistor device 102(1) includes a gate terminal 106(1) and current-carrying terminals (e.g., source and drain terminals) 107(1) and 107(2). The current-carrying terminals 107(1) and 107(2) are formed in a doped well 109 of the epitaxial layer 112. The doped well 109 may be moderately doped with a first type of dopant. The second transistor device 102(2) includes a gate terminal 106(2) and current-carrying terminals (e.g., source and drain terminals) 107(3) and 107(4). The current-carrying terminals 107(3) and 107(4) are formed in a doped well 108, which is formed in the doped well 109. For a particular transistor device 102, the current-carrying terminal 107, serving as the source, is the terminal through which corresponding charge carriers (e.g., electrons or holes) enter the transistor device 102. Accordingly, the drain terminal 107 is the terminal where the corresponding charge carriers (e.g., electrons or holes) leave the transistor device 102. The determination of the source and drain depends on the charge carriers of the particular transistor device 102 and the circuit components to which the transistor device 102 is connected. In some embodiments, the current-carrying terminals 107(2) and 107(3) are drain terminals and the current-carrying terminals 107(1) and 107(4) are source terminals.

[0025] The DTI structure 105, interposed between the first device region 101 and the second device region 104, includes an inner dielectric sidewall 110n, an outer dielectric sidewall 110u (collectively referred to as dielectric sidewall 110), and a doped semiconductor filler 111. The second device region 104 includes a lightly doped epitaxial layer 112. The first device region 101 further includes a region 113, which may contain additional transistor devices (not shown) or other active or passive IC components (not shown).

[0026] Figure 1B It shows Figure 1A Part 100 of the embodiments along Figure 1A A simplified cross-sectional view along section line A-A' shows some additional features of portion 100. An epitaxial layer 112 is formed on a semiconductor substrate 121. The semiconductor substrate 121 may include, for example, single-crystal silicon, on which the epitaxial layer 112 is grown. Alternatively, the semiconductor substrate 121 may include a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), or a more advanced semiconductor substrate. The semiconductor substrate 121 may be heavily doped with a first-type dopant to make it a low-resistivity (or high-conductivity) substrate. In some embodiments, the semiconductor substrate 121 may be heavily doped with a P-type dopant, such as boron (B), aluminum (Al), indium (In), gallium (Ga), or any suitable P-type dopant, to form a low-resistivity P++ substrate. In some embodiments, the heavily doped semiconductor substrate 121 has at least 10-1 ppm.20 10 atoms 20 / cm 3 ), at least 10 19 / cm 3 Or other similar doping concentrations. Note that in some alternative embodiments, the semiconductor substrate 121 has a lower doping concentration, which is less expensive to manufacture than the concentrations described above, and may be classified as enhanced (P+) or moderate (P) doped.

[0027] Epitaxial layer 112 may be lightly doped with a type-1 dopant. In some embodiments, epitaxial layer 112 is lightly doped with a p-type dopant, such as boron (B), aluminum (Al), indium (In), gallium (Ga), or any suitable p-type dopant, to form a lightly doped p-type epitaxial layer 112. In some embodiments, the lightly doped epitaxial layer 112 has approximately 10 cm² per cubic centimeter. 14 Up to 10 15 10 atoms 14 / cm 3 -10 15 / cm 3 Between 10 14 / cm 3 Up to 10 16 / cm 3 The doping concentration can be between or similar to the specified values. The epitaxial layer 112 can be doped using, for example, in-situ doping during deposition, post-deposition diffusion, ion implantation, and / or any other suitable doping method.

[0028] The doped well 109 can be formed, for example, by adding a dopant to the first device region 101 of the epitaxial layer 112. The well 109 can be doped using, for example, diffusion, ion implantation, and / or any other suitable doping method. In some embodiments, the well is moderately doped with a P-type dopant, such as boron (B), aluminum (Al), indium (In), gallium (Ga), or any suitable P-type dopant, to form the P-type well 109. In some embodiments, the moderately doped P-type well 109 has approximately 10 cm² per cubic centimeter. 15 Up to 10 16 10 atoms 15 / cm 3 -10 16 / cm 3 Between 10 15 / cm 3 Up to 10 17 / cm 3 Doping concentration between or other similar values.

[0029] A DTI structure 105, comprising an inner dielectric sidewall 110n, an outer dielectric sidewall 110u, and a doped semiconductor filler 111, extends through the epitaxial layer 112 and into the semiconductor substrate 121. In some embodiments, the DTI structure 105 has a high aspect ratio, wherein, in a cross-sectional view, its height H is at least 4:1 compared to its width W. The dielectric sidewalls 110 providing electrical isolation between adjacent portions of the doped semiconductor filler 111 may comprise silicon dioxide (SiO2), silicon nitride (Si3N4), or other suitable dielectric materials. The doped semiconductor filler 111 may be polysilicon, commonly referred to as polysilicon or poly. The doped semiconductor filler 111 may be reinforced with dopants of a complementary type, wherein the dopant type is complementary to the first type of dopant. For example, if the first type of dopant is a P-type dopant (e.g., P-, P, P+, or P++), then the complementary type of dopant is an N-type dopant (e.g., N-, N, N+, or N++). Conversely, if the first type of dopant is an N-type dopant (e.g., N-, N, N+, or N++), then the complementary type of dopant is a P-type dopant (e.g., P-, P, P+, or P++).

[0030] In some embodiments, the doped semiconductor filler 111 may be enhanced N-type doped (N+) polysilicon, for example, doped with an N-type dopant such as phosphorus (P), antimony (Sb), or arsenic (As). In some embodiments, the doping concentration of the enhanced doped semiconductor filler 111 is approximately 10⁻⁶ per cubic centimeter. 16 Up to 10 20 10 atoms 16 / cm 3 -10 20 / cm 3 The doped semiconductor filler 111 can be doped using, for example, in-situ doping during deposition, post-deposition diffusion, ion implantation, and / or any other suitable doping method.

[0031] In some implementations, the heavy doping concentration (e.g., P++) is at least an order of magnitude larger than the enhancement doping concentration (e.g., P+), which in turn is at least an order of magnitude larger than the medium doping concentration (e.g., P), and the medium doping concentration is at least an order of magnitude larger than the light doping concentration (e.g., P-). For example, in a particular example implementation, the heavy, enhancement, medium, and light doping concentrations may each be approximately 10-. 20 / cm 3 10 19 / cm 3 10 15 / cm 3 and 10 14 / cm 3In another example implementation, the heavy, enhanced, medium, and light doping concentrations can each be approximately 10. 19 / cm 3 10 18 / cm 3 10 17 / cm 3 and 10 16 / cm 3 .

[0032] The proximity region 122 of the semiconductor substrate 121 is adjacent to the doped semiconductor filler 111 and optionally also to a portion of the dielectric sidewall 110—the doping can be enhanced with the same type of dopant as the doped semiconductor filler 111, which is a complementary type of dopant. This doping of the proximity region 122 enhances the ability of the DTI structure to trap charge carriers near the bottom of the DTI structure 105 and prevents them from forming unwanted current paths in portions 100 of the integrated circuit. In some embodiments, the proximity region 122 may be laterally recessed by a non-zero distance from the outermost edge of the dielectric sidewall 110 opposite to the doped semiconductor filler 111. In some embodiments, the proximity region 122 may have an outer edge directly below the dielectric sidewall 110. In some embodiments, the proximity region 122 may extend to a maximum depth directly below the doped semiconductor filler 111 and to a smaller depth extending laterally beyond the doped semiconductor filler 111.

[0033] In some embodiments, the neighboring region 122 may be an enhanced N-type dopant (N+) doped with an N-type dopant, such as phosphorus (P), antimony (Sb), arsenic (As), or any suitable N-type dopant. In some embodiments, the doping concentration of the enhanced-doped neighboring region 122 is approximately 10⁻⁶ per cubic centimeter. 16 Up to 10 20 10 atoms 16 / cm 3 -10 20 / cm 3 The adjacent region 122 can be doped using, for example, in-situ doping during deposition, post-deposition diffusion, ion implantation, and / or any other suitable doping method. The DTI structure with N+ type polysilicon filling and optional N+ adjacent regions, as described above, is particularly useful for suppressing substrate implantation of negative charge carriers (electrons), which is especially advantageous for preventing latch-up.

[0034] In transistor device 102, gate terminal 106 may comprise a metal, such as copper or aluminum, highly conductive doped polysilicon, or any other suitable conductive material. Gate terminal 106 may be formed over a corresponding gate dielectric layer 120 (e.g., 120(1), 120(2)) that separates gate terminal 106 from a corresponding channel region 123 in well 109 or 108. For example, gate terminal 106(1) of the first transistor device 102(1) is separated from channel region 123(1) in well 109 of epitaxial layer 112 by gate dielectric layer 120(1). Gate dielectric layer 120 may comprise, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride, carbon-doped silicon oxide, other suitable dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 120 may include a high dielectric constant dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon hafnium oxide (HfSiO), hafnium silicon oxynitride (HfSiON), tantalum hafnium oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium titanium tantalum oxide (HfTiTaO), hafnium aluminum oxynitride (HfAlON), hafnium zirconium oxide (HfZrO), other suitable high dielectric constant dielectric materials, or combinations thereof.

[0035] In one embodiment, transistor device 102(1) is an N-channel metal-oxide-semiconductor (NMOS) FET, and transistor device 102(2) is a P-channel metal-oxide-semiconductor (PMOS) FET. Transistor devices 102(1) and 102(2) can be high-power transistor devices. It is noteworthy that alternative embodiments of transistor devices 102(1) and 102(2) may have slightly different structures and geometries optimized for handling large currents. NMOS transistor device 102(1) includes enhanced N-type (N+) doped current-carrying terminals 107(1) and 107(2) (e.g., source and drain), which may be doped with N-type dopants such as phosphorus (P), antimony (Sb), arsenic (As), or any suitable N-type dopant. In some embodiments, the doping concentration of the enhanced N-type doped (N+) current-carrying terminals 107(1) and 107(2) is approximately 10⁻⁶ ppm. 16 Up to 10 20 10 atoms 16 / cm 3 -10 20 / cm 3 The current-carrying terminals 107(1) and 107(2) can be doped using, for example, diffusion, ion implantation and / or any other suitable doping method.

[0036] Accordingly, in the same embodiment, the PMOS transistor device 102(2) includes enhanced P-type (P+) doped current-carrying terminals 107(3) and 107(4) (e.g., source and drain), which may be doped with P-type dopants, such as boron (B), aluminum (Al), indium (In), gallium (Ga), or any suitable P-type dopant. The current-carrying terminals 107 of the PMOS transistor device are formed in doped wells 108, which are formed within the aforementioned P-type wells 109 and may be moderately doped with N-type dopants, such as phosphorus (P), antimony (Sb), arsenic (As), or any suitable N-type dopant, to form N-type wells 108. N-type wells 108 may be doped using, for example, diffusion, ion implantation, and / or any other suitable doping method. In some embodiments, the moderately doped N-type well 108 has approximately 103 cm-1. 15 Up to 10 16 10 atoms 15 / cm 3 -10 16 / cm 3 The doping concentrations between ) are as follows. Meanwhile, the doping concentrations of the enhanced P-type doped (P+) current-carrying terminals 107(3) and 107(4) are approximately 10 ppm. 16 Up to 10 20 10 atoms 16 / cm 3 -10 20 / cm 3 The current-carrying terminals 107(1) and 107(2) can be doped using, for example, diffusion, ion implantation and / or any other suitable doping method.

[0037] Figure 1C It shows Figure 1B An embodiment of a simplified cross-sectional view of portion 100, wherein some IC interconnect (or interconnect layer) components are provided above portion 100. Specifically, Figure 1CThe diagram shows an inter-layer dielectric (ILD) 130—e.g., vias 131(1), 131(2), and 131(3)—over the components of portion 100 and vias 131, which connect various components of portion 100—e.g., doped semiconductor filler 111, gate terminal 106(1), and current-carrying terminal 107(2), respectively—through the ILD 130 to a first metallization layer (M1) (not shown). The ILD 130 may be formed by, for example, chemical vapor deposition (CVD), plasma vapor deposition (PVD), spin coating, thermal oxidation, or any suitable technique. The vias 131 may be connected to other vias, ground, power rails, device operating voltages, or other electrically conductive features via contacts 132 (e.g., contact 132(1)) schematically shown. In some embodiments, contact 132(1) connects the doped semiconductor filler 111 to ground or a shared voltage via via 131(1). In some embodiments, contact 132(1) is configured to connect to a non-zero voltage to provide a small positive bias to the doped semiconductor filler 111, for example, via via 131(1). The purpose of connecting the voltage to the doped semiconductor filler 111 is to help trap charge carriers through the bottom of the doped semiconductor filler 111 to prevent these charge carriers from forming unwanted current paths in section 100.

[0038] Via 131 may include a metal, such as copper, aluminum, tungsten, or the like. ILD 130 may include, for example, a low dielectric constant dielectric (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., SiO2), a nitride (e.g., SiN), a carbide (e.g., SiC), an oxynitride (e.g., SiON), a carbon oxide (e.g., SiOC), an undoped silicate glass (USG), doped silicon dioxide (e.g., carbon-doped silicon dioxide), a borosilicate glass (BSG), a phosphoric silicate glass (PSG), a borophosphosilicate glass (BPSG), a fluorinated silicate glass (FSG), a spin-on glass (SOG), or the like.

[0039] Figure 1D It shows Figure 1A and Figure 1BA simplified cross-sectional view of an alternative embodiment 140 of part 100. Specifically, alternative embodiment 140 includes a buried doped barrier layer 141 below and in contact with doped well 109. The buried doped barrier layer 141 may be moderately doped with a complementary type of dopant. In some embodiments, where doped well 109 is a P-type doped well, the buried doped barrier layer 141 is moderately doped with an N-type dopant, such as phosphorus (P), antimony (Sb), arsenic (As), or any suitable N-type dopant, to form an N-type buried layer (NBL). In some embodiments, the moderately doped N-type buried layer has approximately 10 cm² per cubic centimeter. 15 Up to 10 16 10 atoms 15 / cm 3 -10 16 / cm 3 The doping concentration is between [values]. The N-type buried layer is doped using, for example, in-situ doping during deposition, post-deposition diffusion, ion implantation (selectively including annealing), and / or any other suitable doping method. The buried doped barrier layer 141 is used to help electrically isolate the active device in the first device region 101 from devices outside the first device region 101, because the formed junction makes it more difficult for charge carriers to cross the buried doped barrier layer 141.

[0040] Figure 1E Embodiments according to this disclosure are shown and related Figure 1B A simplified cross-sectional view of part 150 of the integrated circuit related to part 100. Part 150 can be considered as... Figure 1B The diagram is a shifted view, with portion 150 showing transistor device 102(3) in the second device region 104. The transistor device 102(3) formed in the doped well 153 in the epitaxial layer 112 is substantially the same as the transistor device 102(1) described above. Well 153 is substantially the same as well 109 described above. The DTI structure 105 helps prevent unwanted flow of charge carriers from transistor devices 102(1) and 102(2) to transistor device 102(3). As will be understood by those skilled in the art, the second device region 104 may include additional transistor devices (not shown), such as transistor devices similar to transistor device 102(2).

[0041] Figure 1F A simplified cross-sectional view of portion 160 of an integrated circuit according to an alternative embodiment of this disclosure is shown. Portion 160 is substantially similar to that described above. Figure 1EThe portion 150 has a neighboring region 122, but no neighboring region 122. Forgoing the formation of the neighboring region 122—in other words, skipping the accompanying photolithography and doping steps—reduces the cost of manufacturing the integrated circuit according to this disclosure. Since the bottom of the doped semiconductor filler 111 remains in direct contact with the semiconductor substrate 121, the doped semiconductor filler 111 serves to capture charge carriers near the bottom of the doped semiconductor filler 111 and prevent them from forming undesirable current paths in the portion 160 of the integrated circuit. Therefore, the neighboring region 122 can be considered an optional feature of any of the foregoing embodiments described herein.

[0042] Figure 1G A simplified cross-sectional view of portion 170 of an integrated circuit according to an alternative embodiment of this disclosure is shown. Portion 170 is substantially similar to that described above. Figure 1E Part 150, but of which DTI structure 171 is higher. Figure 1E The DTI structure 171 is shallower than the DTI structure 105 in the preceding figures. Specifically, the shallower DTI structure 171 (including the outer dielectric sidewall 110u, the inner dielectric sidewall 110n, and the doped semiconductor filler 111) extends through the epitaxial layer 112 but also terminates at the epitaxial layer 112. Because of its shallower depth and the fact that it does not require etching into the semiconductor substrate 121, the shallower DTI structure 171 is... Figure 1E Compared to the DTI structure 105, the DTI structure 171 is simpler, faster, and less expensive to form. It can be formed using a reference elsewhere. Figure 1E The shallower DTI structure 171 is formed using substantially the same technique as the deeper DTI structure 105. The shallower DTI structure 171 also includes a proximity region 122, which is connected to... Figure 1B The adjacent region 122 described above is substantially the same as that in the following figures and can be used with... Figure 1B It is formed in essentially the same manner as the adjacent region 122 in the following figures.

[0043] Figure 1H A simplified cross-sectional view of portion 175 of an integrated circuit according to an alternative embodiment of this disclosure is shown. Portion 175 is substantially similar to that described above. Figure 1G The portion 170 has a neighboring region 122, but no neighboring region 122. Forgoing the formation of the neighboring region 122—in other words, skipping the accompanying photolithography and doping steps—reduces the manufacturing cost of the integrated circuit according to this disclosure. Since the bottom of the doped semiconductor filler 111 remains in direct contact with the epitaxial layer 112, the doped semiconductor filler 111 serves to capture charge carriers near the bottom of the doped semiconductor filler 111 and prevent them from forming undesirable current paths in the portion 175 of the integrated circuit. Therefore, the neighboring region 122 can be considered an optional feature of the shallower DTI structure 171.

[0044] Figure 1I A simplified cross-sectional view of portion 180 of an integrated circuit according to an alternative embodiment of this disclosure is shown. Portion 180 incorporates... Figure 1D Some features of part 140 and Figure 1G Some features of part 170. Specifically, part 180 will refer to Figure 1D The embedded doped barrier layer 141 and as referenced Figure 1G The aforementioned shallower DTI structure 171 is combined. In Figure 1I In the illustrated embodiment, the DTI structure 171 terminates within the buried doped barrier layer 141, and a proximity region 122 is formed within the buried doped barrier layer 141. In other embodiments (not shown), the DTI structure may extend through the buried doped barrier layer 141 and terminate within the epitaxial layer 112, where a proximity region 122 may also be formed. The advantages of the buried doped barrier layer and the shallower DTI structure (at the cost of higher complexity and manufacturing costs) have been referenced above. Figure 1D and Figure 1G The corresponding components are described, and are generally applicable as well. Figure 1I Part 180. The location of the adjacent region 122 in the buried doped barrier layer 141 can bring the additional benefit of preventing parasitic currents.

[0045] Figure 1J A simplified cross-sectional view of portion 190 of an integrated circuit according to an alternative embodiment of this disclosure is shown. Portion 190 incorporates... Figure 1D Some features of part 140 and Figure 1H Some features of part 175. Specifically, part 190 will be as referenced. Figure 1D The embedded doped barrier layer 141 and Figure 1H The shallower DTI structure is combined with a lack of adjacent regions, and therefore the bottom of the doped semiconductor filler 111 contacts the epitaxial layer. Figure 1J In the illustrated embodiment, the DTI structure 171 terminates within a buried doped barrier layer 141, and the bottom of the doped semiconductor filler 111 specifically contacts the buried doped barrier layer 141 formed in the epitaxial layer. The advantages of the buried doped barrier layer and the shallower DTI structure (at the cost of higher complexity and manufacturing cost) have been referenced above. Figure 1D and Figure 1G It has been described, and is generally applicable as well. Figure 1J Part 190. Similarly, the benefits of relinquishing the neighboring zone 122 have been referenced above. Figure 1H It has been described, and is generally applicable as well. Figure 1J Part 190.

[0046] Figure 2-9 Simplified cross-sectional views of various example stages of the fabrication of a DTI structure according to some embodiments of this disclosure are shown. Although Figure 2-9 Described as a series of actions, it should be understood that these actions are not limiting, as the order of these actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In some embodiments, some of the actions shown and / or described may be omitted in whole or in part. In some embodiments, additional actions not described herein may also be performed as part of the manufacturing process.

[0047] Figure 2 A simplified cross-sectional view of a portion 200 of a wafer is shown, the wafer including a semiconductor substrate 121, an epitaxial layer 112 formed on the substrate, and a first-type doped well 109 in the epitaxial layer 112. The semiconductor substrate 121 may be doped using, for example, diffusion, ion implantation (optionally including annealing), and / or any other suitable doping method. The epitaxial layer 112 may be grown over the semiconductor substrate 121 using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable deposition technique.

[0048] Figure 3 It shows Figure 2 A cross-sectional view of portion 200 after being covered by mask layer 301, which may be a suitable photoresist or hard mask layer deposited by spin coating, deposition, or the like. In embodiments where mask layer 301 includes photoresist, a photolithography process may be performed in which mask layer 301 is selectively exposed to photomask-based electromagnetic radiation, thereby altering the solubility of the exposed areas of mask layer 301 to define soluble regions, such as region 302.

[0049] Figure 4 This illustrates the process after removing the soluble region 302 of the mask layer 301 to define an opening 401 in the mask layer 301 corresponding to region 302. Figure 3 A cross-sectional view of part 200. In some embodiments, region 302 can be removed by exposing mask layer 301 to developer of dissolving region 302.

[0050] Figure 5 This illustrates the process after forming the trench 501 defined by the opening 401 in the mask layer 301. Figure 4 A cross-sectional view of part 200. Trench 501 can be formed by dry etching of the epitaxial layer 112 and the semiconductor substrate 121 using a dry etchant of a gaseous mixture of, for example, xenon and fluoride (e.g., XeF6), sulfur and fluoride (e.g., SF6), or some other suitable mixture.

[0051] Figure 6 This illustrates the dielectric sidewall structure 610 after forming the surface of the coated trench 501. Figure 5 A cross-sectional view of portion 200. The dielectric sidewall structure 610 may include, for example, silicon dioxide and may be formed by any suitable deposition technique, such as a deposition process, a thermal oxidation process, etc. In some embodiments, the mask layer 301 may be held in place above the epitaxial layer to prevent the formation of the dielectric sidewall structure 610 along the top surface of the epitaxial layer.

[0052] In some embodiments (not shown), the thickness of the dielectric sidewall structure 610 may be substantially constant along its height. In other embodiments, the thickness of the dielectric sidewall structure 610 may vary with its height. For example, in some embodiments, the dielectric sidewall structure 610 may have a first thickness along the sidewall of the semiconductor substrate 121, a different second thickness along the sidewall of the epitaxial layer 112 below the first type doped well 109, and a different third thickness along the sidewall of the first type doped well 109. In some embodiments, the first thickness may be greater than the second thickness and the second thickness may be less than the third thickness.

[0053] Figure 7 The diagram shows the bottom portion of the dielectric sidewall structure 610 after removing the bottom 701 of the trench 501, leaving the outer dielectric sidewall 110u and the inner dielectric sidewall 110n. Figure 6 A cross-sectional view of part 200. The bottom of the dielectric sidewall structure 610 can be removed, for example, by an etching process. Note that this etching process can be used with reference to... Figure 5 The etching process uses different chemicals because each etching may have a specific chemical to be selective for a specific material. In some embodiments, the mask layer 301 may be held in place above the epitaxial layer to prevent etching of the top surface of the epitaxial layer.

[0054] Figure 8 This illustrates enhanced doping of the semiconductor substrate 121 in the region adjacent to the bottom of trench 501 to form the adjacent region 122. Figure 7 A cross-sectional view of portion 200. The adjacent region 122 can be doped using, for example, diffusion, ion implantation, or any suitable doping technique. In some embodiments, the mask layer 301 may be held in place above the epitaxial layer to prevent dopant from implanting into the top surface of the epitaxial layer.

[0055] Figure 9 This illustrates the process of depositing doped semiconductor filler 111 in trench 501 to form DTI structure 105. Figure 8A cross-sectional view of part 200. The doped semiconductor filler 111 can be deposited using, for example, CVD or any suitable deposition technique. In some embodiments, after the doped semiconductor filler 111 is formed in trench 501, a planarization process can be performed to remove the mask layer (e.g., Figure 8 The 301) and a portion of the doped semiconductor fill 111 outside the trench 501. In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process, an etching process, or the like.

[0056] After the above wafer processing is completed, the wafer can be individually processed into individual dies corresponding to each IC.

[0057] Figure 10 This is a flowchart illustrating a method 1000 for forming a DTI structure according to some embodiments of this disclosure. While the methods and other approaches shown and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted and other actions or events not shown may be included. In some embodiments, an action may correspond, for example, previously... Figure 2-9 The structure shown.

[0058] In action 1001, an epitaxial layer is formed on the semiconductor substrate. Figure 2 Cross-sectional views corresponding to some embodiments of action 1001 are shown.

[0059] In action 1002, a trench is formed through the epitaxial layer to be inserted between the first device region and the second device region of the first transistor device having a first type of doped well. Figure 2-7 Cross-sectional views corresponding to some embodiments of action 1002 are shown.

[0060] In action 1003, enhanced doping is performed in the adjacent region of the semiconductor substrate below the trench using complementary type dopants. Figure 8 Cross-sectional views corresponding to some embodiments of action 1003 are shown.

[0061] In action 1004, the trench is filled with a complementary type of doped semiconductor filler to create a deep trench isolation (DTI) structure. Figure 9 Cross-sectional views corresponding to some embodiments of action 1004 are shown.

[0062] Note that multiple subsequent steps (such as forming a metallization layer and other back-end ofline (BEOL) steps) can be performed to produce a usable working IC device.

[0063] Some embodiments relate to an integrated circuit (IC) structure having a semiconductor substrate, an epitaxial layer on the semiconductor substrate, a first device region having a first transistor device in a first well having a doped semiconductor material in the epitaxial layer, a second device region in the epitaxial layer, and a deep trench isolation (DTI) structure interposed between the first and second device regions. The DTI structure extends through the epitaxial layer and includes a doped semiconductor filler.

[0064] In some embodiments, the deep trench isolation structure includes dielectric sidewalls laterally interposed between the doped semiconductor filler and the epitaxial layer. In some embodiments, the deep trench isolation structure extends into the semiconductor substrate, and the doped semiconductor filler of the deep trench isolation structure is electrically connected to the semiconductor substrate. In some embodiments, the semiconductor substrate is doped with a first type of dopant, the epitaxial layer is doped with the first type of dopant, the first well of the first device region is doped with the first type of dopant, the first transistor device includes a drain and a source doped with complementary type dopant, and the doped semiconductor filler of the deep trench isolation structure is doped with the complementary type of dopant. In some embodiments, the semiconductor substrate includes a neighboring region adjacent to the doped semiconductor filler, and the neighboring region is enhanced with the complementary type of dopant. In some embodiments, the semiconductor substrate is P-type doped, the epitaxial layer is P-type doped, the first well of the first device region is P-type doped, the first transistor device includes an N-type doped drain and an N-type doped source formed in the first well, and the doped semiconductor filler of the deep trench isolation structure is N-type doped. In some embodiments, the semiconductor substrate is heavily P-type doped, the doped semiconductor filler is enhanced N-type doped, the epitaxial layer is lightly P-type doped, and the doping concentration of the heavily P-type doped semiconductor substrate is at least an order of magnitude greater than the doping concentration of the enhanced N-type doped doped semiconductor filler, and the doping concentration of the enhanced N-type doped semiconductor filler is at least an order of magnitude greater than the doping concentration of the lightly P-type doped epitaxial layer. In some embodiments, the first device region further includes an N-type doped second well, the second well including a second transistor device, the second transistor device including an enhanced P-type doped source and an enhanced P-type doped drain formed therein. In some embodiments, the semiconductor substrate includes a proximity region adjacent to the doped semiconductor filler, the proximity region being enhanced N-type doped. In some embodiments, the doped semiconductor filler is configured to be connected to either ground or a positive bias voltage. In some embodiments, the deep trench isolation structure forms a trench laterally surrounding the first device region. In some embodiments, the integrated circuit structure further includes a buried doped barrier layer below and in contact with the first well of the doped semiconductor material in the first device region, wherein the first well of the doped semiconductor material is doped with a first type of dopant, and the buried doped barrier layer is doped with a complementary type of dopant.

[0065] Some embodiments relate to a method of manufacturing an IC structure. The method includes: forming an epitaxial layer on a semiconductor substrate, forming a trench through the epitaxial layer to be interposed between a first device region and a second device region of a first transistor device having a first type of doped well, and filling the trench with a complementary type of doped semiconductor filler to produce a deep trench isolation (DTI) structure.

[0066] In some embodiments, the method further includes forming dielectric sidewalls in the trench before filling the trench with the complementary type of doped semiconductor filler. In some embodiments, forming the trench includes extending the trench into the semiconductor substrate, and filling the trench with the complementary type of doped semiconductor filler includes making the complementary type of doped semiconductor filler electrically connected to the semiconductor substrate. In some embodiments, the method further includes enhancing doping of a neighboring region of the semiconductor substrate below the trench with the complementary type of dopant after forming the trench and before filling the trench, wherein the neighboring region is adjacent to the complementary type of doped semiconductor filler after filling the trench. In some embodiments, forming the trench includes forming a trench laterally surrounding the first device region. In some embodiments, the method further includes forming a buried doped barrier layer in the first device region after forming the epitaxial layer, the buried doped barrier layer being doped with the complementary type of dopant.

[0067] Some embodiments relate to an integrated circuit (IC) structure having a low-resistivity P-type semiconductor substrate, a substantially P-type doped epitaxial layer on the semiconductor substrate, a first device region of a first transistor device in a well comprising P-type doped semiconductor material in the epitaxial layer, a second region in the epitaxial layer, and a deep trench isolation (DTI) structure interposed between the first device region and the second region. The DTI structure extends through the epitaxial layer and includes sidewalls and an N-type doped semiconductor fill electrically connected to the substrate, the sidewalls comprising a dielectric material.

[0068] In some embodiments, the P-type semiconductor substrate includes a proximity region below and adjacent to the N-type doped semiconductor filler in the deep trench isolation structure, and the proximity region is enhanced N-type doped.

[0069] It should be understood that in this written description and the appended claims, the terms "first," "second," "third," etc., are merely general identifying terms used for ease of description and to distinguish different terms. In themselves, these terms do not imply any temporal order or structural proximity of the components and are not intended to describe corresponding components in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An integrated circuit structure, characterized in that, include: Semiconductor substrate; Epitaxial layer on the semiconductor substrate; The first device region includes a first transistor device in a first well of doped semiconductor material in the epitaxial layer; The second device region is located in the epitaxial layer; as well as A deep trench isolation structure is inserted between the first device region and the second device region, wherein the deep trench isolation structure extends through the epitaxial layer and includes a doped semiconductor filler.

2. The integrated circuit structure according to claim 1, characterized in that, The deep trench isolation structure includes a dielectric sidewall laterally inserted between the doped semiconductor filler and the epitaxial layer.

3. The integrated circuit structure according to claim 1, characterized in that, in: The deep trench isolation structure extends into the semiconductor substrate; and The doped semiconductor filler of the deep trench isolation structure is electrically connected to the semiconductor substrate.

4. The integrated circuit structure according to claim 1, characterized in that, in: The semiconductor substrate is doped with a first type of dopant; The epitaxial layer is doped with the first type of dopant; The first well in the first device area is doped with the first type of dopant; The first transistor device includes a drain and a source doped with complementary dopants; and The doped semiconductor filler of the deep trench isolation structure is doped with the complementary type of dopant.

5. The integrated circuit structure according to claim 4, characterized in that, in: The semiconductor substrate includes a proximity region adjacent to the doped semiconductor filler; and The adjacent region is enhanced with the complementary type of dopant.

6. The integrated circuit structure according to claim 1, characterized in that, The doped semiconductor filler is configured to be connected to either ground or a positive bias voltage.

7. The integrated circuit structure according to claim 1, characterized in that, The deep trench isolation structure forms a trench that laterally surrounds the first device area.

8. The integrated circuit structure according to claim 1, characterized in that, Also includes: An embedded, doped barrier layer is located below and in contact with the first well of the doped semiconductor material in the first device region, wherein: The first well of the doped semiconductor material is doped with a first type of dopant; and The embedded doped barrier layer is doped with complementary type dopants.

9. An integrated circuit structure, characterized in that, include: P-type semiconductor substrate; The epitaxial layer is P-type doped on the P-type semiconductor substrate; The first device region includes a first transistor device in a well of P-type doped semiconductor material in the epitaxial layer; The second region is located within the epitaxial layer; as well as A deep trench isolation structure, inserted between the first device area and the second area, wherein the deep trench isolation structure extends through the epitaxial layer and includes: Sidewalls, including dielectric material; and The N-type doped semiconductor filler is electrically connected to the P-type semiconductor substrate.

10. The integrated circuit structure according to claim 9, characterized in that, in: The P-type semiconductor substrate includes a proximity region below and adjacent to the N-type doped semiconductor filler in the deep trench isolation structure; and The adjacent region is enhanced N-type doped.

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