A transient voltage suppression protection device

Abstract

A transient voltage suppression protection device includes one or more cells, each cell including a substrate of a first doping type, an epitaxial layer of a second doping type on the substrate, a separation structure dividing the epitaxial layer into a first region and a second region, a buried layer of the second doping type between the epitaxial layer and the substrate in the second region, a first doped region of the second doping type on a first surface of the epitaxial layer in the first region and extending into the epitaxial layer in the first region, a second doped region of the first doping type on the first surface of the epitaxial layer in the second region and extending into the epitaxial layer in the second region, a fourth doped region of the second doping type exposed on a surface of the substrate away from the epitaxial layer, and a trench extending from the surface of the epitaxial layer in the second region toward the buried layer at least to the buried layer in the second region, the trench filled with a conductive fill layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a transient voltage suppression and protection device. Background Technology

[0002] In modern electronic systems, transient voltage events (such as electrostatic discharge, lightning surges, and power switching surges) are one of the main causes of damage to electronic equipment. To protect sensitive electronic components from transient voltage damage, transient voltage suppressor (TVS) devices are widely used in various circuits. However, as electronic devices become increasingly high-speed and highly integrated, higher demands are placed on the performance of TVS devices, especially in high-speed signal lines (such as USB, HDMI, and Ethernet). These devices not only need to have efficient transient voltage suppression capabilities but also low capacitance and low clamping voltage to avoid interference with signal transmission and ensure device safety.

[0003] Traditional TVS devices typically employ unidirectional or bidirectional diode structures. While they effectively suppress transient voltages, their capacitance values ​​are relatively high (typically between tens and hundreds of picofarads) and their clamping voltages are also high, making them unsuitable for high-speed signal lines and low-voltage equipment. Furthermore, traditional TVS devices have limited Ipp (Peak Pulse Current) withstand capability under high-energy transient events, making them prone to failure due to overload.

[0004] To address these issues, various improvement schemes have been proposed in existing technologies. For example, optimizing the TVS device structure design or using new materials can reduce capacitance and clamping voltage, but this often comes at the cost of sacrificing the TVS device's energy absorption capability or Ipp (Peak Pulse Current). Alternatively, increasing the TVS device area can improve the Ipp value, but this leads to increased device size, making it difficult to meet miniaturization requirements. SCR devices can also be introduced as TVS devices, as they have small capacitance and high IPP capability per unit area, but their high trigger voltage limits their application scenarios. Utility Model Content

[0005] In view of the above problems, the purpose of this application is to provide a transient voltage suppression protection device with low capacitance, low clamping voltage, and high Ipp (Peak Pulse Current).

[0006] According to one aspect of the present invention, a transient voltage suppression protection device is provided, comprising one or more cells, each cell comprising: a substrate of a first doping type; an epitaxial layer of a second doping type located on the substrate; an isolation structure dividing the epitaxial layer into a first region and a second region; a buried layer of the second doping type located between the epitaxial layer of the second region and the substrate; a first doped region of the second doping type located on a first surface of the epitaxial layer of the first region and extending into the epitaxial layer of the first region; a second doped region of the first doping type located on a first surface of the epitaxial layer of the second region and extending into the epitaxial layer of the second region; a fourth doped region of the second doping type exposed on a surface of the substrate away from the epitaxial layer; and a trench extending from the surface of the epitaxial layer of the second region toward the buried layer, extending at least into the buried layer of the second region, the trench being filled with a conductive filler layer.

[0007] Optionally, the epitaxial layer of the second region and the buried layer of the second region constitute the first channel, and the epitaxial layer of the second region, the conductive filling layer of the second region, and the buried layer of the second region constitute the second channel.

[0008] Optionally, the resistance of the conductive filling layer is lower than that of the epitaxial layer.

[0009] Optionally, the conductive filling layer is a polycrystalline silicon layer.

[0010] Optionally, the conductive filling layer is an amorphous silicon layer.

[0011] Optionally, the conductive filler layer is a titanium nitride layer.

[0012] Optionally, the conductive filling layer is a metal layer.

[0013] Optionally, the metal layer is one of a tungsten layer, a molybdenum layer, or a copper layer.

[0014] Optionally, each cell further includes: a first electrode connected to the first doped region and the second doped region respectively, the first electrode being connected to an input / output terminal; and a third electrode located on the second surface of the substrate, the third electrode being connected to a ground terminal.

[0015] Optionally, each element includes a first NPN transistor, a second NPN transistor, and a PNP transistor; the second NPN transistor includes a first doped region in the first region, an epitaxial layer in the first region, the substrate, and a fourth doped region in the substrate; the PNP transistor includes a second doped region in the second region, an epitaxial layer in the second region, a conductive filling layer in the second region, a buried layer in the second region, and the substrate; the first NPN transistor includes an epitaxial layer in the second region, a conductive filling layer in the second region, a buried layer in the second region, the substrate, and a fourth doped region in the substrate.

[0016] Optionally, the collector region of the second NPN transistor is connected to the input / output terminal via a first electrode, and the emitter region of the second NPN transistor is connected to the ground terminal via a third electrode; the emitter region of the PNP transistor is connected to the input / output terminal via a first electrode, and the collector region of the PNP transistor is connected to the ground terminal via a third electrode; the collector region of the first NPN transistor is connected to the base region of the PNP transistor, the emitter region of the first NPN transistor is connected to the ground terminal via a third electrode, and the base region of the first NPN transistor is connected to the emitter region of the PNP transistor.

[0017] Optionally, the conductive filling layer extends from the surface of the epitaxial layer into the interior of the buried layer; or the conductive filling layer extends from the surface of the epitaxial layer into the interior of the substrate.

[0018] Optionally, the resistivity of the buried layer is greater than, equal to, or less than the resistivity of the conductive filler layer.

[0019] Optionally, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked together, the first epitaxial layer being located on the substrate, the second epitaxial layer being located on the first epitaxial layer, and the resistivity of the first epitaxial layer being less than the resistivity of the second epitaxial layer.

[0020] Optionally, the buried layer is located between the first epitaxial layer and the substrate.

[0021] Optionally, the resistivity of the first epitaxial layer is 0.02 Ω•cm to 10 Ω•cm; and the resistivity of the second epitaxial layer is 10 Ω•cm to 10000 Ω•cm.

[0022] Optionally, the thickness of the first epitaxial layer is 2 μm to 10 μm; the thickness of the second epitaxial layer is 5 μm to 30 μm.

[0023] Optionally, it may also include a third doped region of the first doping type, the third doped region being located in the epitaxial layer of the second region and being separate from the second doped region.

[0024] Optionally, the top of the conductive filling layer is located in the third doped region.

[0025] Optionally, it also includes a second electrode, which is connected to the conductive filling layer.

[0026] Optionally, the collector region of the second NPN transistor is connected to the input / output terminal via a first electrode, and the emitter region of the second NPN transistor is connected to the ground terminal via a third electrode; the emitter region of the PNP transistor is connected to the input / output terminal via a first electrode, and the collector region of the PNP transistor is connected to the ground terminal via a third electrode; the collector region of the first NPN transistor is connected to the base region of the PNP transistor, the emitter region of the first NPN transistor is connected to the ground terminal via a third electrode, and the base region of the first NPN transistor is connected to the emitter region of the PNP transistor; the base region of the PNP transistor and the collector region of the first NPN transistor are connected to the power supply terminal.

[0027] Optionally, it further includes a passivation layer that covers the surfaces of the first electrode and the second electrode and fills the gap between the first electrode and the second electrode, the passivation layer having a first opening exposing the first electrode and a second opening exposing the second electrode.

[0028] Optionally, the second electrode is connected to the power supply terminal via an opening in the passivation layer.

[0029] Optionally, it may also include a passivation layer covering the surface of the first electrode, the passivation layer having an opening that exposes the first electrode.

[0030] Optionally, it further includes a dielectric layer covering the surface of the epitaxial layer, the dielectric layer having openings extending through its thickness, the openings exposing the surfaces of the first doped region, the second doped region, and the top of the conductive filling layer, respectively.

[0031] Optionally, it further includes a passivation layer covering the surface of the first electrode and the surface of the dielectric layer, the passivation layer having an opening that exposes the first electrode.

[0032] Optionally, the passivation layer covers the surfaces of the first electrode, the second electrode, and the dielectric layer, and the passivation layer has a first opening exposing the first electrode and a second opening exposing the second electrode.

[0033] Optionally, the second region surrounds the first region, and the first region and the second region include two annular isolation structures.

[0034] Optionally, the second region and the edge of the transient voltage suppression protection device include one of the aforementioned isolation structures.

[0035] Optionally, it includes multiple cells connected in parallel, the substrates of the multiple cells are integral structures, the epitaxial layers of the multiple cells are integral structures, and each cell adopts its own corresponding input / output terminal.

[0036] This application provides a PNPN vertical structure SCR device that can achieve a two-stage scan effect. Under low current, the PNP structure breaks down, resulting in a single scan characteristic. Under high current, when the substrate parasitic resistance voltage reaches 0.7V, the back substrate and the fourth doped region form a PN junction and conduct, at which point the SCR enters a low-resistance conduction state, resulting in a second scan characteristic.

[0037] This device adjusts the trigger voltage of the Zener diode formed by the buried layer and the substrate by adjusting the injection dose of the buried layer, thus avoiding the problem of high trigger voltage in traditional SCR structures.

[0038] The transient voltage suppression protection device of this embodiment introduces a conductive fill layer. The epitaxial layer and the buried layer constitute a first channel, and the epitaxial layer, the conductive fill layer, and the buried layer constitute a second channel. The resistance of the conductive fill layer is lower than that of the epitaxial layer. The introduction of the conductive fill layer is equivalent to having a lower-resistance second channel running parallel to the first channel. Most of the current flows out through the low-resistance second channel, improving the device's peak current (Ipp) capability per unit area and reducing the device's clamping voltage.

[0039] In a preferred embodiment, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked together. Compared with the second epitaxial layer, the first epitaxial layer has a lower resistivity, which can reduce the resistance in the current channel, thereby reducing the saturation voltage drop of the device when it is turned on and reducing energy loss. The second epitaxial layer has a higher resistivity, which can significantly reduce the parasitic capacitance between the second doped region and the epitaxial layer (specifically the second epitaxial layer), thereby reducing the overall capacitance of the device.

[0040] In a preferred embodiment, by introducing a third doped region to enrich the top of the conductive filling layer, the electric field distribution and current path can be optimized without increasing parasitic capacitance, thereby reducing the resistance in the second channel, which in turn reduces the saturation voltage drop of the device when it is turned on and reduces energy loss.

[0041] In a preferred embodiment, the conductive filling layer extends into the substrate. If the resistivity of the buried layer is lower than that of the conductive filling layer, when the electric field reaches a certain level, the diode formed by the buried layer and the substrate will break down first. When the electric field increases further, the diode formed by the conductive filling layer and the substrate will also break down. When the resistivity of the buried layer is the same as that of the conductive filling layer, both will break down simultaneously. In this case, the extension of the conductive filling layer into the substrate is equivalent to increasing the area of ​​the PN junction, which can reduce the resistance and improve the Ipp (Peak Pulse Current) capability. When the resistivity of the buried layer is higher than that of the conductive filling layer, the diode formed by the conductive filling layer and the substrate will break down first, and the diode formed by the buried layer and the second doped region will break down only when the electric field reaches a certain level.

[0042] This application, through innovative device structure design and manufacturing process, significantly improves the Ipp (Peak Pulse Current) value without increasing the device area compared to traditional technologies, while maintaining low capacitance and low clamping voltage. This meets the stringent requirements of high-speed signal lines and low-voltage equipment for transient voltage protection devices. The device features fast response, low clamping voltage, high energy absorption capability, and excellent signal integrity protection characteristics, and can be widely used in communications, consumer electronics, industrial control, and other fields. Attached Figure Description

[0043] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which: Figure 1a A top view of the transient voltage suppression protection device according to the first embodiment of this application is shown; Figure 1b Used Figure 1a Cross-sectional view along the AA direction; Figure 2 An equivalent circuit diagram of a transient voltage suppression protection device according to a first embodiment of this application is shown; Figure 3 A schematic diagram of the transient voltage suppression and protection device according to a second embodiment of this application is shown; Figure 4a A top view of the transient voltage suppression protection device according to a third embodiment of this application is shown; Figure 4b Used Figure 4a Cross-sectional view along the AA direction; Figure 5 A schematic diagram of the transient voltage suppression protection device according to the fourth embodiment of this application is shown; Figure 6 A schematic diagram of the transient voltage suppression and protection device according to the fifth embodiment of this application is shown; Figure 7 An equivalent circuit diagram of a transient voltage suppression protection device according to a fifth embodiment of this application is shown; Figures 8a to 8o Cross-sectional views of various stages in the fabrication process of the transient voltage suppression and protection device according to the application embodiment are shown; Figure 9 A comparison diagram showing the current-voltage relationship between the transient voltage suppression protection device of this application embodiment and a conventional transient voltage suppression protection device is presented; Figure 10a A cross-sectional structural schematic diagram of a transient voltage suppression protection device according to a sixth embodiment of this application is shown; Figure 10b An equivalent circuit diagram of a transient voltage suppression protection device according to a sixth embodiment of this application is shown. Detailed Implementation

[0044] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0045] This application may be presented in various forms, some of which will be described below.

[0046] Figure 1 shows a top view of a cell of a transient voltage suppression protection device according to the first embodiment of this application. Figure 1b Used Figure 1a Cross-sectional view along the AA direction; Figure 2 An equivalent circuit diagram of a cell of a transient voltage suppression protection device according to a first embodiment of this application is shown. It is worth noting that, in order to more clearly show the positional relationship between the isolation structure, the first doped region, the second doped region, and the conductive filling layer, the dielectric layer, the first electrode, the second electrode, and the passivation layer are not shown in the top view shown in FIG1.

[0047] like Figure 1a , Figure 1b and Figure 2 As shown, the transient voltage suppression protection device consists of only one cell, which includes a substrate 101, an epitaxial layer 102, and a buried layer 103. The epitaxial layer 102 is located on the substrate 101. The buried layer 103 is located between the substrate 101 and the epitaxial layer 102.

[0048] The substrate 101 has a first doping type, and the buried layer 103 and the epitaxial layer 102 each have a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. The P-type dopant may include boron (B), aluminum (Al), indium (In), or combinations thereof, while the N-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. The buried layer 103 has a patterned structure; in other words, the buried layer 103 exposes a portion of the surface of the substrate 101.

[0049] The substrate 101 has a fourth doped region 112 of the second doping type, which extends from the surface of the substrate 101 away from the epitaxial layer 102 toward its interior and is exposed on the surface of the substrate 101 away from the epitaxial layer 102.

[0050] The transient voltage suppression protection device includes an isolation structure 104 extending from the surface of the epitaxial layer 102 toward the substrate 101 until it extends into the substrate 101. The isolation structure 104 includes a first trench, an isolation dielectric layer covering the bottom and sidewalls of the first trench, and a fill layer filling the first trench. The fill layer is isolated from the substrate 101 and the epitaxial layer 102 via the isolation dielectric layer. In one embodiment, the isolation dielectric layer is, for example, a silicon oxide (SiO2) layer, and the fill layer is, for example, a polysilicon layer. In one embodiment, the opening size of the isolation structure 104 is 0.5 μm to 3 μm, and the isolation structure 104 penetrates the epitaxial layer 102 and extends into the substrate 101 for 2 μm to 20 μm.

[0051] The top view of the isolation structure 104 is ring-shaped, for example... Figure 1a The diagram shows a circular ring. In other embodiments, the isolation structure 104 can also be configured as a square ring structure or an irregularly shaped ring structure; this embodiment is not limited to this. The isolation structure 104 isolates the epitaxial layer 102 to form multiple regions. In this embodiment, the isolation structure 104 isolates the epitaxial layer 102 to form a first region Z01 and a second region Z02 surrounding the first region Z01. The buried layer 103 is located between the epitaxial layer 102 and the substrate 101 in the second region Z02, but not between the epitaxial layer 102 and the substrate 101 in the first region Z01.

[0052] The transient voltage suppression protection device includes a first doped region 105 of a second doping type, a second doped region 106 of the same type, and a conductive filling layer 107. Further, the first doped region 105 is located on the first surface of the epitaxial layer 102 of the first region Z01 and extends into the epitaxial layer 102 of the first region Z01; the second doped region 106 is located on the first surface of the epitaxial layer 102 of the second region Z02 and extends into the epitaxial layer 102 of the second region Z02. The conductive filling layer 107 is located in the epitaxial layer 102 of the second region Z02 and is separated from the second doped region 106. The conductive filling layer 107 extends from the surface of the epitaxial layer 102 of the second region Z02 toward the buried layer 103. In this embodiment, the conductive filling layer 107 extends through the epitaxial layer 102 into the interior of the buried layer 103. The conductive filling layer 107 is located in a second trench. The resistance of the conductive filling layer 107 is lower than the resistance of the epitaxial layer 102. In one embodiment, the conductive filling layer is, for example, a polysilicon layer. In other embodiments, the conductive filling layer may also be one or more of an amorphous silicon layer, a titanium nitride layer, and a metal layer (one of a tungsten layer, a molybdenum layer, or a copper layer).

[0053] In this embodiment, the top view shape of the first doped region 105 is circular, and the top view shape of the second doped region 106 is correspondingly set to be annular around the first doped region 105. The top view shape of the conductive filling layer 107 is set to be linear, and multiple linear conductive filling layers 107 surround the second doped region 106. It should be noted that Figure 1 only shows the top view shape of the conductive filling layer 107 as an example. In the preferred embodiment, the transient voltage suppression protection device is symmetrical both vertically and horizontally.

[0054] The transient voltage suppression protection device also includes a dielectric layer 108, a first electrode 109a, a third electrode 109c, and a passivation layer 110. The dielectric layer 108 covers the surface of the epitaxial layer 102 and has openings extending through its thickness, exposing the surfaces of the first doped region 105, the second doped region 106, and the top of the conductive filling layer 107, respectively. The first electrode 109a is located on the dielectric layer 108 and is connected to the first doped region 105 and the second doped region 106 via the openings in the dielectric layer 108. The third electrode 109c is located on the second surface of the substrate 101.

[0055] Passivation layer 110 covers the surface of the first electrode 109a and the surface of the exposed dielectric layer 108. Passivation layer 110 has an opening that exposes the surface of the first electrode 109a, which is connected to the input / output terminal I / O, and the third electrode 109c is connected to the ground terminal GND.

[0056] In a transient voltage suppression protection device, a second NPN transistor (NPN2) is formed by a first doped region 105 of the first region Z01, an epitaxial layer 102 of the first region Z01, a substrate 101, and a fourth doped region 112 in the substrate 101. The first doped region 105 of the first region Z01 constitutes the collector region of the second NPN transistor, the substrate 101 constitutes the base region of the second NPN transistor, and the fourth doped region 112 constitutes the emitter region of the second NPN transistor. The collector region of the second NPN transistor is connected to the input / output terminal I / O via a first electrode 109a, and the emitter region of the second NPN transistor is connected to the ground terminal GND via a third electrode 109c.

[0057] A PNP transistor is formed by the second doped region 106 of the second region Z02, the epitaxial layer 102 of the second region Z02, the conductive filling layer 107 of the second region Z02, the buried layer 103 of the second region Z02, and the substrate 101. The second doped region 106 of the second region Z02 constitutes the emitter region of the PNP transistor, and the epitaxial layer 102, the conductive filling layer 107, and the buried layer 103 constitute the base region of the PNP transistor; the substrate 101 constitutes the collector region of the PNP transistor. The base region has parallel first and second channels, with the epitaxial layer 102 and the buried layer 103 forming the first channel, and the epitaxial layer 102, the conductive filling layer 107, and the buried layer 103 forming the second channel. The emitter region of the PNP transistor is connected to the input / output terminal I / O via the first electrode 109a, and the collector region of the PNP transistor is connected to the ground terminal GND via the third electrode 109c.

[0058] The epitaxial layer 102 of the second region Z02, the conductive filling layer 107 of the second region Z02, the buried layer 103 of the second region Z02, the substrate 101, and the fourth doped region 112 in the substrate 101 form a first NPN transistor (NPN1). The epitaxial layer 102, the conductive filling layer 107, and the buried layer 103 constitute the collector region of the first NPN transistor, the substrate 101 constitutes the base region of the first NPN transistor, and the fourth doped region 112 constitutes the emitter region of the first NPN transistor. The collector region of the first NPN transistor has a first channel and a second channel in parallel. The epitaxial layer 102 and the buried layer 103 constitute the first channel, and the epitaxial layer 102, the conductive filling layer 107, and the buried layer 103 constitute the second channel. The collector region of the first NPN transistor is connected to the base region of the PNP transistor, the emitter region of the first NPN transistor is connected to the ground terminal GND via the third electrode 109c, and the base region of the first NPN transistor is connected to the emitter region of the PNP transistor.

[0059] When the input / output (I / O) terminal is connected to a high potential and the ground terminal (GND) is connected to a low potential, current flows through the first electrode 109a into the forward direction of the PN junction formed by the second doped region 106 and the epitaxial layer 102. After the forward PN junction is turned on, part of the current flows through the epitaxial layer 102 into the buried layer 103 (first channel), and another part of the current flows through the epitaxial layer 102 and the conductive filling layer 107 into the buried layer 103 (second channel). Since the resistance of the conductive filling layer 107 is lower than the resistance of the epitaxial layer 102, most of the current flows through the second channel. When the electric field reaches a certain level, the depletion region of the PN junction formed by the buried layer 103 and the substrate 101 begins to widen and avalanche breakdown occurs. Avalanche breakdown causes collisional ionization, generating electron-hole pairs. Electrons are absorbed into the upper buried layer 103, and holes are injected into the substrate 101. The PNP transistor is turned on and enters the amplification region. The breakdown voltage drops rapidly to the PNP transistor's turn-on voltage, and the first negative resistance flyback phenomenon occurs, which can reduce the clamping voltage. As the current continues to increase, the resistance R parasitic on the substrate 101... P When the voltage it bears reaches 0.7V, the first NPN transistor turns on and enters the amplification region. At this time, the SCR structure composed of PNPN transistors turns on and the second negative resistance flyback phenomenon occurs, which can reduce the clamping voltage more significantly and meet the needs of large surge current.

[0060] This application provides a PNPN vertical structure SCR device that can achieve the effect of two-stage retracement. Figure 9 A comparison graph showing the current-voltage relationship between the transient voltage suppression protection device of this application embodiment and a conventional transient voltage suppression protection device is provided; as shown. Figure 9 As shown, under low current, the PNP structure breaks down and a first sweepback characteristic occurs; under high current, when the substrate parasitic resistance voltage reaches 0.7V, the substrate 101 on the back side and the fourth doped region 112 form a PN junction and conduct. At this time, the SCR enters a low-resistance conduction state and a second sweepback characteristic occurs.

[0061] This device adjusts the trigger voltage of the Zener diode formed by the buried layer and substrate 101 by adjusting the injection dose of the buried layer, thus avoiding the problem of high trigger voltage in traditional SCR structures.

[0062] The transient voltage suppression protection device of this embodiment introduces a conductive filling layer 107. The epitaxial layer 102 and the buried layer 103 form a first channel, while the epitaxial layer 102, the conductive filling layer 107, and the buried layer 103 form a second channel. The resistance of the conductive filling layer 107 is lower than that of the epitaxial layer 102. The introduction of the conductive filling layer 107 is equivalent to having a lower-resistance second channel running parallel to the first channel. Most of the current flows out through the low-resistance second channel, improving the device's peak current (Ipp) capability per unit area and reducing the device's clamping voltage.

[0063] Figure 3 A schematic cross-sectional view of a transient voltage suppression protection device according to a second embodiment of this application is shown, as follows. Figure 3 As shown, the device structure of the second embodiment is largely the same as that of the first embodiment. The difference from the first embodiment is that in this embodiment, the epitaxial layer 102 includes a first epitaxial layer 102a and a second epitaxial layer 102b stacked together. The thickness of the first epitaxial layer 102a is 2μm to 10μm and the resistivity is 0.02Ω•cm to 10Ω•cm; the thickness of the second epitaxial layer 102b is 5μm to 30μm and the resistivity is 10Ω•cm to 10000Ω•cm.

[0064] Compared to the second epitaxial layer 102b, the first epitaxial layer 102a has a lower resistivity, which can reduce the resistance in the current channel, thereby reducing the saturation voltage drop of the device when it is turned on and reducing energy loss; the second epitaxial layer 102a has a higher resistivity, which can significantly reduce the parasitic capacitance between the second doped region 106 and the epitaxial layer 102 (specifically the second epitaxial layer 102a), thereby reducing the overall capacitance of the device.

[0065] Figure 4a A top view of the transient voltage suppression protection device according to a third embodiment of this application is shown. Figure 4b It shows Figure 4a Cross-sectional view along the AA direction; as shown Figure 4a and Figure 4b As shown, the device structure of the third embodiment is largely the same as that of the second embodiment. The difference is that this embodiment further includes a third doped region 111, which is located in the epitaxial layer 102 of the second region Z02 (specifically in the second epitaxial layer 102b) and exposed on the surface of the epitaxial layer 102. The third doped region 111 is separated from the second doped region 106, and the third doped region 111 has a second doping type opposite to the first doping type.

[0066] The top of the conductive filling layer 107 is located in the third doped region 111. The epitaxial layer 102, the third doped region 111, the conductive filling layer 107, and the buried layer 103 constitute the second channel. The introduction of the third doped region 111 is equivalent to enriching the top of the conductive filling layer 107, which can optimize the electric field distribution and current path without increasing parasitic capacitance, reduce the resistance in the second channel, thereby reducing the saturation voltage drop of the device when it is turned on and reducing energy loss.

[0067] Figure 5 A schematic cross-sectional view of a transient voltage suppression protection device according to a fourth embodiment of this application is shown, as follows. Figure 5 As shown, the device structure of the fourth embodiment is largely the same as that of the third embodiment. The difference from the third embodiment is that in this embodiment, the conductive filling layer 107 penetrates the epitaxial layer 102 and the buried layer 103 and extends into the substrate 101.

[0068] In the first to third embodiments, the conductive filling layer 107 extends into the buried layer 103, and the breakdown voltage is determined by the diode Z1 formed by the buried layer 103 and the substrate 101.

[0069] In this embodiment, the conductive filling layer 107 extends into the substrate 101. At this point, it is necessary to compare the resistivity of the buried layer 103 and the conductive filling layer 107. If the resistivity of the buried layer 103 is lower than that of the conductive filling layer 107, the diode formed by the buried layer 103 and the second doped region 106 will break down first. When the electric field reaches a certain level, the diode formed by the conductive filling layer 107 and the substrate 101 will also break down. When the resistivity of the buried layer 103 is the same as that of the conductive filling layer 107, both will break down simultaneously. In this case, the extension of the conductive filling layer 107 into the substrate 101 is equivalent to increasing the area of ​​the PN junction, which can reduce the resistance and improve the Ipp (Peak Pulse Current) capability. When the resistivity of the buried layer 103 is higher than that of the conductive filling layer 107, the diode formed by the conductive filling layer 107 and the substrate 101 will break down first. When the electric field reaches a certain level, the diode formed by the buried layer 103 and the second doped region 106 will break down.

[0070] Figure 6 A schematic cross-sectional view of a transient voltage suppression protection device according to a fifth embodiment of this application is shown, as follows. Figure 6As shown, the device structure of the fifth embodiment is largely the same as that of the third embodiment. The difference is that this embodiment further includes a second electrode 109b, which is located on the dielectric layer 108 and connected to the conductive filling layer 107 via an opening in the dielectric layer 108. Further, although both the first electrode 109a and the second electrode 109b are located on the dielectric layer 108, they are separated from each other. A passivation layer 110 covers the surface of the first electrode 109a, the surface of the second electrode 109b, and the exposed surface of the dielectric layer 108, and fills the gap between the first electrode 109a and the second electrode 109b to isolate them. The passivation layer 110 also has a second opening penetrating the thickness of the passivation layer 110, which exposes the surface of the second electrode 109b. The second electrode 109b is connected to the power supply terminal Vcc, and the buried layer 103 is connected to the second electrode 109b via the conductive filling layer 107, and thus connected to the power supply terminal Vcc.

[0071] Figure 7 An equivalent circuit diagram of a transient voltage suppression protection device according to a fifth embodiment of this application is shown, as follows: Figure 7 As shown, the base region of the PNP transistor and the collector region of the first NPN transistor are connected to the power supply terminal Vcc.

[0072] This application also provides a method for fabricating a transient voltage suppression and protection device, which will be described below. Figure 4a and Figure 4b The third embodiment shown is used as an example to illustrate the preparation method of the transient voltage suppression and protection device of this application. Figures 8a to 8o Cross-sectional views of various stages in the fabrication process of the transient voltage suppression and protection device according to the application embodiment are shown.

[0073] like Figure 8a As shown, a substrate 101 is provided, which has a first doping type (e.g., P-type doping). In one embodiment, the resistivity of the substrate 101 is 0.001 Ω•cm to 0.05 Ω•cm.

[0074] like Figure 8b As shown, a buried layer 103 of the second doping type is formed in the substrate 101.

[0075] In this step, a buried layer 103 is formed in the substrate 101 by ion implantation and high-temperature annealing. The buried layer 103 is selectively formed in a portion of the substrate 101. In one embodiment, phosphorus or arsenic is implanted into the substrate 101 to form a second-doped buried layer 103. The ion implantation energy is 60 keV to 150 keV, and the implantation dose is 2E. 14 cm-2 ~2E 16 cm -2 The material is annealed at 900℃~1250℃ for 0.5H~5H, and the depth of the 103 buried layer is 0.5μm~5μm.

[0076] like Figure 8c As shown, the first epitaxial layer 102a is formed in the epitaxial layer.

[0077] In this step, a first epitaxial layer 102a is formed on the first surface of the substrate 101 by epitaxial growth. The first epitaxial layer 102a has a second doping type. The first epitaxial layer 102a blankets the first surface of the substrate 101, including a buried layer 103 exposed on the first surface of the substrate 101. In one embodiment, the thickness of the first epitaxial layer 102a is 2 μm to 10 μm, and the resistivity of the first epitaxial layer 102a is 0.02 Ω•cm to 10 Ω•cm.

[0078] like Figure 8d As shown, a second epitaxial layer 102b is formed in the epitaxial layer.

[0079] In this step, a second epitaxial layer 102b is formed on the surface of the first epitaxial layer 102a by epitaxial growth. The second epitaxial layer 102b has a second doping type. The second epitaxial layer 102b blankets the surface of the first epitaxial layer 102a. In one embodiment, the thickness of the second epitaxial layer 102b is 5 μm to 30 μm, and the resistivity of the second epitaxial layer 102b is 10 Ω•cm to 10000 Ω•cm.

[0080] like Figure 8e As shown, a hard mask layer HM is formed on the second epitaxial layer 102b.

[0081] In this step, for example, a deposition process is used to form a hard mask layer HM on the second epitaxial layer 102b. In one embodiment, the hard mask layer HM is, for example, a SiO2 layer, and the thickness of the hard mask layer HM is 5000 Å to 30000 Å.

[0082] like Figure 8f As shown, an isolation structure 104 is formed.

[0083] In this step, a hard mask layer HM is patterned using photolithography. The epitaxial layer and the substrate 101 are etched through the opening of the hard mask layer to form a first trench that penetrates the epitaxial layer and extends into the substrate 101. In one embodiment, the opening size of the first trench is 0.5μm to 3μm, and the first trench penetrates the epitaxial layer and extends into the substrate 101 by 2μm to 20μm.

[0084] Next, for example, a deep trench oxidation process is used to form an isolation layer at the bottom and sidewalls of the first trench. In one embodiment, a silicon dioxide isolation layer is grown at a high temperature of 900°C to 1250°C, and the thickness of the silicon dioxide isolation layer is 500 Å to 5000 Å.

[0085] Next, an undoped polysilicon layer is formed, filling the first trench and covering the surface of the hard mask layer HM. The polysilicon layer on the surface of the hard mask layer HM is then removed using a CMP (Chemical Mechanical Polishing) process. The remaining polysilicon layer fills the first trench to form an isolation structure. This isolation structure divides the epitaxial layer into a first region Z01 and a second region Z02.

[0086] like Figure 8g As shown, for example, a wet etching process is used to remove the hard mask layer HM.

[0087] like Figure 8h As shown, a first doped region 105 of the second doping type and a third doped region 111 of the second doping type are formed.

[0088] In this step, for example, ion implantation and high-temperature annealing processes are used to form a first doped region 105 of a second doping type in the epitaxial layer (specifically, the second epitaxial layer 102b). In one embodiment, for example, phosphorus or arsenic implantation processes are used to form the first doped region 105 of the second doping type and the third doped region 111 of the second doping type, with an implantation energy of 60 keV to 150 keV and an implantation dose of 2E. 14 cm -2 ~2E 16 cm -2 The high-temperature annealing temperature is 900℃~1250℃, and the junction depth of the first doped region 105 and the second doped third doped region 111 is 1μm~10μm.

[0089] like Figure 8i As shown, a second doped region 106 of the first doping type is formed.

[0090] In this step, for example, ion implantation and high-temperature annealing processes are used to form a second doped region 106 of the first doping type in the epitaxial layer (specifically, the second epitaxial layer 102b). In one embodiment, for example, a boron implantation process is used to form the second doped region 106 of the first doping type, with an implantation energy of 60 keV to 150 keV and an implantation dose of 2E. 14 cm -2 ~2E 16 cm -2 The high-temperature annealing temperature is 900℃~1250℃, and the junction depth of the second doped region 106 is 1μm~10μm.

[0091] like Figure 8j As shown, a conductive filling layer 107 is formed.

[0092] In this step, a patterned mask layer is formed using photolithography. The epitaxial layer 102 and the buried layer 103 are etched through the opening of the mask layer to form a second trench penetrating the epitaxial layer 102 and reaching the interior of the buried layer 103. In one embodiment, the opening size of the second trench is 0.5 μm to 3 μm.

[0093] Next, a conductive layer is formed, which fills the second trench and covers the surface of the epitaxial layer 102. The conductive layer on the surface of the epitaxial layer 102 is removed using a CMP process, and the remaining conductive layer fills the second trench to form a conductive filling layer 107. The conductive filling layer 107 is, for example, a polysilicon layer, a metal layer (e.g., tungsten metal), etc.

[0094] like Figure 8k As shown, a dielectric layer 108 is formed.

[0095] In this step, a dielectric layer 108 is formed on the surface of the epitaxial layer 102. Then, photolithography and etching processes are used to form openings in the dielectric layer 108, exposing the surfaces of the first doped region 105, the second doped region 106, the third doped region 111, and the top of the conductive filling layer 107. In one embodiment, the dielectric layer 108 is, for example, a SiO2 layer with a thickness of, for example, 0.2 μm to 3 μm.

[0096] like Figure 8l As shown, a first electrode 109a and a second electrode 109b are formed.

[0097] In this step, a metal layer is formed on the surface of the dielectric layer 108, covering the surface of the dielectric layer 108 and filling the openings in the dielectric layer 108. Next, photolithography and etching processes are used to pattern the metal layer to form a first electrode 109a and a second electrode 109b that are separated from each other. The first electrode 109a penetrates the dielectric layer 108 and contacts the first doped region 105 and the second doped region 106, while the second electrode 109b penetrates the dielectric layer 108 and contacts the top of the conductive filling layer 107. In one embodiment, the thickness of the metal layer forming the first electrode 109a and the second electrode 109b is, for example, 1 μm to 8 μm.

[0098] like Figure 8m As shown, a passivation layer 110 is formed.

[0099] In this step, a passivation layer 110 is formed on the surfaces of the first electrode 109a and the second electrode 109b. The passivation layer 110 covers the surfaces of the first electrode 109a and the second electrode 109b and fills the gap between the first electrode 109a and the second electrode 109b to isolate the first electrode 109a and the second electrode 109b. Next, the passivation layer 110 is patterned using photolithography and etching processes to form openings in the passivation layer 110, and the openings in the passivation layer 110 expose the surface of the first electrode 109a.

[0100] like Figure 8n As shown, the surface of substrate 101 away from epitaxial layer 102 is thinned, and ion implantation is selectively performed on the thinned substrate 101 to form a fourth doped region 112 of the second doping type. In one embodiment, N-type impurities (phosphorus or arsenic) are implanted into the thinned substrate 101 at an implantation energy of 60 keV to 150 keV and an implantation dose of 2E. 14 cm -2 ~2E 16 cm -2 A fourth doped region 112 of the second doping type is formed in the substrate 101 by high-temperature annealing at 900℃~1250℃. The junction depth of the fourth doped region 112 is 1μm~10μm.

[0101] like Figure 8o As shown, a third electrode 109c is formed on the surface of the substrate 101 away from the epitaxial layer 102. The third electrode 109c is, for example, a metal layer, and the thickness of the third electrode 109c is 0.5 μm to 5 μm.

[0102] Figure 10a A schematic cross-sectional view of a transient voltage suppression protection device according to a sixth embodiment of this application is shown. Figure 10b An equivalent circuit diagram of a transient voltage suppression protection device according to a sixth embodiment of this application is shown; as follows: Figure 10a and Figure 10b As shown, the transient voltage suppression protection device includes two cells, such as a first cell 10a and a second cell 10b, where the first cell 10a and the second cell 10b are protection devices shown in any one of the first to fifth embodiments.

[0103] In this embodiment, the first electrode 109a of the first cell 10a and the second cell 10b is connected to the first input / output terminal I / O1 and the second input / output terminal I / O2, respectively. The third electrode 109c of the first cell 10a and the second cell 10b is connected to a common ground terminal GND. Although only the first cell 10a and the second cell 10b are shown in the sixth embodiment of this application, it should be understood that the transient voltage suppression protection device may also include more cells, wherein the first electrode 109a of each cell is connected to a corresponding input / output terminal.

[0104] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A transient voltage suppression and protection device, characterized in that, It includes one or more cells, each cell including: Substrate of the first doping type; A second doped epitaxial layer is located on the substrate; An isolation structure divides the epitaxial layer into a first region and a second region; The second type of buried layer is located between the epitaxial layer and the substrate in the second region; The first doped region of the second doping type is located on the first surface of the epitaxial layer of the first region and extends into the epitaxial layer of the first region; The second doped region of the first doping type is located on the first surface of the epitaxial layer of the second region and extends into the epitaxial layer of the second region; The fourth doped region of the second doping type is exposed on the surface of the substrate away from the epitaxial layer; A trench extends from the surface of the epitaxial layer of the second region toward the buried layer, extending at least to the buried layer of the second region, and the trench is filled with a conductive filler layer.

2. The transient voltage suppression and protection device according to claim 1, characterized in that, The epitaxial layer and the buried layer of the second region constitute the first channel, and the epitaxial layer, the conductive filling layer, and the buried layer of the second region constitute the second channel.

3. The transient voltage suppression and protection device according to claim 1, characterized in that, The resistance of the conductive filling layer is lower than that of the epitaxial layer.

4. The transient voltage suppression and protection device according to claim 1, characterized in that, The conductive filling layer is a polycrystalline silicon layer.

5. The transient voltage suppression and protection device according to claim 1, characterized in that, The conductive filling layer is an amorphous silicon layer.

6. The transient voltage suppression and protection device according to claim 1, characterized in that, The conductive filler layer is a titanium nitride layer.

7. The transient voltage suppression and protection device according to claim 1, characterized in that, The conductive filler layer is a metal layer.

8. The transient voltage suppression and protection device according to claim 7, characterized in that, The metal layer is one of a tungsten layer, a molybdenum layer, or a copper layer.

9. The transient voltage suppression and protection device according to claim 1, characterized in that, Each cell also includes: A first electrode is connected to both the first doped region and the second doped region, and the first electrode is connected to an input / output terminal; and The third electrode is located on the second surface of the substrate and is connected to ground.

10. The transient voltage suppression and protection device according to claim 1, characterized in that, Each element includes a first NPN transistor, a second NPN transistor, and a PNP transistor; The second NPN transistor includes a first doped region in the first region, an epitaxial layer in the first region, the substrate, and a fourth doped region in the substrate; The PNP transistor includes a second doped region in the second region, an epitaxial layer in the second region, a conductive filling layer in the second region, a buried layer in the second region, and the substrate. The first NPN transistor includes an epitaxial layer in the second region, a conductive filling layer in the second region, a buried layer in the second region, the substrate, and a fourth doped region in the substrate.

11. The transient voltage suppression and protection device according to claim 10, characterized in that, The collector region of the second NPN transistor is connected to the input / output terminal via the first electrode, and the emitter region of the second NPN transistor is connected to the ground terminal via the third electrode. The emitter region of the PNP transistor is connected to the input / output terminal via the first electrode, and the collector region of the PNP transistor is connected to the ground terminal via the third electrode. The collector region of the first NPN transistor is connected to the base region of the PNP transistor, the emitter region of the first NPN transistor is connected to the ground terminal via the third electrode, and the base region of the first NPN transistor is connected to the emitter region of the PNP transistor.

12. The transient voltage suppression and protection device according to any one of claims 1-11, characterized in that, The conductive filling layer extends from the surface of the epitaxial layer into the interior of the buried layer; or the conductive filling layer extends from the surface of the epitaxial layer into the interior of the substrate.

13. The transient voltage suppression and protection device according to claim 1, characterized in that, The resistivity of the buried layer is greater than, equal to or less than the resistivity of the conductive filler layer.

14. The transient voltage suppression and protection device according to claim 1, characterized in that, The epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked together. The first epitaxial layer is located on the substrate, and the second epitaxial layer is located on the first epitaxial layer. The resistivity of the first epitaxial layer is less than the resistivity of the second epitaxial layer.

15. The transient voltage suppression and protection device according to claim 14, characterized in that, The buried layer is located between the first epitaxial layer and the substrate.

16. The transient voltage suppression and protection device according to claim 14, characterized in that, The resistivity of the first epitaxial layer is 0.02 Ω•cm to 10 Ω•cm; the resistivity of the second epitaxial layer is 10 Ω•cm to 10000 Ω•cm.

17. The transient voltage suppression and protection device according to claim 14, characterized in that, The thickness of the first epitaxial layer is 2μm to 10μm; the thickness of the second epitaxial layer is 5μm to 30μm.

18. The transient voltage suppression and protection device according to claim 1, characterized in that, It also includes a third doped region of the first doping type, which is located in the epitaxial layer of the second region and is separated from the second doped region.

19. The transient voltage suppression and protection device according to claim 18, characterized in that, The top of the conductive filling layer is located in the third doped region.

20. The transient voltage suppression and protection device according to claim 10, characterized in that, It also includes a second electrode, which is connected to the conductive filling layer.

21. The transient voltage suppression and protection device according to claim 20, characterized in that, The collector region of the second NPN transistor is connected to the input / output terminal via the first electrode, and the emitter region of the second NPN transistor is connected to the ground terminal via the third electrode. The emitter region of the PNP transistor is connected to the input / output terminal via the first electrode, and the collector region of the PNP transistor is connected to the ground terminal via the third electrode. The collector region of the first NPN transistor is connected to the base region of the PNP transistor, the emitter region of the first NPN transistor is connected to the ground terminal via the third electrode, and the base region of the first NPN transistor is connected to the emitter region of the PNP transistor. The base region of the PNP transistor and the collector region of the first NPN transistor are connected to the power supply.

22. The transient voltage suppression and protection device according to claim 20, characterized in that, It also includes a passivation layer that covers the surfaces of the first electrode and the second electrode and fills the gap between the first electrode and the second electrode. The passivation layer has a first opening that exposes the first electrode and a second opening that exposes the second electrode.

23. The transient voltage suppression and protection device according to claim 22, characterized in that, The second electrode is connected to the power supply terminal through an opening in the passivation layer.

24. The transient voltage suppression and protection device according to claim 1, characterized in that, It also includes a passivation layer that covers the surface of the first electrode and has an opening that exposes the first electrode.

25. The transient voltage suppression and protection device according to claim 1, characterized in that, It also includes a dielectric layer that covers the surface of the epitaxial layer, the dielectric layer having openings extending through its thickness, the openings exposing the surfaces of the first doped region, the second doped region, and the top of the conductive filling layer, respectively.

26. The transient voltage suppression and protection device according to claim 25, characterized in that, It also includes a passivation layer that covers the surface of the first electrode and the surface of the dielectric layer, the passivation layer having an opening that exposes the first electrode.

27. The transient voltage suppression and protection device according to claim 26, characterized in that, The passivation layer covers the surfaces of the first electrode, the second electrode, and the dielectric layer, and has a first opening exposing the first electrode and a second opening exposing the second electrode.

28. The transient voltage suppression and protection device according to claim 1, characterized in that, The second region surrounds the first region, and the first region and the second region include two annular isolation structures.

29. The transient voltage suppression and protection device according to claim 1, characterized in that, The second region and the edge of the transient voltage suppression protection device include the isolation structure described above.

30. The transient voltage suppression and protection device according to claim 1, characterized in that, It includes multiple cells connected in parallel, the substrates of the multiple cells are a single structure, the epitaxial layers of the multiple cells are a single structure, and each cell uses its own corresponding input / output terminal.

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