Semiconductor device

Abstract

The utility model discloses a semiconductor device contains the substrate of first conductive type, the first buried layer of second conductive type sets up in the substrate, and power element sets up in the first buried layer, and the sealing ring of first conductive type sets up in the substrate, surrounds the first buried layer. The second buried layer of second conductive type sets up in the substrate, is located between the first buried layer and the sealing ring, and second buried layer and first buried layer and sealing ring all laterally separate, wherein first buried layer is configured as the input voltage of electrically coupled to power element, and second buried layer is configured as the output voltage of electrically coupled to power element.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to a semiconductor device having a parasitic clamping structure. Background Technology

[0002] In electronic circuits, overvoltage protection mechanisms are typically required to limit signal potentials within a safe range to prevent damage to electronic components. One current overvoltage protection mechanism involves placing diodes in the circuit. When the negative potential of the input signal exceeds a set threshold, the diode conducts, dissipating the excess current and protecting the electronic components. However, conducting large currents requires a very large number of diodes, leading to a significant increase in chip area, which is detrimental to chip miniaturization. Another overvoltage protection mechanism involves incorporating voltage clamping circuits for negative voltage detection and using their channels to dissipate large currents, thus protecting the electronic components. However, incorporating voltage clamping circuits increases circuit complexity and manufacturing costs, and these circuits also occupy a significant area, hindering chip miniaturization. Utility Model Content

[0003] In view of this, the purpose of this utility model is to provide a semiconductor device that, through the arrangement of a buried layer, generates a parasitic clamping structure around a power component, including a parasitic bipolar junction transistor and a parasitic diode, to achieve a negative voltage clamping effect, thereby protecting the power component and other electronic components. These parasitic clamping structures do not significantly increase the footprint, which is beneficial for chip miniaturization. Furthermore, these parasitic clamping structures do not increase the number of process steps or photomasks, thus saving manufacturing costs.

[0004] According to one embodiment, the present invention provides a semiconductor device including a substrate, a first buried layer, a power element, a sealing ring, and a second buried layer. The substrate has a first conductivity type, the first buried layer has a second conductivity type, and is disposed within the substrate. The power element is disposed within the first buried layer. The sealing ring is disposed within the substrate, surrounding the first buried layer, and has a first conductivity type. The second buried layer has a second conductivity type, is disposed within the substrate, located between the first buried layer and the sealing ring, and is laterally spaced from both the first buried layer and the sealing ring. The first buried layer is configured to be electrically coupled to the input voltage of the power element, and the second buried layer is configured to be electrically coupled to the output voltage of the power element.

[0005] A portion of the substrate is located between the first buried layer and the second buried layer, and the first buried layer, the portion of the substrate, and the second buried layer constitute a parasitic bipolar junction transistor clamping structure, while the second buried layer and the substrate constitute a parasitic diode clamping structure.

[0006] It also includes a doped region having the first conductivity type, located between the first buried layer and the second buried layer, disposed within the substrate, wherein the doped region is configured to be electrically coupled to a ground voltage, and the doped region is laterally separated from the first buried layer, the second buried layer and the sealing ring.

[0007] The sealing ring is configured to be electrically coupled to a ground voltage.

[0008] The system also includes a doped region having the first conductivity type, disposed within the substrate, located between the first buried layer and the sealing ring, wherein the doped region includes multiple blocks, which are laterally separated from the first buried layer, the second buried layer and the sealing ring, and each of the multiple blocks is configured to be electrically coupled to a ground voltage.

[0009] The sealing ring is configured to be electrically coupled to the ground voltage.

[0010] The second buried layer includes multiple blocks, and the multiple blocks of the doped region and the multiple blocks of the second buried layer are alternately arranged along one side of the power element and laterally spaced from each other.

[0011] It also includes a third buried layer having the second conductivity type, disposed within the substrate, located between the first buried layer and the sealing ring, and the third buried layer is configured to be electrically coupled to the input voltage of the power element.

[0012] The second buried layer includes multiple blocks, and the multiple blocks of the second buried layer, the multiple blocks of the doped region, and the third buried layer are alternately arranged along one side of the power device and laterally separated from each other, and one block of the doped region is located between one block of the second buried layer and the third buried layer.

[0013] According to another embodiment, the present invention provides a semiconductor device including a substrate, a first buried layer, a power element, a second buried layer, a third buried layer, and a doped region. The substrate has a first conductivity type, the first buried layer has a second conductivity type and is disposed within the substrate, and the power element is disposed in the first buried layer. The second buried layer has a second conductivity type, is disposed within the substrate, located on one side of the power element, and the second buried layer and the first buried layer are laterally separated in a first direction. The third buried layer has a second conductivity type, is disposed within the substrate, located on the aforementioned side of the power element, and the third buried layer and the second buried layer are laterally separated in a second direction. The doped region has a first conductivity type, is disposed within the substrate, located on the aforementioned side of the power element, and the second buried layer, the doped region, and the third buried layer are laterally separated in a second direction and arranged alternately, wherein the doped region is located between the second buried layer and the third buried layer. The first buried layer and the third buried layer are both configured to be electrically coupled to the input voltage of the power element, the second buried layer is configured to be electrically coupled to the output voltage of the power element, and the doped region is configured to be electrically coupled to ground voltage. Attached Figure Description

[0014] To facilitate understanding, the accompanying drawings and detailed textual descriptions can be consulted while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which also illustrate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0015] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0016] Figure 2 It is along Figure 1 The cross-sectional tangent A-A' is a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0017] Figure 3 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0018] Figure 4 It is along Figure 3 The cross-sectional tangent B-B' is a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0019] Figure 5 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0020] Figure 6 It is along Figure 5 The cross-sectional tangents C-C' and D-D' are shown in a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0021] Figure 7 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0022] Figure 8 It is along Figure 7 The cross-sectional tangents E-E', F-F', and G-G' are shown in a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0023] Figure 9 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0024] Figure 10 It is along Figure 9 The cross-sectional tangents H-H', I-I', and J-J' are shown in a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures: 100A, 100B, 100C, 100D, 100E ~ Semiconductor device; 101 ~ Substrate; 101P ~ Part of the substrate; 103 ~ First buried layer; 104 ~ First heavily doped contact region; 105 ~ Second buried layer; 105P1, 105P2, 105P3 ~ Blocks; 106 ~ Second heavily doped contact region; 106P1, 106P2, 106P3 ~ Heavily doped contact region; 107 ~ Sealing ring; 108 ~ Isolation structure; 109 ~ Doped region; 109P1, 109P2, 109P3 ~ Blocks; 11 0 ~ Power components; 110A, 110B, 110C, 110D ~ Sides; 111, 112 ~ Contact windows; 113 ~ Third buried layer; 114, 114A, 114B ~ Parasitic bipolar junction transistor clamping structure; 115 ~ Third doped contact region; 116 ~ Parasitic diode clamping structure; 120 ~ Other electronic components; VIN ~ Input voltage; VOUT ~ Output voltage; GND ~ Ground voltage; A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I', J-J' ~ Sectional tangents. Detailed Implementation

[0026] This utility model provides several different embodiments that can be used to implement different features of the utility model. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," so that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this utility model may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate the relationship between different embodiments and / or configurations.

[0027] Furthermore, regarding spatially related descriptive terms mentioned in this utility model, such as "below," "low," "high," "below," "above," "above," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0028] Although this utility model uses terms such as "first," "second," and "third" to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this utility model, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0029] The terms "about" or "generally" used in this invention typically mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without a specific mention of "about" or "generally," the meaning of "about" or "substantially" may be implied.

[0030] The terms "electrically coupled" and "electrically connected" as used in this invention include any direct or indirect electrical connection means. For example, if the text describes a first component being electrically coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0031] Although the present invention is described below by way of specific embodiments, the principles of the present invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the present invention, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.

[0032] This invention relates to a semiconductor device with parasitic clamping structures. Through the installation of a buried layer, parasitic clamping structures are generated around the power element, including parasitic bipolar junction transistors and parasitic diodes, achieving a negative voltage clamping effect and thus protecting the power element. These parasitic clamping structures are located inside the sealing ring of the power element, without increasing the footprint, which is beneficial for chip miniaturization. Furthermore, these parasitic clamping structures can be formed simultaneously during the power element manufacturing process, thus without increasing the number of process steps and photomasks in the semiconductor device, thereby saving manufacturing costs.

[0033] Figure 1 This is a top view schematic diagram of a semiconductor device 100A according to an embodiment of the present invention. Figure 2 It is along Figure 1 The cross-sectional tangent A-A' is a partial cross-sectional schematic diagram of a semiconductor device 100A according to an embodiment of the present invention. (See also...) Figure 1 and Figure 2 The semiconductor device 100A includes at least a substrate 101, a first buried layer 103, a power element 110, a sealing ring 107, and a second buried layer 105. The substrate 101 has a first conductivity type, such as a P-type semiconductor substrate. The first buried layer 103 has a second conductivity type, such as an N-type buried layer (NBL), and is disposed within the substrate 101. The power element 110 is disposed in the first buried layer 103. The power element 110 is, for example, a metal-oxide-semiconductor (MOS) transistor. (For simplicity and clarity, the diagram is omitted.) Figure 1 and Figure 2 The detailed structure of power element 110 is not shown. One end of power element 110 is electrically connected to the input voltage VIN through contact window 111, and the other end is electrically connected to the output voltage VOUT through contact window 112, wherein contact window 112 is located on one side 110A of power element 110. The second buried layer 105 has a second conductivity type, such as an N-type buried layer (NBL), and is disposed within the substrate 101, close to the side 110A of power element 110, and laterally separated from the first buried layer 103, such as... Figure 2 As shown, a portion 101P of the substrate 101 is located between the first buried layer 103 and the second buried layer 105.

[0034] According to an embodiment of the present invention, the first buried layer 103 is configured to be electrically coupled to the input voltage VIN of the power element 110, and the second buried layer 105 is configured to be electrically coupled to the output voltage VOUT of the power element 110. A portion 101P of the substrate 101 is located between the first buried layer 103 and the second buried layer 105. Therefore, the first buried layer 103 of the second conductivity type, the portion 101P of the substrate 101 of the first conductivity type, and the second buried layer 105 of the second conductivity type can constitute a parasitic bipolar junction transistor clamping structure 114, such as a parasitic NPN bipolar junction transistor. In addition, the second buried layer 105 of the second conductivity type and the substrate 101 of the first conductivity type can also constitute a parasitic diode clamping structure 116.

[0035] Generally, when a power device is suddenly turned off, the inductance in the electronic circuit causes current continuity. Without negative voltage clamping, the output voltage of the power device will reach a very deep negative voltage, damaging the power device. In the semiconductor device 100A, a large area of ​​parasitic bipolar junction transistor clamping structure 114 and parasitic diode clamping structure 116 are formed through the second buried layer 105. When the output voltage VOUT of the power device 110 is instantaneously brought to a negative voltage, these parasitic clamping structures can quickly clamp the output voltage within the negative critical voltage range, thereby effectively protecting the power device. This is beneficial for applications in high-voltage, high-current electronic power systems.

[0036] See Figure 1 In some embodiments, other electronic components 120 may be disposed near one side 110D of the power component 110. A sealing ring 107 is disposed within the substrate 101, surrounding the first buried layer 103, the second buried layer 105, the power component 110, and the other electronic components 120. In one embodiment, the sealing ring 107 has a first conductivity type, such as a heavily doped P-type region (P+), the doping concentration of the sealing ring 107 is higher than the doping concentration of the substrate 101, and the sealing ring 107 is electrically coupled to ground voltage GND. The second buried layer 105 is located between the first buried layer 103 and the sealing ring 107, and the second buried layer 105 is laterally spaced from both the first buried layer 103 and the sealing ring 107 in the XY plane.

[0037] See Figure 2 The semiconductor device 100A further includes a first heavily doped contact region 104 and a second heavily doped contact region 106, both having a second conductivity type, such as an N-type heavily doped region (N+). The first heavily doped contact region 104 is disposed within a first buried layer 103, and the first buried layer 103 is electrically coupled to the input voltage VIN of the power element 110 via the first heavily doped contact region 104. The second heavily doped contact region 106 is disposed within a second buried layer 105, and the second buried layer 105 is electrically coupled to the output voltage VOUT of the power element 110 via the second heavily doped contact region 106. Furthermore, to make the planar configuration of the semiconductor device 100A clearer and easier to understand from a top view, Figure 1 The drawing of isolation structure 108 is omitted. For example... Figure 2 As shown, multiple isolation structures 108, such as shallow trench isolation regions, are disposed within the substrate 101 to electrically isolate the first heavily doped contact region 104, the second heavily doped contact region 106, and the sealing ring 107 from each other, and to electrically isolate the power element 110 from the first heavily doped contact region 104.

[0038] like Figure 1As shown, in one embodiment, the contact window 112 for the output voltage VOUT of the power element 110 is located on side 110A of the power element 110, and the second buried layer 105 is close to this side 110A. In other embodiments, the electronic element 120 is close to one side 110D of the power element 110, and the second buried layer 105 may continuously or segmentally surround the other three sides 110A, 110B, and 110C of the power element 110, thereby providing a larger area for the parasitic bipolar junction transistor clamping structure 114 and the parasitic diode clamping structure 116.

[0039] Figure 3 This is a top view schematic diagram of a semiconductor device 100B according to an embodiment of the present invention. Figure 4 It is along Figure 3 The cross-sectional tangent B-B' is a partial cross-sectional schematic diagram of a semiconductor device 100B according to an embodiment of the present invention. Furthermore, to make the planar configuration of the semiconductor device 100B clearer and easier to understand from a top view, Figure 3 The isolation structure 108 is omitted from the drawing. In this embodiment, the semiconductor device 100B further includes a doped region 109 having a first conductivity type, such as a heavily doped P-type region (P+), and the doping concentration of the doped region 109 is higher than the doping concentration of the substrate 101. Figure 4 As shown, the doped region 109 is located between the first buried layer 103 and the second buried layer 105, and is disposed in a portion 101P of the substrate 101. The doped region 109 is electrically isolated from the first heavily doped contact region 104 and the second heavily doped contact region 106 via an isolation structure 108. In one embodiment, the doped region 109 and the sealing ring 107 may have the same doping concentration, and both the doped region 109 and the sealing ring 107 are configured to be electrically coupled to the ground voltage GND. Figure 3 As shown, the doped region 109 is laterally spaced from the first buried layer 103, the second buried layer 105, and the sealing ring 107 in the XY plane. In one embodiment, the contact window 112 of the output voltage VOUT of the power element 110 is located on side 110A of the power element 110, and the doped region 109 is close to this side 110A. In other embodiments, the electronic element 120 is close to one side 110D of the power element 110, the second buried layer 105 continuously or segmentally surrounds the other three sides 110A, 110B, and 110C of the power element 110, and the doped region 109 also continuously or segmentally surrounds the three sides 110A, 110B, and 110C of the power element 110.

[0040] In semiconductor device 100B, the doped region 109 electrically coupled to ground voltage GND can reduce the resistance of a portion 101P of substrate 101 to ground voltage GND, thereby improving the conduction effect of parasitic bipolar junction transistor clamping structure 114 and improving the negative voltage clamping effect of semiconductor device 100B. Furthermore, details of other features of semiconductor device 100B can be found in the aforementioned description of semiconductor device 100A, and will not be repeated here.

[0041] Figure 5 This is a top view schematic diagram of a semiconductor device 100C according to an embodiment of the present invention. Figure 6 The cross-sections (a) and (b) are respectively along... Figure 5 The cross-sectional tangents C-C' and D-D' are shown in a partial cross-sectional view of a semiconductor device 100C according to an embodiment of the present invention. Furthermore, to make the planar configuration of the semiconductor device 100C clearer and easier to understand from a top view, Figure 5 The drawing of isolation structure 108 is omitted. See also Figure 5 The second buried layer 105 of the semiconductor device 100C may include multiple blocks 105P1, 105P2, and 105P3, and the doped region 109 of the semiconductor device 100C may include multiple blocks 109P1, 109P2, and 109P3. These blocks of the doped region 109 all have a first conductivity type, such as a P-type heavily doped region (P+), and are located between the first buried layer 103 and the sealing ring 107. These blocks of the doped region 109 and these blocks of the second buried layer 105 may be arranged alternately along the side 110A of the power element 110 and laterally spaced from each other, and these blocks of the doped region 109 are laterally spaced from the first buried layer 103 and the sealing ring 107 in the XY plane. Furthermore, these blocks of the doped region 109 and these blocks of the second buried layer 105 are laterally separated from the first buried layer 103 in a first direction (e.g., the Y-axis) and are arranged alternately in a second direction (e.g., the X-axis).

[0042] See Figure 6 In cross-section (a), the blocks 109P1, 109P2, and 109P3 of the doped region 109 are disposed within the substrate 101, and the doping concentration of each of these blocks is higher than that of the substrate 101. These blocks of the doped region 109 and the sealing ring 107 may have the same doping concentration and are all configured to be electrically coupled to the ground voltage GND. Figure 5 and Figure 6As shown in cross section (b), the semiconductor device 100C also includes a plurality of heavily doped contact regions 106P1, 106P2 and 106P3, which are respectively disposed in a plurality of blocks 105P1, 105P2 and 105P3 of the second buried layer 105. These heavily doped contact regions all have a second conductivity type, such as an N-type heavily doped region (N+). The plurality of blocks 105P1, 105P2 and 105P3 of the second buried layer 105 can be electrically coupled to the output voltage VOUT of the power element 110 via these heavily doped contact regions 106P1, 106P2 and 106P3, respectively.

[0043] See Figure 5 In one embodiment, the contact window 112 for the output voltage VOUT of the power element 110 is located on side 110A of the power element 110, with these blocks of the second buried layer 105 and these blocks of the doped region 109 close to side 110A of the power element 110. In other embodiments, the electronic element 120 is located close to side 110D of the power element 110, and the plurality of blocks of the second buried layer 105 and the plurality of blocks of the doped region 109 may be arranged alternately and continuously or segmentally around the other three sides 110A, 110B, and 110C of the power element 110. Although Figure 5 The diagram shows three blocks of the second buried layer 105 and three blocks of the doped region 109, but the number of blocks of the second buried layer 105 and the doped region 109 is not limited thereto. The number and configuration of blocks of the second buried layer 105 of the second conductivity type and the doped region of the first conductivity type can be adjusted according to the negative voltage clamping requirements of the power element 110.

[0044] In semiconductor device 100C, these blocks of doped regions 109 electrically coupled to ground voltage GND can reduce the resistance of substrate 101 to ground voltage GND, thereby improving the conduction effect of parasitic bipolar junction transistor clamping structure 114 and improving the negative voltage clamping effect of semiconductor device 100C. Furthermore, arranging multiple blocks of doped regions 109 among multiple blocks of the second buried layer 105 can save space, which is beneficial for chip miniaturization. In some embodiments, the area ratio of each block 105P1 / 105P2 / 105P3 of the second buried layer 105 to each block 109P1 / 109P2 / 109P3 of the doped region 109 can be from 1:1 to 4:1, for example, 1:1, 2:1, or 4:1. Details of other features of semiconductor device 100C can be found in the aforementioned description of semiconductor device 100A, and will not be repeated here.

[0045] Figure 7 This is a top view schematic diagram of a semiconductor device 100D according to an embodiment of the present invention. Figure 8 Sections (a), (b), and (c) are along... Figure 7The cross-sectional tangents E-E', F-F', and G-G' are shown in a partial cross-sectional view of a semiconductor device 100D according to an embodiment of the present invention. Furthermore, to make the planar configuration of the semiconductor device 100D clearer and easier to understand from a top view, Figure 7 The drawing of isolation structure 108 is omitted. See also Figure 7 The second buried layer 105 of the semiconductor device 100D includes multiple blocks 105P1 and 105P2, and the doped region 109 includes multiple blocks 109P1, 109P2, and 109P3. Furthermore, the semiconductor device 100D also includes a third buried layer 113 and a third heavily doped contact region 115. The third buried layer 113 has a second conductivity type, such as an N-type buried layer (NBL), and is disposed within the substrate 101, located between the first buried layer 103 and the sealing ring 107. The third heavily doped contact region 115 has a second conductivity type, such as an N-type heavily doped region (N+), and is disposed within the third buried layer 113.

[0046] See Figure 7 and Figure 8 In cross-section (a), the third buried layer 113 and the first buried layer 103 are connected to each other, and the third buried layer 113 is in lateral contact with the first buried layer 103. The third heavily doped contact region 115 and the first heavily doped contact region 104 are connected to each other, and both the first buried layer 103 and the third buried layer 113 are electrically coupled to the input voltage VIN of the power element 110 via the first heavily doped contact region 104 and the third heavily doped contact region 115. Furthermore, Figure 8 For details of section (b), please refer to the aforementioned Figure 6 The relevant description of the cross section (a) shows that multiple blocks 109P1, 109P2 and 109P3 of the doped region 109 are configured to be electrically coupled to the ground voltage GND. Figure 8 For details of section (c), please refer to the aforementioned Figure 6 The relevant description of section (b) shows that multiple blocks 105P1 and 105P2 of the second buried layer 105 are configured to be electrically coupled to the output voltage VOUT of the power element 110.

[0047] See also Figure 7 Multiple blocks of doped region 109 and multiple blocks of second buried layer 105 are laterally separated from first buried layer 103 in a first direction (Y-axis). Third buried layer 113, multiple blocks of doped region 109, and multiple blocks of second buried layer 105 are laterally separated in a second direction (X-axis) and alternately arranged along one side edge 110A of power element 110, wherein doped region 109P1 is located between block 105P1 and third buried layer 113, and doped region 109P2 is located between third buried layer 113 and block 105P2. Although Figure 7The diagram shows two blocks 105P1 and 105P2 of the second buried layer 105, one block of the third buried layer 113, and three blocks 109P1, 109P2, and 109P3 of the doped region 109. However, the number of blocks in the second buried layer 105, the third buried layer 113, and the doped region 109 is not limited thereto, and the number and configuration of the aforementioned features can be adjusted according to the negative voltage clamping requirements of the power element 110.

[0048] In the semiconductor device 100D, the first buried layer 103, a portion 101P of the substrate 101, and the second buried layer 105 can constitute a parasitic bipolar junction transistor clamping structure 114A. Furthermore, the third buried layer 113, the substrate 101, and the second buried layer 105, electrically coupled to the input voltage VIN of the power element 110, can constitute another parasitic bipolar junction transistor clamping structure 114B, thereby increasing the equivalent area of ​​the parasitic bipolar junction transistor. Simultaneously, multiple blocks of the doped region 109 electrically coupled to the ground voltage GND can reduce the resistance of the substrate 101 to the ground voltage GND. Therefore, the semiconductor device 100D can very effectively utilize the conduction characteristics of the parasitic bipolar junction transistor, further enhancing the negative voltage clamping effect. Moreover, alternating the arrangement of the third buried layer 113, multiple blocks of the doped region 109, and multiple blocks of the second buried layer 105 can save space and facilitate chip miniaturization. In some embodiments, based on the area of ​​each block 109P1 / 109P2 / 109P3 of the doped region 109, the ratio of the area of ​​each block 105P1 / 105P2 of the second buried layer 105 to the area of ​​each block 109P1 / 109P2 / 109P3 of the doped region 109 to the area of ​​the third buried layer 113 can be from 1:1:1 to 4:1:4, for example, 1:1:1, 2:1:2, or 4:1:4. Furthermore, details of other features of the semiconductor device 100D can be found in the aforementioned description of the semiconductor device 100A, and will not be repeated here.

[0049] Figure 9 This is a top view schematic diagram of a semiconductor device 100E according to an embodiment of the present invention. Figure 10 Sections (a), (b), and (c) are along... Figure 9 The cross-sectional tangents H-H', I-I', and J-J' are shown in the schematic diagram of a partial cross-sectional view of a semiconductor device 100D according to an embodiment of the present invention. Furthermore, to make the planar configuration of the features of the semiconductor device 100E clearer and easier to understand from a top view, Figure 9The isolation structure 108 is omitted from the drawing. The third buried layer 113 and the first buried layer 103 of the semiconductor device 100E are laterally separated, and the third heavily doped contact region 115 and the first heavily doped contact region 104 are also laterally separated by the isolation structure 108. The third buried layer 113 is electrically coupled to the input voltage VIN of the power element 110 via the third heavily doped contact region 115, and the first buried layer 103 is electrically coupled to the input voltage VIN of the power element 110 via the first heavily doped contact region 104. Similar to the aforementioned semiconductor device 100D, the semiconductor device 100E can generate parasitic bipolar junction transistor clamping structures 114A and 114B and a parasitic diode clamping structure 116. Details of other features of the semiconductor device 100E can be found in the relevant description of the aforementioned semiconductor device 100D, and will not be repeated here. Similarly, the semiconductor device 100E can increase the equivalent area of ​​the parasitic bipolar junction transistor and reduce the substrate resistance, thereby effectively utilizing the conduction characteristics of the parasitic bipolar junction transistor and improving the negative voltage clamping effect.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; A first buried layer having a second conductivity type is disposed within the substrate; A power element is disposed in the first buried layer; A sealing ring is disposed within the substrate and surrounds the first embedded layer, wherein the sealing ring has the first conductivity type; as well as A second embedded layer, having the second conductivity type, is disposed within the substrate, located between the first embedded layer and the sealing ring, and the second embedded layer is laterally spaced from both the first embedded layer and the sealing ring. The first buried layer is configured to be electrically coupled to an input voltage of the power element, and the second buried layer is configured to be electrically coupled to an output voltage of the power element.

2. The semiconductor device as claimed in claim 1, characterized in that, A portion of the substrate is located between the first buried layer and the second buried layer, and the first buried layer, the portion of the substrate, and the second buried layer constitute a parasitic bipolar junction transistor clamping structure, and the second buried layer and the substrate constitute a parasitic diode clamping structure.

3. The semiconductor device as claimed in claim 1, characterized in that, It also includes a doped region having the first conductivity type, located between the first buried layer and the second buried layer, disposed within the substrate, wherein the doped region is configured to be electrically coupled to a ground voltage, and the doped region is laterally separated from the first buried layer, the second buried layer and the sealing ring.

4. The semiconductor device as claimed in claim 1, characterized in that, The sealing ring is configured to be electrically coupled to a ground voltage.

5. The semiconductor device as claimed in claim 1, characterized in that, It also includes a doped region having the first conductivity type, disposed within the substrate, located between the first buried layer and the sealing ring, wherein the doped region includes multiple blocks, the multiple blocks being laterally separated from the first buried layer, the second buried layer and the sealing ring, and the multiple blocks being configured to be electrically coupled to a ground voltage.

6. The semiconductor device as claimed in claim 5, characterized in that, The sealing ring is configured to be electrically coupled to the ground voltage.

7. The semiconductor device as claimed in claim 5, characterized in that, The second buried layer includes multiple blocks, and the multiple blocks of the doped region and the multiple blocks of the second buried layer are alternately arranged along one side of the power element and laterally spaced from each other.

8. The semiconductor device as claimed in claim 5, characterized in that, It also includes a third buried layer having the second conductivity type, disposed within the substrate, located between the first buried layer and the sealing ring, and the third buried layer is configured to be electrically coupled to the input voltage of the power element.

9. The semiconductor device as claimed in claim 8, characterized in that, The second buried layer includes multiple blocks, the multiple blocks of the second buried layer, the multiple blocks of the doped region and the third buried layer are alternately arranged along one side of the power device and laterally spaced from each other, and one block of the doped region is located between one block of the second buried layer and the third buried layer.

10. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; A first buried layer having a second conductivity type is disposed within the substrate; A power element is disposed in the first buried layer; A second buried layer having the second conductivity type is disposed in the substrate, located on one side of the power element, and the second buried layer and the first buried layer are laterally separated in a first direction; A third buried layer, having the second conductivity type, is disposed within the substrate, located on the side of the power element, and the third buried layer and the second buried layer are laterally spaced apart in a second direction; and A doped region, having the first conductivity type, is disposed within the substrate and located on the side of the power device, wherein the second buried layer, the doped region, and the third buried layer are laterally spaced apart and alternately arranged in the second direction, and the doped region is located between the second buried layer and the third buried layer. The first buried layer and the third buried layer are both configured to be electrically coupled to an input voltage of the power element, the second buried layer is configured to be electrically coupled to an output voltage of the power element, and the doped region is configured to be electrically coupled to a ground voltage.

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