image sensor

Abstract

Embodiments of the present application relate to image sensors. An image sensor includes a photodetector disposed in a semiconductor substrate. The photodetector includes a collector region and a pinning region. The pinning region is disposed between the collector region and a front side of the semiconductor substrate. The pinning region and the semiconductor substrate include a first doping type, and the collector region includes a second doping type opposite the first doping type. An isolation structure is located in the semiconductor substrate and adjacent the photodetector. A doped liner region extends along opposing sidewalls of the isolation structure and includes the first doping type. The doped liner region extends from a side of the collector region and the pinning region to the sidewalls of the isolation structure. The first doping type is n-type, and the second doping type is p-type.

Description

Technical Field

[0001] This utility model relates to an image sensor. Background Technology

[0002] Many modern electronic devices (e.g., smartphones, digital cameras, biomedical imaging devices, automotive imaging devices, etc.) include image sensors. Image sensors include one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output an electrical signal corresponding to the incident radiation. Some types of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD image sensors, CMOS image sensors are favored due to their lower power consumption, smaller size, faster data processing, direct data output, and lower manufacturing cost. Utility Model Content

[0003] The image sensor of this embodiment includes a semiconductor substrate, a photodetector, an isolation structure, and a doped substrate region. The semiconductor substrate includes opposing front and back sides. The photodetector is disposed in the semiconductor substrate and includes a collector region and a pinned region, the pinned region being disposed between the collector region and the front side of the semiconductor substrate. The pinned region and the semiconductor substrate include a first doping type, and the collector region includes a second doping type opposite to the first doping type. The isolation structure is located in the semiconductor substrate and adjacent to the photodetector. The doped substrate region extends along opposing sidewalls of the isolation structure and includes the first doping type, wherein the doped substrate region extends from the sidewalls of the collector region and the pinned region to the sidewalls of the isolation structure, wherein the first doping type is n-type and the second doping type is p-type.

[0004] The image sensor of this embodiment includes a first integrated circuit chip, a second integrated circuit chip, and a third integrated circuit chip. The first integrated circuit chip includes a first photodetector and a second photodetector, a first p-type floating diffusion node, and an isolation structure. The first and second photodetectors are disposed in a first substrate, wherein the first and second photodetectors respectively include a p-type collector region and an n-type pinned region. The first p-type floating diffusion node is disposed in the first substrate and adjacent to the first photodetector. The isolation structure is disposed in the first substrate and covers the first and second photodetectors. The second integrated circuit chip is located on and coupled to the first integrated circuit chip, wherein the second integrated circuit chip includes a plurality of first pixel devices located on a second substrate, wherein the plurality of first pixel devices include a reset transistor, a source follower transistor, and a select transistor, wherein the gate of the source follower transistor is coupled to the first p-type floating diffusion node. The third integrated circuit chip is located on and coupled to the second integrated circuit chip, wherein the third integrated circuit chip includes a plurality of semiconductor devices located on a third substrate and coupled to the second integrated circuit chip. Attached Figure Description

[0005] This disclosure can be better understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, it should be emphasized that the drawings only show typical embodiments of the present invention and should not be considered as limiting the scope of the claim, as the present invention can be equally applied to other embodiments.

[0006] Figure 1 The illustration shows some embodiments of an image sensor including pixels with low leakage current photodetectors.

[0007] Figure 2A The illustration includes cross-sectional views of some embodiments of an image sensor with pixels having low leakage current photodetectors, wherein the pixels span a first integrated circuit chip and a second integrated circuit chip.

[0008] Figure 2B-2E illustrate Figure 2A Cross-sectional views of some other embodiments of the image sensor.

[0009] Figure 3 Explanation along Figure 2A The line A-A' is captured Figure 2A Top view of some embodiments of the image sensor.

[0010] Figure 4A and Figure 4B illustrate Figure 2A Cross-sectional views of some other embodiments of the image sensor.

[0011] Figure 5 Explanation along Figure 4B The line A-A' is captured Figure 4B Top view of some embodiments of the image sensor.

[0012] Figure 6 illustrate Figure 2A Circuit diagrams of some other embodiments of the image sensor, wherein the image sensor also includes a third integrated circuit chip.

[0013] Figure 7 illustrate Figure 2A Cross-sectional views of some other embodiments of the image sensor, wherein the image sensor also includes a third integrated circuit chip.

[0014] Figure 8-21 Cross-sectional views illustrating some embodiments of a method for forming an image sensor including a photodetector with low leakage current.

[0015] Figure 22 Flowcharts illustrating some embodiments of a method for forming an image sensor including a photodetector with low leakage current. Detailed Implementation

[0016] This disclosure provides numerous different embodiments or examples for implementing various features of the present invention. Specific examples of components and arrangements are described below to simplify the disclosure. These are merely examples and are not intended to be limiting. For instance, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, but does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0018] Complementary metal-oxide-semiconductor (CMOS) image sensors comprise an array of photodetectors within a semiconductor substrate. Each photodetector includes a pn junction between its collector region and an adjacent region of the semiconductor substrate. The photodetectors are configured to accumulate photogenerated charge, and transfer transistors are configured to selectively transfer the photogenerated charge to a floating diffusion node. The photodetectors can be isolated from each other via a deep trench isolation (DTI) structure disposed in a trench within the semiconductor substrate. The DTI structure provides good electrical and optical isolation between the photodetectors. The collector region of the photodetector comprises an n-type dopant (e.g., arsenic, antimony, phosphorus, etc.), and the region of the semiconductor substrate adjacent to the collector region comprises a p-type dopant (e.g., boron, indium, aluminum, etc.). Furthermore, the floating diffusion node includes an n-type dopant, and the transfer transistor and other pixel devices (e.g., reset transistor, select transistor, source follower transistor, etc.) can each be configured as an n-channel transistor (e.g., an n-channel metal-oxide-semiconductor (NMOS) transistor) to facilitate readout of the photodetector.

[0019] While DTI structures offer good electrical and optical isolation, problems can arise during the fabrication or use of CMOS image sensors. For example, during the fabrication of a CMOS image sensor, a collector region is formed in a semiconductor substrate, and a DTI structure is formed in a semiconductor substrate adjacent to the collector region. The DTI structure can be formed by etching the front surface of the semiconductor substrate to form a trench, followed by forming DTI material in the trench (e.g., through a thermal oxidation process). The DTI structure includes DTI material, which can be or includes oxides such as silicon dioxide. During the formation of the DTI structure, the n-type dopant (e.g., arsenic and / or phosphorus) in the collector region has a first segregation coefficient greater than a second segregation coefficient of the p-type dopant (e.g., boron) in the semiconductor substrate. Therefore, the n-type dopant in the collector region may readily diffuse away from the collector region and accumulate along the interface between the DTI structure and the semiconductor substrate. For example, the n-type dopant may diffuse away from the collector region during the thermal oxidation process of forming the DTI structure or during one or more annealing processes (e.g., for forming transport transistors, other pixel devices, and / or interconnect structures on the semiconductor substrate). This can lead to unwanted leakage currents (e.g., dark currents) and / or white pixels in CMOS image sensors. Furthermore, the outward diffusion of n-type dopant from the collector region into the DTI structure may reduce the size of the collector region, thereby decreasing the potential well capacity of the photodetector and degrading the overall performance of the CMOS image sensor.

[0020] Therefore, the various embodiments disclosed herein pertain to image sensors with photodetectors having low leakage current. In some embodiments, the image sensor includes a photodetector having a collector region and a pinned region in a semiconductor substrate. The collector region includes a p-type dopant, and the pinned region and other regions of the semiconductor substrate adjacent to the collector region include n-type dopant. A deep trench isolation (DTI) structure is arranged in the semiconductor substrate and adjacent to the collector region. A doped liner region is disposed between the DTI structure and the photodetector and includes n-type dopant. The n-type dopant (e.g., arsenic, phosphorus, etc.) in the doped liner region has a first segregation coefficient (e.g., about 3 to 10), which is greater than a second segregation coefficient (e.g., about 0.1 to 0.3) of the p-type dopant (e.g., boron) in the collector region. The first and second segregation coefficients are segregation ratios at the interface between the semiconductor substrate and the DTI structure. The larger first segregation coefficient of the n-type dopant in the doped liner region (and other doped regions of the semiconductor substrate adjacent to the collector region) causes the n-type dopant to accumulate along the interface between the semiconductor substrate and the DTI structure. Furthermore, the smaller second segregation coefficient of the p-type dopant in the collector region mitigates the outward diffusion of p-type dopant from the collector region (e.g., towards the DTI structure interface). For example, during the thermal oxidation process used to form the DTI structure, n-type dopant may accumulate along the interface between the DTI structure and the semiconductor substrate, while p-type dopant in the collector region is less likely to diffuse into the DTI structure. Therefore, dopant segregation between the collector region and the adjacent region of the semiconductor substrate may increase. Consequently, unwanted leakage current (e.g., dark current) and / or white pixels in the image sensor are reduced. Furthermore, the size of the collector region may be maintained or increased, thereby increasing the potential well capacity of the photodetector. Therefore, the overall performance of the image sensor is improved.

[0021] Figure 1 Schematic diagram 100 illustrating some embodiments of an image sensor with pixels having low leakage current photodetectors.

[0022] The image sensor includes a pixel 104. Pixel 104 includes a photodetector 106, a transmission transistor 116, and a plurality of pixel transistors 120, 122, and 124 disposed in a first substrate 102a. The first substrate 102 has a front side 102f relative to a back side 102b. The first substrate 102 includes a first doping type (e.g., n-type). In some embodiments, the photodetector 106 includes a collector region 108 and a pinned region 110 disposed between the top of the collector region 108 and the front side 102f of the first substrate 102. The collector region 108 includes a second doping type (e.g., p-type) opposite to the first doping type. The pinned region 110 includes the first doping type (e.g., n-type). In various embodiments, the first doping type is n-type and the second doping type is p-type. The photodetector 106 is configured to convert incident light into an electrical signal. In various embodiments, the photodetector 106 is configured as a photodiode, a pinned photodiode, or some other suitable photodetector. In some embodiments, collector region 108 is referred to as first doped region and pinned region 110 is referred to as second doped region.

[0023] An isolation structure 114 is disposed in a first substrate 102. In some embodiments, the isolation structure 114 extends continuously from a front side 102f to a back side 102b of the first substrate 102. In various embodiments, the isolation structure 114 extends around the peripheral periphery of the photodetector 106 and is configured to provide optical and electrical isolation for the photodetector 106. The isolation structure 114 may be referred to as a deep trench isolation (DTI) structure or a front side deep trench isolation (FDTI) structure. A doped liner region 112 is disposed in the first substrate 102 and extends along opposite sidewalls of the isolation structure 114. The doped liner region 112 includes a first doping type (e.g., n-type) and extends from one or more sides of the photodetector 106 to the isolation structure 114.

[0024] A transfer transistor 116 is disposed on a first substrate 102 and includes a transfer gate dielectric layer 132, a transfer gate electrode 130 located on the transfer gate dielectric layer 132, and sidewall spacers 134 along the sidewalls of the transfer gate electrode 130 and the transfer gate dielectric layer 132. In some embodiments, the transfer transistor 116 is configured to selectively transfer accumulated charge from the photodetector 106 to a floating diffusion node 118. The floating diffusion node 118 is disposed in the first substrate 102 and includes a second doping type (e.g., p-type). In various embodiments, the transfer gate electrode 130 is spaced between the floating diffusion node 118 and the photodetector 106.

[0025] In some embodiments, the collector region 108 and the floating diffusion node 118 each include a p-type dopant, which may be, for example, boron, indium, aluminum, gallium, or some other suitable p-type dopant. In various embodiments, the first substrate 102 (e.g., a region of the first substrate 102 adjacent to the collector region 108 and / or the floating diffusion node 118), the pinned region 110, and the doped substrate region 112 include an n-type dopant, which may be, for example, arsenic, antimony, phosphorus, or some other suitable n-type dopant.

[0026] The plurality of pixel transistors 120, 122, 124 include a reset transistor 120, a source follower transistor 122, and a select transistor 124. The reset transistor 120 has a first source / drain region coupled to a floating diffusion node 118 and a second source / drain region coupled to a reference voltage node 126. In some embodiments, the reference voltage node 126 is coupled to ground (e.g., 0 volts). In some embodiments, a first substrate 102 is electrically coupled to a power supply voltage node 128, which may be, for example, in the range of about 0.9 to 5 volts. The reset transistor 120 is controlled by a reset signal RST and is configured to selectively couple the floating diffusion node 118 to the reference voltage node 126. In various embodiments, the reset transistor 120 is configured to selectively couple a photodetector 106 to the reference voltage node 126 in coordination with a transfer transistor 116, thereby clearing accumulated charge from the photodetector 106. The source follower transistor 122 has a first source / drain region coupled to a first source / drain region of the select transistor 124, and a second source / drain region coupled to a reference voltage node 126. The source follower transistor 122 is controlled by the charge of the floating diffusion node 118. In various embodiments, the source follower transistor 122 is configured to buffer and / or amplify the voltage of the floating diffusion node 118 for non-destructive reading of the pixel 104. The second source / drain region of the select transistor 124 is coupled to an output terminal (not labeled). The select transistor 124 is configured to selectively deliver a buffered and / or amplified voltage from the source follower transistor 122 to the output terminal. In various embodiments, the transfer transistor 116 and the plurality of pixel transistors 120, 122, 124 are each configured as a p-type transistor (e.g., a p-channel metal-oxide-semiconductor (PMOS) transistor). In some embodiments, the transmission transistor 116 and the plurality of pixel transistors 120, 122, 124 may each be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET), a nanosheet field-effect transistor, some other type of transistor, or any combination thereof.

[0027] During image sensor operation, incident radiation (e.g., incident light) strikes photodetector 106 to generate electron-hole pairs. In some embodiments, the formation of electron-hole pairs can release mobile holes collected in collector region 108, allowing photodetector 106 to convert the incident radiation into an electrical signal. During image sensor fabrication, an etching process is performed to form trenches in first substrate 102, which are subsequently filled with isolation structure 114. Isolation structure 114 may be, for example, or comprise oxides such as silicon dioxide or some other suitable material. In various embodiments, isolation structure 114 is substantially composed of silicon dioxide. In various embodiments, isolation structure 114 may be formed in the trenches by a thermal oxidation process.

[0028] The n-type dopants of the first substrate 102, doped liner region 112, and pinned region 110 have a first segregation coefficient k1 (e.g., in the range of about 3 to 10), which is greater than the second segregation coefficient k2 (e.g., in the range of about 0.1 to 0.3) of the p-type dopants of the collector region 108 and floating diffusion node 118. In various embodiments, the first and second segregation coefficients k1 and k2 refer to the segregation ratio or distribution coefficient at the interface between the first substrate 102 and the isolation structure 114, respectively, and are defined as the ratio of the dopant concentration in the isolation structure 114 to the dopant concentration in the first substrate 102 when the isolation structure 114 is formed in a silicon substrate containing the respective dopants. For example, k1 = Cn 102 / Cn 114 Cn 102 It is the concentration of n-type dopant in the first substrate 102 at the interface, Cn 114 This refers to the concentration of n-type dopant in the isolation structure 114 at the interface. Since the doped substrate region 112 contains n-type dopant with a high first segregation coefficient k1 and is disposed at the interface between the isolation structure 114 and the first substrate 102, n-type dopant may accumulate at the interface between the isolation structure 114 and the first substrate 102. This mitigates or prevents the diffusion of p-type dopant from the collector region 108 outside the interface between the isolation structure 114 and the first substrate 102, thereby increasing dopant segregation in the image sensor. As a result, dark current and / or white pixels are reduced, thereby reducing leakage current and improving the overall performance of the image sensor. Furthermore, the p-type dopant in the collector region 108 is less likely to diffuse out during the image sensor manufacturing process, mitigating the reduction in the size of the photodetector 106, thereby increasing and / or maintaining the potential well capacity of the photodetector 106 and improving the performance of the image sensor. In addition, the transmission transistor 116 and the plurality of pixel transistors 120, 122, and 124 are each configured as p-type transistors, which is beneficial for accurate and efficient readout of the photodetector 106.

[0029] In various embodiments, the doping concentration of the bulk region of the first substrate 102 is approximately 10. 14 Up to 1016 atoms / cm 3 Within the range or other suitable values. In some cases, the body region of the first substrate 102 is the region of the first substrate 102 adjacent to the photodetector 106, the floating diffusion node 118, the doped substrate region 112, and the pinned region 110. The doping concentration of the collector region 108, for example, is about 5*10⁻⁶. 16 Up to 10 18 atoms / cm 3 Within the range or other suitable values. The doping concentration of the collector region 108 is greater than the doping concentration of the bulk region of the first substrate 102. The doping concentration of the pinned region 110, for example, is within the range of approximately 10. 17 Up to 10 19 atoms / cm 3 Within the range or other suitable values. In some embodiments, the doping concentration of pinned region 110 is greater than that of collector region 108. This will partially benefit the pinned region 110 in pinning the depletion region between pinned region 110 and collector region 108, thereby improving the quantum efficiency (QE) of photodetector 106 and further reducing dark current.

[0030] The doping concentration of the doped substrate region 112, for example, is about 10. 17 Up to 10 19 atoms / cm 3 Within the range or other suitable values. In various embodiments, the doping concentration of the doped substrate region 112 is equal to the doping concentration of the pinned region 110, thereby further improving the QE of the photodetector 106. Furthermore, the doping concentration of the doped substrate region 112 is greater than the doping concentration of the collector region 108. Therefore, the negative effects (e.g., dark current, white spots, etc.) caused by defects (e.g., dangling bonds) along the isolation structure 114 can be reduced, thereby reducing leakage current in the image sensor. The doping concentration of the floating diffusion node 118, for example, is in the range of approximately 5*10⁻⁶. 16 Up to 10 18 atoms / cm 3 Within the range or other suitable values. In a further embodiment, the doping concentration of the floating diffusion node 118 is equal to the doping concentration of the collector region 108.

[0031] Figure 2A The illustration shows a cross-sectional view 200a of some embodiments of an image sensor including a first IC chip and a second IC chip.

[0032] In some embodiments, the image sensor includes a first IC chip 202 and a second IC chip 204 stacked vertically. The first IC chip 202 includes a first substrate 102, a first interconnect structure 205 on a front side 102f of the first substrate 102, and a first bonding structure 206 on the first interconnect structure 205. The first substrate 102 may be, for example, silicon, epitaxial silicon, silicon-germanium (SiGe), silicon-on-insulator (SOI) substrate, or some other suitable substrate material. The first substrate 102 includes a first dopant having a first doping type. In some embodiments, the first doping type is n-type, and the first dopant may be, for example, one or more of arsenic, phosphorus, and antimony, or some other suitable n-type dopant. A plurality of photodetectors 106 are disposed in the first substrate 102. The photodetectors each include a pinned region 110 and a collector region 108. The pinned region 110 includes the first doping type, and the collector region 108 includes a second dopant having a second doping type opposite to the first doping type. In various embodiments, the second doping type is p-type, and the second dopant may be, for example, one or more or some other suitable p-type dopants selected from boron, indium, aluminum, and gallium. In some embodiments, the pinned region 110 extends continuously from the bottom of the collector region 108 to the front side 102f of the first substrate 102. A floating diffusion node 118 is disposed in the first substrate 102 adjacent to the corresponding photodetector 106. The floating diffusion node 118 includes a second doping type (e.g., p-type).

[0033] A plurality of transmission transistors 116 are disposed on the front side 102f of the first substrate 102, each adjacent to a corresponding photodetector 106. Each transmission transistor 116 includes a transmission gate dielectric layer 132 on the first substrate 102 and a transmission gate electrode 130 on the transmission gate dielectric layer 132. An isolation structure 114 is disposed in the first substrate 102 between adjacent photodetectors 106. In various embodiments, the isolation structure 114 continuously covers the periphery of each photodetector 106. In some embodiments, the isolation structure 114 extends continuously vertically from the front side 102f of the first substrate 102 to the back side 102b of the first substrate 102. The isolation structure 114 may be, for example, or include silicon dioxide, silicon oxynitride, silicon oxycarbide, other dielectric materials, or any combination thereof. The isolation structure 114 is configured to increase electrical and optical isolation between the photodetectors 106. A doped substrate region 112 is disposed on the first substrate 102 and extends along the sidewall of the isolation structure 114. The doped substrate region 112 includes a first doping type (e.g., n-type).

[0034] In some embodiments, the doped liner region 112 extends continuously from the front side 102f of the first substrate to the back side 102b of the first substrate 102 along the sidewall of the isolation structure 114. In various embodiments, the lateral thickness Lt of the doped liner region 112 along the isolation structure 114 is less than the vertical thickness Vt of the pinned region 110. This will partially benefit the doped liner region 112 in slowing the outward diffusion of p-type dopant from the collector region 108 during the formation of the isolation structure 114, while maintaining or increasing the size of the collector region 108, thereby increasing the quantum efficiency of the photodetector 106. The doped liner region 112 extends continuously from one side of the collector region 108 to one side of the pinned region 110. Furthermore, the doped liner region 112 is disposed between the floating diffusion node 118 and the isolation structure 114. Therefore, the outward diffusion of p-type dopant in the floating diffusion node 118 is reduced, thereby further reducing leakage current and increasing the readout efficiency of the pixel 104.

[0035] In a further embodiment, pinning region 110 includes a first n-type dopant (e.g., antimony) and doped substrate region 112 includes a second n-type dopant (e.g., arsenic) different from the first n-type dopant. In various embodiments, the size (e.g., atomic radius) of the first n-type dopant is larger than the size (e.g., atomic radius) of the second n-type dopant. Because the size of the first n-type dopant is larger than that of the second n-type dopant, the first n-type dopant is less likely to penetrate the lattice of the first substrate 102, while the second n-type dopant is more likely to penetrate the lattice of the first substrate 102. Therefore, the second n-type dopant in doped substrate region 112 may more easily accumulate along the interface between the first substrate 102 and isolation structure 114, thereby enhancing dopant segregation and mitigating dark current and / or white spot. Furthermore, the less diffusion of the first n-type dopant is beneficial for pinning region 110 to increase the quantum efficiency of photodetector 106, while maintaining or increasing the size of collector region 108, thereby increasing the potential well capacity of photodetector 106. In various embodiments, the first n-type dopant of the pinned region 110 is or includes antimony, and the second n-type dopant of the doped substrate region 112 is or includes arsenic.

[0036] A mesh structure 234 is disposed on the back side 102b of the first substrate 102. The mesh structure 234 includes sidewalls defining an opening above the photodetector 106. The mesh structure 234 is configured to mitigate crosstalk between adjacent photodetectors 106. In various embodiments, the mesh structure 234 directly overlies the isolation structure 114 and / or the mesh structure 234 is aligned with the isolation structure 114. A plurality of filters 232 are disposed on the back side 102b of the first substrate 102. Each filter 232 is configured to allow passage of a first wavelength range while blocking a second wavelength range different from the first wavelength range. A plurality of microlenses 236 are disposed on the plurality of filters 232 and are configured to focus incident light toward the photodetector 106.

[0037] The second integrated circuit chip 204 includes a second substrate 203, a second interconnect structure 220 on the front side 203f of the second substrate 203, and a second bonding structure 222 on the second interconnect structure 220. The second substrate 203 may be, for example, silicon, epitaxial silicon, SiGe, SOI substrate, or some other suitable substrate material. The second substrate 203 includes a second doping type (e.g., p-type). A plurality of pixel transistors 120, 122, 124 are disposed in and / or on the second substrate 203. The first and second interconnect structures 205, 220 respectively include an interconnect dielectric structure 208, a plurality of conductive wirings 210, and a plurality of conductive vias 212. The first and second interconnect structures 205, 220 are configured to facilitate electrical coupling between and / or on the first integrated circuit chip 202 and the second integrated circuit chip 204. A first bonding structure 206 meets the second bonding structure 222 at a first bonding interface including conductor-to-conductor bonding and dielectric-to-dielectric bonding. The first and second bonding structures 206 and 222 respectively include a bonding dielectric structure 214, a plurality of conductive bonding contacts 216 and a plurality of conductive bonding pads 218.

[0038] A plurality of pixel transistors 120, 122, and 124 are disposed on the front side 203f of the second substrate 203. The plurality of pixel transistors 120, 122, and 124 each include a gate dielectric structure 226 on the second substrate 203, a gate electrode 224 on the gate dielectric structure 226, and a pair of source / drain regions 227 in corresponding well regions 230. In some embodiments, the well region 230 includes a first doping type (e.g., n-type) and each pair of source / drain regions 227 includes a second doping type (e.g., p-type). In a further embodiment, the gate electrode 224 of each of the pixel transistors 120, 122, and 124 includes one or more gate electrode layers having a p-type work function. In various embodiments, the transfer gate electrode 130 and the gate electrode 224 may include one or more gate electrode layers, respectively including p-type polysilicon, a metal having a p-type work function, or some other suitable material. In some embodiments, the p-type work function may be, for example, a work function of about 4.5 to 5.1 eV, greater than about 4.8 eV, 5.0 eV, or 5.2 eV, or some other suitable value. In some embodiments, the metal having a p-type work function may be, for example, or include titanium aluminum nitride, tungsten carbide nitride, nickel, platinum, some other suitable p-type work function metals, or any combination thereof. The transfer gate electrode 130 and the gate dielectric structure 226 may, for example, each include, or include, silicon dioxide, hafnium oxide, zirconium oxide, some other suitable dielectric material, or any combination thereof.

[0039] In various embodiments, the image sensor includes a plurality of pixels 104, each spanning a first integrated circuit chip 202 and a second integrated circuit chip 204. In some embodiments, each pixel 104 includes one or more photodetectors 106, one or more transmission transistors 116, and a plurality of pixel transistors 120, 122, 124. For example, each of the pixels 104 may include four transistors (e.g., a single transmission transistor, a reset transistor, a select transistor, and a source follower transistor) and a single photodetector. The pixels 104 span the first and second integrated circuit chips 202 and 204 in such a manner that the corresponding transmission transistors 116 and photodetectors 106 are configured in the first integrated circuit chip 202, while the corresponding plurality of pixel transistors 120, 122, 124 are configured in the second integrated circuit chip 204. Configuring the plurality of pixel transistors 120, 122, 124 in the second integrated circuit chip 204 creates more space for the photodetectors 106 on the first substrate 102 of the first integrated circuit chip 202. Therefore, the density of photodetectors 106 in the first integrated circuit chip 202 may be increased, and the feature size of pixels 104 in the first integrated circuit chip 202 may be reduced, while maintaining good electrical and optical isolation between adjacent pixels in the plurality of pixels 104.

[0040] Figure 2B illustrate Figure 2A A cross-sectional view 200b of some other embodiments of the image sensor, wherein the isolation structure 114 extends from the front side 102f of the first substrate 102 to a point below the back side 102b of the first substrate 102.

[0041] In some embodiments, the top surface of the isolation structure 114 is offset vertically from the back side 102b of the first substrate 102. A doped liner region 112 extends continuously from the sidewall of the isolation structure 114 to the top surface of the isolation structure 114. In various embodiments, the doped liner region 112 extends continuously from the top surface of the isolation structure 114 to the back side 102b of the first substrate 102.

[0042] Figure 2C illustrate Figure 2A A cross-sectional view 200c of some other embodiments of the image sensor, wherein in-pixel transistors 242 are disposed on a second substrate 203.

[0043] The in-pixel transistor 242 is part of the in-pixel circuitry. In some embodiments, the in-pixel circuitry includes a line amplifier, a correlated double sampling (CDS) circuit, some other suitable circuitry, or any combination thereof. The in-pixel transistor 242 includes a gate dielectric structure 246 on a second substrate 203, a gate electrode 244 on the gate dielectric structure 246, and a pair of source / drain regions 248 on opposite sides of the gate electrode 244 in the second substrate 203. In various embodiments, the pair of source / drain regions 248 includes a first doping type (e.g., n-type). In some embodiments, the in-pixel transistor 242 is configured as an n-type transistor, and the gate electrode 244 includes one or more gate electrode layers having an n-type work function. The in-pixel transistor 242 may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET), a nanosheet field-effect transistor, or some other type of transistor.

[0044] Figure 2D illustrate Figure 2A A cross-sectional view 200d of some other embodiments of the image sensor, wherein the sidewalls of the isolation structure 114 are inclined relative to the front side 102f of the first substrate 102. In various embodiments, the isolation structure 114 includes a plurality of isolation segments disposed between each photodetector 106, and the width of each isolation segment decreases continuously from the front side 102f to the back side 102b.

[0045] Figure 2E illustrate Figure 2AA cross-sectional view 200e of some other embodiments of the image sensor, wherein the isolation structure 114 includes a first isolation layer 250 and a second isolation layer 252. In some embodiments, the material of the first isolation layer 250 is different from the material of the second isolation layer 252. In some embodiments, the first isolation layer 250 may be or may include silicon dioxide or some other suitable material. The second isolation layer 252 may be or may include silicon dioxide, silicon oxynitride, silicon carbide, metals such as aluminum, tungsten, titanium nitride, or some other suitable material. In a further embodiment, the first isolation layer 250 may be or may include epitaxial silicon, doped epitaxial silicon, doped silicon oxide, or the like. In various embodiments, the first isolation layer 250 may include doped epitaxial silicon or doped silicon oxide having a first doping type (e.g., n-type), the doping concentration of which may be equal to or less than the doping concentration of the doped substrate region 112. In such embodiments, a first isolation layer 250 of a first doping type further enhances dopant segregation and / or mitigates problems (e.g., dark current) caused by defects (e.g., dangling bonds) along the isolation structure 114 in the first substrate 102.

[0046] Figure 3 Explanation along Figure 2A The line A-A' intercepts Figure 2A Top view 300 of some embodiments of the image sensor.

[0047] like Figure 3 As shown, when viewed from above, the isolation structure 114 has a grid layout. The isolation structure 114 continuously surrounds the photodetector of each pixel 104. Figure 2A 106 in the middle). In various embodiments, the pinning area 110 directly covers each photodetector ( Figure 2A The 106) polar region ( Figure 2A 108 in the middle). In some embodiments, the periphery of the pinning region 110 is adjacent to the collector region ( Figure 2A The outer periphery of 108 in the first substrate 102 is aligned. A power supply voltage node 304 is disposed within a region of each pixel 104 in the first substrate 102, wherein the region of each pixel 104 is defined by the inner sidewall of the isolation structure 114. The power supply voltage node 304 represents a connection to the first substrate 102, and a supply voltage is applied to the body region of the first substrate 102. In some embodiments, the power supply voltage node 304 is or includes a doped region of the first substrate 102, the doped region including a first doping type (e.g., n-type) whose doping concentration is greater than that of the collector region (…). Figure 2A The doping concentration of 108 in the middle.

[0048] Figure 4A illustrate Figure 2AA cross-sectional view 400a of some other embodiments of the image sensor. In some embodiments, the image sensor includes pixels 104 having a shared pixel layout, wherein floating diffusion nodes 118 are configured between two or more photodetectors 106. Pixel 104 may be a 1x2 shared layout, a 2x2 shared layout, or a similar layout.

[0049] Figure 4B illustrate Figure 4A A cross-sectional view 400b of some other embodiments of the image sensor shows a second isolation structure 402 disposed in a first substrate 102 and above a floating diffusion node 118. In some embodiments, the second isolation structure 402 extends continuously from the back side 102b of the first substrate 102 to the top of the floating diffusion node 118. The second isolation structure 402 may be or may include silicon dioxide, silicon carbide, silicon nitride, another dielectric material, or any combination thereof. In a further embodiment, a second doped substrate region (not shown) including an n-type dopant may be disposed on the sidewall of the second isolation structure 402.

[0050] Figure 5 Explanation along Figure 4B The line A-A' intercepts Figure 4B Top view 500 of some embodiments of the image sensor.

[0051] like Figure 5 As shown, in some embodiments, pixel 104 includes four photodetectors 106 and a transmission transistor 116 disposed between a floating diffusion node 118 and a corresponding photodetector 106. In some embodiments, the second isolation structure 402 directly contacts the sidewall of the isolation structure 114 and directly covers the floating diffusion node 118. In various embodiments, the second isolation structure 402 has a cross shape. In a further embodiment, the doped liner region 112 extends continuously from the front side 102f of the first substrate 102 to the bottom surface of the second isolation structure 402.

[0052] Figure 6 illustrate Figure 2A Circuit diagram 600 of some other embodiments of the image sensor, wherein the image sensor also includes a third IC chip.

[0053] The image sensor includes a first IC chip 202, a second IC chip 204, and a third IC chip 602. In some embodiments, the first IC chip 202 and the second IC chip 204 are each as follows: Figure 2A , 2BThe image sensor includes the configuration shown and / or described in 2C, 2D, 2E, 4A, or 4B. The image sensor includes pixels 104 spanning a first IC chip 202 and a second IC chip 204. Pixel 104 includes a photodetector 106, a transmission transistor 116, and a plurality of pixel transistors 120, 122, and 124. The photodetector 106 and the transmission transistor 116 are disposed on the first IC chip 202. In some embodiments, the photodetector 106 and the transmission transistor 116 are coupled in series between a floating diffusion node 118 and a power supply voltage node 128. The transmission transistor 116 is controlled by a transmission signal TX. In some embodiments, the anode of the photodetector 106 is electrically coupled to the transmission transistor 116, and the cathode of the photodetector 106 is electrically coupled to the power supply voltage node 128.

[0054] The plurality of pixel transistors 120, 122, and 124 are disposed on the second IC chip 204. The plurality of pixel transistors 120, 122, and 124 include a reset transistor 120, a source follower transistor 122, and a select transistor 124. The reset transistor 120 is coupled in series between a reference voltage node 126 and a floating diffusion node 118. The reset transistor 120 is controlled by a reset signal RST. The source follower transistor 122 is coupled in series between the reference voltage node 126 and the select transistor 124. The gate of the source follower transistor 122 is directly electrically coupled to the floating diffusion node 118. The select transistor 124 is controlled by a select signal SEL and is coupled in series between the source follower transistor 122 and the pixel-internal circuitry 601. In various embodiments, by appropriately biasing the transmission transistor 116 and the plurality of pixel transistors 122, 122, 124, an electrical signal corresponding to the incident light detected by the photosensor 106 is provided at the output of pixel 104 (e.g., the output of selection transistor 124) and transmitted to the in-pixel circuitry 601. The in-pixel circuitry 601 is disposed on the second IC chip 204. In some embodiments, the in-pixel circuitry 601 includes a line amplifier, a correlated double sampling (CDS) circuit, or other suitable circuitry. The in-pixel circuitry 601 may be configured to perform additional processing (e.g., amplification, noise cancellation, etc.) on the electrical signal output from pixel 104 before passing it to an application-specific integrated circuit (ASIC) 604 disposed on a third IC chip 602. Due to the plurality of pixel transistors 120, 122, 124 and the in-pixel circuitry 601 disposed on the second IC chip 204, fewer means (e.g., transistors) of pixel 104 are disposed on the first IC chip 202. This helps to reduce the size of the devices (e.g., photodetectors) on the first IC chip 202 and / or increase the number of photodetectors on the first IC chip 202, thereby improving the performance of the image sensor.

[0055] Figure 7 illustrate Figure 2A A cross-sectional view 700 of some other embodiments of the image sensor, wherein the image sensor also includes a third IC chip.

[0056] The image sensor includes a first IC chip 202, a second IC chip 204, and a third IC chip 602, which are stacked on top of each other in a vertical direction. In various embodiments, the first IC chip 202 and the second IC chip 204 can be as follows: Figure 2A , 2BThe configuration shown and / or described in 2C, 2D, 2E, 4A, or 4B. In some embodiments, the third IC chip 602 includes an ASIC electrically coupled to the second IC chip 204 (e.g., Figure 6 (604). The ASIC on the third IC chip 602 may include, for example, one or more of analog-to-digital conversion (ADC) circuitry, image processing circuitry, buffer circuitry, or similar circuitry.

[0057] In various embodiments, the second IC chip 204 further includes a shallow trench isolation (STI) structure 702 disposed in the second substrate 203, a plurality of through substrate vias (TSVs) 704 extending from the second substrate 203 to the second interconnect structure 220, and a third bonding structure 710 disposed on the back side 203b of the second substrate 203. The STI structure 702 is disposed between pixel transistors 120, 122, 124 and one or more in-pixel transistors 242 and is configured to provide electrical isolation between adjacent devices. The through substrate vias 704 are configured to electrically couple the third bonding structure 710 to the second interconnect structure 220.

[0058] The third IC chip 602 includes a third substrate 706, a third interconnect structure 708 disposed on the front side 706f of the third substrate 706, a fourth bonding structure 712 disposed on the third interconnect structure 708, and a plurality of semiconductor devices 714 in and / or on the third substrate 706. In some embodiments, the third interconnect structure 708 includes a plurality of conductive wirings 210 and a plurality of conductive vias 212 disposed in the interconnect dielectric structure 208. The third interconnect structure 708 is configured to provide electrical coupling to and / or electrical coupling between the plurality of semiconductor devices 714. The third and fourth bonding structures 710 and 712 respectively include a plurality of conductive bonding contacts 216 and a plurality of conductive bonding pads 218 disposed in the bonding dielectric structure 214. The third bonding structure 710 of the second IC chip 204 is bonded to the fourth bonding structure 712 of the third IC chip 602, such that a second bonding interface is disposed between the second IC chip 204 and the third IC chip 602.

[0059] The third substrate 706 may be, for example, silicon, epitaxial silicon, SiGe, SOI substrate, or some other suitable substrate material. Multiple semiconductor devices 714 are disposed on the third substrate 706 and form an ASIC. In various embodiments, the semiconductor devices 714 are transistors and may include at least one n-type transistor and at least one p-type transistor. The semiconductor devices 714 may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), nanosheet field-effect transistors, some other suitable transistors, or any combination thereof. The semiconductor device 714 includes a gate dielectric structure 716 and a gate electrode 718.

[0060] Figures 8 to 21 Various cross-sectional views 800-2100 illustrate some embodiments of a method for forming an image sensor including a photodetector with low leakage current. Although the method description refers to... Figures 8 to 21 The cross-sectional views shown are 800-2100, but it will be understood that... Figures 8 to 21 The structure shown is not limited to this method, but can exist independently of it. Although... Figures 8 to 21 The description is a series of actions, but it will be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted entirely or in part.

[0061] like Figure 8 As shown in cross-sectional view 800, a first substrate 102 is provided, and a plurality of photodetectors 106 are formed in the first substrate 102. The first substrate 102 includes a first dopant having a first doping type (e.g., n-type). In some embodiments, the first doping type is n-type, and the first dopant may be or may include arsenic, antimony, phosphorus, some other suitable N-type dopant, or any combination thereof. In various embodiments, the doping concentration of the first substrate 102 is about 10. 14 Up to 10 16 atoms / cm 3 Within the range of or some other suitable values. The first substrate 102 may be, for example, or include silicon, epitaxial silicon, silicon germanium (SiGe), silicon-on-insulator (SOI) substrate, or some other suitable substrate material. The first substrate 102 has a front side 102f opposite to the back side 102b.

[0062] The photodetector 106 includes a collector region 108 and a pinned region 110. The collector region 108 and pinned region 110 are doped regions of the first substrate 102 and can be formed by an ion implantation process. The collector region 108 is formed by a first ion implantation process, which includes implanting a second dopant having a second doping type (e.g., p-type) into the first substrate 102. In some embodiments, the second doping type is p-type, and the second dopant may be or may include boron, indium, aluminum, gallium, some other suitable p-type dopant, or any combination thereof. The pinned region 110 is formed by a second ion implantation process, which includes implanting a first dopant (e.g., arsenic, antimony, phosphorus, etc.) into the first substrate 102 at a higher doping concentration than adjacent regions of the first substrate 102. The pinned region 110 and the body region of the first substrate 102 surround the collector region 108, such that the boundary of the collector region 108 is defined by a PN junction. In various embodiments, an annealing process is performed after the first ion implantation process and / or the second ion implantation process.

[0063] In some embodiments, the doping concentration of the collector region 108 is approximately 10. 16 Up to 10 18 atoms / cm 3 Within the range of or some other suitable values. In various embodiments, the doping concentration of the pinning region 110 is approximately 10. 17 Up to 10 19 atoms / cm 3 Within the range or some other suitable value. In a further embodiment, the doping concentration of the collector region 108 is greater than the doping concentration of the first substrate 102, and the doping concentration of the pinned region 110 is greater than the doping concentration of the collector region 108.

[0064] like Figure 9 As shown in the cross-sectional view 900, a patterning process is performed on a first substrate 102 to form a plurality of trenches 902 in the first substrate 102. In some embodiments, the patterning process includes: forming a shielding layer (not shown) on a front side 102f of the first substrate 102; performing an etching process (e.g., reactive ion etching, plasma etching, etc.) on the first substrate 102 according to the shielding layer; and performing a removal process to remove the shielding layer. The trenches 902 extend from the front side 102f to a point above the back side 102b and are disposed between adjacent photodetectors 106. After the patterning process, the sidewalls of the first substrate 102 defining the trenches 902 may contain defects (e.g., dangling bonds) due to the etching process.

[0065] like Figure 10As shown in the cross-sectional view 1000, a doped substrate region 112 is formed along a plurality of trenches 902 in a first substrate 102. In some embodiments, the doped substrate region 112 is formed by an ion implantation process, which includes implanting a first dopant (e.g., arsenic, antimony, phosphorus, etc.) into the first substrate 102 at a doping concentration higher than that of adjacent regions of the first substrate 102. In various embodiments, the doped substrate region 112 includes a first doping type (e.g., n-type) at a doping concentration of about 10. 17 Up to 10 19 atoms / cm 3 Within the range of or some other suitable values. In a further embodiment, the doping concentration of the doped liner region 112 is equal to the doping concentration of the pinned region 110 and / or greater than the doping concentration of the collector region 108. The doped liner region 112 extends laterally continuously from one or more corresponding sidewalls of the first substrate 102 defining the trench 902 to the sides of the collector region 108 and the pinned region 110.

[0066] like Figure 11 As shown in the cross-sectional view 1100, in the ditch ( Figure 10 In some embodiments, forming the isolation structure 114 includes forming an isolation structure 114 in a ditch (902). Figure 10 One or more isolation structure materials (e.g., silicon dioxide) are deposited (e.g., by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.) or grown (e.g., by thermal oxidation or similar processes) in the isolation structure 902, and a planarization process (e.g., chemical mechanical planarization (CMP) is performed on the one or more isolation structure materials. The top surface of the isolation structure 114 is coplanar with the front side 102f of the first substrate 102.

[0067] In various embodiments, the doped liner region 112 and the pinned region 110 may both be formed in the first substrate 102 after the isolation structure 114 is formed. In these embodiments, the doped liner region 112 and the pinned region 110 are formed simultaneously by an ion implantation process after the isolation structure 114 is disposed in the first substrate 102.

[0068] In some embodiments, the isolation structure 114 is formed by a thermal oxidation process, which includes multiple trenches ( Figure 9The isolation structure 114 is grown in (902). For example, a thermal oxidation process may include exposing the first substrate 102 to an oxidizing atmosphere at a temperature ranging from 800 to 1200 degrees Celsius, which may include oxygen and another gas (e.g., nitrogen or argon). Since the first substrate 102 contains an n-type dopant with a relatively high first segregation coefficient k1, the n-type dopant may accumulate along the interface between the first substrate 102 and the isolation structure 114. In various embodiments, the first segregation coefficient k1 is greater than the second segregation coefficient k2 of the p-type dopant in the collector region 108, making it less likely that the p-type dopant in the collector region 108 will diffuse to the interface between the first substrate 102 and the isolation structure 114. Therefore, leakage current in the image sensor is reduced.

[0069] In a further embodiment, the doped liner region 112 may be formed during the formation of the isolation structure 114. In these embodiments, the doped liner region 112 is formed when n-type dopant from the first substrate 102 accumulates around the interface between the isolation structure 114 and the first substrate 102 during a thermal oxidation process. In various embodiments, the relatively high first segregation factor k1 of the n-type dopant in the first substrate 102 results in the doped liner region 112 having a higher doping concentration than other regions of the first substrate 102 adjacent to the collector region 108. In a further embodiment, the concentration of n-type dopant in the doped liner region 112 decreases from the surface of the isolation structure 114 toward the direction away from the isolation structure 114. For example, the concentration of n-type dopant in the doped liner region 112 decreases exponentially from the first sidewall of the isolation structure 114 facing the collector region 108 toward the collector region 108.

[0070] like Figure 12 As shown in cross-sectional view 1200, a plurality of transport transistors 116 and floating diffusion nodes 118 are formed on and / or therein on a first substrate 102. The plurality of transport transistors 116 are formed on the front side 102f of the first substrate 102. Each transport transistor 116 includes a transport gate dielectric layer 132 on the first substrate 102, a transport gate electrode 130 on the transport gate dielectric layer 132, and sidewall spacers along the sidewalls of the transport gate electrode 130 and the transport gate dielectric layer 132. The floating diffusion nodes 118 are formed in the first substrate 102 by, for example, an ion implantation process or other suitable fabrication process. In some embodiments, the floating diffusion nodes 118 contain a second dopant (e.g., boron, indium, aluminum, gallium, etc.) and have a second doping type (e.g., p-type) with a doping concentration of about 10⁻⁶. 16 Up to 10 18 atoms / cm 3 Within the range or other suitable values. In various embodiments, the doping concentration of the floating diffusion node 118 is equal to the doping concentration of the collector region 108 and / or less than the doping concentration of the pinned region 110.

[0071] like Figure 13 As shown in cross-sectional view 1300, a first interconnect structure 205 is formed on the front side 102f of the first substrate 102. The first interconnect structure 205 includes a plurality of conductive wirings 210 and a plurality of conductive vias 212 disposed in an interconnect dielectric structure 208. The conductive wirings 210 and vias 212 are each grouped into a plurality of wiring layers and a plurality of via layers, which are stacked alternately. The layers of the first interconnect structure 205 may be formed, for example, by a single damascene process, a dual damascene process, other suitable fabrication processes, or similar methods.

[0072] like Figure 14 As shown in the cross-sectional view 1400, a first bonding structure 206 is formed on a first interconnect structure 205, thereby defining and / or forming a first integrated circuit chip 202. The first bonding structure 206 includes a plurality of conductive bonding contacts 216 and a plurality of conductive bonding pads 218 in a bonding dielectric structure 214. In some embodiments, the process for forming the first integrated circuit chip 202 includes... Figures 8 to 14 The processing steps described and / or explained in the document.

[0073] like Figure 15 As shown in cross-sectional view 1500, a second integrated circuit chip 204 is provided or otherwise formed. The second integrated circuit chip 204 includes a second substrate 203, a second interconnect structure 220 on a front side 203f of the second substrate 203, a second bonding structure 222 on the second interconnect structure 220, a plurality of pixel transistors 120, 122, 124, and one or more in-pixel transistors 242 in and / or on the second substrate 203. A shallow trench isolation (STI) structure 702 is formed in the second substrate 203. The plurality of pixel transistors 120, 122, 124 are formed on the front side 203f of the second substrate 203. One or more in-pixel transistors 242 are formed on the front side 203f of the second substrate 203. The second interconnect structure 220 is formed on the front side 203f of the second substrate. The second bonding structure 222 is formed on the second interconnect structure 220. In various embodiments, the second integrated circuit chip 204 is configured as follows: Figure 2A , 2B As shown and / or described in any of Figures 2C or 7. In a further embodiment, the second integrated circuit chip 204 includes in-pixel circuitry (…). Figure 6 (601).

[0074] like Figure 16 The cross-sectional view at 1600 is shown. Figure 14A first integrated circuit chip 202 is bonded to a second integrated circuit chip 204. A first bonding interface is disposed between a first bonding structure 206 and a second bonding structure 222. In some embodiments, bonding the first integrated circuit chip 202 to the second integrated circuit chip 204 includes conductor-to-conductor bonding and dielectric-to-dielectric bonding. In various embodiments, bonding the first integrated circuit chip 202 to the second integrated circuit chip 204 forms a plurality of pixels spanning the first and second integrated circuit chips 202, 204.

[0075] like Figure 17 As shown in cross-sectional view 1700, a plurality of silicon vias 704 are formed extending through the second substrate 203 to the second interconnect structure 220, and a third bonding structure 710 is formed on the back side 203b of the second substrate 203. The third bonding structure 710 includes a plurality of conductive bonding contacts 216 and a plurality of conductive bonding pads 218 in the bonding dielectric structure 214.

[0076] like Figure 18 As shown in cross-sectional view 1800, a third integrated circuit chip 602 is provided or otherwise formed. The third integrated circuit chip 602 includes a third substrate 706, a third interconnect structure 708 on a front side 706f of the third substrate 706, a fourth bonding structure 712 on the third interconnect structure 708, and a plurality of semiconductor devices 714 in and / or on the third substrate 706. The semiconductor devices 714 are formed on the front side 706f of the third substrate 706. The third interconnect structure 708 is formed on the front side 706f of the third substrate 706 and electrically coupled to the plurality of semiconductor devices 714. Furthermore, the fourth bonding structure 712 is formed on the third interconnect structure 708. In various embodiments, the third integrated circuit chip 602 is configured as follows: Figure 7 As shown and / or described. In a further embodiment, the third integrated circuit chip 602 includes an application-specific integrated circuit (ASIC) (as shown and / or described). Figure 6 (604).

[0077] like Figure 19 As shown in cross-sectional view 1900, a third integrated circuit chip 602 is bonded to a second integrated circuit chip 204. A second bonding interface is configured between a third bonding structure 710 and a fourth bonding structure 712. In some embodiments, bonding the third integrated circuit chip 602 to the second integrated circuit chip 204 includes conductor-to-conductor bonding and dielectric-to-dielectric bonding.

[0078] like Figure 20 As shown in the cross-sectional view 2000, a thinning process is performed on the first substrate 102. The thinning process reduces the thickness of the first substrate 102 from a first thickness 2002 to a second thickness 2004. The thinning process may include, for example, a CMP process, a mechanical polishing process, or other suitable processes.

[0079] like Figure 21 As shown in cross-sectional view 2100, a mesh structure 234, a plurality of filters 232, and a plurality of microlenses 236 are formed on the back side 102b of the first substrate 102. The mesh structure 234 is formed by depositing a mesh structure material on the first substrate 102 and patterning the mesh structure material to form a plurality of openings on the plurality of photodetectors 106. The filters 232 are formed by depositing and patterning individual color filter layers corresponding to the filters 232. The microlenses 236 are formed by depositing microlens material on the filters 232 and patterning the microlens material.

[0080] Figure 22 A flowchart 2200 illustrates some embodiments of a method for forming an image sensor including a photodetector with low leakage current. Although the method is shown and described below as a series of actions or events, it will be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown may be necessary to implement one or more aspects or embodiments described herein. Further, one or more of the actions illustrated herein may be performed in one or more separate actions and / or stages.

[0081] In action 2202, a plurality of photodetectors are formed in a first substrate of the first integrated circuit chip. Each photodetector includes a collector region. The first substrate includes a first doping type (e.g., n-type) and the collector region includes a second doping type (e.g., p-type) opposite to the first doping type. Figure 8 A cross-sectional view 800 is shown, corresponding to some embodiments of action 2202.

[0082] In action 2204, the front side of the first substrate is patterned to form multiple trenches in the first substrate between adjacent photodetectors. Figure 9 A cross-sectional view 900 is shown, corresponding to some embodiments of action 2204.

[0083] In action 2206, a doped liner region including a first doping type is formed in the first substrate and along the sidewall of the first substrate defining the trench. Figure 10 A cross-sectional view 1000 is shown, corresponding to some embodiments of action 2206.

[0084] In action 2208, isolation structures are formed in multiple ditches. Figure 11 A cross-sectional view 1100 is shown, corresponding to some embodiments of action 2208.

[0085] In action 2210, a plurality of transmission transistors are formed on the front side of the first substrate, and a floating diffusion node is formed in the first substrate. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of action 2210.

[0086] In action 2212, a first interconnect structure is formed on the front side of the first substrate, and a first bonding structure is formed on the first interconnect structure. Figure 13 and Figure 14 Cross-sectional views 1300 and 1400 are shown for some embodiments corresponding to action 2212.

[0087] In action 2214, a second integrated circuit chip is formed or otherwise provided. The second integrated circuit chip includes a second substrate, a plurality of pixel devices on the front side of the second substrate, a second interconnect structure on the front side of the second substrate, and a second bonding structure on the second interconnect structure. Figure 15 A cross-sectional view 1500 is shown, corresponding to some embodiments of action 2214.

[0088] In action 2216, the first integrated circuit chip and the second integrated circuit chip are joined at the first joint interface. Figure 16 A cross-sectional view 1600 is shown, corresponding to some embodiments of action 2216.

[0089] In action 2218, a plurality of through-silicon vias (TSVs) are formed extending through the second substrate to the second interconnect structure. Figure 17 A cross-sectional view 1700 is shown, corresponding to some embodiments of action 2218.

[0090] In action 2220, a third bonding structure is formed on the back side of the second substrate and electrically coupled to a silicon via. Figure 17 A cross-sectional view 1700 is shown, corresponding to some embodiments of action 2220.

[0091] In action 2222, a third integrated circuit chip is formed or otherwise provided. The third integrated circuit chip includes a third substrate, a plurality of semiconductor devices on the front side of the third substrate, a third interconnect structure on the front side of the third substrate, and a fourth bonding structure on the third interconnect structure. Figure 18 A cross-sectional view 1800 is shown, corresponding to some embodiments of action 2222.

[0092] In action 2224, the second integrated circuit chip and the third integrated circuit chip are joined at the second joint interface. Figure 19 A cross-sectional view 1900 is shown, corresponding to some embodiments of action 2224.

[0093] In action 2226, a plurality of filters and a plurality of microlenses are formed on the back side of the first substrate. Figure 21 A cross-sectional view 2100 is shown, corresponding to some embodiments of action 2226.

[0094] Therefore, in some embodiments, this invention relates to an image sensor including a substrate having a first doping type and a photodetector having a collector region having a second doping type in the substrate. An isolation structure is disposed in the substrate, and a doped substrate region having the first doping type extends from the isolation structure to the collector region. The first doping type is n-type and the second doping type is p-type.

[0095] In some embodiments, this invention relates to an image sensor. The image sensor includes a semiconductor substrate having opposing front and back sides; a photodetector disposed in the semiconductor substrate, including a collector region and a pinned region, the pinned region being disposed between the collector region and the front side of the semiconductor substrate, wherein the pinned region and the semiconductor substrate include a first doping type, and the collector region includes a second doping type opposite to the first doping type; and a doped liner region extending along opposing sidewalls of the isolation structure and including the first doping type, wherein the doped liner region extends from the sides of the collector region and the pinned region to the sidewalls of the isolation structure, wherein the first doping type is n-type and the second doping type is p-type.

[0096] In some embodiments, it further includes: a floating diffusion node located in the semiconductor substrate and adjacent to the photodetector, wherein the floating diffusion node includes the second doping type.

[0097] In some embodiments, the doping concentration of the pinned region is greater than the doping concentration of the collector region and the floating diffusion node, and the doping concentration of the doped substrate region is less than or equal to the doping concentration of the pinned region.

[0098] In some embodiments, the device further includes: a transmission transistor, comprising a transmission gate structure located on the front side of the semiconductor substrate and arranged between the photodetector and the floating diffusion node, wherein the transmission transistor is a p-type transistor.

[0099] In some embodiments, it further includes: a reset transistor including a first source / drain region coupled to the floating diffusion node and a second source / drain region coupled to a ground node, wherein the transfer transistor and the reset transistor are configured to selectively electrically couple the collector region to the ground node, wherein a body region of the semiconductor substrate surrounding the collector region is electrically coupled to a power supply voltage node.

[0100] In some embodiments, the transistor further includes: a source follower transistor including a gate structure coupled to the floating diffusion node and a first source / drain region coupled to the ground node; and a select transistor including a first source / drain region coupled to a second source / drain region of the source follower transistor, wherein the reset transistor, the source follower transistor, and the select transistor are each configured as p-type transistors.

[0101] In some embodiments, the photodetector and the transmission transistor are disposed on a first integrated circuit chip, wherein the reset transistor, the source follower transistor and the selection transistor are disposed on a second semiconductor substrate of a second integrated circuit chip, wherein the second integrated circuit chip is disposed on the first integrated circuit chip.

[0102] In some embodiments, the isolation structure and the doped liner region extend laterally from the front side of the semiconductor substrate to the back side of the semiconductor substrate.

[0103] In some embodiments, this invention relates to an image sensor. The image sensor includes a first integrated circuit (IC) chip comprising a first photodetector and a second photodetector disposed in a first substrate, wherein the first photodetector and the second photodetector respectively include a p-type collector region and an n-type pinned region; a first p-type floating diffusion node disposed in the first substrate and adjacent to the first photodetector; and an isolation structure disposed in the first substrate and enclosing the first photodetector and the second photodetector; a second integrated circuit chip located on and coupled to the first integrated circuit chip, wherein the second integrated circuit chip includes a plurality of first pixel devices located on a second substrate, wherein the plurality of first pixel devices include a reset transistor, a source follower transistor, and a select transistor, wherein the gate of the source follower transistor is coupled to the first p-type floating diffusion node; and a third integrated circuit chip located on and coupled to the second integrated circuit chip, wherein the third integrated circuit chip includes a plurality of semiconductor devices located on a third substrate and coupled to the second integrated circuit chip.

[0104] In some embodiments, each of the plurality of first pixel devices is configured as a p-type transistor.

[0105] In some embodiments, the second integrated circuit chip further includes in-pixel circuitry including one or more n-type transistors located on the second substrate, wherein the plurality of semiconductor devices are part of an application-specific integrated circuit electrically coupled to the in-pixel circuitry.

[0106] In some embodiments, the method further includes an n-type doped liner region along the sidewall of the isolation structure, wherein the n-type doped liner region is disposed between the isolation structure and the first photodetector and the second photodetector.

[0107] In some embodiments, the n-type pinning region includes a first dopant, and the n-type doped substrate region includes a second dopant that is different from the first dopant.

[0108] In some embodiments, the isolation structure continuously and laterally covers the outer periphery of the first photodetector and the outer periphery of the second photodetector, wherein a section of the isolation structure is disposed between the first photodetector and the second photodetector.

[0109] In some embodiments, it further includes: a second isolation structure located in the first substrate and covering the first p-type floating diffusion node.

[0110] In yet another embodiment, this disclosure relates to a method of forming an image sensor. The method includes forming a photodetector in a semiconductor substrate, wherein the semiconductor substrate includes a first doping type and opposing front and back sides, wherein the photodetector includes a collector region having a second doping type opposite to the first doping type; patterning the semiconductor substrate to form a plurality of trenches extending from the front side to a point below the front side; forming doped substrate regions along sidewalls of the semiconductor substrate defining the plurality of trenches, wherein the doped substrate regions include the first doping type having a different doping concentration than the semiconductor substrate; forming an isolation structure in the plurality of trenches, wherein the doped substrate regions are disposed along the sidewalls of the isolation structure; and forming a floating diffusion node in the semiconductor substrate, the floating diffusion node being laterally offset from the photodetector, wherein the floating diffusion node includes the second doping type, wherein the first doping type is n-type and the second doping type is p-type.

[0111] In some embodiments, the method further includes forming a transfer gate electrode on the front side of the semiconductor substrate and between the collector region and the floating diffusion node, wherein the transfer gate electrode comprises a plurality of gate electrode layers having a p-type work function.

[0112] In some embodiments, the photodetector includes a pinned region disposed between the collector region and the front side of the semiconductor substrate, wherein the pinned region includes the first doping type, and wherein the doped substrate region and the pinned region are formed simultaneously.

[0113] In some embodiments, the doping concentration of the pinned region and the doped substrate region is greater than the doping concentration of the collector region.

[0114] In some embodiments, the method further includes: forming a first interconnect structure on the semiconductor substrate and forming a first bonding structure on the first interconnect structure; forming a plurality of pixel devices on the front side of the second semiconductor substrate, wherein the plurality of pixel devices includes a source follower transistor, a reset transistor, and a select transistor, wherein the plurality of pixel devices are all configured as p-type transistors; forming a second interconnect structure on the second semiconductor substrate and forming a second bonding structure on the second interconnect structure; and bonding the first bonding structure to the second bonding structure, wherein the gate of the source follower transistor is electrically coupled to the floating diffusion node.

[0115] The features of the above embodiments are designed to facilitate understanding of this disclosure by those skilled in the art. Those skilled in the art should understand that this disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An image sensor, characterized in that... include: A semiconductor substrate, including a front side and a back side opposite to each other; A photodetector is disposed in the semiconductor substrate and includes a collector region and a pinned region, the pinned region being disposed between the collector region and the front side of the semiconductor substrate, wherein the pinned region and the semiconductor substrate include a first doping type, and the collector region includes a second doping type opposite to the first doping type; An isolation structure is located in the semiconductor substrate and adjacent to the photodetector; as well as A doped liner region extends along the opposite sidewalls of the isolation structure and includes the first doping type, wherein the doped liner region extends from the sides of the collector region and the pinning region to the sidewalls of the isolation structure, wherein the first doping type is n-type and the second doping type is p-type.

2. The image sensor according to claim 1, characterized in that... Also includes: A floating diffusion node is located in the semiconductor substrate and adjacent to the photodetector, wherein the floating diffusion node includes the second doping type.

3. The image sensor according to claim 2, characterized in that... The doping concentration of the pinned region is greater than that of the collector region and the floating diffusion node, wherein the doping concentration of the doped substrate region is less than or equal to that of the pinned region.

4. The image sensor according to claim 2, characterized in that... Also includes: A transmission transistor includes a transmission gate structure located on the front side of the semiconductor substrate and arranged between the photodetector and the floating diffusion node, wherein the transmission transistor is a p-type transistor.

5. The image sensor according to claim 4, characterized in that... Also includes: A reset transistor includes a first source / drain region coupled to the floating diffusion node and a second source / drain region coupled to a ground node, wherein the transfer transistor and the reset transistor are configured to selectively electrically couple the collector region to the ground node, wherein a body region of the semiconductor substrate surrounding the collector region is electrically coupled to a power supply voltage node.

6. The image sensor according to claim 5, characterized in that... Also includes: A source follower transistor includes a gate structure coupled to the floating diffusion node and a first source / drain region coupled to the ground node; and The selection transistor includes a first source / drain region coupled to a second source / drain region of the source follower transistor, wherein the reset transistor, the source follower transistor, and the selection transistor are each configured as p-type transistors.

7. The image sensor according to claim 6, characterized in that... The photodetector and the transmission transistor are disposed on a first integrated circuit chip, wherein the reset transistor, the source follower transistor and the selection transistor are disposed on a second semiconductor substrate of a second integrated circuit chip, wherein the second integrated circuit chip is disposed on the first integrated circuit chip.

8. The image sensor according to claim 1, characterized in that... The isolation structure and the doped liner region extend laterally from the front side of the semiconductor substrate to the back side of the semiconductor substrate.

9. An image sensor, characterized in that... include: The first integrated circuit chip includes: A first photodetector and a second photodetector are disposed in a first substrate, wherein the first photodetector and the second photodetector respectively include a p-type collector region and an n-type pinned region; A first p-type floating diffusion node is disposed in the first substrate and adjacent to the first photodetector; and An isolation structure is disposed in the first substrate and covers the first photodetector and the second photodetector; A second integrated circuit chip, located on and coupled to the first integrated circuit chip, wherein the second integrated circuit chip includes a plurality of first pixel devices located on a second substrate, wherein the plurality of first pixel devices includes a reset transistor, a source follower transistor, and a select transistor, wherein the gate of the source follower transistor is coupled to the first p-type floating diffusion node; and A third integrated circuit chip is located on and coupled to the second integrated circuit chip, wherein the third integrated circuit chip includes a plurality of semiconductor devices located on a third substrate and coupled to the second integrated circuit chip.

10. The image sensor according to claim 9, characterized in that... Each of the plurality of first pixel devices is configured as a p-type transistor.

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