Integrated wafer

Abstract

The utility model provides a kind of integrated wafer including first semiconductor substrate with front side and back side opposite to front side.Light detector is located in first semiconductor substrate.Back side deep trench isolation (DTI) structure includes conductive back side isolation layer and dielectric back side isolation layer, from back side to front side extends into first semiconductor substrate, and extends between light detector and adjacent light detector to isolate light detector and adjacent light detector.Dielectric back side isolation layer is located between conductive back side isolation layer and first semiconductor substrate.First interconnection structure includes first multiple conductive interconnections along the front side of first semiconductor substrate.Conductive front side DTI structure extends from first interconnection structure to conductive back side isolation layer, and couples conductive back side isolation layer to first interconnection structure.

Description

Technical Field

[0001] This utility model relates to an integrated chip. Background Technology

[0002] Many modern electronic devices include image sensors. Image sensors can be backside-illuminated sensors or frontside-illuminated sensors. Backside-illuminated sensors increase the amount of light captured by the sensor, while frontside-illuminated sensors offer better response uniformity. In many image sensors, deep trench isolation (DTI) structures are used to provide electrical and / or optical isolation between the pixels of the image sensor. Utility Model Content

[0003] This invention provides an integrated chip including a first semiconductor substrate having a front side and a back side opposite to the front side. A photodetector is located in the first semiconductor substrate. A back-side deep trench isolation structure includes a conductive back-side isolation layer and a dielectric back-side isolation layer, extending from the back side toward the front side into the first semiconductor substrate and extending between the photodetector and a neighboring photodetector to isolate the photodetector from the neighboring photodetector. The dielectric back-side isolation layer is located between the conductive back-side isolation layer and the first semiconductor substrate. A first interconnect structure includes a first plurality of conductive interconnects along the front side of the first semiconductor substrate. A conductive front-side deep trench isolation structure extends from the first interconnect structure to the conductive back-side isolation layer and couples the conductive back-side isolation layer to the first interconnect structure.

[0004] This invention provides an integrated chip including a first semiconductor substrate having a front side and a back side opposite to the front side. A photodetector is located in the first semiconductor substrate. A first dielectric structure includes a first plurality of dielectric layers along the front side of the first semiconductor substrate. A first interconnect structure includes a first plurality of conductive interconnects located in the first dielectric structure. A conductive front-side deep trench isolation structure is located in the first dielectric structure, on the first conductive interconnects of the first interconnect structure, and coupled to the first interconnect structure. The back-side deep trench isolation structure includes a conductive back-side isolation layer and a dielectric back-side isolation layer, extending from the back side toward the front side into the first semiconductor substrate. The dielectric back-side isolation layer is located between the conductive back-side isolation layer and the first semiconductor substrate. A first portion of the conductive back-side isolation layer extends between the photodetector and a neighboring photodetector to isolate the photodetector from the neighboring photodetector. A second portion of the conductive back-side isolation layer is laterally spaced from the photodetector and the neighboring photodetector. The second portion extends from the back side through the first semiconductor substrate to the conductive front-side deep trench isolation structure and is coupled to the conductive front-side deep trench isolation structure. Attached Figure Description

[0005] A thorough understanding of the various aspects of this invention will be best achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 The diagram shows a cross-sectional view of an integrated wafer according to several embodiments, including a front-side deep trench isolation (DTI) structure that couples interconnect structures to a back-side DTI structure.

[0007] Figure 2 Show Figure 1 Top view of some embodiments of the integrated chip.

[0008] Figures 3 to 7 Show Figure 1 Cross-sectional views of some other embodiments of the integrated chip.

[0009] Figures 8 to 10 Show Figures 1 to 7 Cross-sectional views of various embodiments of the back-side DTI structure and the front-side DTI structure in any of the figures.

[0010] Figure 11 and Figure 12 Show Figures 4 to 6 Cross-sectional views of some other embodiments of the integrated chip.

[0011] Figures 13-36 A cross-sectional view illustrating some embodiments of forming an integrated wafer including an interconnect structure coupled to a back-side DTI structure and a front-side DTI structure.

[0012] Figure 37 The flowchart illustrates a method for forming an integrated wafer that includes coupling interconnect structures to a back-side deep trench isolation structure and a front-side deep trench isolation structure, according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of this subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, the present invention may reuse reference numerals and / or letters in various instances. Such reuse is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0015] The integrated chip includes an image sensor. The image sensor includes a photodetector along a semiconductor substrate. Interconnect structures are configured on the front side of the semiconductor substrate. A back-side deep trench isolation (DTI) structure extends from the back side of the semiconductor substrate toward the front side and is located between the photodetectors to electrically and / or optically isolate the photodetectors from each other. In some integrated chips, the back-side DTI structure is formed by etching the semiconductor substrate from the back side to form a back-side trench in the semiconductor substrate and filling the back-side trench with a dielectric isolation layer. In some cases, etching the semiconductor substrate to form the back-side trench may create defects (e.g., point defects, dangling bonds, or the like) on the sidewalls of the semiconductor substrate defining the back-side trench. These defects may increase dark current in the photodetectors, potentially increasing noise and degrading the performance of the image sensor.

[0016] In various embodiments of this invention, the back-side DTI structure further includes a conductive isolation layer on the dielectric isolation layer within the back-side trench, and a conductive front-side DTI structure that couples the interconnect structure to the conductive isolation layer of the back-side DTI structure. By coupling the interconnect structure to the conductive isolation layer of the back-side DTI structure through the conductive front-side DTI structure, a bias voltage can be provided to the conductive isolation layer of the back-side DTI structure. Applying a bias voltage to the back-side DTI structure can reduce dark current caused by defects in the back-side trench. Therefore, the performance of the image sensor may be improved.

[0017] Figure 1 A cross-sectional view 100 of an integrated wafer is shown in some embodiments, including a front deep trench isolation (DTI) structure 132 that couples interconnect structure 124 to a back-side DTI structure 108. Figure 2 Show Figure 1 A top view 200 of an integrated chip in some embodiments. In some embodiments, Figure 1 The section line A-A' corresponds to Figure 2 The cross-section line A-A'.

[0018] Reference Figure 1 and Figure 2 The integrated chip includes a first semiconductor substrate 106. The active pixel region 102 of the integrated chip includes a plurality of photodetectors 104 (e.g., photodiodes or the like) distributed laterally along the first semiconductor substrate 106.

[0019] A back-side DTI structure 108 fills a back-side deep trench (not shown) in the first semiconductor substrate 106. The back-side DTI structure 108 extends in a grid-like arrangement along the back side 106b of the first semiconductor substrate 106 between the photodetectors 104 to electrically and / or optically isolate the photodetectors 104 from each other. The back-side DTI structure 108 includes a dielectric back-side isolation layer 110 and a conductive back-side isolation layer 112. The conductive back-side isolation layer 112 is located above and between the sidewalls of the dielectric back-side isolation layer 110. The dielectric back-side isolation layer 110 separates the conductive back-side isolation layer 112 from the first semiconductor substrate 106. The back-side DTI structure 108 is located in the active pixel region 102 of the integrated wafer and extends along the boundary between the active pixel region 102 and the dummy pixel region 114 of the integrated wafer.

[0020] A first dielectric structure 116 is located above a first semiconductor substrate 106 and extends along the back side 106b of the first semiconductor substrate 106. The first dielectric structure 116 includes one or more dielectric layers. A color filter 118 is located above the first dielectric structure 116 in the active pixel region 102. In some embodiments, the color filter 118 is also located above the first dielectric structure 116 in a dummy pixel region 114. A microlens 119 is located above the color filter 118 in the active pixel region 102.

[0021] The second dielectric structure 120 is located below the first semiconductor substrate 106 and extends along the front side 106a of the first semiconductor substrate 106. The second dielectric structure 120 includes multiple dielectric layers. A gate electrode 122 (e.g., a transfer gate electrode, a reset gate electrode, a source follower gate electrode, a row select gate electrode, or the like) is located directly below the photodetector 104 and within the second dielectric structure 120 (e.g., between sidewalls). The interconnect structure 124 includes multiple contacts 126, multiple conductive lines 128, and multiple conductive vias 130 located within the second dielectric structure 120.

[0022] In some embodiments, defects may exist on the sidewalls of the first semiconductor substrate 106 at the junction of the first semiconductor substrate 106 and the dielectric back-side isolation layer 110 of the back-side DTI structure 108. These defects may increase dark current in the photodetector 104. However, applying a bias voltage to the back-side DTI structure 108 can reduce dark current, thereby improving the performance of the image sensor. For example, applying a negative bias voltage to the conductive back-side isolation layer 112 can attract holes (e.g., positive charge carriers) to the back-side DTI structure 108. These holes can combine with stray electrons from back-side trench defects, preventing stray electrons from reaching the photodetector and generating dark current. Therefore, in various embodiments of the present invention, the front-side DTI structure 132 couples the conductive back-side isolation layer 112 to the interconnect structure 124, allowing a bias voltage to be provided to the back-side DTI structure 108 through the front-side DTI structure 132 to improve the performance of the image sensor.

[0023] The front-side DTI structure 132 includes a conductor (e.g., a conductive front-side isolation layer). The front-side DTI structure 132 is located in the dummy pixel region 114 and directly below a portion 109 of the back-side DTI structure 108 within the dummy pixel region 114. A portion 109 of the back-side DTI structure 108 extends from the back side 106b through the first semiconductor substrate 106 to the front side 106a. A portion 109 of the dielectric back-side isolation layer 110 extends from the back side 106b to the front side 106a (e.g., extending to the top of the second dielectric structure 120). A portion 109 of the conductive back-side isolation layer 112 passes through the front side 106a and extends into the second dielectric structure 120. The front-side DTI structure 132 extends from a conductive interconnect (e.g., a conductive line 128) of the interconnect structure 124 through the second dielectric structure 120 to a portion 109 of the conductive back-side isolation layer 112. Since the front-side DTI structure 132 is configured outside the active pixel region 102 (e.g., in the dummy pixel region 114), the impact of the front-side DTI structure 132 on the image sensor performance is reduced.

[0024] In some embodiments, the bias circuit 134 is coupled to the conductive back-side isolation layer 112 of the back-side DTI structure 108 via the interconnect structure 124 and the front-side DTI structure 132. The bias circuit 134 provides a bias (e.g., voltage) to the conductive back-side isolation layer 112 of the back-side DTI structure 108 via the interconnect structure 124 and the front-side DTI structure 132.

[0025] In some embodiments, the integrated wafer further includes a second front-side DTI structure 202 and a third front-side DTI structure 204, which are spaced apart from the front-side DTI structure 132. The front-side DTI structures 202 and 204 extend from the interconnect structure 124 to the back-side DTI structure 108 in the dummy pixel region 114, and further couple the interconnect structure 124 to the conductive back-side isolation layer 112. In some embodiments, the second front-side DTI structure 202 and the third front-side DTI structure 204 comprise the same conductive material as the front-side DTI structure 132. For example, a conductive front-side isolation layer (not shown) forms the front-side DTI structures 132, 202, and 204. The front-side DTI structures 132, 204, and 204 are in... Figure 2 They are shown as “dashed parts” (e.g., dashed lines) so that their relationship to the back-side DTI structure 108 in top view 200 can be seen. In some embodiments, the front-side DTI structures 132, 202, 204 may be referred to as DTI contacts.

[0026] In some embodiments, a portion (not shown) of the back-side DTI structure 108 located in the active pixel region 102 extends into the first semiconductor substrate 106 but does not pass through the first semiconductor substrate 106. For example, in the active pixel region 102, the first semiconductor substrate 106 extends directly below the back-side DTI structure 108.

[0027] In some embodiments, the first semiconductor substrate 106 comprises silicon or some other suitable semiconductor. In some embodiments, the dielectric back-side isolation layer 110 comprises hafnium oxide, zirconium dioxide, aluminum oxide, silicon oxide, or some other suitable material. In some embodiments, the conductive back-side isolation layer 112 comprises tungsten, aluminum, titanium, copper, or some other suitable material. In some embodiments, the dielectric layer of the first dielectric structure 116 and / or the dielectric layer of the second dielectric structure 120 comprises silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or some other suitable material. In some embodiments, the front-side DTI structure 132 comprises tungsten, aluminum, titanium, or some other suitable material. In some embodiments, the gate electrode 122 comprises polysilicon, tungsten, titanium, tantalum, or some other suitable material. In some embodiments, the contacts 126, conductive lines 128, and conductive vias 130 of the interconnect structure 124 comprise copper, aluminum, tungsten, titanium, ruthenium, or some other suitable material.

[0028] Figure 3 Show Figure 1 A cross-sectional view 300 of some embodiments of the integrated chip, wherein a portion (not shown) of the back-side DTI structure 108 located in the active pixel region 102 extends through the first semiconductor substrate 106 to the second dielectric structure 120. In some embodiments, Figure 3 The section line A-A' corresponds to Figure 2 The cross-section line A-A'.

[0029] In the active pixel region 102, a dielectric back-side isolation layer 110 extends from the back side 106b to the front side 106a and the second dielectric structure 120. Furthermore, in the active pixel region 102, a conductive back-side isolation layer 112 extends from the back side 106b through the front side 106a and into the second dielectric structure 120. In some embodiments, the conductive back-side isolation layer 112 in the active pixel region 102 extends to the same depth below the back side 106b of the first semiconductor substrate 106 as the conductive back-side isolation layer 112 in the dummy pixel region 114 (which lands on the front DTI structure 132).

[0030] Figure 4 Show Figure 1 Cross-sectional view 400 of some embodiments of the integrated chip and Figure 5 Show Figure 1A cross-sectional view 500 of some embodiments of the integrated wafer, which also includes a front shallow trench isolation (STI) structure 402 located below the back-side DTI structure 108 and a conductive grid 404 located above the back-side DTI structure 108. In some embodiments, Figure 4 The section line A-A' corresponds to Figure 2 The cross-section line A-A'. In some embodiments, Figure 5 The profile line B-B' corresponds to Figure 2 The cross-section line B-B'.

[0031] Figure 6 Show Figure 3 Cross-sectional view 600 of some embodiments of the integrated chip, Figure 7 Show Figure 3 A cross-sectional view 700 of some embodiments of the integrated chip, which also includes a front-side STI structure 402 located below the back-side DTI structure 108 and a conductive grid 404 located above the back-side DTI structure 108. In some embodiments, Figure 6 The section line A-A' corresponds to Figure 2 The cross-section line A-A'. In some embodiments, Figure 7 The profile line B-B' corresponds to Figure 2 The cross-section line B-B'.

[0032] Reference Figures 4 to 7 The front-side STI structure 402 is located in a front-side shallow trench (not shown) of the first semiconductor substrate 106, which extends from the front side 106a toward the back side 106b into the first semiconductor substrate 106. The front-side STI structure 402 is located directly below the back-side DTI structure 108 and extends in a grid-like arrangement along the front side 106a of the first semiconductor substrate 106 between the photodetectors 104. The front-side STI structure 402 includes one or more dielectric layers (e.g., dielectric front isolation layers). In some embodiments, the front-side STI structure 402 is part of the dielectric structure 120. In some embodiments, the front-side STI structure 402 includes silicon dioxide, silicon nitride, or other suitable materials.

[0033] The front-side DTI structure 132 extends from below the front-side STI structure 402 into the front-side STI structure 402, until it reaches below the top of the front-side STI structure 402. The top surface (not shown) of the front-side DTI structure 132 is located above the front side 106a of the first semiconductor substrate 106 and is directly spaced from the lower surface (not shown) of the front-side STI structure 402 of the first semiconductor substrate 106. The back-side DTI structure 108 (e.g., a portion 109 of the back-side DTI structure 108) extends into the front-side DTI structure 132 and is located directly above the front-side STI structure 402.

[0034] Conductive grids 404 are spaced above the first semiconductor substrate 106 and within the first dielectric structure 116. Conductive grids 404 are simultaneously located in the active pixel region 102 and the dummy pixel region 114 of the integrated wafer. Conductive grids 404 are directly above the back-side DTI structure 108 and have a grid-like layout. In some embodiments, conductive grids 404 comprise tungsten, titanium nitride, or other suitable materials.

[0035] In some embodiments (such as) Figure 4 and Figure 5 As shown), in the active pixel region 102, the back-side DTI structure 108 is spaced above the front-side STI structure 402, and the first semiconductor substrate 106 is located therebetween. In some other embodiments (e.g., as shown) Figure 6 and Figure 7 As shown), in the active pixel region 102, the back-side DTI structure 108 extends through the first semiconductor substrate 106 into the front-side STI structure 402.

[0036] Figures 8 to 10 Show Figures 1 to 7 Cross-sectional views 800 to 1000 of various embodiments of the rear-side DTI structure 108 and the front-side DTI structure 132 in any of the figures.

[0037] In some embodiments (e.g., such as) Figure 8 As shown), the front DTI structure 132 and the back DTI structure 108 have lateral offsets. For example, the back DTI structure 108 extends along the top surface 132a of the front DTI structure 132 and extends below the top surface 132a along the outer side wall 132b of the front DTI structure 132.

[0038] In some embodiments (e.g., such as) Figure 9 As shown), the dorsal DTI structure 108 extends into the front DTI structure 132. For example, the dorsal DTI structure 108 is located between a pair of inner sidewalls 132c of the front DTI structure 132 and on the upper surface 132d of the front DTI structure 132, which is located below the top surface 132a of the front DTI structure 132.

[0039] In some embodiments (e.g., such as) Figure 10 As shown), the dorsal DTI structure 108 extends into the front DTI structure 132, and the front DTI structure 132 and the dorsal DTI structure 108 are laterally offset. For example, the dorsal DTI structure 108 is located on the upper surface 132e of the front DTI structure 132, which is located below the top surface 132a of the front DTI structure 132, and the dorsal DTI structure 108 extends along the inner sidewall 132f and the outer sidewall 132g of the front DTI structure 132.

[0040] In some embodiments (e.g., such as) Figure 8 As shown, the front DTI structure 132 includes a first conductive front insulating layer 802 and a second conductive front insulating layer 804. The first conductive front insulating layer 802 is lining a front deep trench (not shown) and contacts a conductive back insulating layer 112. The second conductive front insulating layer 804 is located on the first conductive front insulating layer 802 and fills the front deep trench. In some such embodiments, the first conductive front insulating layer 802 includes a first conductor, and the second conductive front insulating layer 804 includes a second conductor different from the first conductor.

[0041] Figure 11 Show Figure 4 A cross-sectional view 1100 of some embodiments of the integrated chip, which also includes a black level correction region 1102 located next to the dummy pixel region 114, and a pad region 1104 located next to the black level correction region 1102.

[0042] A back-side ground electrode 1106 is located in the black level correction region 1102. The back-side ground electrode 1106 is laterally spaced from and coupled to the conductive grid 404. The back-side ground electrode 1106 is located within the first dielectric structure 116 and extends into the first semiconductor substrate 106. The back-side ground electrode 1106 contacts the first semiconductor substrate 106 and couples the conductive grid 404 to the first semiconductor substrate 106. In some embodiments, the back-side ground electrode 1106 comprises tungsten, titanium nitride, or other suitable materials.

[0043] Pad trenches (not shown) and conductive pads 1108 are located in pad regions 1104 of the integrated wafer. The pad trenches are defined by the sidewalls of a first dielectric structure 116, the sidewalls of a first semiconductor substrate 106, and the sidewalls of a second dielectric structure 120. Conductive pads 1108 are located at the bottom of the pad trenches. In some embodiments, conductive pads 1108 comprise tungsten, aluminum, titanium, titanium nitride, copper, or other suitable materials. A dielectric layer 1110 is lining the pad trenches. Conductive pads 1108 are located on and extend through the dielectric layer 1110 to interconnect structures 124 (e.g., conductive lines 128 of interconnect structures 124). In some embodiments, the dielectric layer 1110 comprises silicon oxide, silicon nitride, some high-k dielectric material, or other suitable materials.

[0044] A first semiconductor substrate 106, a photodetector 104, a first dielectric structure 116, a conductive grid 404, a color filter 118, a microlens 119, a back-side ground electrode 1106, a second dielectric structure 120, an interconnect structure 124, and conductive pads 1108 are located on a first wafer 1112. A second wafer 1114 is bonded below the first wafer 1112. The second wafer includes a second semiconductor substrate 1116, a dielectric structure 1118 (including multiple dielectric layers) located on the second semiconductor substrate 1116, and an interconnect structure 1120 (including contacts 126, conductive lines 128, and conductive vias 130 and the like) located within the dielectric structure 1118. Interconnect structures 124 and 1120 include bonding pads 1124. The first wafer 1112 and the second wafer 1114 are bonded along the bonding pads 1124 and the dielectric structures 120 and 1118.

[0045] Transistor 1122 is disposed along second semiconductor substrate 1116. In some embodiments, transistor 1122 is part of bias circuit 134. Transistor 1122 is coupled to interconnect structure 124 via interconnect structure 1120. For example, transistor 1122 of bias circuit 134 is coupled to front-side DTI structure 132 via interconnect structure 1120 and interconnect structure 124. In some embodiments, transistor 1122 includes metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), fin field-effect transistors (FinFETs), gate all-around field-effect transistors (GAAFETs), or other suitable devices.

[0046] In some integrated chips, the back-side DTI structure 108 is coupled to the conductive pad 1108 via a conductive grid 404 and a back-side ground electrode 1106, and a bias voltage is provided to the back-side DTI structure 108 via the conductive pad 1108, the back-side ground electrode 1106, and the conductive grid 404. However, this wiring can increase complexity, limit the flexibility of integrated chip design, and potentially increase the cost of the integrated chip. By coupling the back-side DTI structure 108 to the interconnect structure 124 via a front-side DTI structure 132, as shown in various embodiments of the present invention, the wiring can be simplified. Furthermore, by coupling the back-side DTI structure 108 to the interconnect structure 124 via the front-side DTI structure 132, the back-side DTI structure 108 and the conductive grid 404 can have separate bias voltages, which can increase the flexibility of integrated chip design. Therefore, the performance of the integrated chip can be improved, and the cost of the integrated chip can be reduced.

[0047] Figure 12 Show Figure 11 A cross-sectional view 1200 of some embodiments of the integrated chip.

[0048] In some embodiments, the second dielectric structure 120 includes a gate dielectric layer 1202, a dielectric layer 1204, a dielectric layer 1206, and one or more dielectric layers 1208. The gate dielectric layer 1202 is located below the first semiconductor substrate 106 and extends along the front side 106a of the first semiconductor substrate 106 between the gate electrode 122 and the front side 106a. The dielectric layer 1204 is located below the gate dielectric layer 1202. The gate electrode 122 is located between the sidewalls of the dielectric layer 1204. The dielectric layer 1206 is located below the dielectric layer 1204. A contact 126 extends through the dielectric layer 1206 to the gate electrode 122. A front-side DTI structure 132 extends through the dielectric layer 1206, the dielectric layer 1204, and the gate dielectric layer 1202 into the front-side STI structure 402. One or more dielectric layers 1208 are located beneath dielectric layer 1206, and conductive interconnects (e.g., conductive lines 128, conductive vias 130, bonding pads 1124, and the like) are located within one or more dielectric layers 1208. In some embodiments, dielectric layers 1202, 1204, 1206, and 1208 comprise silicon oxide, silicon nitride, silicon carbide, aluminum oxide, some high-k dielectric material, or other suitable materials.

[0049] In some embodiments, the dielectric structure 116 includes a dielectric layer 1218 on the back side 106b of the first semiconductor substrate 106 and a dielectric layer 1220 on the dielectric layer 1218. In some embodiments, a conductive grid 404 is located on the dielectric layer 1218 and between the sidewalls of the dielectric layer 1220. In some embodiments, the dielectric layer 1218 and the dielectric layer 1220 include silicon oxide, silicon nitride, some high-k dielectric material, or other suitable materials.

[0050] In some embodiments, the conductive grid 404 includes a first conductive layer 1210 and a second conductive layer 1212 located on the first conductive layer 1210. Furthermore, the back-side ground electrode 1106 includes the first conductive layer 1210 and the second conductive layer 1212 located on the first conductive layer 1210. In some embodiments, the conductive layer 1210 includes titanium nitride or other suitable materials, and the conductive layer 1212 includes tungsten or other suitable materials.

[0051] In some embodiments, the conductive pad 1108 includes a first conductive pad layer 1214 and a second conductive pad layer 1216 located on the first conductive pad layer 1214. In some embodiments, the conductive pad layer 1214 and / or the conductive pad layer 1216 include tungsten, aluminum, titanium, titanium nitride, copper, or other suitable materials.

[0052] Figures 13 to 36 The illustrated embodiments include cross-sectional views 1300 to 3600 showing a method of coupling interconnect structure 124 to front-side DTI structure 132 of an integrated wafer with a back-side DTI structure 108. Although Figures 13 to 36 It is about describing a method, but it should be understood that... Figures 13 to 36 The structures revealed are not limited to this method, but can exist as independent structures independent of this method.

[0053] like Figure 13 As shown in the cross-sectional view 1300, a photodetector 104 (e.g., a photodiode) is formed along a first semiconductor substrate 106 in the active pixel region 102 of the integrated wafer. Furthermore, the first semiconductor substrate 106 is etched from the front side 106a toward the back side 106b to form a front shallow trench (not shown) in the first semiconductor substrate 106, and dielectric material is deposited in the front shallow trench to form a front STI structure 402. Additionally, a dielectric structure 120 (e.g., including a gate dielectric layer 1202, a dielectric layer 1204, and a dielectric layer 1206) and a gate electrode 122 are formed on the front side 106a of the first semiconductor substrate 106. In some embodiments, the front STI structure 402 is considered part of the dielectric structure 120.

[0054] like Figure 14As shown in the cross-sectional view 1400, a dielectric structure 120 (e.g., dielectric layer 1206) is etched to form a contact opening 1402 in the dielectric structure 120, which exposes a portion of the gate electrode 122. In some embodiments, a masking layer 1404 is formed on the dielectric structure 120, and etching is performed according to the masking layer 1404. In some embodiments, etching includes a dry etching process (e.g., plasma etching, reactive ion etching, ion beam etching, or the like) or other suitable processes.

[0055] like Figure 15 As shown in the cross-sectional view 1500, dielectric structure 120 (e.g., dielectric layer 1206, dielectric layer 1204, and gate dielectric layer 1202) and front-side STI structure 402 are etched to form a front-side deep trench 1502 in the dielectric structure 120 and the front-side STI structure 402 in the dummy pixel region 114 of the integrated wafer. In some embodiments, a mask layer 1504 is formed on the dielectric structure 120, and etching is performed according to the mask layer 1504. In some embodiments, etching includes a dry etching process or other suitable process. In some embodiments, additional front-side deep trenches (not shown) are formed in the dielectric structure 120 and the front-side STI structure 402, and are laterally spaced from the front-side deep trench 1502.

[0056] like Figure 16 As shown in the cross-sectional view 1600, a contact 126 is formed in a contact opening 1402, and a front-side DTI structure 132 is formed in a front-side deep trench 1502. In some embodiments, the contact 126 and the front-side DTI structure 132 are formed by depositing a conductive layer (not shown) in the contact opening 1402 and the front-side deep trench 1502, and performing a planarization process on the conductive layer to remove the conductive layer on the dielectric structure 120, and further defining the contact 126 and the front-side DTI structure 132. In some embodiments, the conductive layer (not shown) includes tungsten, aluminum, titanium, or other suitable materials, and is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable processes. In some embodiments, the planarization process includes a chemical mechanical planarization (CMP) process, a blanket etch back process, or other suitable processes.

[0057] like Figure 17 As shown in cross-sectional view 1700, dielectric layer 1208 and conductive interconnects (e.g., conductive lines 128, conductive vias 130, bonding pads 1124, and the like) are formed on dielectric layer 1206. Furthermore, second wafer 1114 and first wafer 1112 are bonded together along bonding pads 1124 and dielectric structures 120, 1118. In some embodiments, bonding includes thermal bonding, fusion bonding, or other suitable processes.

[0058] Figures 18 to 22 Cross-sectional views 1800 to 2200 illustrate a method of forming a back-side DTI structure 108 in a first semiconductor substrate 106 and coupling it to a front-side DTI structure 132, according to some embodiments.

[0059] like Figure 18 As shown in cross-sectional view 1800, a first semiconductor substrate 106 is etched from the back side 106b toward the front side 106a in the active pixel region 102 and the dummy pixel region 114 using a first etching process to form a back side trench 1802 in the first semiconductor substrate 106. The first etching process extends the back side trench 1802 to a depth below the back side 106b that is separated from the front side 106a and the front STI structure 402 in both the active pixel region 102 and the dummy pixel region 114 (e.g., into the first semiconductor substrate 106 but not through it). In some embodiments, a mask layer 1804 is formed on the back side 106b, and etching is performed according to the mask layer 1804. In some embodiments, etching includes a dry etching process or other suitable processes.

[0060] like Figure 19 As shown in cross-sectional view 1900, a first semiconductor substrate 106 is etched in a dummy pixel region 114 from a back side 106b toward a front side 106a using a second etching process to extend a back side trench 1802 through the first semiconductor substrate 106 to a front side DTI structure 132 in the dummy pixel region 114. In some embodiments, a mask layer 1902 is formed on the back side 106b and in a portion of the back side trench 1802 in the active pixel region 102, and etching is performed according to the mask layer 1902. In some embodiments, etching includes a dry etching process or other suitable processes.

[0061] like Figure 20 As shown in the cross-sectional view 2000, a dielectric back-side isolation layer 110 is deposited along the back side 106b and lining the back-side trench 1802 (e.g., on the sidewalls and upper surface of the first semiconductor substrate 106 defining the back-side trench 1802). In some embodiments, the dielectric back-side isolation layer 110 comprises hafnium oxide, zirconium dioxide, aluminum oxide, silicon oxide, or other suitable materials and is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0062] like Figure 21As shown in the cross-sectional view 2100, the dielectric back-side isolation layer 110 and the front-side STI structure 402 are etched in the dummy pixel region 114 using a third etch process to extend the back-side trench 1802 through the dielectric back-side isolation layer 110 and the front-side STI structure 402 to the front-side DTI structure 132, thereby exposing the front-side DTI structure 132. In some embodiments, a mask layer 2102 is formed on the back side 106b and in portions of the back-side trench 1802 in the active pixel region 102, and etching is performed according to the mask layer 2102. In some embodiments, the etching includes a dry etching process or other suitable processes.

[0063] like Figure 22 As shown in cross-sectional view 2200, a conductive back-side isolation layer 112 is deposited on a dielectric back-side isolation layer 110 and a front-side DTI structure 132 in a back-side trench 1802. The conductive back-side isolation layer 112 fills the back-side trench 1802. Furthermore, a planarization process is performed on the conductive back-side isolation layer 112 and the dielectric back-side isolation layer 110 to remove the conductive back-side isolation layer 112 and the dielectric back-side isolation layer 110 on the back side 106b of the first semiconductor substrate 106. The dielectric back-side isolation layer 110 and the conductive back-side isolation layer 112 together form the back-side DTI structure 108. In some embodiments, the conductive back-side isolation layer 112 comprises tungsten, aluminum, titanium, or other suitable materials and is deposited by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable processes. In some embodiments, the planarization process includes a chemical mechanical polishing process, a blanket etch-back process, or other suitable processes.

[0064] Figures 23 to 26 Cross-sectional views 2300 to 2600 show some other embodiments of a method for forming a back-side DTI structure 108 in a first semiconductor substrate 106 and coupling it to a front-side DTI structure 132.

[0065] like Figure 23 As shown in cross-sectional view 2300, a first semiconductor substrate 106 is etched from the back side 106b toward the front side 106a in the active pixel region 102 and the dummy pixel region 114 using a first etching process to form a back-side trench 2302 in the first semiconductor substrate 106. The first etching process extends the back-side trench 2302 through the first semiconductor substrate 106 to the front-side STI structure 402 in the active pixel region 102 and the dummy pixel region 114. In some embodiments, a mask layer 2304 is formed on the back side 106b, and etching is performed according to the mask layer 2304. In some embodiments, etching includes a dry etching process or other suitable processes.

[0066] like Figure 24As shown in the cross-sectional view 2400, a dielectric back-side isolation layer 110 is deposited on the back side 106b and lining the back-side trench 2302 (e.g., on the sidewall of the first semiconductor substrate 106 defining the back-side trench 2302, and on the upper surface of the front-side STI structure 402 defining the back-side trench 2302).

[0067] like Figure 25 As shown in cross-sectional view 2500, the dielectric back-side isolation layer 110 and the front-side STI structure 402 are etched in the active pixel region 102 and the dummy pixel region 114 using a second etching process to extend the back-side trench 2302 through the dielectric back-side isolation layer 110 and into the front-side STI structure 402, reaching the front-side DTI structure 132 in the active pixel region 102 and the dummy pixel region 114. The etching exposes the front-side DTI structure 132 in the dummy pixel region 114. In some embodiments, the etching removes the dielectric back-side isolation layer 110 on the back side 106b of the first semiconductor substrate 106. In some embodiments, the etching includes a dry etching process or other suitable processes. In some embodiments, the etching is a blanket etching process performed without a mask layer.

[0068] like Figure 26 As shown in cross-sectional view 2600, a conductive back-side isolation layer 112 is deposited in the back-side trench 2302, on the dielectric back-side isolation layer 110, on the front-side STI structure 402, and on the front-side DTI structure 132. The conductive back-side isolation layer 112 fills the back-side trench 2302. Furthermore, a planarization process is performed on the conductive back-side isolation layer 112 to remove the conductive back-side isolation layer 112 on the back side 106b of the first semiconductor substrate 106. The dielectric back-side isolation layer 110 and the conductive back-side isolation layer 112 together form the back-side DTI structure 108.

[0069] Figures 27 to 36 Cross-sectional views 2700 to 3600 illustrate the remaining aspects of methods for forming an integrated wafer according to some embodiments. Although in Figures 27 to 36 In the diagram, the back-side DTI structure 108 is shown extending through the first semiconductor substrate 106 into the front-side STI structure 402 within the active pixel region 102. However, it is understood that the back-side DTI structure 108 may alternatively extend into the first semiconductor substrate 106 but not through it (e.g., as shown in...). Figure 22 and Figure 11 (As shown).

[0070] like Figure 27As shown in cross-sectional view 2700, dielectric layer 1218 is deposited on the back side 106b of the first semiconductor substrate 106 and on the back side DTI structure 108. In some embodiments, dielectric layer 1218 comprises silicon oxide, silicon nitride or other suitable materials and is deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable processes.

[0071] like Figure 28 As shown in cross-sectional view 2800, the dielectric layer 1218 and the first semiconductor substrate 106 are etched to form a ground trench 2802 in the dielectric layer 1218 and the first semiconductor substrate 106. In some embodiments, a masking layer 2804 is formed on the dielectric layer 1218, and etching is performed according to the masking layer 2804. In some embodiments, etching includes a dry etching process or other suitable processes.

[0072] like Figure 29 As shown in cross-sectional view 2900, a conductive layer 1210 is deposited on a dielectric layer 1218 and lining a ground trench 2802 (e.g., on the sidewalls and top surface of the first semiconductor substrate 106, and on the sidewalls of the dielectric layer 1218). Furthermore, a conductive layer 1212 is deposited on the conductive layer 1210 and fills the ground trench 2802. In some embodiments, the conductive layer 1210 comprises titanium nitride or other suitable materials and is deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. In some embodiments, the conductive layer 1212 comprises tungsten or other suitable materials and is deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0073] like Figure 30 As shown in the cross-sectional view 3000, conductive layers 1212 and 1210 are etched to form (e.g., define) a conductive grid 404 and a back-side ground electrode 1106 from conductive layers 1212 and 1210. In some embodiments, a masking layer 3002 is formed on conductive layer 1212, and etching is performed based on masking layer 3002. In some embodiments, etching includes a dry etching process or other suitable processes.

[0074] like Figure 31 As shown in cross-sectional view 3100, dielectric layer 1220 is deposited on conductive grid 404, back-side ground electrode 1106, and dielectric layer 1218. In some embodiments, dielectric layer 1220 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0075] like Figure 32As shown in the cross-sectional view 3200, dielectric structures 116 (e.g., dielectric layers 1220, 1218), the first semiconductor substrate 106, the front STI structure 402, and dielectric structures 120 (e.g., dielectric layers 1202, 1204, 1206) are etched to form pad trenches 3202 that pass through dielectric structures 116, through the first semiconductor substrate 106, and extend into dielectric structures 120. In some embodiments, a masking layer 3204 is formed on dielectric layer 1220, and etching is performed based on masking layer 3204. In some embodiments, etching includes a dry etching process or other suitable processes.

[0076] like Figure 33 As shown in cross-sectional view 3300, a dielectric layer 1110 is deposited along and lining the pad trench 3202 (e.g., on the sidewalls of the dielectric structure 116 defining the pad trench 3202, the sidewalls of the first semiconductor substrate 106, and the sidewalls of the dielectric structure 120). In some embodiments, the dielectric layer 1110 comprises silicon oxide, silicon nitride, some high dielectric constant dielectric material, or other suitable material, and is deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0077] like Figure 34 As shown in cross-sectional view 3400, dielectric layer 1110 and dielectric structure 120 are etched to form pad contact openings 3402 in dielectric layer 1110 and dielectric structure 120, which expose conductive lines 128 of a portion of interconnect structure 124. In some embodiments, a masking layer 3404 is formed on dielectric layer 1220 and dielectric layer 1110, and etching is performed according to masking layer 3404. In some embodiments, etching includes a dry etching process or other suitable processes.

[0078] like Figure 35 As shown in cross-sectional view 3500, a conductive pad 1108 is formed in a pad contact opening 3402 and located on a conductive line 128 of the interconnect structure 124. In some embodiments, forming the conductive pad 1108 includes depositing a conductive pad layer 1214 in the pad contact opening 3402, depositing a conductive pad layer 1216 on the conductive pad layer 1214, and etching the conductive pad layer 1216 and the conductive pad layer 1214 to form the conductive pad 1108 from the conductive pad layer 1214 and the conductive pad layer 1216. The conductive pad layer 1214 includes a conductor different from the conductive pad layer 1216. In some embodiments, the conductive pad layer 1214 and / or the conductive pad layer 1216 include tungsten, aluminum, titanium, titanium nitride, copper, or other suitable materials and are deposited by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable processes.

[0079] like Figure 36As shown in the cross-sectional view 3600, a color filter 118 is formed on a dielectric layer 1220 in the active pixel region 102. Furthermore, a microlens 119 is formed on the color filter 118.

[0080] Figure 37 A flowchart illustrating some embodiments of a method 3700 for forming an integrated wafer including a front-side deep trench isolation structure coupling interconnect structures to a back-side deep trench isolation structure is provided. While method 3700 is shown and described as a series of actions or events, it should be understood that the order of these actions or events should not be construed as limiting. For example, some actions may occur in a different order than those shown and / or described, and / or simultaneously with other actions or events. Furthermore, not all actions shown may require the implementation of one or more aspects or embodiments described herein. Moreover, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0081] In box 3702, a photodetector is formed along the semiconductor substrate. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of block 3702 is shown.

[0082] In box 3704, a first dielectric structure is formed along the front side of the semiconductor substrate. Figures 13 to 17 Cross-sectional views 1300 to 1700 are shown corresponding to some embodiments of block 3704.

[0083] In box 3706, a first dielectric structure is etched to form a front-side deep trench in the first dielectric structure along the front side of the semiconductor substrate. Figure 15 A cross-sectional view 1500 corresponding to some embodiments of block 3706 is shown.

[0084] In box 3708, a conductive front deep trench isolation structure is formed in the front deep trench. Figure 16 A cross-sectional view 1600 corresponding to some embodiments of block 3708 is shown.

[0085] In block 3710, an interconnect structure is formed in the first dielectric structure and on the front deep trench isolation structure. Figure 17 A cross-sectional view 1700 is shown corresponding to some embodiments of block 3710.

[0086] In box 3712, the semiconductor substrate is etched from the back side toward the front side to form a back-side deep trench in the semiconductor substrate. Figures 18 to 19 Cross-sectional views 1800 to 1900 are shown corresponding to some embodiments of block 3712. Figure 23 A cross-sectional view 2300 corresponding to some other embodiments of block 3712 is shown.

[0087] In box 3714, a dielectric back-side isolation layer is deposited in the back-side deep trench. Figure 20 A cross-sectional view 2000 corresponding to some embodiments of block 3714 is shown. Figure 24 A cross-sectional view 2400 corresponding to some other embodiments of block 3714 is shown.

[0088] In box 3716, the dielectric back-side isolation layer and the first dielectric structure are etched to expose the front-side deep trench isolation structure. Figure 21 A cross-sectional view 2100 corresponding to some embodiments of block 3716 is shown. Figure 25 A cross-sectional view 2500 corresponding to some other embodiments of block 3716 is shown.

[0089] In box 3718, a conductive back-side isolation layer is deposited on the dielectric back-side isolation layer in the back-side deep trench and on the front-side deep trench isolation structure. Figure 22 A cross-sectional view 2200 corresponding to some embodiments of block 3718 is shown. Figure 26 A cross-sectional view 2600 corresponding to some other embodiments of block 3718 is shown.

[0090] Therefore, this utility model relates to an integrated wafer and a method for forming the integrated wafer, the integrated wafer including a front-side DTI structure that couples an interconnect structure to a back-side DTI structure.

[0091] Accordingly, in some embodiments, the present invention relates to an integrated wafer including a first semiconductor substrate having a front side and a back side opposite to the front side. A photodetector is located in the first semiconductor substrate. A back-side deep trench isolation (DTI) structure includes a conductive back-side isolation layer and a dielectric back-side isolation layer extending from the back side toward the front side into the first semiconductor substrate and extending between the photodetector and a neighboring photodetector to isolate the photodetector from the neighboring photodetector. The dielectric back-side isolation layer is located between the conductive back-side isolation layer and the first semiconductor substrate. A first interconnect structure includes a first plurality of conductive interconnects along the front side of the first semiconductor substrate. A conductive front-side deep trench isolation structure extends from the first interconnect structure to the conductive back-side isolation layer and couples the conductive back-side isolation layer to the first interconnect structure.

[0092] In one embodiment, the bias circuit is coupled to a conductive back-side isolation layer via a first interconnect structure and a conductive front-side deep trench isolation structure. In another embodiment, the integrated wafer further includes a second interconnect structure, a second semiconductor substrate, and the bias circuit. The second interconnect structure includes a second plurality of conductive interconnects located below and coupled to the first interconnect structure. The second semiconductor substrate is located below the second interconnect structure. The bias circuit runs along the second semiconductor substrate and is coupled to the conductive back-side isolation layer via the second interconnect structure, the first interconnect structure, and the conductive front-side deep trench isolation structure. In one embodiment, a photodetector is located in an active pixel region, wherein the conductive front-side deep trench isolation structure is located in a dummy pixel region adjacent to the active pixel region, wherein the back-side deep trench isolation structure is located in both the active pixel region and the dummy pixel region, and wherein the conductive back-side isolation layer contacts the conductive front-side deep trench isolation structure in the dummy pixel region. In one embodiment, between the photodetector and a neighboring photodetector, a first semiconductor substrate extends directly beneath a back-side deep trench isolation structure, and wherein, directly above a conductive front-side deep trench isolation structure, the back-side deep trench isolation structure extends through the first semiconductor substrate to the upper surface of the conductive front-side deep trench isolation structure. In another embodiment, between the photodetector and a neighboring photodetector, the back-side deep trench isolation structure extends through the first semiconductor substrate to a dielectric layer along the front side of the first semiconductor substrate, and wherein, directly above a conductive front-side deep trench isolation structure, the back-side deep trench isolation structure extends through the first semiconductor substrate and the dielectric layer to the upper surface of the conductive front-side deep trench isolation structure. In one embodiment, the integrated wafer further includes a dielectric front-side shallow trench isolation structure extending from the front side toward the back side into the first semiconductor substrate, located directly beneath the back-side deep trench isolation structure. A conductive front-side deep trench isolation structure extends into the dielectric front-side shallow trench isolation structure from below it, and a back-side deep trench isolation structure extends into the dielectric front-side shallow trench isolation structure directly above it. In one embodiment, the back-side deep trench isolation structure is located on the top surface of the conductive front-side deep trench isolation structure and extends along the outer sidewall of the conductive front-side deep trench isolation structure to below the top surface of the conductive front-side deep trench isolation structure. In another embodiment, the back-side deep trench isolation structure extends into the conductive front-side deep trench isolation structure below its top surface, and is located between a pair of inner sidewalls of the conductive front-side deep trench isolation structure, and on the upper surface of the conductive front-side deep trench isolation structure, which is lower than its top surface.In one embodiment, the back-side deep trench isolation structure extends into the conductive front-side deep trench isolation structure, below the top surface of the conductive front-side deep trench isolation structure. The back-side deep trench isolation structure is located on the upper surface of the conductive front-side deep trench isolation structure, with the upper surface below the top surface of the conductive front-side deep trench isolation structure. The back-side deep trench isolation structure extends along the outer sidewall of the conductive front-side deep trench isolation structure. In one embodiment, the conductive front-side deep trench isolation structure is a first conductive front-side deep trench isolation structure. The integrated wafer also includes a second conductive front-side deep trench isolation structure laterally spaced from the first conductive front-side deep trench isolation structure and extending from the first interconnect structure to the conductive back-side isolation layer.

[0093] In other embodiments, the present invention relates to an integrated wafer including a first semiconductor substrate having a front side and a back side opposite the front side. A photodetector is located in the first semiconductor substrate. A first dielectric structure includes a first plurality of dielectric layers along the front side of the first semiconductor substrate. A first interconnect structure includes a first plurality of conductive interconnects located in the first dielectric structure. A conductive front-side deep trench isolation (DTI) structure is located in the first dielectric structure, on the first conductive interconnects of the first interconnect structure, and coupled to the first interconnect structure. A back-side deep trench isolation structure includes a conductive back-side isolation layer and a dielectric back-side isolation layer extending from the back side toward the front side into the first semiconductor substrate. The dielectric back-side isolation layer is located between the conductive back-side isolation layer and the first semiconductor substrate. A first portion of the conductive back-side isolation layer extends between the photodetector and a neighboring photodetector to isolate the photodetector from the neighboring photodetector. A second portion of the conductive back-side isolation layer is laterally spaced from the photodetector and the neighboring photodetector. The second part extends from the back side through the first semiconductor substrate to the conductive front deep trench isolation structure and is coupled to the conductive front deep trench isolation structure.

[0094] In one embodiment, the integrated wafer further includes a conductive grid, a color filter, a microlens, a back-side ground electrode, and conductive pads. The conductive grid is spaced above the back-side deep trench isolation structure. The color filter is spaced above the conductive grid. The microlens is located above the color filter. The back-side ground electrode is located beside the conductive grid, coupled to the conductive grid, and laterally spaced from the conductive front-side deep trench isolation structure. The conductive pads are along the front side of the first semiconductor substrate and laterally spaced from the back-side ground electrode. In one embodiment, the integrated wafer further includes a second semiconductor substrate, a bias circuit, and a second interconnect structure. The second semiconductor substrate is spaced below the first semiconductor substrate. The bias circuit is along the second semiconductor substrate. The second interconnect structure includes a second plurality of conductive interconnects located between the second semiconductor substrate and the first interconnect structure, and coupled to the first interconnect structure, such that the bias circuit is coupled to the conductive back-side isolation layer through the second interconnect structure, the first interconnect structure, and the conductive front-side deep trench isolation structure. In one embodiment, the top surface of the conductive front-side deep trench isolation structure is located above the front side of the first semiconductor substrate and directly spaced below the first semiconductor substrate.

[0095] In other embodiments, the present invention relates to a method of forming an integrated wafer. The method includes forming a photodetector in a first semiconductor substrate. The first semiconductor substrate has a front side and a back side opposite the front side. The method includes depositing a first plurality of dielectric layers on the front side of the first semiconductor substrate to form a first dielectric structure along the front side of the first semiconductor substrate. The method includes etching the first dielectric structure to form a front-side deep trench in the first dielectric structure. The method includes depositing a conductive front-side isolation layer in the front-side deep trench to form a conductive front-side deep trench isolation (DTI) structure in the front-side deep trench. The method includes forming a first interconnect structure, including forming a first plurality of conductive interconnects in the first dielectric structure and on the conductive front-side deep trench isolation structure. First conductive lines of the first interconnect structure are formed on the conductive front-side deep trench isolation structure. The method includes etching the first semiconductor substrate from the back side to the front side to form a back-side trench in the first semiconductor substrate. The method includes depositing a dielectric back-side isolation layer in the back-side trench. The method includes etching a dielectric back-side isolation layer and a first dielectric structure along the bottom of a back-side trench to extend the back-side trench into the first dielectric structure and expose a portion of a conductive front-side deep trench isolation structure. The method also includes depositing a conductive back-side isolation layer on the dielectric back-side isolation layer, in the back-side trench, and on the conductive front-side deep trench isolation structure.

[0096] In one embodiment, the method further includes: forming a gate electrode along the front side of a first semiconductor substrate; etching a first dielectric structure to form a contact opening over the gate electrode; and depositing a conductive front-side isolation layer in the contact opening and on the gate electrode. In one embodiment, the method further includes: etching the first semiconductor substrate from the front side toward the back side to form a front-side shallow trench in the first semiconductor substrate; and depositing a dielectric front-side isolation layer in the front-side shallow trench to form a front-side shallow trench isolation structure in the front-side shallow trench, wherein the front-side shallow trench isolation structure is part of the first dielectric structure, wherein a front-side deep trench is formed in the front-side shallow trench isolation structure, and wherein a back-side deep trench is formed in the front-side shallow trench isolation structure. In one embodiment, etching the first semiconductor substrate from the back side toward the front side to form a back-side deep trench in the first semiconductor substrate includes: performing a first etching process on the first semiconductor substrate from the back side to the front side such that the back-side deep trench extends through the first semiconductor substrate to the first dielectric structure. In one embodiment, etching a first semiconductor substrate from the back side toward the front side to form a back-side deep trench in the first semiconductor substrate includes: performing a first etching process on the first semiconductor substrate from the back side toward the front side to form a back-side deep trench in the first semiconductor substrate between a photodetector and an adjacent photodetector and directly above a conductive front-side deep trench isolation structure; and performing a second etching process on the first semiconductor substrate directly above the conductive front-side deep trench isolation structure to allow the back-side deep trench to extend through the first semiconductor substrate to a first dielectric structure.

[0097] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, characterized in that, include: A first semiconductor substrate has a front side and a back side opposite to the front side; A photodetector is located within the first semiconductor substrate; A back-side deep trench isolation structure includes a conductive back-side isolation layer and a dielectric back-side isolation layer, which extend from the back side toward the front side into the first semiconductor substrate and extend between the photodetector and a neighboring photodetector to isolate the photodetector from the neighboring photodetector. The dielectric back-side isolation layer is located between the conductive back-side isolation layer and the first semiconductor substrate. A first interconnect structure includes a first plurality of conductive interconnects along the front side of the first semiconductor substrate; as well as A conductive front-side deep trench isolation structure extends from the first interconnect structure to the conductive back-side isolation layer and couples the conductive back-side isolation layer to the first interconnect structure.

2. The integrated chip as described in claim 1, characterized in that, The bias circuit is coupled to the conductive back isolation layer through the first interconnect structure and the conductive front deep trench isolation structure.

3. The integrated chip as described in claim 1, characterized in that, The photodetector is located in the active pixel region, wherein the conductive front deep trench isolation structure is located in the dummy pixel region, the dummy pixel region is located next to the active pixel region, wherein the back deep trench isolation structure is located in both the active pixel region and the dummy pixel region, and wherein the conductive back isolation layer contacts the conductive front deep trench isolation structure in the dummy pixel region.

4. The integrated chip as described in claim 1, characterized in that, Between the photodetector and the adjacent photodetector, the first semiconductor substrate extends directly below the back-side deep trench isolation structure, and the back-side deep trench isolation structure extends through the first semiconductor substrate to the upper surface of the conductive front-side deep trench isolation structure, directly above the conductive front-side deep trench isolation structure.

5. The integrated chip as described in claim 1, characterized in that, Between the photodetector and the adjacent photodetector, the back-side deep trench isolation structure extends through the first semiconductor substrate to a dielectric layer along the front side of the first semiconductor substrate, and wherein, directly above the conductive front-side deep trench isolation structure, the back-side deep trench isolation structure extends through the first semiconductor substrate and the dielectric layer to the upper surface of the conductive front-side deep trench isolation structure.

6. The integrated chip as claimed in claim 1, characterized in that, Also includes: A dielectric front shallow trench isolation structure extends from the front side toward the back side into the first semiconductor substrate, located directly below the back deep trench isolation structure, wherein the conductive front deep trench isolation structure extends from below the dielectric front shallow trench isolation structure into the dielectric front shallow trench isolation structure, and wherein the back deep trench isolation structure extends directly above the conductive front deep trench isolation structure into the dielectric front shallow trench structure.

7. An integrated chip, characterized in that, include: A first semiconductor substrate has a front side and a back side opposite to the front side; A photodetector is located within the first semiconductor substrate; A first dielectric structure includes a first plurality of dielectric layers along the front side of the first semiconductor substrate; The first interconnect structure includes a first plurality of conductive interconnects located within the first dielectric structure; A conductive front-side deep trench isolation structure is located within the first dielectric structure, on the first conductive interconnect of the first interconnect structure, and coupled to the first interconnect structure. as well as A back-side deep trench isolation structure includes a conductive back-side isolation layer and a dielectric back-side isolation layer, extending from the back side toward the front side into a first semiconductor substrate. The dielectric back-side isolation layer is located between the conductive back-side isolation layer and the first semiconductor substrate. A first portion of the conductive back-side isolation layer extends between a photodetector and a neighboring photodetector to isolate the photodetector from the neighboring photodetector. A second portion of the conductive back-side isolation layer is laterally spaced from the photodetector and the neighboring photodetector. The second portion extends from the back side through the first semiconductor substrate to the conductive front-side deep trench isolation structure and is coupled to the conductive front-side deep trench isolation structure.

8. The integrated chip as claimed in claim 7, characterized in that, Also includes: A conductive grid is spaced above the back-side deep trench isolation structure; Color filters are spaced above the conductive grid; Microlenses are located above the color filter; The back-side grounding electrode is located next to the conductive grid, coupled to the conductive grid, and laterally spaced from the conductive front-side deep trench isolation structure. as well as A conductive pad is located along the front side of the first semiconductor substrate and is laterally spaced from the back-side ground electrode.

9. The integrated chip as claimed in claim 8, characterized in that, Also includes: The second semiconductor substrate is disposed below the first semiconductor substrate at a distance; The bias circuit extends along the second semiconductor substrate; as well as The second interconnect structure includes a second plurality of conductive interconnects located between the second semiconductor substrate and the first interconnect structure, and coupled to the first interconnect structure, such that the bias circuit is coupled to the conductive back isolation layer through the second interconnect structure, the first interconnect structure and the conductive front trench isolation structure.

10. The integrated wafer as claimed in claim 7, characterized in that, The top surface of the conductive front deep trench isolation structure is located above the front side of the first semiconductor substrate and directly spaced below the first semiconductor substrate.

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