A photodetector and a pet system

Abstract

The application provides an optoelectronic detector and a PET system, and relates to the technical field of imaging. The application vertically stacks each die in a photosensitive layer for sensing optical photons and each die in a logic layer for signal processing to form a multi-layer stacked structure. To adapt to the size and quantity difference between the photosensitive unit and the logic unit, the application sets an intermediate layer between the photosensitive layer and the logic layer to reconstruct the electrical connection relationship between the upper and lower layers. The intermediate layer re-routes and converges the output of the photosensitive unit to the downstream logic unit, effectively solving the balance problem between the need to combine signals to extract key information and the need to reduce the number of channels to solve the power consumption and improve reliability. In addition, the intermediate layer decouples the hard binding of the photosensitive layer and the logic layer in physical size and I / O layout, so that the upper and lower layers can each use the optimal process and design, thereby flexibly adapting to the inherent size difference between the two.

Description

Technical Field

[0001] This application relates to the field of imaging technology, specifically to a photodetector and a PET system. Background Technology

[0002] A photodetector is a fundamental optoelectronic device that converts incident optical photons (such as visible light and near-infrared light) into processable electrical signals. It is widely used in various technical fields such as medical imaging, biosensing, lidar, and high-energy physics. For example, in high-end medical imaging systems such as positron emission tomography (PET), photodetectors are typically optically coupled with scintillation crystal arrays to form gamma photon detection units, which are used to capture optical photons converted from the scintillation crystals.

[0003] In practical applications, the overall performance of a photodetector (such as its integration level) directly determines the imaging accuracy, sensitivity, and final diagnostic or detection capabilities of the system. However, a typical photodetector usually comprises two core components: a photosensitive structure for directly detecting optical photons and a signal processing structure for processing the signals generated by the photosensitive structure. In traditional planar integration schemes, the photosensitive structure and the signal processing structure are fabricated together on the same plane of the same chip.

[0004] The aforementioned layout results in signal processing structures (such as various active or passive electronic components) occupying valuable chip surface area, significantly reducing the effective photosensitive area (i.e., duty cycle) facing the photon incident side and impairing photon detection efficiency (PDE). Furthermore, the requirements for photosensitive and signal processing structures in semiconductor manufacturing processes often differ; forcibly integrating them under the same process makes it difficult to simultaneously optimize their performance. Therefore, how to rationally separate and arrange photosensitive and signal processing structures spatially to improve the photosensitive efficiency, signal quality, and overall integration of photodetectors is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] In view of this, embodiments of this application provide a photodetector and a PET system, wherein the photosensitive layer die and the logic layer die are stacked longitudinally along the optical photon propagation direction to avoid the occupancy of the photosensitive area caused by their integration in the same plane.

[0006] In a first aspect, this application provides a photodetector for a medical imaging device. The photodetector includes a photosensitive layer, a logic layer, and an interposer. The photosensitive layer includes at least one first die, which includes multiple photosensitive units for detecting optical photons. The logic layer includes at least one second die, which includes multiple logic units. An interposer is disposed between the photosensitive layer and the logic layer, and the interposer has multiple conductive paths for simultaneously connecting at least two photosensitive units in the first die to one logic unit in the second die. The first dies of the photosensitive layer, the interposer, and the second dies of the logic layer form a stacked package structure.

[0007] Secondly, this application provides a PET system. The PET system includes one or more PET detection modules. Each PET detection module includes a detector holder and multiple gamma photon detection units, wherein the multiple gamma photon detection units are disposed on the detector holder. Each gamma photon detection unit includes a scintillation crystal array and a silicon photomultiplier (SiPM) array. The scintillation crystal array is configured to convert gamma photons into optical photons. The SiPM array is coupled to the scintillation crystal array and includes multiple stacked packaged SiPMs, each SiPM including a first die, a second die, and an interposer layer disposed between the first die and the second die. The first die includes multiple photosensitive units for detecting optical photons. The second die includes a logic layer formed by multiple logic units. The interposer layer is configured to route signals from at least two photosensitive units to the same logic unit.

[0008] Thirdly, this application provides a PET system. The PET system includes one or more PET detection modules. Each PET detection module includes a detector holder and multiple gamma photon detection units, wherein the multiple gamma photon detection units are disposed on the detector holder. Each gamma photon detection unit includes a scintillation crystal array and a silicon photomultiplier (SiPM) array. The scintillation crystal array is configured to convert gamma photons into optical photons. The SiPM array is coupled to the scintillation crystal array and includes multiple stacked packaged SiPMs, each SiPM including a first die, a second die, and an interposer layer disposed between the first die and the second die. The first die includes multiple photosensitive units for detecting optical photons, the multiple photosensitive units forming a photosensitive layer. The second die includes a logic layer formed by multiple logic units. The photosensitive layer provides quenching circuits, at least one of which is simultaneously connected to at least two photosensitive units. The interposer layer is configured to route drive signals from the logic units to the quenching circuits.

[0009] Therefore, this application vertically stacks the photosensitive layer for sensing optical photons and the logic layer for signal processing, forming a multi-layered stacked structure. To accommodate the differences in size and number between the photosensitive and logic units, this application sets up an intermediary layer between the photosensitive and logic layers, reconstructing the electrical connection between the upper and lower layers. Specifically, the intermediary layer reroutes and converges the outputs of the photosensitive units to the downstream logic units, effectively solving the quantity differences caused by signal merging requirements. Furthermore, the intermediary layer decouples the hard binding of the photosensitive and logic layers in terms of physical size and I / O layout, allowing each layer to adopt optimal processes and designs, thus flexibly adapting to their inherent size differences. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a planar photodetector from a top-down perspective, provided by the related technology of this application.

[0012] Figure 2 This is a schematic cross-sectional view of a three-dimensional photodetector along the photon propagation direction provided by the related technology of this application.

[0013] Figure 3 This is a schematic cross-sectional view of a photodetector along the optical photon propagation direction provided in some embodiments of this application.

[0014] Figure 4 This is a cross-sectional schematic diagram of a photodetector with a driving circuit provided in some embodiments of this application.

[0015] Figure 5 This is a cross-sectional schematic diagram of a photodetector comprising multiple substrates provided in some embodiments of this application.

[0016] Figure 6 This is a cross-sectional schematic diagram of a photodetector under partial maintenance conditions provided in some embodiments of this application.

[0017] Figure 7 This is a top view schematic diagram of a photodetector provided in some embodiments of this application.

[0018] Figure 8 This is a partial perspective view of a PET detector system provided in some embodiments of this application.

[0019] Among them, 100 is a planar photodetector; 110 is a photosensitive area; 120 is a peripheral area; 200 is a stereo photodetector; 210 is a photosensitive array; 211 is a photosensitive unit; 220 is a logic array; 221 is a logic unit; 300 is a photodetector; 310 is a photosensitive layer; 311 is a photosensitive unit; 312 is a first die; 320 is an interposer; 321 is a first surface; 322 is a second surface; 323 is a first lead; 324 is a second lead; 325 is a third connection port; 326 is a substrate; 330 is a logic layer; 331 is a logic unit; 332 is a second die; 340 is an external drive circuit board; 341 is a connection point; 350 is a scintillation crystal array; 800 is a detector system; 801 is a gamma photon detection unit; and 810 is a patient. Detailed Implementation

[0020] To more clearly illustrate the technical solutions of the embodiments in this specification, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can implement this specification without using the details described. In other instances, to avoid unnecessarily obscuring various aspects of this specification, well-known methods, processes, systems, components, and / or circuits have been described in general terms at a relatively high level. Various modifications to the embodiments disclosed in this specification will be apparent to those skilled in the art, and the general principles defined in this specification can be applied to other embodiments and application scenarios without departing from the spirit and scope of this specification. Therefore, this specification is not limited to the illustrated embodiments, but conforms to the broadest scope consistent with the scope of the specification.

[0021] The terminology used in this specification is for describing specific exemplary embodiments only and does not limit the scope of this specification. The singular forms “a,” “an,” and “the” used in this specification may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that, as used in this specification, the terms “comprising” and “including” indicate only the presence of the stated features, integrals, steps, operations, components, and / or parts, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, components, parts, and / or combinations thereof.

[0022] It should be understood that the terms "system," "unit," "module," "and / or," and "block" used in this specification are methods of distinguishing different components, elements, parts, sections, or assemblies at different levels in ascending order. However, other expressions that achieve the same purpose may be used instead of the above terms.

[0023] It should be understood that when a unit, engine, module, or block is referred to as being "on," "connected to," or "coupled to" another unit, engine, module, or block, it can be directly on, connected to, or coupled to other units, engines, modules, or blocks, or communicate with other units, engines, modules, or blocks, or intervening units, engines, modules, or blocks. In this specification, the term "and / or" may include any one or more of the relevant listed items or a combination thereof.

[0024] The embodiments of the systems and methods provided in this disclosure are not intended to limit the scope of this disclosure, but are merely representative of possible embodiments. Furthermore, the steps of the method do not necessarily need to be performed in any particular order, or even sequentially, nor do they necessarily need to be performed only once. The following description, taken in conjunction with the accompanying drawings, sets forth numerous specific details to provide a comprehensive understanding of possible variations of the systems and methods. However, the disclosed concepts, systems, methods, apparatuses, etc., may be implemented without some or all of the specific details. For clarity, technical materials known in the art related to this disclosure have not been described in detail.

[0025] Application Overview: Based on the aforementioned background technology, in order to further illustrate the technical problems existing in the photodetectors of the prior art, this application provides a schematic diagram of the structure of a planar photodetector from a top-down perspective. Figure 1 ).

[0026] like Figure 1 As shown, the planar photodetector 100 comprises a photosensitive area 110 and a peripheral area 120. The photosensitive area 110 is the core region for directly receiving and converting optical photons, and it may include multiple photosensitive units (e.g., single-photon avalanche diodes, SPADs) arranged in an array. The peripheral area 120 surrounds the photosensitive area 110 and is primarily used to integrate various circuits required for signal processing, such as trigger networks, time-to-digital converters (TDCs), analog-to-digital converters (ADCs), and other logic circuits. These logic circuits constitute the signal processing section of the photodetector.

[0027] During operation, incident optical photons are captured by the photosensitive unit in the photosensitive area 110 and converted into electrical signals (denoted as detection signals). These detection signals are then transmitted through the metal interconnects inside the chip to the logic circuits in the peripheral area 120 for further processing, ultimately generating information such as time and energy that can be used for system analysis.

[0028] However, the planar integration layout has significant technical drawbacks. First, the peripheral area 120, due to the integration of numerous metal interconnects and transistors, is essentially insensitive to incident optical photons, constituting an ineffective photosensitive area. This results in valuable chip surface space being occupied by non-photosensitive portions, significantly reducing the duty cycle of the effective photosensitive area and thus impairing photon detection efficiency (PDE). Second, there are fundamental differences in semiconductor manufacturing process requirements between photosensitive units (such as SPADs) and logic circuits (such as TDCs and ADCs). Photosensitive units typically require specialized CMOS image sensor (CIS) processes to optimize their photosensitivity, while high-speed logic circuits are better suited to standard logic CMOS processes. Forcing both onto the same wafer makes it difficult to simultaneously meet the performance optimization requirements of these two different functional modules, limiting the overall performance improvement of the device.

[0029] To address the aforementioned issues, three-dimensional (3D) stacking technology can be employed to separate photosensitive and logic processing functions into different physical layers. 3D stacking refers to the technique of stacking semiconductor components fabricated on different wafers in a three-dimensional space. Specifically, for photodetectors, the semiconductor layer used for photosensitive sensing (photosensitive array) and the semiconductor layer used for signal processing (logic array) can be stacked and packaged vertically, rather than arranged horizontally on the same plane. This eliminates the need for the logic array to occupy the surface area of ​​the photosensitive array, thereby maximizing the duty cycle of the photosensitive region and allowing the photosensitive array and logic array to be manufactured using their respective most suitable independent semiconductor processes to fully leverage their performance advantages.

[0030] To further illustrate the three-dimensional stacked photodetector, this application also provides a cross-sectional schematic diagram of a three-dimensional photodetector along the photon propagation direction in the related art. Figure 2 ).

[0031] like Figure 2 As shown, the stereo photodetector 200 may include a photosensitive array 210 and a logic array 220. The photosensitive array 210 forms the top layer of the stereo photodetector 200, facing the incident direction of the optical photons, serving as the photosensitive interface of the entire device, and is mainly used to capture incident optical photons and convert them into electrical signals. The logic array 220 is located downstream of the photosensitive array 210, and is mainly used to receive the detection signals of the optical photons from the photosensitive array 210, and perform corresponding signal processing and logic operations.

[0032] Based on the stereo photodetector 200, incident optical photons are first captured by the top-layer photosensitive array 210 and converted into recognizable electrical signals. Subsequently, the electrical signals are transmitted vertically downwards to the bottom-layer logic array 220, where signal processing and information extraction are performed, ultimately outputting digital information characterizing the photon event.

[0033] In practical applications, a photosensitive array 210 typically includes multiple photosensitive units 211, and a logic array 220 typically includes multiple logic units 221. The logic unit 221 can be an application-specific integrated circuit (ASIC) or an analog front-end (AFE), primarily used for processing signals from the photosensitive units 211 (e.g., digitization). During signal processing, a logic unit 221 usually needs to combine signals from multiple photosensitive units 211. Therefore, in direct signal connection scenarios, the size of a logic unit 221 is often designed based on the corresponding photosensitive unit array (e.g., 2×2 units) to ensure that the logic unit 221 can receive the detection signals from its respective photosensitive units 211.

[0034] However, based on the function of the logic unit 221 itself, its size requirement is often small, while the connected photosensitive unit 211, in order to achieve photosensitive function, is often larger. The aforementioned direct connection results in the size of the logic unit 221 being consistent with the overall size of the corresponding photosensitive unit 211, which may seriously affect the physical layout and I / O interface of the logic unit 221, specifically causing the following new technical problems: First, there is poor process compatibility: the manufacturing of photosensitive units 211 (such as SPADs) typically requires special CMOS image sensor (CIS) processes to optimize their photosensitive characteristics, while logic units 221 (such as ASICs / AFEs) are better suited to standard logic CMOS processes to pursue high speed and low power consumption. Forcing the two to be strictly aligned in physical layout will severely restrict the independent optimization of their respective processes, resulting in overall performance not reaching its optimal level.

[0035] Second, design flexibility is limited: the optimal arrangement of photosensitive units 211 (such as hexagonal close-packed or rectangular close-packed) may conflict with the optimal circuit layout of logic units 221, and rigid binding will sacrifice the performance of one or both.

[0036] Furthermore, in practical applications of the stereo photodetector 200, especially in medical scenarios such as PET systems, the stereo photodetector 200 often requires a large sensing area due to the demands of the scenario. Although a single die can provide multiple photosensitive units to form a photosensitive array 210, it is difficult to construct using a single die due to the physical limitations of the die, and an integrated solution of multiple dies is required. That is, the large array is divided into multiple smaller dies, each die's size being within the economic zone of standard processes. Through encapsulation, a detection area far exceeding the size of a single wafer can be spliced ​​together, breaking through the physical limitations of photolithography equipment. This further leads to the difference in the number of dies between the two structural layers, and exacerbates the difference in size between the two. Here, a die (plural form: dice) refers to the smallest unit of complete circuit functionality fabricated on a wafer through processes such as photolithography, doping, and deposition on semiconductor material (usually single-crystal silicon).

[0037] To address the aforementioned technical challenges and accommodate the differences in size and number between photosensitive units and logic units, this application incorporates an intermediary layer between the photosensitive layer and the logic layer, reconstructing the electrical connections between the upper and lower layers. Specifically, the intermediary layer reroutes and converges the outputs of the photosensitive units to the downstream logic units, effectively resolving the quantity differences arising from signal merging requirements. Furthermore, the intermediary layer decouples the rigid physical dimensions and I / O layout of the photosensitive layer and the logic layer, allowing each layer to employ optimal processes and designs, thereby flexibly adapting to their inherent size differences.

[0038] The following will combine Figures 3-8 The photodetector provided in this application will be described.

[0039] Exemplary photodetector: To illustrate the photodetector provided in this application, this application also provides a schematic cross-sectional view of the photodetector along the optical photon propagation direction. Figure 3 ).

[0040] like Figure 3 As shown, the photodetector 300 may sequentially include a photosensitive layer 310, an intermediate layer 320, and a logic layer 330 along the direction of optical photon propagation. That is, the intermediate layer 320 is located downstream of the photosensitive layer 310 along the direction of optical photon propagation, and the logic layer 330 is located downstream of the intermediate layer 320 along the direction of optical photon propagation.

[0041] The photosensitive layer 310 is the core functional layer in the photodetector used to directly receive and convert optical photons. Structurally, it forms the top layer of the entire detector and faces the incident direction of the optical photons. The photosensitive layer 310 can generate a corresponding detection signal in response to optical photons. The photosensitive layer 310 includes multiple photosensitive units 311 with independent photosensitivity. Each photosensitive unit 311 can sense optical photons and generate a corresponding detection signal. Therefore, in subsequent processing, the landing point of the optical photons in the photosensitive layer 310 can be determined based on the photosensitive unit 311 that generated the detection signal.

[0042] As mentioned above, the photosensitive unit 311 is the basic functional structure of the photosensitive layer 310. It is arranged in an array on the photosensitive layer 310 to encode the position of incident optical photons. For example, the photosensitive unit 311 can be a single-photon avalanche diode (SPAD) unit, each operating in Geiger mode. When a photon is incident, it triggers an avalanche effect, generating a current pulse signal with consistent amplitude. Furthermore, the photosensitive layer 310 is constructed from a solid die structure, and the aforementioned photosensitive units 311 are formed from the die. To avoid affecting the circuitry, this is not described in detail here; please refer to section 5 for more information. Figure 7 Related descriptions.

[0043] In practical applications, the device type (generally SPAD) and property parameters of the photosensitive unit 311 can be configured according to the actual scenario. In positron emission tomography (PET) systems, the photosensitive unit is mainly used to detect visible light or near-infrared photons converted from scintillation crystals, so it needs to be optimized for specific wavelength ranges; in lidar applications, the photosensitive unit may need higher temporal resolution to achieve accurate ranging; and in the field of biofluorescence detection, the photosensitive unit may need higher sensitivity to detect weak light signals.

[0044] Intermediate layer 320 refers to the functional intermediate structure located between photosensitive layer 310 and logic layer 330. Its main function is to reconstruct the electrical connection between the upper and lower layers and realize the rerouting and convergence of signals.

[0045] Based on the connection relationship between the photosensitive layer 310 and the logic layer 330 discussed in the aforementioned application overview, and considering that a single logic unit 331 can drive multiple (i.e., at least two) photosensitive units 311 in actual construction, similar to the die (denoted as the first die) in the aforementioned photosensitive layer 310, the logic unit 331 in the logic layer 330 is also constructed using a die (denoted as the second die). Therefore, to achieve the connection between the two, the intermediary layer 320 is provided with multiple conductive paths, which are used to connect at least two photosensitive units in the first die to one logic unit in the second die.

[0046] In some embodiments, considering the aforementioned multiple-to-one (i.e., multiple photosensitive units 311 connected to one logic unit 331) scenario, the aforementioned conductive path is implemented in two main ways. One is to merge before transmission (i.e., merge signals at the first die), and the other is to transmit before merging (i.e., merge signals at the second die). In both cases, the interposer layer 320 needs to provide a channel connecting the two.

[0047] Intermediate layer 320 has a first surface 321 and a second surface 322 disposed opposite to each other, wherein the first surface 321 is close to the photosensitive layer 310, and the second surface 322 is away from the photosensitive layer 310 and close to the logic layer 330. Based on the aforementioned conductive path requirements, the intermediate layer includes a plurality of first leads extending from the first surface close to the photosensitive layer to the second surface away from the photosensitive layer. The contacts (i.e., pins) of each photosensitive unit 311 in the photosensitive layer 310 are in contact with the first surface 321, and the logic unit 331 is used to control the electrical contacts of the photosensitive unit 311 to contact the second surface 322. Thus, the intermediate layer 320 can achieve electrical connection between the electrical contacts of the photosensitive unit 311 and the electrical contacts of the logic unit 331 through the first leads 323 passing through the first surface 321 and the second surface 322, thereby realizing the electrical interconnection between the photosensitive layer 310 and the logic layer 330. Furthermore, for ease of explanation, the electrical contact connecting the first lead 323 to the photosensitive layer 310 is referred to as the first connection port, and the electrical contact connecting the first lead 323 to the logic layer 330 is referred to as the second connection port.

[0048] The first lead 323 refers to a conductive channel within the interposer layer 320 used for vertical electrical signal transmission. It extends from the first surface 321 to the second surface 322, connecting at least the output terminals of each photosensitive unit 311 in the photosensitive layer 310 and the input terminals of each logic unit 331 in the logic layer 330. Furthermore, considering that the driving of the photosensitive units is generally also implemented by the logic layer, the electrical contacts on the first surface that contact the interposer layer may also include various driving terminals and control terminals (such as power supply, bias voltage, ground, etc.). Similarly, the contacts in the logic unit 331 used to drive the photosensitive units can also be connected to the second surface, thereby driving the corresponding contacts in the photosensitive unit 311 through the first lead 323.

[0049] In practical implementation, the first lead 323 can form a conductive channel penetrating the first and second surfaces between the surface contacts of the first and second surfaces. The surface contacts of the first lead 323 can be configured based on the form of the electrical contacts they connect to. For example, when the electrical contacts of the photosensitive unit are micro-bumps, the surface contacts they connect to can be mating pad structures to achieve reliable flip-chip bonding. As another example, when the electrical contacts of the photosensitive unit are aluminum pads, the surface contacts they connect to can be copper pillars or metallized contact surfaces at the ends of redistribution layers (RDLs), achieving electrical connection through wire bonding or thermo-press bonding.

[0050] In some embodiments, considering that the first lead 323 is mainly used to adapt to the differences in number and size between photosensitive units and logic units, the conductive path of the first lead 323 may further include a through-silicon via (TSV) and a redistribution layer (RDL). The TSV provides a low-impedance signal path in the vertical direction, enabling direct electrical connection between the first and second surfaces; the RDL provides horizontal wiring capability within the interposer layer, used to reroute and converge the output signals of multiple photosensitive units to the input terminals of the logic units, thereby effectively solving the mismatch problem in I / O density and physical layout between the upper and lower layers.

[0051] Figure 3 Only the scenario of merging at the second die is shown. At this time, one end of the first lead is connected to a photosensitive unit, and the other end is connected to a second connection port of a logic unit on the second surface. The various first leads connected to the logic unit form a conductive path to route the signals output by at least two photosensitive units to at least two second connection ports, and merge them through the at least two second connection ports to transmit them to a logic unit.

[0052] remove Figure 3 In addition to the scenario shown, the aforementioned signal merging can also be completed at the first die. Furthermore, one end of the first lead is connected to a first connection port on the first surface of at least two photosensitive units, and the other end is connected to a logic unit, forming a conductive path between at least two photosensitive units and a logic unit, so as to merge and route the signals output by the at least two photosensitive units respectively through the first connection port to a single logic unit.

[0053] In some embodiments, the interposer 320 can be implemented as an independent interposer, which can be made of high-resistivity silicon, glass, or an organic substrate. During the manufacturing process, through-silicon vias (TSVs) or through-glass vias (TGVs) penetrating the first surface 321 and the second surface 322 are formed inside the interposer using semiconductor microfabrication processes, and redistribution layers (RDLs) are fabricated on both surfaces. As a physically independent and complete functional unit, the planar dimensions of the interposer 320 can be customized according to the arrangement of photosensitive units 311 in the upper photosensitive layer 310 and the layout of logic units 331 in the downstream logic layer 330, thereby decoupling the size constraints of the upper and lower layers at the physical level and providing a basis for modular manufacturing and maintenance.

[0054] The logic layer 330 is a functional circuit layer located downstream of the intermediate layer 320, used to receive and process electrical signals from the photosensitive layer 310. Structurally, it forms the bottom layer of the entire detector and is located away from the incident surface along the optical photon propagation direction. The logic layer 330 can respond to the detection signals output by the photosensitive units 311, performing processing operations such as signal merging, timing discrimination, and energy identification, thereby generating time and energy signals that can be used for system analysis. The logic layer 330 includes multiple logic units 331 with independent signal processing capabilities. Each logic unit 331 is electrically connected to at least two photosensitive units 311 through a first lead 323 in the intermediate layer 320 to achieve collaborative processing of multiple raw detection signals (such as avalanche signals).

[0055] As mentioned above, logic unit 331 is the basic functional structure of logic layer 330. It is arranged in an array on logic layer 330 and is used to integrate and analyze electrical signals from multiple photosensitive units 311. In some embodiments, logic unit 331 may include external circuitry for processing the detection signals from photosensitive units 311. For example, logic unit 331 may be implemented as an analog front end (AFE), serving as a key interface circuit connecting the analog signals output from the photosensitive layer to the subsequent digital processing system. AFE typically integrates functions such as signal amplification, filtering, combining, and pre-processing for analog-to-digital conversion. It can amplify and combine detection signals (such as weak avalanche current signals) from multiple photosensitive units 311 with low noise and provide high-quality input for subsequent high-precision timing and energy digitization. For another example, logic unit 331 may also integrate processing structures for the aforementioned combined signals (such as timing processing and energy quantization).

[0056] In some embodiments, to achieve independent control of the photosensitive unit, efficient merging of multiple signals, and accurate extraction of key information, the logic unit may include multiple enable control modules, a signal merging module, and a signal conversion module.

[0057] An enable control module is a functional circuit in a logic unit used to drive the enable state of a single photosensitive unit. This module is electrically connected to a photosensitive unit (such as a pin that controls the enable state of the photosensitive unit, denoted as the enable terminal) via a first lead in the interposer layer. It is configured to output a control signal according to an external instruction to turn the corresponding photosensitive unit's operating state on or off. In some embodiments, the enable control module may consist of a configuration register and a CMOS driver buffer. When a disable instruction is received, its output terminal pulls down the gate voltage of the bias switch inside the photosensitive unit, cutting off the unit's bias power supply and preventing it from responding to incident photons.

[0058] A signal combining module is a functional circuit within a logic unit used to linearly superimpose analog signals output from multiple photosensitive units. This module is electrically connected to the signal terminals of at least two photosensitive units (e.g., 2×2, 3×3, etc.) via a first lead in the interposer layer. It is configured to combine the avalanche current pulses generated by the corresponding multiple photosensitive units into a single combined electrical signal in the analog domain, the amplitude of which is proportional to the number of photosensitive units triggered simultaneously. The signal combining module needs to have high input impedance to reduce signal loading effects and maintain a fast signal rise time to support high-precision timing. In practical implementations, the signal combining module can be part of the analog front-end (AFE) or directly constructed from discrete active or passive circuit components.

[0059] The signal conversion module refers to the mixed signal processing circuit in the logic unit used to extract time and energy information from the merged electrical signal. This module is connected to the signal merging module and is configured to perform timing processing and energy identification processing in parallel on the same merged electrical signal, generating time and energy signals respectively. The signal conversion module needs to include a high-speed, low-jitter timing channel and a high-linearity energy quantization channel. In some embodiments, the signal conversion module includes a high-speed comparator and a time-to-digital converter (TDC) for generating the time signal, and a peak-hold circuit in conjunction with an analog-to-digital converter (ADC) for generating the energy signal. It also supports switching between algorithms such as multi-photon averaging timing, first-photon timing, or maximum likelihood timing to adapt to the time resolution requirements of different application scenarios.

[0060] To facilitate the modular design of the aforementioned logic unit, in one embodiment, the photosensitive unit has two independent ports, serving as an enable terminal and a signal terminal respectively, to achieve physical separation of control and signal. In another embodiment, the photosensitive unit employs a single composite port, which is used to receive both the enable control signal and output an avalanche signal. For example, in a structure where the quench resistor is not integrated into the photosensitive unit, this composite port can simultaneously connect to an external quench circuit and an enable controller, distinguishing between enable and signal functions through timing or level control, thereby reducing the number of pins while ensuring functional integrity.

[0061] During operation, the incident optical photons are first captured by one or more photosensitive units 311 in the photosensitive layer 310, triggering an avalanche effect in Geiger mode and generating a corresponding current pulse signal (i.e., a detection signal). The detection signal is vertically transmitted to the logic layer 330 via the interposer layer 320 through the first leads 323 connected to each other. In the logic layer 330, the corresponding logic unit 331 performs analog domain merging of the signals from at least two photosensitive units 311 and simultaneously performs time discrimination and energy quantization, finally outputting digitized time and energy signals.

[0062] In summary, the aforementioned Figure 3 The photodetector 300 shown incorporates an intermediary layer between the photosensitive layer and the logic layer to accommodate differences in size and number between the photosensitive and logic units, thus reconstructing the electrical connections between the upper and lower layers. Specifically, the intermediary layer reroutes and converges the outputs of the photosensitive units to the downstream logic units, effectively resolving the quantity differences caused by signal merging requirements. Furthermore, the intermediary layer decouples the rigid physical dimensions and I / O layout of the photosensitive and logic layers, allowing each layer to employ optimal processes and designs, thereby flexibly adapting to their inherent size differences.

[0063] Specifically, the interposer layer, through its internal redistribution layer (RDL) and vertical interconnect structure (such as TSV), reroutes the output signals of the numerous photosensitive units densely arranged in the upper photosensitive layer according to a preset grouping rule. This allows multiple photosensitive units that originally required a one-to-one connection to be aggregated and connected to downstream logic units. For example, signals from multiple (e.g., 2×2, 4×4) photosensitive units can be merged through the routing network of the interposer layer and processed by only one logic unit, thus directly solving the problem of mismatched I / O numbers between upper and lower layers caused by the "many-to-one" signal merging architecture. Furthermore, since the interposer layer is an independent physical carrier, the pad layout on its upper surface can perfectly match the photosensitive unit arrangement of the photosensitive layer, while the pad layout on its lower surface can freely adapt to the circuit design of the logic layer; the two do not need to be consistent in size or pin position. This decoupling design allows the photosensitive layer to be manufactured using a CMOS image sensor (CIS) process specifically designed to optimize photosensitive performance, while the logic layer can be manufactured using a high-speed, low-power standard logic CMOS process. Both layers can leverage the maximum advantages of their respective processes, ultimately improving the photon detection efficiency, temporal resolution, and signal-to-noise ratio of the entire photodetector.

[0064] As mentioned above, the first die can be fabricated using CMOS technology, and the second die can be fabricated using logic circuit technology. In the photodetector, in addition to the aforementioned photosensitive unit and logic unit, a quenching circuit related to the avalanche state of the photosensitive unit is also included. The photosensitive element of this application is constructed based on silicon photomultiplier tube (SiPM) technology, and its working principle is as follows: In "Geiger mode," the reverse bias voltage of an avalanche photodiode (APD) is applied to a level higher than its breakdown voltage. At this point, the electric field inside the photosensitive unit is extremely strong. Once a photon is incident, generating an electron-hole pair, this charge carrier is accelerated by the electric field, ionizing through collisions and exciting a massive number of secondary electrons, triggering an "avalanche" that produces a huge, easily detectable current pulse. Without intervention, this avalanche will continue. To stop the process, after the avalanche generates a sufficiently large signal, the voltage across the APD is rapidly reduced, stopping the avalanche.

[0065] The avalanche cessation described above can be achieved based on the aforementioned quenching circuit. In practical implementation, the quenching circuit can generally include three types: conventional surface polysilicon resistors integrated between the photosensitive units, epitaxial resistor quenching (EQR) integrated within the first die but outside the photosensitive unit (generally at the silicon substrate), and external quenching auxiliary circuits.

[0066] In the photodetector provided in this application, considering the case where multiple photosensitive units are connected to a single logic unit, the aforementioned quenching circuit can be disposed in either the first die or the second die as needed to support the quenching of the photosensitive units. That is, there are two possible locations for the quenching circuit: first, it can be disposed inside the second die (or in the logic layer); second, it can be disposed inside the first die (or in the photosensitive layer). Both methods can achieve quenching control of the photosensitive units and do not conflict with each other.

[0067] In some embodiments, considering that the quenching circuit employs an external quenching auxiliary circuit which can be based on logic circuitry and signal merging, the quenching circuit can be configured at the second die. That is, the photodetector also includes a quenching circuit disposed within the second die, with at least two photosensitive units corresponding to the logic unit connected to a quenching circuit and used to route signals from the at least two photosensitive units to the quenching circuit. For example, Figure 3 In the scenario shown, the quenching circuit can be integrated into the second die to simultaneously drive the avalanche state of each photosensitive unit connected to a single logic unit. In this case, the manufacturing process of the quenching module itself is also matched to the logic unit, resulting in a better driving effect. Furthermore, the quenching circuit can also synchronously drive each photosensitive unit connected to its associated logic unit, thereby reducing the number of quenching circuits and improving integration.

[0068] In some embodiments, when the quenching circuit is disposed in the photosensitive layer (i.e., within the first die), the quenching circuit is integrated with multiple photosensitive units to synchronously control the quenching state of these photosensitive units. The drive signal of the quenching circuit is routed to the quenching circuit through the conductive path of the interposer, and the quenching circuit performs the quenching operation. For example, the quenching circuit in the photosensitive layer can be connected to 2×2 photosensitive units simultaneously, and its output signal is converged through the interposer and transmitted to the logic unit, realizing efficient quenching management of multiple photosensitive units.

[0069] The aforementioned photodetector can be further enhanced with additional devices based on the specific application scenario. In some embodiments, when the photodetector is applied in a PET system, it may further include a scintillation crystal array. The scintillation crystal array is positioned upstream of the photosensitive layer along the optical photon propagation direction and is configured to convert gamma photons into optical photons; the photosensitive unit is configured as a single-photon avalanche diode.

[0070] A scintillation crystal array is a functional layer composed of multiple independent small scintillation crystals arranged in a regular pattern. The material is typically a high-density, high-atomic-number inorganic crystal, such as lutetium-yttrium silicate (LYSO), bismuth germanate (BGO), or lutetium silicate (LSO). When high-energy gamma photons (such as the 511 keV photons commonly found in PET) are incident on a scintillation crystal, the crystal absorbs the energy through the photoelectric effect or Compton scattering, and then emits a large number of optical photons (i.e., scintillation light) with wavelengths in the visible or near-infrared band. These optical photons propagate downwards into the photosensitive layer, are captured by downstream photosensitive units, and are converted into electrical signals.

[0071] In practical implementation, the scintillation crystal array and the photosensitive layer are tightly bonded together using an optical coupling medium (such as optical silicone grease or transparent epoxy resin) to minimize reflection and scattering losses of optical photons at the interface and improve photon collection efficiency. Each scintillation crystal unit typically corresponds spatially to a region composed of one or more photosensitive units in the photosensitive layer. The photosensitive units within this region collectively receive optical photons from the same scintillation crystal and combine and process their signals to accurately reconstruct the energy and incident position information of the gamma photons. For details on the specific application and imaging principle of the photodetector provided in this application in a PET system, please refer to [link to relevant documentation]. Figure 8 The details and related descriptions will not be elaborated here.

[0072] In practical applications, in addition to devices added based on the application scenario (such as the aforementioned scintillation crystal array), photodetectors or their application scenarios are also equipped with external driving circuit boards. These external driving circuit boards provide the photodetector with operating power and timing control signals, and receive the processed output results.

[0073] For example, the external driver circuit board can be implemented as a multilayer printed circuit board (PCB) that integrates a low dropout regulator (LDO) for providing a stable operating voltage, a field programmable gate array (FPGA) for generating the enable timing signals required by the photosensitive unit and receiving digital outputs from the logic layer, and a communication interface chip (such as USB or Ethernet PHY) for uploading the processed data to the host computer system.

[0074] It should be noted that the photodetector provided in this application does not necessarily include an external driving circuit board due to the inherent liquidity of the device itself. The external driving circuit board is generally presented in its application scenario and is the external structure of the photodetector.

[0075] To achieve coupling with an external driver circuit board, in some embodiments, the output terminal of the logic unit is located on the side away from the interposer layer, i.e., facing the opposite direction to the photosensitive layer. This output terminal can be directly electrically connected to an external driver circuit (such as a printed circuit board PCB) via solder balls, pads, or other standard electrical connection structures.

[0076] However, the aforementioned structure, which directly connects the logic unit output to an external driver circuit board (such as a PCB), has significant limitations in practical applications. Firstly, the surface of a driver circuit board (such as a system motherboard) typically integrates various electronic components (such as capacitors, inductors, and chips), resulting in significant surface variations and irregular shapes. When a large photodetector module needs to be directly mounted on this surface, its flat bottom cannot fully conform to the uneven PCB surface, easily causing some solder joints to be suspended, poor contact, or mechanical stress concentration, thus affecting the reliability of the electrical connection and even leading to device failure.

[0077] Secondly, in large imaging systems such as positron emission tomography (PET), photodetector modules typically have a large physical size, forming a complete detection ring around the patient. In such applications, if the direct connection method described above is used, if a local area inside the detector (such as a single photosensitive unit or logic unit) fails, it is difficult to replace or repair the entire module because it is soldered as a whole to the PCB. Repair often requires disassembling the entire large-area detector module from the system, which is not only complex and time-consuming, but may also damage surrounding healthy areas due to repeated thermal stress, significantly reducing the maintainability and efficiency of the system.

[0078] To address the aforementioned issues, this application further improves the connection between the logic layer and the driver circuit based on the aforementioned intermediary layer. For details, please refer to... Figure 4 The photodetector shown has a driving circuit.

[0079] like Figure 4As shown, the photodetector 300 can also be used to connect to an external driving circuit board 340. Unlike the connection method described above, the external driving circuit board 340 can be electrically connected to the logic layer 330 via an interposer layer 320. Some reference numerals are omitted to simplify the accompanying drawings.

[0080] Specifically, the interposer layer 320 also includes a plurality of second leads 324, and the output terminal of each logic unit 331 is led out to the outside of the logic unit 331 through the second leads 324 to form a third connection port 325. Thus, the external driver circuit board 340 can be electrically connected to the logic layer 330 through the third connection port 325.

[0081] In some embodiments, the second lead 324 may be disposed inside the interposer layer 320, extending from the output of the logic layer 330 to the side or a specific area of ​​the interposer layer 320, and forming an exposed pad, solder ball, or other standard electrical contact structure at that location, serving as a third connection port 325 for mating with the external driver circuit board 340. By integrating the signal drive path within the interposer layer 320, the bottom surface of the photodetector 300 no longer needs to have I / O contacts for connecting to the external driver circuit board 340, thereby avoiding the problem of direct mounting to uneven areas on the surface of the external driver circuit board 340.

[0082] In some embodiments, the second lead 324 can be formed directly on the second surface 322 of the intermediary layer 320, that is, a redistribution layer structure is constructed on the second surface 322, extending horizontally from the output end around the logic unit 331 along the second surface 322 to the edge, forming a third connection port 325.

[0083] In some embodiments, the second lead 324 can also be embedded inside the interposer 320 using through-hole technology. That is, the second lead 324 can be formed by a horizontal redistribution layer and a vertical interconnect structure (such as a through-silicon via, TSV) inside the interposer 320. Specifically, the output terminal of the logic unit 331 is electrically connected to the second lead 324 at the second surface 322. The second lead 324 first enters the interposer through the vertical interconnect structure, then is led out to the area outside the logic unit 331 through the horizontal redistribution layer, and finally is exposed on the second surface 322 again through the vertical interconnect structure to form the third connection port 325.

[0084] As described above, to accommodate the layout of the second lead 324, in the logic unit 331, its input terminal (for connecting the photosensitive unit 311) is integrated in the central region near the second surface 322 of the interposer layer 320, while its output terminal (for connecting the external driver circuit board 340) is arranged in the surrounding area of ​​the logic unit 331. Accordingly, the conductive path (i.e., the contact of the first lead 323 on the second surface 322) is concentrated in the central region of the logic unit 331, while the driving path (i.e., the contact of the second lead 324 on the second surface 322) is distributed in the surrounding area. Inside the interposer layer 320, the wiring paths of the first lead 323 and the second lead 324 are isolated from each other, avoiding spatial conflicts between horizontal wiring and vertical interconnection.

[0085] Specifically, in Figure 4 In the diagram, the input terminal of logic unit 331 is labeled 3311, and the output terminal is labeled 3312. The second lead 324 is directly rewired on the second surface 322 to form a third connection port 325. Thus, the third connection port is used to connect to an external driver board via connection point 341 to form a drive path between the external driver board and the logic layer.

[0086] In some embodiments, the connection point 341 in the external driver circuit board 340 used for electrically connecting to the third connection port 325 can be reused as a support structure for the interposer layer 320. That is, the external driver circuit board 340 is provided with a plurality of connection points 341, which are electrically connected to the third connection port 325 and have a height (i.e., the dimension in the stacking direction, which can also be referred to as the thickness) not less than the height (i.e., the dimension in the stacking direction) of the logic unit 331 to support the interposer layer 320.

[0087] Specifically, the connection point 341 can be implemented as a conductive structure with a certain height, such as a high solder ball, a copper pillar bump, or a conductive adhesive pillar. One end of the connection point is fixed to the corresponding pad on the external drive circuit board 340, and the other end contacts the third connection port 325 on the interposer layer 320 to form an electrical connection point 341. The height of the connection point 341 is not less than the overall height of the logic unit 331. After the interposer layer 320 and the external drive circuit board 340 are assembled, the connection point 341 provides a reliable electrical signal path and also provides effective mechanical support for the interposer layer 320 and the photosensitive layer 310 above it, preventing structural deformation or connection failure caused by gravity or external vibration.

[0088] Furthermore, considering the unevenness of the surface of the aforementioned external drive circuit board 340, the height supported by the aforementioned connection point 341 can avoid the uneven surface and form a mounting surface that can stably place the interposer layer 320. This mounting surface is mainly affected by the height of the logic unit 331 and the height of the devices in the area where the interposer layer 320 is placed in the external drive circuit board 340. Therefore, the height supported by the connection point 341 is not less than the sum of the height of the logic unit 331 and the maximum height of the device in the area where the interposer layer 320 is placed in the external drive circuit board 340 at the connection position of the connection point 341 on the external drive circuit board 340.

[0089] In some embodiments, to facilitate maintenance of the photodetector 300, the connection point 341 is configured as a detachable connection structure. That is, the substrate 326 serves as the physical carrier, and the first die 312 and the second die 332 integrated on it are removed along with the substrate 326 during disassembly, enabling modular maintenance. A detachable connection structure refers to a connection method that allows for non-destructive separation or removal under specific operating conditions (such as localized heating, application of mechanical force, etc.). For example, the connection point 341 can be made of a low-melting-point solder (such as indium-based or bismuth-based alloys), which remains solid at room temperature to maintain electrical and mechanical connections. During maintenance, localized hot air heating above its melting point softens or melts the connection point 341, thereby achieving non-destructive disassembly of the module. For example, connection point 341 can also be implemented as a press-type detachable mechanical structure, which includes elastic conductive contacts and a latching mechanism. Under normal working conditions, the contact is maintained by mechanical locking force. When disassembly is required, the locking state can be released by pressing the release mechanism with a special tool to achieve physical separation. At the same time, the internally integrated micro-leads ensure that the signal path is controllably disconnected during the separation process.

[0090] In scenarios where the photodetector 300 is large, the interposer layer 320 typically comprises multiple physically separable substrates, each connected to the external driving circuit board 340 via corresponding connection points 341. Based on this detachable connection structure, when the connection point 341 corresponding to any substrate is detached, that substrate, along with a portion of the logic layer 330 and a portion of the photosensitive layer 310 electrically connected to it, can be separated from the external driving circuit board 340. This design divides the entire large-area detector into several functionally independent, physically separable sub-modules, ensuring that local faults only affect the corresponding sub-regions without impacting the overall system. The substrate can be referenced... Figure 5 The removal of substrate 326 shown can be found in [reference needed]. Figure 6 The example shown.

[0091] Taking PET system maintenance as an example, when a photoelectric detection submodule in a PET system malfunctions or fails, maintenance personnel can locate the faulty area and perform localized heating (or pressure release) on the corresponding connection point 341 of the submodule to melt (or unlock) it. Then, the entire substrate (including the first die, the interlayer sub-board, and the corresponding second die) can be removed, replaced with a new pre-installed submodule, and re-welded (or locked) in place. This process eliminates the need to disassemble the entire ring detector, significantly reducing maintenance costs, shortening downtime, and avoiding interference with surrounding normal modules, greatly improving the maintainability and operational efficiency of large imaging systems.

[0092] In some embodiments, when the detachable connection structure is implemented using a thermoplastic material (i.e., connection point 341 is made of thermoplastic material), to prevent the heat applied to connection point 341 during disassembly from affecting other critical connection structures inside the photodetector, these critical connection structures may be thermally insulated. The function of the thermal insulation is to block or significantly reduce the conduction of heat to the sensitive area, thereby ensuring internal electrical stability and preventing desoldering, deterioration, or functional failure when connection point 341 is locally heated and melted.

[0093] Based on the above discussion, the connection structures that need to be protected generally include: the connection structure between the first lead 323 and the photosensitive unit 311, the connection structure between the first lead 323 and the logic unit 331, and the connection structure between the second lead 324 and the logic unit 331.

[0094] In some embodiments, the aforementioned thermal insulation encapsulation can be implemented by at least one of the following: encapsulation using thermal insulation materials, encapsulation based on a thermal barrier structure, and encapsulation using high-temperature resistant connecting materials. Encapsulation using thermal insulation materials can refer to encapsulating the aforementioned connecting structure with a low thermal conductivity thermal insulation material (such as epoxy resin containing silica microspheres or boron nitride filler). Encapsulation based on a thermal barrier structure can refer to constructing a physical thermal barrier structure (such as an air gap, a metal reflective layer, or a low thermal conductivity trench) around the connecting structure to block the heat flow path. Encapsulation using high-temperature resistant connecting materials can refer to directly using high-temperature resistant connecting materials (such as gold-tin eutectic solder, high-melting-point copper pillars, etc.) with a melting point or thermal failure temperature much higher than the melting temperature of the thermally fused connection point 341, thereby maintaining the integrity of the connection during thermal disassembly. The aforementioned high temperature can refer to the temperature at which the aforementioned connection point 341 is locally heated and melted.

[0095] As mentioned above, in practical applications, the photodetector 300 may be a large-size detector. The following example, using a detector in a PET system, illustrates the implementation of large-size detectors at the semiconductor level. Figure 5 This is a cross-sectional schematic diagram of a photodetector comprising multiple substrates.

[0096] like Figure 5 As shown, the photosensitive layer 310 can be constructed from multiple dies. That is, the photosensitive layer 310 includes multiple first dies 312, and each first die 312 includes multiple photosensitive units 311.

[0097] The first die 312 refers to an independent die (also referred to as a silicon chip) processed by semiconductor technology, on which multiple photosensitive units 311 (such as SPAD units) are integrated in an array to form a fully functional photosensitive photonic module. The use of multiple first dies 312, spliced ​​together, can effectively avoid problems such as low yield, high thermal stress, and easy warping in single large-area wafer manufacturing, thereby improving production efficiency and product reliability.

[0098] Correspondingly, the interposer layer 320 includes multiple substrates 326 that match the dimensions of the first die 312. Each substrate 326 corresponds one-to-one with a first die 312, and each substrate 326 is strictly matched to its corresponding first die 312 in terms of planar dimensions and layout. This ensures that the photosensitive layer and the interposer layer are dimensionally matched, preventing signal routing failures due to size differences. Specifically, it integrates each first lead 323 corresponding to the first die 312. The substrate 326 refers to an independent unit formed by physically dividing the interposer layer 320, precisely matching the planar dimensions of a single first die 312. Each substrate 326 integrates vertical interconnect channels (such as TSVs) and horizontal redistribution layers required for all photosensitive units 311 on the corresponding first die 312, thus functioning as an independent signal transceiver module to achieve electrical connections between upper and lower layers. That is, the interposer 320 includes a plurality of substrates 326 that match the size of the first die 312 and correspond one-to-one with the first die 312, and integrates each conductive path (first lead 323) corresponding to the first die 312 to connect the photosensitive unit 311 in the first die 312 with the logic unit 331 in at least one corresponding second die 332.

[0099] Furthermore, to control the photosensitive units 311 in the first die 312, each first die 312 can be connected to multiple logic units 331 via a corresponding substrate 326. These multiple logic units 331 together constitute a functional unit, which is also built based on a die and can be referred to as a second die 332. That is, the logic layer 330 includes multiple second dies 332, and the multiple second dies 332 correspond one-to-one with the multiple first dies 312. Each logic unit 331 in each second die 332 is electrically connected to the multiple photosensitive units 311 in the corresponding first die 312 via a first lead 323 in the corresponding substrate 326. Here, the second die 332 refers to a group of logic units 331 in the logic layer 330 that are specifically designated for processing the output signal of a specific first die 312. The second die 332 is physically and functionally aligned with the corresponding first die 312 and substrate 326 to form a complete "photosensitive-transfer-processing" minimum functional unit (MFU), which facilitates modular design, testing and maintenance.

[0100] In addition to the above structure, Figure 5 The photodetector 300 shown also includes an external driving circuit board 340 and a scintillation crystal array 350, which can be found in the above description and will not be repeated here. For ease of understanding, Figure 5 Some of the structures already shown above are not marked.

[0101] In the actual design process of the aforementioned photodetector 300, the first die 312 is typically used as the reference unit for the entire modular structure, and a top-down collaborative design is carried out. Specifically, the physical dimensions of a single first die 312 and the arrangement density and number of its internal photosensitive units 311 are determined firstly based on the comprehensive requirements of the PET system for spatial resolution, photon detection efficiency, and manufacturing process.

[0102] Subsequently, based on the size and I / O layout of the first die 312, a corresponding substrate 326 is custom-designed. The planar contour of the substrate 326 is strictly matched with that of the first die 312, and the distribution and number of the first leads 323 inside it are mapped one-to-one according to the output / enable terminal positions of each photosensitive unit 311 on the first die 312. The signal is rerouted through a redistribution layer to adapt to the input requirements of the downstream logic unit 331.

[0103] Furthermore, based on the first die 312, the total number of photosensitive units 311, and the signal merging strategy (e.g., merging every N photosensitive units 311 into one logic unit 331), the required number of logic units 331 is determined, and the corresponding second die 332 is configured accordingly. The second die 332 is integrated into a readout circuit chip (such as an ASIC die), and its input pad layout is precisely aligned with the lead outlet at the bottom of the substrate 326, ensuring that high-density, low-crosstalk vertical interconnection can be achieved through the interposer layer 320.

[0104] Based on the above structure, the overall structure of the photodetector 300 can be realized through die-to-die packaging technology. Specifically, each first die 312 in the photosensitive layer 310, each substrate 326 in the interposer layer 320, and each logic unit 331 in the logic layer 330 (usually integrated on the same readout circuit chip in the form of a second die 332) are manufactured as independent dies during the manufacturing stage. Subsequently, using advanced packaging processes such as high-precision flip-chip bonding or thermocompression bonding, the first dies 312, substrate 326, and the readout circuit chip containing the logic units 331 are aligned and stacked layer by layer in the vertical direction to form a three-dimensional integrated minimum functional unit (MFU).

[0105] In this die-to-die stacked structure, the first die 312, as the photosensitive die, is located on the top layer; the substrate 326, as the interposer die, is located in the middle layer; and the second die 332 (such as an ASIC die), containing multiple logic units 331, is located on the bottom layer as the logic die. The three are electrically connected to the first lead 323 and the second lead 324 inside the substrate 326 via micro-interconnect structures such as micro-bumps or copper pillars. This structure not only achieves complete physical separation between photosensitive and logic processing functions but also allows each layer to be manufactured independently using the semiconductor process best suited to its functional characteristics—for example, the first die 312 can use a CMOS image sensor (CIS) process optimized for photosensitive performance, while the readout circuit chip containing the logic units 331 can use a high-speed, low-power standard logic CMOS process.

[0106] Through a modular construction method based on die-to-die packaging, multiple MFUs can be further spliced ​​side by side to form a large-area, high-performance photodetector array, which not only meets the requirements of PET and other systems for high detection efficiency and high temporal resolution, but also takes into account the feasibility of large-scale manufacturing and the convenience of later maintenance.

[0107] Based on the modular design described above, the substrate 326 not only serves as an intermediary die for signal switching but also as a physically separable substrate 326, enabling independent maintenance and replacement of local modules. Specifically, each substrate 326, together with the first die 312 above it and the second die 332 downstream it, constitutes a complete minimum functional unit (MFU). This MFU is electrically connected and mechanically supported to an external drive circuit board 340 through multiple connection points 341 at its bottom. When an MFU fails, only the connection point 341 corresponding to that MFU needs to be disassembled to separate the substrate 326, along with the integrated first die 312 and second die 332, from the system without affecting other normally functioning MFUs.

[0108] To visually illustrate this maintainability design, this application also provides a cross-sectional schematic diagram of a photodetector under partial maintenance conditions. Figure 6 ).like Figure 6 As shown, the connection point 341 corresponding to one of the substrates 326 has been removed (e.g., by melting the molten material through local heating), causing the substrate 326, the first die 312 above it, and the second die 332 downstream it to lose electrical connection and mechanical support with the external drive circuit board 340, and thus become removable. The remaining MFUs are still firmly connected to the external drive circuit board 340 through their respective connection points 341, maintaining normal operation.

[0109] Right now Figure 6 Two sets of minimum functional units (MFUs) can be formed based on the first die 312. The connection point 341 of the MFU on the left side of the figure is firmly connected to the external drive circuit board 340 and maintains normal operation. The connection point 341 of the MFU on the right side of the figure is removed (e.g., melted) and is in a "removable" state.

[0110] In actual maintenance, the location of the faulty MFU is first determined through system self-testing or external diagnostics. Then, a localized hot air gun or laser heating device is used to precisely heat the connection point 341 at the bottom of the target substrate 326, raising its temperature above the melting point of the hot-melt material, thereby softening or melting the connection point 341. After the connection is released, a precision clamp is used to remove the entire module, including the faulty substrate 326, the first die 312, and the second die 332, from the external drive circuit board 340. Finally, a brand-new, pre-packaged and tested MFU is aligned with its original position, and a hot-pressing or reflow soldering process is applied to solidify the new connection point 341, completing the replacement. The entire process does not require disassembling the entire ring detector, significantly reducing maintenance costs, shortening downtime, and avoiding interference with surrounding normal modules, greatly improving the availability and maintenance efficiency of large PET systems.

[0111] To further optimize signal transmission performance and improve system temporal resolution, in some embodiments, the photosensitive units 311 corresponding to the same logic unit 331 are arranged continuously on the plane of the first die 312, that is, the continuously arranged photosensitive units 311 correspond to the logic unit 331 in the same second die 332. Continuous arrangement can mean that the photosensitive units 311 are adjacent to each other on the chip surface, forming a compact region (such as a rectangular, square, or strip array) with no gaps or large blank areas inserted in between. This layout can significantly shorten the average interconnect length between each photosensitive unit 311 and its shared logic unit 331, reducing signal transmission delay and waveform distortion caused by parasitic parameters of metal wiring.

[0112] To further illustrate this point, this application also provides a top view schematic diagram of a photodetector ( Figure 7 ). Figure 7 The image does not contain a scintillation crystal array; the photosensitive layer 310 is shown directly, and the downstream logic units 331 are shown with dashed lines.

[0113] like Figure 7 As shown, within a single first die 312, multiple photosensitive units 311 serving various logic units 331 in the same second die 332 are arranged in a continuous subarray. For example, Figure 7 As shown, each logic unit 331 corresponds to four photosensitive units 311 arranged in a 2×2 pattern, and each second die 332 involves four logic units 331. Taking the first die 312 in the upper left corner of the figure as an example, its 16 photosensitive units 311 correspond to four logic units 331. Specifically, the four photosensitive units 311 arranged in a 2×2 pattern in the upper left corner correspond to the logic unit 331 in the upper left corner; the four photosensitive units 311 arranged in a 2×2 pattern in the lower left corner correspond to the logic unit 331 in the lower left corner; the four photosensitive units 311 arranged in a 2×2 pattern in the upper right corner correspond to the logic unit 331 in the upper right corner; and the four photosensitive units 311 arranged in a 2×2 pattern in the lower right corner correspond to the logic unit 331 in the lower right corner. Four logic units 331 constitute one second die 332. In addition, it should be noted that in practice, one second die 332 can correspond to more photosensitive units 311; this is only an example.

[0114] To simplify wiring and further reduce signal delay, the position of the second die 332 of logic unit 331 in logic layer 330 is limited to the planar area defined by its corresponding photosensitive unit 311. Specifically, this "planar area" refers to the two-dimensional range enclosed by a group of continuously arranged photosensitive units 311 in the vertical projection direction. That is, the second die is located within the continuous space formed by the corresponding photosensitive units.

[0115] Therefore, by arranging the logic unit 331 in this area (e.g., near the center or centroid), the interconnection path from each photosensitive unit 311 to the logic unit 331 can be approximately radial, avoiding long-distance winding, thereby minimizing transmission line effects and improving signal integrity and timing consistency.

[0116] Finally, considering the actual manufacturing and assembly requirements of multi-wafer integration, there is a significant difference in size between the gaps between photosensitive units within a wafer and the gaps between wafers. Specifically, the gap between adjacent photosensitive units 311 within the same first die 312 (i.e., the SPAD gap) is typically small (e.g., less than 100 micrometers, for example, 65 micrometers) to maximize the photosensitive duty cycle; while the splicing gap between adjacent first dies 312 is relatively large (e.g., around 1000 micrometers, for example, 600 micrometers), mainly to meet the process requirements of dicing, mounting alignment, and thermal expansion compensation. This dimensional difference is... Figure 6 , 7 This is also clearly reflected in the fact that the internal units of the wafer are arranged closely together, while there are obvious gaps at the wafer boundaries, which shows the multi-wafer structure of the photosensitive layer.

[0117] Exemplary PET system: Based on the aforementioned photodetector, it can be used to construct a detector system for positron emission tomography (PET). PET is a medical imaging scanning system that uses multiple gamma photon detection units arranged in a multi-ring or flat plate configuration to detect annihilation radiation sources located within the scanner's field of view and perform image reconstruction. The photodetector provided in this application is particularly suitable for such high-performance PET systems due to its high photon detection efficiency, excellent temporal resolution, and modular maintainability.

[0118] This application Figure 8 A perspective view is shown of a PET detector system 800 according to one embodiment and radionuclides 811 and 812 located within the scanning cavity of the PET detector system 800 in a patient 810 (illustrated as a human torso). In the illustrated embodiment, the PET detector system 800 includes a plurality of gamma photon detection units 801. The gamma photon detection units 801 are presented in a multi-layered ring structure, each ring structure including forty-eight gamma photon detection units. The number of detection units and the number of detection ring layers can be adjusted according to specific applications, cost, target size, and resolution requirements.

[0119] It should be noted that the arrangement of the gamma photon detection unit 801 within the aforementioned PET detector system 800 generally relies on the detector frame. That is, the detector frame forms the mounting frame for the gamma photon detection unit 801, creating a ring-shaped detection structure.

[0120] In practical applications, except Figure 8 Besides the ring-shaped detector gantry shown, detector gantry can also take the form of a polygonal ring, a flat-panel / panel array, a rotating partial ring / sector, or a dual-panel / dual-head. Furthermore, for imaging specific organs, detector gantry can be designed in irregular shapes, such as a helmet-like gantry for brain imaging, a pendant-type gantry for breast imaging, or a rectangular / box-shaped array for small animal imaging.

[0121] This application does not limit the specific form of the detector holder within the PET system or PET detection module (i.e., the PET detector system), and it can be flexibly adjusted according to actual needs. The imaging principle is explained below using a commonly used ring detector holder as an example, and it can be adapted for specific applications.

[0122] Radionuclides 811 and 812 represent positron-active aggregates that emit a pair of 511 keV gamma photons in opposite directions upon annihilation. The gamma photon pair emitted by radionuclide 811 is detected by detector units 821 and 823. A processor or other circuitry can use the known detector locations and the arrival times of the gamma photons measured by detector units 821 and 823 to calculate the response line (LOR) 830, thereby determining the location of radionuclide 811. Simultaneously, the system can identify the event as a valid annihilation event based on whether the total detected energy falls within the expected threshold range of 511 keV.

[0123] The gamma photon pair emitted by radionuclide 812 is detected by detector units 822 and 824. The processor can then calculate response line 840 to locate radionuclide 812. If radionuclide 811 and 812 emit gamma photon pairs almost simultaneously, there is a risk that the processor may misjudge response line 850 (i.e., incorrectly assume that a coincidence event exists between detector units 824 and 821).

[0124] Throughout this disclosure, the detector unit is described as a basic unit for a PET detection module (e.g., a detector unit ring). Each detector unit contains a scintillation crystal with a distal face (e.g., facing the inner diameter of the ring) facing the scanning cavity for receiving gamma photons. The detector ring can be either fully ring-shaped or non-fully ring-shaped (e.g., containing only top and bottom units). Furthermore, the PET detection module can also consist of two or more detector units arranged radially opposite each other or obliquely staggered along the scanning cavity to collaboratively detect annihilation events. For example, a subject can be positioned between two opposing sensing faces for localization. Therefore, a detector unit typically comprises multiple scintillation crystals arranged in a one-dimensional or two-dimensional array with their distal faces facing the scanning area.

[0125] The time span during which a radionuclide annihilates is called a scan. PET systems locate positron sources by capturing multiple response lines. The PET detector system described in this application can achieve high-sensitivity imaging using a ring structure constructed from the aforementioned photodetectors, eliminating the need for the shielding collimators commonly used in SPECT. In other schemes, axial collimators (septa) can be placed between the detector rings to suppress scattering; however, thanks to fast scintillators and advanced electronics processing, modern PET systems often operate in "3D mode" without septa, thereby improving event processing rate and system sensitivity.

[0126] The system distinguishes genuine double-gamma annihilation events from a large number of irrelevant "single events" using a time-based coincidence window. The coincidence window (typically less than 5 nanoseconds, e.g., 2 nanoseconds) filters out random combinations that cannot possibly originate from the same annihilation event. For example, in a detector ring with a diameter of 70 cm, the gamma photon generated by the positron annihilation at the center takes approximately 1.167 nanoseconds to reach the detector on the opposite side; annihilation along the circumference takes approximately 2.33 nanoseconds. Therefore, the coincidence window, together with the geometric pairing rules, ensures that only plausible events are recorded.

[0127] Events that meet the criteria are called "prompt" events, which may include "random" coincidences (from different annihilation sources) or "true" coincidences (from the same annihilation). The number of true coincidence events equals the number of prompt events minus the number of random coincidence events.

[0128] The system can further filter "scattering" events—events where gamma photons, after partially depositing energy in tissue, are deflected into the detector. Because their energy is below 511 keV and their origin is uncertain, they are typically eliminated through an energy window. Typically, the system uses both low-level discrimination (LLD, e.g., 325–511 keV) and high-level discrimination (ULD, e.g., 511–675 keV) to screen for valid events.

[0129] To achieve gamma photon detection, the aforementioned detection unit converts high-energy gamma photons into visible or near-infrared optical photons, which are then detected by a photoelectric sensor. This process is accomplished collaboratively by a scintillation crystal and a photoelectric sensor.

[0130] Scintillation crystals are typically high-density, high-atomic-number inorganic crystals (such as BGO, LSO, and LYSO), which convert gamma photon energy into a large number of optical photons through the photoelectric effect or Compton scattering. Photoelectric sensors then convert these optical photons into electrical pulse signals for subsequent event analysis.

[0131] Based on the aforementioned scintillation crystal, when coupled with the photodetector provided in this application to serve as a PET detection module, each PET detection module includes a detector holder and multiple gamma photon detection units. The multiple gamma photon detection units are disposed on the detector holder, and each gamma photon detection unit includes a photosensitive layer, an interposer layer, a logic layer, and a scintillation crystal array. The specific structures are described above and will not be repeated here.

[0132] When applied to PET systems, the aforementioned logic unit typically includes a trigger network (or trigger), a time-to-digital converter (TDC), and an analog-to-digital converter (ADC). The trigger network primarily collects avalanche signals from each SPAD, generates a global trigger pulse, and marks photon arrival events. The TDC is used to accurately measure photon arrival times. The ADC converts analog signals (such as energy integral values) into digital quantities for measurement. Furthermore, control circuitry for signal detection (such as quenching control circuitry) is generally integrated into the trigger network.

[0133] Therefore, this application provides a PET system including one or more PET detection modules. Each PET detection module includes a detector holder and multiple gamma photon detection units. The multiple gamma photon detection units are disposed on the detector holder, and each gamma photon detection unit includes a scintillation crystal array and a silicon photomultiplier (SiPM) array. The scintillation crystal array is configured to convert gamma photons into optical photons. The silicon photomultiplier (SiPM) array is coupled to the scintillation crystal array.

[0134] A silicon photomultiplier (SiPM) comprises multiple stacked packaged SiPMs, each including a first die, a second die, and an interposer layer disposed between the first and second dies. The first die includes multiple photosensitive units for detecting optical photons. The second die includes a logic layer formed by multiple logic units. The interposer layer is configured to route signals from at least two photosensitive units to the same logic unit. For details, please refer to the foregoing description, which will not be repeated here.

[0135] Furthermore, considering the case where the quenching circuit is located in the photosensitive layer, this application also provides a PET system with a quenching circuit located in the photosensitive layer. Similar to the aforementioned system, this PET system includes one or more PET detection modules. Each PET detection module includes a detector holder and multiple gamma photon detection units. The multiple gamma photon detection units are disposed on the detector holder, and each gamma photon detection unit includes a scintillation crystal array and a silicon photomultiplier (SiPM) array. The scintillation crystal array is configured to convert gamma photons into optical photons. The silicon photomultiplier (SiPM) array is coupled to the scintillation crystal array.

[0136] A silicon photomultiplier (SiPM) comprises multiple stacked packaged SiPMs, each including a first die, a second die, and an interposer layer disposed between the first and second dies. The first die includes multiple photosensitive units for detecting optical photons, forming a photosensitive layer. The second die includes a logic layer formed by multiple logic units. A quenching circuit is disposed on the photosensitive layer, with at least one quenching circuit simultaneously connected to at least two photosensitive units. The interposer layer is configured to route drive signals from the logic units to the quenching circuit.

[0137] Unexpected technical effects: In summary, the photodetector and PET system provided in this application achieve the following outstanding technical effects: ① The photosensitive layer and logic layer are stacked vertically along the optical photon propagation direction, with the intermediate layer located between them. The readout circuit no longer occupies the surface of the photosensitive area, thus improving the photon detection efficiency. The analog signal transmission path is shortened to the micrometer level, reducing parasitic capacitance and external noise coupling, thereby improving the signal-to-noise ratio.

[0138] ② The detector wafer, the interposer substrate, and the logic unit group constitute the smallest functional unit (MFU). The interposer, through a redistribution layer, converges the signals from multiple photosensitive units into a single logic unit, adapting to the characteristic of gamma photons generating multiphoton clusters in a scintillation crystal. The photosensitive layer is manufactured using CMOS image sensor technology, while the logic layer is manufactured using standard logic CMOS technology; the two processes are independent of each other.

[0139] ③ The interposer layer is divided into multiple physically separable substrates. Each substrate, together with the corresponding detector wafer and logic unit group, constitutes a minimum functional unit (MFU). The MFU is connected to the driver circuit board via connectors made of thermoplastic material, and critical internal connection points are thermally insulated. In case of partial failure, only the corresponding connector needs to be melted to remove and replace the MFU, without disassembling the entire detector module.

[0140] As used herein, unless otherwise expressly stated, references to “photosensor,” “photodiode,” and / or “photodetector” do not imply limitation or exclusion of any particular embodiment. As used herein, the term “readout” refers to the measurement, investigation, evaluation, or processing of the referenced subject matter. Similarly, the use of “lateral” readout, “lateral” readout, and “lateral” sensing generally refers to the photosensitivity of a scintillator, where the sensing surface of the photosensor is coupled to a scintillator surface parallel to the transverse axis of the scanner aperture, and therefore not obtained from either end face parallel to the axis of the scanner aperture. Furthermore, as used herein, “scintillator,” “crystal,” “pixel,” and “block” can each refer to scintillator materials configured in different ways.

[0141] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects may be any one or a combination of the above, or any other possible beneficial effects.

[0142] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0143] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0144] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0145] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0146] In addition, the functional units in the various embodiments of this disclosure can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0147] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0148] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A photodetector for use in medical imaging equipment, characterized in that, include: The photosensitive layer includes at least one first die, the first die including a plurality of photosensitive units for detecting optical photons; The logic layer includes at least one second die, the second die including multiple logic units; as well as An intermediary layer is disposed between the photosensitive layer and the logic layer. The intermediary layer has multiple conductive paths, which are used to connect at least two photosensitive units in the first die to one logic unit in the second die simultaneously. The first dies of the photosensitive layer, the intermediate layer, and the second dies of the logic layer form a stacked package structure.

2. The photodetector according to claim 1, characterized in that, The intermediate layer, located downstream of the photosensitive layer along the direction of optical photon propagation, includes a plurality of first leads extending from a first surface near the photosensitive layer to a second surface away from the photosensitive layer; One end of the first lead is connected to a first connection port on the first surface of at least two of the photosensitive units, and the other end is connected to a logic unit, forming a conductive path between the at least two photosensitive units and the logic unit, so as to combine and route the signals output by the at least two photosensitive units to one logic unit through the first connection port; or... One end of the first lead is connected to one of the photosensitive units, and the other end is connected to a second connection port of a logic unit on the second surface. The first leads connected to the logic unit form the conductive path to route the signals output by at least two of the photosensitive units to at least two of the second connection ports, and then merge and transmit them to one of the logic units through the at least two second connection ports.

3. The photodetector according to claim 1, characterized in that, The interposer layer further includes a plurality of second leads, one end of which is connected to a logic unit, and the other end is connected to the outside of the logic unit and forms a third connection port on the second surface of the interposer layer away from the photosensitive layer. The third connection port is used to connect to an external driver circuit board via a connection point to form a drive path between the external driver circuit board and the logic layer.

4. The photodetector according to claim 3, characterized in that, The dimension of the connection point in the stacking direction of the stacked package structure is larger than the dimension of the logic unit in the stacking direction, so as to support the interposer layer; The second core is fixedly disposed on the second surface.

5. The photodetector according to claim 4, characterized in that, The intermediate layer includes multiple substrates, and the photosensitive unit is fixedly disposed on the first surface of the corresponding substrate; The connection point is detachably connected to the external drive circuit board so that when any connection point of the substrate is separated from the external drive circuit board, the first die and the second die disposed on the substrate are separated from the external drive circuit board along with the substrate.

6. The photodetector according to claim 1, characterized in that, The interposer layer includes multiple substrates that match the size of the first die and correspond one-to-one with the first die, and integrates each conductive path corresponding to the first die to connect the photosensitive unit in the first die to the logic unit in at least one corresponding second die.

7. The photodetector according to claim 6, characterized in that, The photosensitive units in the first die that are connected to the logic units in the same second die are arranged continuously on a plane, and the second die is located in the continuous space formed by the corresponding photosensitive units.

8. The photodetector according to claim 1, characterized in that, The photodetector further includes a quenching circuit disposed within the second die, wherein at least two photosensitive units corresponding to the logic unit are connected to a quenching circuit and are used to route the signals of at least two photosensitive units to the quenching circuit.

9. A PET system, characterized in that, The PET system includes one or more PET detection modules; The PET detection module includes a detector frame and multiple gamma photon detection units, wherein the multiple gamma photon detection units are disposed on the detector frame, and each gamma photon detection unit includes: A scintillation crystal array is configured to convert gamma photons into optical photons; A silicon photomultiplier array, coupled to the scintillation crystal array, includes multiple silicon photomultipliers with stacked package structures, each silicon photomultiplier including a first die, a second die, and an interlayer disposed between the first die and the second die; The first die includes multiple photosensitive units for detecting optical photons; The second die includes a logic layer formed by multiple logic units; The intermediary layer is configured to route signals from at least two of the photosensitive units to the same logic unit.

10. A PET system, characterized in that, The PET system includes one or more PET detection modules; The PET detection module includes a detector frame and multiple gamma photon detection units, wherein the multiple gamma photon detection units are disposed on the detector frame, and each gamma photon detection unit includes: A scintillation crystal array is configured to convert gamma photons into optical photons; A silicon photomultiplier array, coupled to the scintillation crystal array, includes multiple silicon photomultipliers with stacked package structures, each silicon photomultiplier including a first die, a second die, and an interlayer disposed between the first die and the second die; The first die includes a plurality of photosensitive units for detecting optical photons, and the plurality of photosensitive units form a photosensitive layer; The second die includes a logic layer formed by multiple logic units; The photosensitive layer is provided with a quenching circuit, and at least one quenching circuit is simultaneously connected to at least two of the photosensitive units; The intermediary layer is configured to route the drive signal of the quenching circuit from the logic unit to the quenching circuit.

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