An infrared detector chip packaging structure

CN224910038UActive Publication Date: 2026-10-27WUHAN GAOXIN TECH
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202621326659.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2026-08-26
Publication Date
2026-10-27
Estimated Expiration
2036-08-26

AI Technical Summary

Technical Problem

但是吸气剂在通电激活过程中会释放大量热量,这些热量会通过台阶向下热传导至芯片上的非有效元表面,从而影响甚至损坏参考元

Benefits of technology

(1)本实用新型在过渡环的内壁上设置第一内部台阶,并使第一内部台阶在芯片上的正投影与芯片上的有效元区域和参考元区域错开,通过将吸气剂结构布置在该第一内部台阶上,可以降低吸气剂激活时释放热量对参考元的影响;

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN224910038U_ABST
    Figure CN224910038U_ABST
Patent Text Reader

Abstract

The utility model belongs to infrared detector technical field, concretely relates to a kind of infrared detector chip packaging structure, including chip, transition ring and window piece that are sequentially laminated, chip, transition ring and window piece are welded to form packaging cavity;Effective element area and reference element area are provided on chip;The inner wall of transition ring is provided with the internal step that is protruded to packaging cavity, and the internal step includes first internal step, the orthographic projection of first internal step on chip is staggered with effective element area and reference element area, and first internal step is provided with getter structure.This utility model is provided with first internal step on the inner wall of transition ring, and the orthographic projection of first internal step on chip is staggered with effective element area and reference element area on chip, by being arranged on the first internal step with getter structure, the influence of the heat release when getter activates to effective element and reference element can be reduced.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This utility model belongs to the field of infrared detector technology, and specifically relates to an infrared detector chip packaging structure. Background Technology

[0002] The packaging structure of an infrared detector chip mainly includes a chip, a transition ring, and a window. The chip and transition ring, as well as the transition ring and window, are hermetically bonded using solder to form a sealed package cavity. In addition to effective elements used for imaging, infrared chips typically also include reference elements and blind elements to correct for non-uniformity. To prevent infrared radiation from interfering with the reference function of these non-effective elements, a light-blocking layer needs to be fabricated on top of them. However, directly fabricating the light-blocking layer on the window using micro / nano fabrication processes such as photolithography, deposition, and etching presents challenges due to its complex process steps and high cost.

[0003] One improvement involves creating a step on the inner wall of the transition ring corresponding to the region of the non-active element to shield the reference element from infrared radiation. This approach not only simplifies the chip manufacturing process and reduces production costs, but also allows the step to hold the getter, maintaining the vacuum level within the package cavity. However, the getter releases a significant amount of heat during the power-on activation process. This heat is conducted downwards through the step to the surface of the non-active element on the chip, potentially affecting or even damaging the reference element. Utility Model Content

[0004] In order to overcome the shortcomings of the existing technology, the purpose of this utility model is to provide an infrared detector chip packaging structure that can at least solve some of the problems of the existing technology.

[0005] To achieve the above objectives, the technical solution of this utility model is an infrared detector chip packaging structure, comprising a chip, a transition ring, and a window stacked sequentially, wherein the chip, the transition ring, and the window are welded to form a packaging cavity; the chip is provided with an effective element region and a reference element region; the inner wall of the transition ring is provided with an internal step protruding into the packaging cavity, the internal step including a first internal step, the orthographic projection of the first internal step on the chip being offset from the effective element region and the reference element region, and a getter structure is provided on the first internal step.

[0006] As one implementation method, the first internal step and the reference element region are respectively disposed on opposite sides of the effective element region.

[0007] As one embodiment, the getter structure is provided at least one of the top surface, bottom surface, and side surface of the first internal step.

[0008] As one implementation, the internal step further includes a second internal step, the orthographic projection of which covers the reference element region on the chip.

[0009] As one embodiment, a groove is provided on the bottom surface of the second internal step, and the reference element area is located below the groove; a getter structure is provided on the top surface of the second internal step at the position corresponding to the groove.

[0010] As one implementation, the transition ring, the first internal step, and the second internal step together enclose a light-transmitting hole, and the center of the effective element region is located on the central axis of the light-transmitting hole.

[0011] As one embodiment, an external support is provided on the outer wall of the transition ring, and an external electrode corresponding to each getter structure is provided on the external support, and the external electrode is electrically connected to the corresponding getter structure.

[0012] As one embodiment, the getter structure includes an internal electrode and a getter disposed on the internal electrode. The internal electrode is disposed on the first internal step or the second internal step, and the internal electrode is connected to the corresponding external electrode.

[0013] As one implementation method, the external support, the internal step, and the transition ring are integrally formed.

[0014] As one embodiment, a second welding area is provided on the top surface of the transition ring, and a barrier structure is provided between the second welding area and the external electrode to prevent solder from overflowing from the window and the second welding area to the external electrode.

[0015] Compared with the prior art, the beneficial effects of this utility model are as follows: (1) The present invention provides a first internal step on the inner wall of the transition ring and makes the orthographic projection of the first internal step on the chip offset from the effective element area and the reference element area on the chip. By arranging the getter structure on the first internal step, the influence of the heat released when the getter is activated on the reference element can be reduced. (2) The present invention also provides a second internal step on the inner wall of the transition ring, and makes the orthographic projection of the second internal step on the chip cover the reference element area, which can shield the reference element from infrared radiation, and also make the infrared detector chip optically equidistant and the imaging more uniform; at the same time, a groove is provided on the bottom surface of the second internal step corresponding to the reference element area, and a getter structure is provided on the top surface of the second internal step corresponding to the groove. This can not only increase the getter area and improve the vacuum degree in the encapsulation cavity after activation, thereby improving the product performance, but also the groove can increase the distance between the getter and the non-effective element, and reduce the influence of the getter activation heat on the reference element. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an infrared detector chip packaging structure provided in an embodiment of this utility model; Figure 2 A schematic diagram of another infrared detector chip packaging structure provided in this embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the window provided in an embodiment of the present utility model; Figure 4 A schematic diagram of the chip structure provided in an embodiment of this utility model; Figure 5 A schematic diagram of the transition ring provided in an embodiment of this utility model; In the diagram: 1. Window; 11. First soldering area; 12. Light-transmitting area; 2. First solder bonding layer; 3. Getter; 4. Transition ring; 41. Second soldering area; 42. Fourth soldering area; 43. Internal electrode; 44. External electrode; 45. First internal step; 46. Second internal step; 47. External support; 48. Groove; 5. Chip; 51. Third soldering area; 52. Effective element area; 53. Reference element area; 6. Second solder bonding layer. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present utility model.

[0019] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0021] like Figure 1 As shown, this embodiment provides an infrared detector chip packaging structure, including a chip 5, a transition ring 4, and a window 1 stacked sequentially. The chip 5, the transition ring 4, and the window 1 are welded to form a packaging cavity. The chip 5 has an effective element region 52 and a reference element region 53. The inner wall of the transition ring 4 has an internal step protruding into the packaging cavity. The internal step includes a first internal step 45. The orthographic projection of the first internal step 45 on the chip 5 is offset from the effective element region 52 and the reference element region 53, and a getter structure is disposed on the first internal step 45. In this embodiment, the first internal step 45 is disposed on the inner wall of the transition ring 4, and the orthographic projection of the first internal step 45 on the chip 5 is offset from the effective element region 52 and the reference element region 53 on the chip 5. By arranging the getter structure on this first internal step 45, the impact of the heat released when the getter 3 is activated on the effective and reference elements can be reduced.

[0022] Preferably, the first internal step 45 and the reference element region 53 are respectively disposed on opposite sides of the effective element region 52. By disposing the first internal step 45 and the reference element region 53 on opposite sides of the effective element region 52, the impact of heat released during activation of the getter 3 on the effective element and the reference element can be further reduced.

[0023] Furthermore, at least one of the top, bottom, and side surfaces of the first internal step 45 is provided with the getter structure. In this embodiment, the getter structure on the first internal step 45 can be arranged at least one of its top, bottom, and side surfaces, with flexible positioning and not limited by the size of the chip 5. The area of ​​the getter 3 can be increased without increasing the package size, thereby improving the vacuum maintenance capability and getter capacity of the cavity.

[0024] In some embodiments, the internal step further includes a second internal step 46, the orthographic projection of which covers the reference element region 53 on the chip 5. By placing the reference element region 53 directly below the second internal step 46, the shielding effect of the second internal step 46 isolates interference from non-target signals such as infrared radiation and stray light, thereby improving the calibration effect of non-effective elements and further enhancing the detection accuracy of effective elements. Furthermore, it eliminates the need for additional metal fabrication, light-absorbing films, or silicon strip arrangements on the chip 5, simplifying the design and manufacturing process of the chip 5. The reference element region 53 is equipped with optical reference elements and / or thermal short reference elements, and can also be equipped with blind elements. By using the second internal step 46 to shield the optical reference elements, the interference of infrared radiation can be eliminated, so that its output only reflects the inherent noise of the optical system and the background interference of the calibrated effective elements can be eliminated. By using the second internal step 46 to shield the thermal short reference elements, the additional heat input of stray light can be avoided, so that the temperature of the thermal short reference elements after shielding is completely determined by the substrate of chip 5, making the output more stable and improving the accuracy of temperature drift compensation. By using the second internal step 46 to shield the blind elements, infrared radiation can be shielded, avoiding the interference of infrared radiation with its reference function, and more accurately compensating for the process non-uniformity of the effective elements.

[0025] like Figure 2 As shown, furthermore, a groove 48 is provided on the bottom surface of the second internal step 46, and the reference element region 53 is located below the groove 48; a getter structure is provided on the top surface of the second internal step 46 at the position corresponding to the groove 48. The reference element region 53 is located directly below the groove 48 on the bottom surface of the second internal step 46, and a getter structure is provided on the top surface of the second internal step 46 at the position corresponding to the groove 48. This not only further increases the area of ​​the getter 3, allowing it to fully absorb internal gas after activation and achieve a good high vacuum effect, enabling the product to perform better under high vacuum, thereby improving the long-term reliability of the device, but also the groove 48 increases the thermal conduction distance between the getter 3 and the non-effective element, reducing the impact of the activation heat of the getter 3 on the reference element.

[0026] Furthermore, the transition ring 4, the first internal step 45, and the second internal step 46 together enclose a light-transmitting aperture, and the center of the effective element region 52 is located on the central axis of the light-transmitting aperture. The first internal step 45 and the second internal step 46 block the field of view of the effective element region 52 from the side with the larger light transmission distance of the light-transmitting area 12 on the window 1, so that the center of the effective element region 52 is located on the central axis of the light-transmitting aperture. This compensates for the asymmetry in the light transmission distance caused by the chip 5's design layout limitations, resulting in symmetrical light transmission distances around the effective element region 52 and consistent field of view angles, further improving the imaging effect, making the imaging more uniform, and the output more stable. In one embodiment, the light-transmitting aperture and the effective element region 52 have the same shape, the effective element region 52 is located within the orthographic projection range of the light-transmitting aperture on the chip 5, and the distance between the outer periphery of the effective element region 52 and the outer periphery of the light-transmitting aperture is consistent. Therefore, the field of view angles at various positions on the outer periphery of the effective element region 52 are consistent.

[0027] In some embodiments, an external support 47 is provided on the outer wall of the transition ring 4, and an external electrode 44 corresponding to each getter structure is provided on the external support 47, and the external electrode 44 is electrically connected to the corresponding getter structure. By energizing the external electrode 44 of the welded encapsulation structure, the getter structure is activated, thereby activating the getter 3. The getter material is heated by electricity and performs its gettering function, absorbing the residual gas in the encapsulation cavity, thereby maintaining a high vacuum inside the encapsulation cavity. The external electrode 44 can be formed by printing metal material on the surface of the external support 47 or by brazing metal electrode sheets.

[0028] In this embodiment, the getter structure includes an internal electrode 43 and a getter 3 disposed on the internal electrode 43. The internal electrode 43 is disposed on the first internal step 45 or the second internal step 46, and the internal electrode 43 is connected to the corresponding external electrode 44. The internal electrode 43 is a metal electrode, and its material includes, but is not limited to, Kovar metal 4J42 and Kovar metal 4J29. It can be formed by welding electrode sheets or printing or electroplating metal solder. The getter 3 is welded and fixed to the internal electrode 43. The getter 3 can be made of getter materials such as barium aluminum alloy, zirconium vanadium iron, and zirconium aluminum. The two ends of each getter 3 are respectively disposed on two internal electrodes 43, and the two internal electrodes 43 are respectively connected to two external electrodes 44.

[0029] Preferably, the outer support 47, the inner step, and the transition ring 4 are integrally formed. By integrally forming the outer support 47, the inner step, and the transition ring 4, the processing technology can be simplified, processing costs can be reduced, and the processing cycle can be shortened, so as to facilitate mass production.

[0030] In one embodiment, the outer support 47, the inner step, and the transition ring 4 can be integrally formed by sintering ceramic powder, with metal wires embedded within them. In another embodiment, the outer support 47, the inner step, and the transition ring 4 can be integrally formed by stacking and sintering multi-layered ceramic substrates, with metal wires embedded between the substrates of the outer support 47, the inner step, and the transition ring 4. The inner electrode 43 is brazed to a designated position on the transition ring 4 by printing metal paste onto the ceramic surface of the welding area of ​​the transition ring 4, the inner electrode 43 area on the inner step, and the outer electrode 44 area on the outer support 47, followed by nickel and gold plating. Alternatively, metal paste can be printed onto the ceramic surface of the outer electrode 44 area on the outer support 47 in the welding area of ​​the transition ring 4, and the inner electrode 43 is integrally formed on the inner step through high-temperature co-firing. Finally, after processes such as cutting and degassing, a single transition ring 4 product is formed. The ceramic materials used include commonly used grades such as 92% alumina and 95% alumina. These materials are not only reliable in strength and technically stable, but also facilitate the embedding of metal wires, making them simple to manufacture and inexpensive. They can replace both metal and ceramic housings, reducing packaging costs. An internal wiring design using a transition ring 4 connects the two ends of the metal wire to the internal electrode 43 in the getter structure within the packaging cavity and the external electrode 44 outside the packaging cavity, respectively. This achieves conductivity between the internal and external electrodes 43. The structure is simple and low-cost. Furthermore, when the external electrode 44 is energized, the internal electrode 43 is energized through the metal wire, thereby activating the internal getter 3.

[0031] Furthermore, a second welding area 41 is provided on the top surface of the transition ring 4. A barrier structure is provided between the second welding area 41 and the external electrode 44 to prevent the solder between the window 1 and the second welding area 41 from overflowing to the external electrode 44. This can effectively prevent the solder on the second welding area 41 from overflowing to the external electrode 44 in a high-temperature molten state, prevent the second welding area 41 from short-circuiting with the external electrode 44, and further improve the yield of infrared chip packaging.

[0032] As one implementation, the barrier structure is a stepped structure. Specifically, the top surface of the outer support 47 can be lowered to below the top surface of the transition ring 4 or raised to above the top surface of the transition ring 4. Alternatively, the area on the top surface of the outer support 47 where the outer electrode 44 is located and its adjacent area can be lowered to below the top surface of the transition ring 4 or raised to above the top surface of the transition ring 4. This forms a stepped structure between the second welding area 41 and the outer electrode 44, increasing the distance between the second welding area 41 and the outer electrode 44, thereby preventing the solder between the second welding area 41 and the window 1 from overflowing to the outer electrode 44 in a high-temperature molten state.

[0033] As another implementation, the barrier structure can be an isolation groove, isolation wall, or barrier area, preventing the solder between the second welding area 41 and the window 1 from directly crossing the isolation groove, isolation wall, or barrier area to contact the external electrode 44 when it melts at high temperature, thus preventing solder overflow and short circuit problems. Specifically, the top surface of the external support 47 is flush with the top surface of the transition ring 4, and the isolation groove, isolation wall, or barrier area is located at the junction of the two. It can be arranged along the entire length of the external support 47, or in segments along the length of the external support 47, with the length of each segment completely covering the length range of the external electrode on one side. The barrier area can be a solder barrier area or an insulating paste area, which can play a good barrier role, thereby preventing solder overflow without reducing or increasing the height difference.

[0034] The transition ring 4 in this embodiment has a simple structure, is easy to manufacture, and is inexpensive. The window 1 and chip 5 can be connected together by vacuum soldering, achieving wafer-level packaging of the infrared detector chip 5. This also increases the distance between the window 1 and chip 5, reducing imaging dark spots caused by minor defects and dust particles on the surface of the window 1. Furthermore, the transition ring 4 has no redundant structure and its size is close to that of the chip 5, allowing for the use of a smaller window 1, thus reducing the final package size. The structure of the transition ring 4 can be specifically adjusted according to the specifications of the chip 5 and design requirements, including but not limited to the structure shown in the attached figures.

[0035] like Figure 3 As shown, in some embodiments, the window 1 is provided with a light-transmitting area 12 and a first welding area 11 arranged around the light-transmitting area 12. A second welding area 41 is provided at the top of the transition ring 4. The first welding area 11 and the second welding area 41 are welded together by a first solder connection layer 2. The center of the window 1 is the light-transmitting area 12, which allows light to pass through and illuminate the effective element area 52 of the chip 5. The first welding area 11 is a ring structure arranged around the light-transmitting area 12, which is welded to the transition ring 4 by the first solder connection layer 2. Specifically, the substrate material of the window 1 can be silicon, germanium, or zinc selenide, etc.; the first welding area 11 is formed by plating a metal material on the substrate of the window 1 to form a metal plating layer. The metal material can be Cr, Ni, Au, etc.

[0036] Preferably, the surface of the light-transmitting area 12 is provided with an infrared anti-reflection structure. Specifically, the infrared anti-reflection structure can be provided on the window 1 substrate on the top and / or bottom surface of the light-transmitting area 12 to increase the infrared light transmittance, thereby improving the sensitivity of the detector. The infrared anti-reflection structure can be achieved by depositing anti-reflection films such as ZnS, AlF3, and MgF2 on the window 1 substrate, or by micro-etching micro-surface structures on the window 1 substrate to increase the transmittance of the window 1.

[0037] like Figure 4As shown, in some embodiments, a ring-shaped third welding area 51 is also provided on the chip 5, and the effective element region 52 and the reference element region 53 are both located within the area enclosed by the third welding area 51; a fourth welding area 42 is provided at the bottom of the transition ring 4, and the third welding area 51 and the fourth welding area 42 are welded together by a second solder connection layer 6. The effective element region 52 is arranged in the middle and is used to receive thermal radiation projected from the object and convert the optical signal into an electrical signal; the reference element region 53, which is arranged on one side of the effective element region 52, has the same structure as the effective element region 52, but cannot receive infrared radiation from the target outside due to the obstruction of the second internal step 46, and is used to correct and improve the imaging quality. Specifically, the third welding area 51 is formed by plating a metal material on the chip 5 to form a metal coating, and the metal material includes, but is not limited to, Cu / Ni / Au, Cu / Ni / Au / Sn and Cu / Ni / Sn.

[0038] like Figure 5 As shown, in this embodiment, the second welding area 41 and the fourth welding area 42 are formed by plating metal material on the top and bottom surfaces of the transition ring 4. The metal material can be Ni / Au. The first welding area 11 and the second welding area 41 are hermetically welded through the first solder connection layer 2, and the third welding area 51 and the fourth welding area 42 are hermetically welded through the second solder connection layer 6, thereby forming a vacuum encapsulation cavity with good hermetical tightness. The first solder connection layer 2 and the second solder connection layer 6 can be made of metallic solder, including but not limited to indium silver solder, gold-tin solder, and tin-silver-copper solder.

[0039] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. An infrared detector chip packaging structure, comprising a chip, a transition ring, and a window stacked sequentially, wherein the chip, the transition ring, and the window are welded to form a packaging cavity; the chip is provided with an effective element region and a reference element region; characterized in that: The inner wall of the transition ring is provided with an internal step that protrudes into the packaging cavity. The internal step includes a first internal step. The orthographic projection of the first internal step on the chip is offset from the effective element region and the reference element region. The first internal step is provided with a getter structure.

2. The infrared detector chip packaging structure as described in claim 1, characterized in that: The first internal step and the reference element region are respectively located on opposite sides of the effective element region.

3. The infrared detector chip packaging structure as described in claim 1, characterized in that: The getter structure is provided at least one of the top surface, bottom surface, and side surface of the first internal step.

4. The infrared detector chip packaging structure as described in claim 1, characterized in that: The internal step also includes a second internal step, the orthographic projection of which covers the reference element region on the chip.

5. The infrared detector chip packaging structure as described in claim 4, characterized in that: A groove is provided on the bottom surface of the second internal step, and the reference element area is located below the groove; a getter structure is provided on the top surface of the second internal step at the position corresponding to the groove.

6. The infrared detector chip packaging structure as described in claim 4, characterized in that: The transition ring, the first internal step, and the second internal step together enclose a light-transmitting aperture, and the center of the effective element region is located on the central axis of the light-transmitting aperture.

7. The infrared detector chip packaging structure as described in claim 5, characterized in that: An external support is provided on the outer wall of the transition ring, and an external electrode corresponding to each getter structure is provided on the external support. The external electrode is electrically connected to the corresponding getter structure.

8. The infrared detector chip packaging structure as described in claim 7, characterized in that: The getter structure includes an internal electrode and a getter disposed on the internal electrode. The internal electrode is disposed on the first internal step or the second internal step, and the internal electrode is connected to the corresponding external electrode.

9. The infrared detector chip packaging structure as described in claim 7, characterized in that: The external support, the internal step, and the transition ring are integrally formed.

10. The infrared detector chip packaging structure as described in claim 7, characterized in that: A second welding area is provided on the top surface of the transition ring, and a barrier structure is provided between the second welding area and the external electrode to prevent solder from overflowing from the window and the second welding area to the external electrode.