Perovskite cells on silicon wafers and their applications

Abstract

The application belongs to the technical field of photovoltaics, and provides a silicon wafer and a perovskite cell using the same. The silicon wafer comprises: a plurality of peak structures, the plurality of peak structures are located on a surface of the silicon wafer, each peak structure comprises a peak top region and a slope region, and the plurality of peak structures are arranged periodically; and a platform region, which is located at a position other than the plurality of peak structures on the surface of the silicon wafer. The surface of the silicon wafer has a pyramid morphology, the pyramid morphology covers the peak structures and the platform region, the pyramid morphology comprises a plurality of pyramids, and at least part of the plurality of pyramids are small-textured pyramids, and the height range of the small-textured pyramids is 0.225 microns to 1.8 microns.

Description

Technical Field

[0001] This application relates primarily to the field of photovoltaic technology, and in particular to a silicon wafer and its application in perovskite solar cells. Background Technology

[0002] Currently, photovoltaic power generation materials are mainly based on monocrystalline silicon, and monocrystalline silicon solar cells have advantages such as high photoelectric conversion efficiency, mature technology, and high reliability. In the process of fabricating crystalline silicon solar cells, the textured surface structure can reduce optical reflection loss and increase light absorption. The quality of the textured pyramid affects the performance and stability of the cell, especially in perovskite-crystalline silicon tandem cells at both ends, where the texture of the front surface plays a crucial role in the deposition of the perovskite film. Utility Model Content

[0003] The technical problem to be solved by this application is to provide perovskite solar cells with silicon wafers and their applications, which can improve the quality of silicon wafers and further improve the performance of perovskite solar cells.

[0004] To address the aforementioned technical problems, this application provides a silicon wafer comprising: multiple mountain peak structures located on the surface of the silicon wafer, each mountain peak structure including a peak area and a slope area, and the multiple mountain peak structures being arranged periodically; and a platform region located on the surface of the silicon wafer outside the multiple mountain peak structures; wherein the surface of the silicon wafer has a pyramidal morphology, the pyramidal morphology covering the mountain peak structures and the platform region, the pyramidal morphology including multiple pyramids, at least a portion of which are small textured pyramids, the height of which ranges from 0.225 micrometers to 1.8 micrometers.

[0005] Optionally, the height of the small velvet pyramid ranges from 0.5 micrometers to 1.6 micrometers.

[0006] Optionally, the slope angle of the slope zone is less than or equal to 15 degrees.

[0007] Optionally, in at least one cross-section of the mountain structure, the peak region includes a peak apex or a peak segment, and the mountain structure includes a first side and a second side opposite to each other with the center point of the peak apex or the peak segment as the boundary, wherein the first side and the second side are asymmetrical.

[0008] Optionally, the slope angle of the mountain structure in the slope zone of the first side and the second side is greater than or equal to 0 degrees and less than or equal to 7 degrees.

[0009] Optionally, the vertical line connecting the peak or the center point to the plane containing the platform area is a height difference line, and the length of the height difference line is less than or equal to 1.5 micrometers.

[0010] Optionally, the small velvet pyramid includes a plurality of pyramids located on the slope area, wherein in at least one cross-section of the mountain structure, the pyramid has a first side and a second side of a triangle, the first side having a first side length and the second side having a second side length, wherein, in at least a portion of the plurality of pyramids located on the slope area: the first side length is greater than the second side length; and the ratio of the first side length to the second side length is greater than or equal to 1 and less than or equal to 1.5.

[0011] Optionally, the silicon wafer surface has one or more detectable regions, the detectable regions including at least one of the mountain peak structures and at least a localized platform region, wherein the number of the small velvety pyramids in the detectable regions accounts for 75% or more of the total number of the plurality of pyramids.

[0012] Optionally, the detectable area includes a field of view of 60mm~80mm*45mm~65mm under 100x magnification of an optical microscope.

[0013] Optionally, the number of the plurality of pyramids included in the field of view is greater than or equal to 900.

[0014] Another aspect of this application proposes a perovskite solar cell, comprising: a silicon wafer as described in any embodiment of this application; and a perovskite layer located on the silicon wafer.

[0015] Compared with the prior art, this application has the following advantages: This application improves the silicon wafer surface with a mountain peak structure by setting small textured pyramids with a specific numerical range on the silicon wafer surface with a mountain peak structure, thereby improving the quality of the silicon wafer and thus improving the performance of the photovoltaic cells subsequently prepared. Attached Figure Description

[0016] The accompanying drawings are included to provide a further understanding of this application. They are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application.

[0017] Figure 1 This is a cross-sectional schematic diagram of a silicon wafer according to some embodiments of this application;

[0018] Figure 2 This is a flowchart of a silicon wafer processing method according to some embodiments of this application;

[0019] Figure 3 This is a top-view SEM (scanning electron microscope) image of the surface morphology of a conventional silicon wafer in existing technology;

[0020] Figure 4This is a top-view SEM image of the surface morphology of a silicon wafer according to one embodiment of this application;

[0021] Figure 5 This is a SEM image of a platform region in the surface morphology of a silicon wafer according to one embodiment of this application;

[0022] Figure 6 This is a SEM image of the mountain peak structure in the surface morphology of a silicon wafer before the small textured surface preparation in one embodiment of this application;

[0023] Figure 7 This is a cross-sectional SEM image of the mountain-shaped structure on the surface morphology of a silicon wafer after a fine textured surface preparation, according to an embodiment of this application.

[0024] Figure 8 This is a SEM image of a portion of the improved silicon wafer in the tandem solar cell under test in Embodiment 1 of this application.

[0025] Figure 9 This is a SEM image of a portion of the stacked battery under test in Embodiment 1 of this application.

[0026] Figure 10 This is a SEM image of a section of the comparative silicon wafer in the comparative tandem solar cell of Comparative Example 1 of this application.

[0027] Figure 11 This is a SEM image of a portion of the comparative stacked battery of Comparative Example 1 of this application, viewed from a cross-sectional perspective. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the application will be described in further detail below with reference to the accompanying drawings. The specific operating methods and functional descriptions in the method embodiments can also be applied to the device embodiments or system embodiments.

[0029] The first aspect of this application refers to Figure 1 A silicon wafer 10 is proposed, which includes multiple peak structures 100. Figure 1 A cross-sectional schematic diagram of a silicon wafer 10, including a portion of the mountain peak structure 100, is shown. According to... Figure 1Multiple peak structures 100 are located on the silicon wafer surface 11 of the silicon wafer 10. Each peak structure 100 includes a peak region 101 and a slope region 102, and the multiple peak structures 100 are periodically arranged on the silicon wafer surface 11. In addition, the silicon wafer 10 also has a platform region 200 located outside the multiple peak structures 100 on the silicon wafer surface 11. In some cases, the formation of the peak structures 100 may be due to periodic lines generated during machine cutting of the wafer raw material of the silicon wafer 10. Since these lines are difficult to avoid, embodiments of this application reprocess the silicon wafer surface structure with these lines to overcome the defective effects of these lines on battery performance.

[0030] Preferably, the silicon wafer surface 11 has a pyramidal morphology, which covers the mountain peak structure 100 and the platform region 200. This pyramidal morphology includes multiple pyramids, and at least a portion of these pyramids are small textured pyramids with a height ranging from 0.225 micrometers to 1.8 micrometers. Figure 1 To more clearly illustrate the surface morphology of the silicon wafer 10, the full pyramid shape is not shown; only a portion of the small textured pyramids 105 located on the slope area 102 are schematically shown. In practical applications, the silicon wafer surface 11 of the silicon wafer 10 can be covered with multiple pyramids, either entirely or in most areas.

[0031] According to the research findings of the inventors of this application, when the height of multiple pyramids in the pyramid textured surface of a silicon wafer is generally greater than 1.8 μm, if perovskite solar cells or perovskite-silicon tandem solar cells are continued to be prepared based on such silicon wafers, due to the uneven deposition of perovskite materials, defects such as pinholes and incomplete coverage are more likely to occur, which can easily lead to problems such as battery leakage, current mismatch and increased series resistance, ultimately resulting in a significant reduction in the efficiency and yield of perovskite solar cells. Figure 1The illustrated implementation effectively solves this problem and ensures the yield of the final perovskite solar cell by controlling the height of the small textured pyramid within the range of 0.225 μm to 1.8 μm. Within this height range, to obtain better cell performance, the height of the small textured pyramid can be controlled within the range of 0.5 μm to 1.6 μm, thereby further improving cell efficiency and yield. In addition, the height of the small textured pyramid can also be set to 0.3 μm, 0.4 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, and 1.7 μm, thus limiting the height of the small textured pyramid to the range of values ​​described above. It is understood that other types of solar cells, not limited to perovskite solar cells, can also be fabricated based on the improved pyramid textured silicon wafer. It should be noted that for the pyramidal morphology on the silicon wafer surface, a smaller textured surface is generally better to facilitate subsequent photovoltaic cell fabrication. However, when the pyramid height is very small, some pyramids disappear, resulting in polished areas on the silicon wafer surface, which is also detrimental to photovoltaic cell fabrication. According to the inventors' experimental verification, when the pyramid height on the silicon wafer surface is less than 0.225 micrometers, the defect rate of the cells increases. Therefore, in the embodiments of this application, the pyramid height is limited to 0.225 micrometers or more. Furthermore, according to the inventors' verification, when the pyramid height is greater than 1.8 micrometers, defective wafers are more likely to occur, as shown in Comparative Example 1 below. Therefore, in the embodiments of this application, the pyramid height is limited to less than or equal to 1.8 micrometers. Within the range of 0.225 micrometers to 1.8 micrometers, a pyramid height of 0.5 micrometers to 1.6 micrometers makes it easier to achieve stable fabrication of subsequent photovoltaic cells, especially perovskite tandem cells. Among these, the range of 0.5 micrometers to 1.1 micrometers can be used to fabricate high-performance perovskite tandem solar cells, as shown in Example 1 below.

[0032] To better understand the structure, another aspect of this application refers to... Figure 2A silicon wafer processing method 20 is shown, comprising the following steps: Step S1 is to obtain a raw silicon wafer, and perform a first cleaning and a first texturing process on the raw silicon wafer to obtain a first silicon wafer intermediate; Step S2 is to perform a second cleaning and polishing on the first silicon wafer intermediate to obtain a second silicon wafer intermediate; and Step S3 is to perform a third cleaning and a second texturing process on the second silicon wafer intermediate to obtain a completed silicon wafer. In this embodiment, the completed silicon wafer includes multiple peak structures and platform regions. The multiple peak structures are located on the surface of the silicon wafer, and the peak structures include a peak area and a slope area. The multiple peak structures are arranged periodically. The platform regions are located on the surface of the silicon wafer outside the multiple peak structures. The silicon wafer surface has a pyramidal morphology, which covers the peak structures and platform regions. The pyramidal morphology includes multiple pyramids, at least a portion of which are small textured pyramids with a height ranging from 0.225 micrometers to 1.8 micrometers. As an example, in one embodiment of this application, the SEM image of the second silicon wafer intermediate obtained in step S2 is shown below. Figure 6 As shown, the top-view SEM image of the fabricated silicon wafer obtained in step S3 is as follows. Figure 4 As shown, the cross-sectional view is as follows Figure 5 and Figure 7 As shown. It should also be noted that flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0033] More preferably, the first texturing step S1 further includes the following specific process conditions: the first texturing is performed using a mixed solution comprising an alkaline solution, an additive, and water, wherein the volume ratio of the alkaline solution, the additive, and water is 3-4:1:155-175, and the additive includes alcohol additives and surfactants. More preferably, the alcohol additives include isopropanol or ethanol; and / or the surfactants include sodium dodecylbenzenesulfonate or polyethylene glycol. In this way, the initial texturing process on the surface of the raw silicon wafer can achieve better results, thereby preparing for subsequent polishing and texturing processes.

[0034] Further preferably, in the above processing method 20, as a preferred implementation, the surface of the first silicon wafer intermediate in step S1 has a first pyramid textured surface, the first pyramid textured surface including a first base, the base of the first base having a range of 1.5μm to 7μm. Further, in step S2, the second silicon wafer intermediate has a second base at a position corresponding to the first base, the base of the second base having a range of 15μm to 30μm. By controlling the numerical range of the second base, the surface flatness of the second silicon wafer intermediate can be high, facilitating the obtaining of a uniform small textured surface morphology in the subsequent texturing process in step S3. This means that, in the preferred embodiment, by controlling the process conditions of steps S1 and S2, such as the polishing time in step S2, the base range of the pyramid textured surface in each step can meet certain numerical range requirements, thereby ultimately obtaining a silicon wafer with a small textured pyramid having a pyramid height range of 0.225μm to 1.8μm. Preferably, the polishing time in step S2 can be set to 30 seconds to 240 seconds. More preferably, controlling the roughness of the second intermediate part to a profile arithmetic mean deviation Ra of less than 300 nm can achieve better subsequent texturing effects and reduce the reflectivity of the silicon wafer surface to below 10%. In this embodiment, processing method 20 obtains a large tower base through a single texturing and polishing process, reducing the slope angle and height of the silicon wafer peak structure, improving the flatness of the silicon wafer, and obtaining a uniform low-reflectivity textured surface through subsequent texturing. This approach can make the surface properties of the silicon wafer (such as reflectivity) more superior, which is beneficial for the subsequent fabrication of photovoltaic cells.

[0035] As a contrasting illustration, Figure 3 This shows an SEM image of a silicon wafer taken according to the prior art. Figure 4 This application is based on Figure 1 The SEM image of the silicon wafer obtained in the illustrated embodiment. Figure 3 and Figure 4 A comparison clearly shows that the silicon wafer proposed in this application has a more uniform pyramidal morphology on its surface, while... Figure 3 In some locations, the pyramids exhibit noticeable defects such as uneven size and tilted positions. Based on Figure 3 The silicon wafers shown are difficult to further process into photovoltaic cells, often resulting in high defect rates. For example, refer to... Figure 5 This application is based on Figure 1 The cross-sectional image of the silicon wafer obtained in the illustrated embodiment, taken under a scanning electron microscope. Figure 5 The topography of the small velvety pyramid on platform region 200 is shown. According to... Figure 5 It can be seen that the pyramidal morphology on the surface of the silicon wafer is uniform, which is beneficial for the subsequent fabrication of photovoltaic cells.

[0036] To avoid ambiguity, a method for obtaining the slope angle applicable to this application is presented below. (Refer to...) Figure 1 In a cross-section including the mountain peak structure 100, the mountain peak structure 100 includes a peak region 101 in Figure 1 The center point of the peak section shown in the cross-section is the first side 111 and the second side 112, which are opposite to the boundary. It should be noted here that... Figure 1 The peak area 101, slope area 102, and plateau area 200 marked in the cross-section are actually the peak area, slope area, and plateau area in three-dimensional space. Figure 1 The intersection of the cross-sections. In this embodiment, the peak region 101 of each mountain structure 100 is presented as a peak segment. It can be understood that, depending on the different morphologies of the peak region or the different locations selected for the cross-section, the peak region can also be presented as the apex of the peak; that is, in a specified cross-section, the peak region presents the intersection point of the peak region in three-dimensional space and the specified cross-section. Figure 1 Taking the peak section shown as an example, in the first side 111, the boundary between the platform area 200 and the slope area 102 is the first boundary point 21. In the second side 112, the boundary between the platform area 200 and the slope area 102 is the third boundary point 23. In both the first and second sides 111 and 112, the boundary between the peak area 101 and the slope area 102 is the second boundary point 22. The line connecting the first boundary point 21 and the second boundary point 22 in the first side 111 is the slope angle marking line of the first side 111, and the line connecting the third boundary point 23 and the second boundary point 22 in the second side 112 is the slope angle marking line of the second side 112. Furthermore, the line connecting the first boundary point 21 and the third boundary point 23 is the extension line of the platform area (or can be understood as the plane where the platform area 200 is located), and the angles between the slope angle marking line and the extension line of the platform area in the first and second sides 111 and 112 are slope angle α and slope angle b, respectively. Figure 1 In the cross-section, both slope angles a and b are less than or equal to 15 degrees. Similarly, if in other embodiments the peak area appears as a apex in the selected cross-section, then connecting the intersection points of the slope areas on both sides and the platform area with this apex will yield the slope angle markings for the first and second sides, and thus the slope angles can be obtained. It is understood that... Figure 1 The accompanying drawings are for illustrative purposes only. To better illustrate the structural details, the angles shown in the drawings for slope angles a and b do not reflect their actual measured values.

[0037] Specifically, to better understand how to determine the bevel angle for a silicon wafer in this application, we first refer to... Figure 6 This is a SEM image of a silicon wafer provided in this application taken before the formation of a small textured surface. According to... Figure 6By selecting the first boundary point 21, the second boundary point 22, and the third boundary point 23 of each of the first and second sides, connecting them, the slope angle markings can be determined and the slope angle value obtained. Figure 6 The slope angle on one side is marked as 14°.

[0038] Furthermore, based on Figure 6 Further preparation of the surface texture yields the aforementioned small-textured pyramid morphology with a gentle slope. Based on this, when... Figure 6 After the silicon wafer surface has a small textured pyramidal morphology, the centroids of multiple pyramids in the pyramidal morphology can be connected first. Then, based on the above reference... Figure 1 The slope angle markings and base plane extension lines are then used to determine the slope angle values. As an example, Figure 7 This paper illustrates the measurement of a silicon wafer with a small textured pyramidal morphology in an SEM image, as provided in this application. It can be seen that... Figure 7 The silicon wafer shown has slope angles of 7.4° and 6.6° on the left and right sides of one of the mountain peak structures, and the length of the gentle slope elevation difference line is 0.89 μm. (The above...) Figures 4-7 The SEM images of the pyramidal morphology of the silicon wafer surface proposed in this application are shown, and the method of obtaining the slope angle by annotating the actual SEM images is given. In different embodiments of this application, the slope angle can be measured by referring to the same method described above.

[0039] Continue to refer to Figure 1 As shown, the first side 111 and the second side 112 of the mountain structure 100 are asymmetrical. More preferably, the smaller of the slope angles a and b in the slope region 102 of the first side 111 and the second side 112 of the mountain structure 100 (i.e., as shown) Figure 1 The slope angle shown is greater than or equal to 0 degrees and less than or equal to 7 degrees. By making the slope angle range from 0 to 15 degrees, or even further from 0 to 7 degrees, the slope of the mountain structure 100 can be made gentler, which facilitates the preparation of the pyramid texture on it, resulting in better uniformity of the final pyramid shape, thereby improving the stability and reliability of the silicon wafer.

[0040] Taking the fabrication of perovskite solar cells based on the aforementioned improved silicon wafers as an example, according to the inventors' experimental verification, when the slope angle is greater than 15 degrees, it is easier to reduce the thickness of the perovskite layer in the sloping region on the slope. Furthermore, perovskite films with a minimum thickness of <150 nm exhibit an "S-shaped inflection point" in their JV curve under AM 1.5 illumination, and the fill factor (FF) decreases by 10%~20%. In flexible devices, locations with slope angles greater than 15 degrees (also considered line marks in related technologies) experience shear stress concentration during bending tests, leading to delamination of the perovskite / hole transport layer (HTL) interface. Therefore, for perovskite solar cells, controlling the slope angle of the mountain-shaped structure as described above can further effectively improve the efficiency and reliability of perovskite solar cells based on the textured surface structure.

[0041] Continue to refer to Figure 1 , Figure 1 The elevation difference line h of the mountain structure 100 is also shown. The elevation difference line h is a perpendicular line connecting the center point and the plane containing the platform region 200. Referring to the preceding text, when the peak region appears as the summit in a selected profile, the elevation difference line is the line connecting the summit and the plane containing the platform region. As based on... Figure 1 In one preferred implementation, the length of the elevation difference line h is less than or equal to 1.5 micrometers. Similar to the slope angle, by controlling the length of the elevation difference line h, the slope height of the mountain structure 100 can be reduced, facilitating the fabrication of the pyramidal textured surface on it. Still taking perovskite solar cells as an example, in subsequent perovskite solar cell fabrication, a gentler, lower mountain structure is beneficial for the stability and reliable coating of the perovskite material, thereby improving the cell performance and product yield of the resulting photovoltaic cells.

[0042] according to Figure 1 The small textured pyramids covering the silicon wafer surface 11 include multiple small textured pyramids 105 located on the slope area 102, in the mountain structure 100, as shown in the image. Figure 1 In the cross-section shown, the pyramid has a first side 103 and a second side 104 of a triangle. The first side 103 has a first side length, and the second side 104 has a second side length. In at least some of the pyramids located on the slope region 102, the first side length is greater than the second side length; the ratio of the first side length to the second side length is greater than 1 and less than or equal to 1.5. It is understood that even without special processing, the pyramid morphology produced in the platform region 200 is generally quite uniform due to its relatively flat surface. By controlling the ratio of the long to short sides of the pyramids located on the slope region 102, the uniformity of the pyramid morphology on the slope region 102 can be effectively improved, thereby improving the quality of the surface pyramid morphology of the silicon wafer 10 and obtaining a more reliable silicon wafer 10 that is easier to fabricate for different types of photovoltaic cells.

[0043] To ensure the quality of the pyramidal morphology on the surface of the silicon wafer 10, preferably, one or more detectable regions can be formed on the silicon wafer surface 11. These detectable regions include at least one peak structure 100 and at least a localized platform region 200. Within the aforementioned detectable regions, small textured pyramids (e.g., those with a textured surface) are formed. Figure 1 The number of small textured pyramids (105) shown accounts for 75% or more of the total number of pyramids. In some embodiments of this application, the detectable area includes a field of view of 60mm~80mm*45mm~65mm under 100x magnification of an optical microscope; specifically, it can be set to a field of view of 69mm*52mm. In a specific detection scenario, if the number of pyramids with a height of 0.3μm~1.5μm is more than 900 within a field of view of 69mm*52mm, then the silicon wafer being detected can be considered to have a uniform pyramid morphology on its surface.

[0044] For example, Figure 3 and Figure 4 The prior art and this application are shown respectively. Figure 1 Images of a portion of the silicon wafer surface as captured by scanning electron microscopy in this embodiment. Figure 3 and Figure 4 The comparison clearly shows that in the existing technology, due to the lack of control over the fabrication process of the small textured pyramids, many of the pyramids are of uneven size and exhibit significant tilting, which is detrimental to the fabrication of perovskite solar cells; while Figure 3 The improved silicon wafer surface 11 shown is mostly composed of small, uniformly sized textured pyramids, resulting in a significant improvement in the surface morphology. In the preferred embodiment described above, by controlling the height of the small textured pyramids within a preferred range, and maintaining a high proportion of optimized small textured pyramids within a certain detectable area, the uniformity of the pyramid morphology on the silicon wafer surface can be improved.

[0045] Based on this, this application proposes a perovskite solar cell, comprising a silicon wafer and a perovskite layer as described in this application, wherein the silicon wafer is, for example, as shown in the image. Figure 1 The silicon wafer 10 shown has a perovskite layer on top in the perovskite solar cell. It is understood that the design of small textured pyramids of a certain size on the silicon wafer surface 11 of the silicon wafer 10 improves the coating effect of the perovskite layer. As mentioned earlier, by controlling the slope angle and other dimensional parameters of the peak structure 100, and ensuring that the number of small textured pyramids within a certain detection area reaches a certain standard, the quality and reliability of the silicon wafer can be further improved, thereby enhancing the performance and yield of the fabricated perovskite solar cell.

[0046] The present invention will be described below by way of specific embodiments. It should be understood that these embodiments are merely illustrative and are not intended to limit the scope of the present invention. Unless otherwise stated, the methods, reagents, and materials used in the embodiments are conventional methods, reagents, and materials in the art. The raw material compounds in the embodiments are all commercially available. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort should fall within the scope of protection of this application.

[0047] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0048] Example 1

[0049] This embodiment describes a perovskite-silicon tandem solar cell (tandem solar cell under test) fabricated using an improved silicon wafer provided in this application, with dimensions of 21cm*10.5cm. The bottom cell of this tandem solar cell is an HJT, and from bottom to top, it consists of a back silver grid line, a TCO layer, a microcrystalline p-silicon layer, an intrinsic passivation layer, a monocrystalline silicon absorber layer (using the improved silicon wafer provided in this application), an intrinsic passivation layer, a microcrystalline n-silicon layer, a TCO composite layer (10nm ITO), a hole transport layer (1nm 4PACz), a perovskite layer (300nm~1.2μm thick FACsMAPbIBr0.25), an electron transport layer (5nm average thickness C60 + 30nm SnO2), a transparent electrode layer (40nm average thickness ITO), and a silver electrode. Before fabricating the tandem solar cell to be tested, five different locations on the improved silicon wafer were randomly selected. Using a 10k resolution scanning electron microscope, the height of the small textured pyramids on the improved silicon wafer was observed to be between 0.5μm and 1.1μm. Based on this, the improved silicon wafer was used to fabricate the tandem solar cell to be tested. A 1cm*1cm local area was selected for each of the five different locations, and these local areas were cut out. Cell tests were performed on these five local areas of the tandem solar cell to obtain the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE values, as shown in Table 1 below.

[0050] Comparative Example 1

[0051] This comparative example is a perovskite-silicon tandem solar cell (comparative tandem solar cell) fabricated using a comparative silicon wafer provided by the prior art. The structure of this comparative tandem solar cell is the same as that of the tandem solar cell under test in Example 1, with dimensions of 21cm*10.5cm. The only difference between Comparative Example 1 and Example 1 is that the monocrystalline silicon absorber layer is made using a comparative silicon wafer. Five different locations on the comparative silicon wafer were randomly selected, and before fabricating the comparative tandem solar cell, the tower height range at these five locations was observed using a 10k resolution scanning electron microscope. All heights were found to be between 1.805μm and 2.1μm. Based on this, a comparative tandem solar cell was fabricated using the comparative silicon wafer. A 1cm*1cm local area was selected corresponding to each of the five different locations, and these local areas were cut out. Cell tests were performed on these five local areas of the comparative tandem solar cell to obtain the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE values, as shown in Table 1 below.

[0052] Table 1:

[0053]

[0054] As can be seen from the comparison in Table 1 above, the observed pyramid heights are relatively small and concentrated when different local locations of the improved silicon wafer proposed in this application are randomly selected. On such a silicon wafer with a uniformly textured surface, perovskite can be deposited uniformly and completely, resulting in a high top-to-bottom current ratio, high final efficiency, and high yield. Therefore, the battery performance values ​​obtained at the five different locations of the tested tandem solar cell in Example 1 are all excellent and stable. Since the five different locations were randomly selected, they can be considered to reliably reflect the overall battery performance level of the entire solar cell. Figure 8 This image shows a localized SEM image taken before the tandem solar cell under test was fabricated using the improved silicon wafer in Example 1. According to... Figure 8 , Figure 8 The heights of the multiple pyramids in the view are 730 nm and 810 nm, all falling within the range of 0.5 μm to 1.1 μm. Furthermore, Figure 9 The SEM image of the tandem solar cell under test, fabricated based on the improved silicon wafer, is shown below. Figure 9 The perovskite layer 312 is located above the monocrystalline silicon absorber layer 310. The interface 311 between the perovskite layer 312 and the monocrystalline silicon absorber layer 310 contains an intrinsic passivation layer, a microcrystalline n-silicon layer, a TCO composite layer, and a hole transport layer. Because these film structures are nanometer-scale in thickness and relatively small, in... Figure 9 The view does not show the distribution of each layer. Based on this, arbitrarily select... Figure 9In the view, at the location of a small textured pyramid 300, it can be seen that the thickness of the perovskite layer 312 is 593 nm from the apex of the pyramid and 1080 nm from the base, demonstrating good coating of the perovskite layer 312. Based on this, to detect whether the height of the pyramid in the tandem solar cell falls within the scope of this application, the attached layer on the silicon wafer can be removed first, and then the accurate height value of the pyramid can be measured. Figure 9 The height of the other pyramids in the view is similar to or smaller than that of the small plush pyramid 300, which reflects the uniformity of the small plush pyramid's shape.

[0055] In contrast, Comparative Example 1 suffers from incomplete perovskite layer coverage and current mismatch, resulting in higher currents in some areas, also due to the current mismatch between the top and bottom cells. At two of the five selected locations, the photoelectric conversion efficiency of the comparative tandem cell in Comparative Example 1 was 13.12% and 14.56%, significantly lower than the other locations. This means that the comparative tandem cell in Comparative Example 1 is unusable and would be discarded in actual production. Figure 10 The image shows a partial cross-sectional view of the comparative silicon wafer of Comparative Example 1 before the comparative tandem solar cell was fabricated. According to... Figure 10 The surface texture of the silicon wafer is quite complex. Since the pyramid shape in the first row of the image is incomplete, four adjacent pyramids (301, 302, 303, and 304) in the second row were selected. The hypotenuse of each pyramid was extended, and the intersection of the extended hypotenuses of two adjacent pyramids was taken as the inflection point. The lower inflection point was selected as the horizontal line, and the apex of the pyramid was drawn perpendicular to the horizontal line to obtain the pyramid height data. Figure 10 The heights of Pyramid 302 are shown to be 2.1 μm and 1.9 μm. It should be noted that the preceding text... Figure 8 The method for measuring the height of the pyramids can also refer to this marking method: select the lowest point of the pyramid's triangle base as a horizontal line and then measure the height. Furthermore, Figure 11 A SEM image of a cross-sectional location of a comparative tandem solar cell fabricated based on a comparative silicon wafer is shown. (Refer to...) Figure 11 The perovskite layer 322 is located above the monocrystalline silicon absorber layer 320. At the interface 321 between the perovskite layer 322 and the monocrystalline silicon absorber layer 320, there is an intrinsic passivation layer, a microcrystalline n-silicon layer, a TCO composite layer, and a hole transport layer. Because these film structures are nanometer-scale in thickness and relatively small, in... Figure 11 The distribution of each layer is not shown in the view. Based on this, Figure 11 It also shows that the perovskite layer 322 is incompletely coated at the location of one of the pyramids. Additionally, it can be seen that... Figure 11The heights of the other pyramids are similar to those of this pyramid. A comparison of Example 1 and Comparative Example 1 shows that controlling the height of the small textured pyramids on the silicon wafer surface within a certain range can improve the yield and stability of the fabricated perovskite solar cells.

[0056] Example 2 (a specific implementation based on processing method 20):

[0057] 1) The original silicon wafer is cleaned for the first time with a solution of H2O2, KOH (concentration of 48%) and H2O, wherein the volume ratio of H2O2, KOH and H2O is 4:1:90, the cleaning time is 2 min to 4 min, and the cleaning temperature is 60℃ to 70℃, in order to remove surface oil and impurities.

[0058] 2) A large textured surface is prepared on both sides of the first silicon wafer intermediate (i.e., the first texturing). The solution used is a mixed solution of KOH (48% concentration), ADD additive, and H2O, wherein the volume ratio of KOH, ADD additive, and H2O is 3.8:1:167. The texturing time is 6-7 minutes, and the texturing temperature is 80℃-82℃ to obtain the first silicon wafer intermediate. This method can effectively reduce silicon wafer line marks and remove damaged layers.

[0059] 3) The first silicon wafer intermediate is then cleaned and polished a second time. The polishing solution (the volume ratio of ADD additive and KOH is 1:13) results in a tower base of 15μm~40μm after polishing, resulting in a flat large tower base silicon wafer surface, which is the second silicon wafer intermediate.

[0060] 4) Finally, after the second silicon wafer intermediate is cleaned for the third time, it is placed in the texturing solution (i.e., the second texturing) to obtain a textured surface morphology of pyramids with a height range of about 0.6 μm, which is the completed silicon wafer.

[0061] Comparative Example 2 (textured morphology of silicon wafer obtained using conventional methods):

[0062] 1) The original silicon wafer is pre-cleaned with a solution of H2O2, KOH (concentration of 48%) and H2O, wherein the volume ratio of H2O2, KOH and H2O is 4:1:90, the cleaning time is 2 min to 4 min, and the cleaning temperature is 60℃ to 70℃, in order to remove surface oil and impurities.

[0063] 2) The pre-cleaned silicon wafer is then cleaned and polished again. The polishing solution (the volume ratio of ADD additive and KOH is 1:13) results in a wafer thickness of 14μm~18μm after polishing.

[0064] 3) Finally, the polished silicon wafer is placed in the texturing solution to obtain the textured surface of the silicon wafer.

[0065] Table 2:

[0066]

[0067] Compared to Example 2, Comparative Example 2 directly polished the silicon wafer without applying step S1 of processing method 20. That is, compared to step S1, Comparative Example 2 only used a single polishing and texturing process followed by steps S2 and S3. It can be seen that after using processing method 20, Example 2, through the pre-preparation of a large textured surface in step S1, significantly increased the overall pyramid base size range after polishing in step S2. Consequently, in the obtained textured surface of the silicon wafer, the proportion of pyramids with a height in the range of 0.525 μm to 0.875 μm exceeded 75%, achieving a uniform and consistent pyramid morphology for the small textured surface. Furthermore, after testing, Table 2 above shows that Example 2 had a smaller surface roughness Ra after the polishing process. Based on this, and building upon the larger pyramid base size and smaller surface roughness, further processing was carried out... Figure 4 The texturing process in step S3 shown can make the silicon wafer finally produced by processing method 20 have the advantage of lower surface reflectivity, thereby improving battery performance.

[0068] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A silicon wafer, characterized in that, include: Multiple mountain peak structures are located on the surface of a silicon wafer. Each mountain peak structure includes a peak area and a slope area, and the multiple mountain peak structures are arranged periodically. The platform region is located outside the multiple mountain-shaped structures on the surface of the silicon wafer; The silicon wafer surface has a pyramid shape, which covers the mountain structure and the platform area. The pyramid shape includes multiple pyramids, at least a portion of which are small textured pyramids. The height of the small textured pyramids ranges from 0.225 micrometers to 1.8 micrometers.

2. The silicon wafer as described in claim 1, characterized in that, The height of the small velvet pyramids ranges from 0.5 micrometers to 1.6 micrometers.

3. The silicon wafer as described in claim 1, characterized in that, The slope angle of the slope zone is less than or equal to 15 degrees.

4. The silicon wafer as described in claim 3, characterized in that, In at least one cross-section of the mountain structure, the peak region includes a peak apex or a peak segment, and the mountain structure includes a first side and a second side opposite to each other with the center point of the peak apex or the peak segment as the boundary, wherein the first side and the second side are asymmetrical figures.

5. The silicon wafer as described in claim 4, characterized in that, The slope angle of the mountain structure in the slope zone of the first side and the second side is greater than or equal to 0 degrees and less than or equal to 7 degrees.

6. The silicon wafer as described in claim 4, characterized in that, The vertical line connecting the peak or center point to the plane containing the platform area is the elevation difference line, and the length of the elevation difference line is less than or equal to 1.5 micrometers.

7. The silicon wafer as described in claim 1, characterized in that, The small velvet pyramids include a plurality of pyramids located on the slope area, wherein in at least one cross-section of the mountain structure, the pyramids have a first side and a second side of a triangle, the first side having a first side length and the second side having a second side length, wherein, in at least a portion of the plurality of pyramids located on the slope area: The length of the first side is greater than the length of the second side; The ratio of the first side length to the second side length is greater than or equal to 1 and less than or equal to 1.

5.

8. The silicon wafer according to any one of claims 1 to 7, characterized in that, The silicon wafer surface has one or more detectable regions, the detectable regions including at least one of the mountain peak structures and at least a localized platform region, wherein the number of the small velvety pyramids in the detectable regions accounts for 75% or more of the total number of the plurality of pyramids.

9. The silicon wafer as described in claim 8, characterized in that, The detectable area includes the field of view of 60mm~80mm*45mm~65mm under 100x magnification of an optical microscope.

10. The silicon wafer as claimed in claim 9, characterized in that, The field of view includes a number of pyramids greater than or equal to 900.

11. A perovskite battery, characterized in that, include: The silicon wafer as described in any one of claims 1 to 10; as well as A perovskite layer is located above the silicon wafer.

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