Light emitting epitaxial wafer and semiconductor light emitting device
Patent Information
- Application Number
- CN202522500209.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2035-11-25
AI Technical Summary
[0036]本申请提供了一种发光外延片和半导体发光器件，在发光外延片的多量子阱层中插入生长第一应力释放层，和/或，在发光外延片的多量子阱层和P型半导体层之间插入生长第二应力释放层，从而通过应力释放而达到减少晶格失配、降低位错密度的目的，保证制备的发光外延片的质量高。在生长应力释放层过程中采用包括氩气的载气，进而能够通过载气带走发光外延片制备过程中解离产生的氢气，以促进应力释放层生长过程中氨气的分解平衡向正向移动，抑制氮空位的生成；而且氩气的原子半径较小，对表面位点的竞争吸附能力较弱，使得应力释放层生长过程中氨气分子直接接触高温衬底并分解，进一步促进氨气的分解反应发生；同时，氢气的减少会降低P型结构掺杂时掺杂元素-H化学键的形成，进而能够提高空穴浓度，达到提升半导体发光器件的发光效率的目的。
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more specifically, to a light-emitting epitaxial wafer and a semiconductor light-emitting device. Background Technology
[0002] Semiconductor light-emitting diodes (LEDs) possess advantages such as small size, robustness, high controllability of emission wavelength, high luminous efficiency, low heat loss, low light decay, energy saving, and environmental friendliness. They are widely used in full-color displays, backlights, signal lights, optoelectronic computer interconnection, and short-range communication, and are gradually becoming a research hotspot in the field of electronic power engineering. Gallium nitride (GaN) materials have a series of advantages, including wide bandgap, high electron mobility, high thermal conductivity, and high stability, thus enjoying wide application and a huge market prospect in high-brightness LEDs. The lighting field is placing increasingly higher demands on LEDs, and improving the luminous efficiency of GaN-based LEDs is one of the main research goals for engineers. Utility Model Content
[0003] In view of this, this application provides a light-emitting epitaxial wafer, a method for preparing the same, and a semiconductor light-emitting device, which effectively solves the technical problems existing in the prior art, ensures high quality of the prepared light-emitting epitaxial wafer, improves the luminous efficiency and recombination efficiency of the semiconductor light-emitting device, and optimizes the performance of the semiconductor light-emitting device.
[0004] To achieve the above objectives, the technical solution provided in this application is as follows:
[0005] A light-emitting epitaxial wafer, the light-emitting epitaxial wafer comprising:
[0006] Substrate;
[0007] An N-type semiconductor layer located on one side of the substrate;
[0008] A multi-quantum well layer located on the side of the N-type semiconductor layer away from the substrate, the multi-quantum well layer comprising a potential well layer and a barrier layer stacked alternately in a predetermined period; wherein, in at least one of the periodically stacked potential well layer and the barrier layer: on the side of the potential well layer away from the barrier layer, and / or on the side of the potential well layer facing the barrier layer, a first stress relief layer is formed based on a carrier gas comprising at least argon;
[0009] A P-type semiconductor layer located on the side of the multi-quantum well layer facing away from the substrate;
[0010] Alternatively, the light-emitting epitaxial wafer may include:
[0011] Substrate;
[0012] An N-type semiconductor layer located on one side of the substrate;
[0013] A multi-quantum well layer located on the side of the N-type semiconductor layer away from the substrate, the multi-quantum well layer comprising a potential well layer and a barrier layer stacked alternately with a predetermined period;
[0014] Located on the side of the multi-quantum-well layer opposite to the substrate, a second stress-relieving layer is formed based on a carrier gas including at least argon.
[0015] A P-type semiconductor layer located on the side of the second stress relief layer facing away from the substrate;
[0016] Alternatively, the light-emitting epitaxial wafer may include:
[0017] Substrate;
[0018] An N-type semiconductor layer located on one side of the substrate;
[0019] A multi-quantum well layer located on the side of the N-type semiconductor layer away from the substrate, the multi-quantum well layer comprising a potential well layer and a barrier layer stacked alternately in a predetermined period; wherein, in at least one of the periodically stacked potential well layer and the barrier layer: on the side of the potential well layer away from the barrier layer, and / or on the side of the potential well layer facing the barrier layer, a first stress relief layer is formed based on a carrier gas comprising at least argon;
[0020] A second stress-relieving layer is formed on the side of the multi-quantum well layer opposite to the substrate, based on a carrier gas including at least argon.
[0021] The P-type semiconductor layer located on the side of the second stress relief layer opposite to the substrate.
[0022] Optionally, when the light-emitting epitaxial wafer includes the first stress-relieving layer, the first stress-relieving layer is an AlInN stress-relieving layer;
[0023] When the light-emitting epitaxial wafer includes the second stress-relieving layer, the second stress-relieving layer is an AlInN stress-relieving layer.
[0024] Optionally, when the light-emitting epitaxial wafer includes the first stress-relieving layer, the thickness of the first stress-relieving layer is 2-10 nm;
[0025] When the light-emitting epitaxial wafer includes the second stress-relieving layer, the thickness of the second stress-relieving layer is 2-10 nm.
[0026] Optionally, the carrier gas is argon or a mixture of argon and nitrogen.
[0027] Optionally, the light-emitting epitaxial wafer further includes:
[0028] At least one of a buffer layer and an unintentionally doped layer is sequentially stacked between the substrate and the N-type semiconductor layer, and along the direction from the substrate to the N-type semiconductor layer.
[0029] Optionally, the unintentionally doped layer includes:
[0030] A 3D layer and a GR layer are sequentially stacked along the direction from the substrate to the N-type semiconductor layer.
[0031] Optionally, the N-type semiconductor layer includes an N-type GaN layer.
[0032] Optionally, the N-type semiconductor layer further includes a low-doped LD layer, wherein the low-doped LD layer is located between the N-type GaN layer and the multiple quantum well layer, and the doping concentration of the low-doped LD layer is less than the doping concentration of the N-type GaN layer.
[0033] Optionally, the light-emitting epitaxial wafer includes a GaN-based light-emitting epitaxial wafer.
[0034] Based on the same inventive concept, this application also provides a semiconductor light-emitting device, which includes the above-mentioned light-emitting epitaxial wafer.
[0035] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:
[0036] This application provides a light-emitting epitaxial wafer and a semiconductor light-emitting device. A first stress-relief layer is grown within the multi-quantum-well layer of the light-emitting epitaxial wafer, and / or a second stress-relief layer is grown between the multi-quantum-well layer and the P-type semiconductor layer of the light-emitting epitaxial wafer. This stress relief reduces lattice mismatch and dislocation density, ensuring high quality of the prepared light-emitting epitaxial wafer. Argon is used as a carrier gas during the growth of the stress-relief layer. This carrier gas carries away hydrogen generated during the fabrication of the light-emitting epitaxial wafer, promoting a positive shift in the ammonia decomposition equilibrium during stress-relief layer growth and suppressing nitrogen vacancy generation. Furthermore, argon's small atomic radius results in weak competitive adsorption at surface sites, allowing ammonia molecules to directly contact and decompose on the high-temperature substrate during stress-relief layer growth, further promoting the ammonia decomposition reaction. Simultaneously, the reduction in hydrogen reduces the formation of -H chemical bonds in the dopant element during P-type doping, thereby increasing the hole concentration and improving the luminous efficiency of the semiconductor light-emitting device.
[0037] Furthermore, during the fabrication of the light-emitting epitaxial wafer, a temperature gradient exists in the growth reaction chamber perpendicular to the carrier disk. Due to the relatively low thermal conductivity of argon, the growth of the first and second stress-relief layers tends to be radial under an argon atmosphere. This facilitates precise control of the stress-relief layer thickness, thereby improving the wave function overlap of charge carriers, enhancing the recombination efficiency of the semiconductor light-emitting device, and optimizing its performance. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0039] Figure 1 A flowchart illustrating a method for preparing a light-emitting epitaxial wafer, as provided in an embodiment of this application;
[0040] Figure 2 A flowchart illustrating another method for preparing a light-emitting epitaxial wafer provided in this application embodiment;
[0041] Figure 3 A flowchart illustrating another method for preparing a light-emitting epitaxial wafer provided in this application embodiment;
[0042] Figures 4 to 7 for Figure 1 A schematic diagram of the corresponding structure for each step in the process;
[0043] Figures 8 to 10 for Figure 2 A schematic diagram of the corresponding structure for the middle part of the steps;
[0044] Figure 11 and Figure 12 for Figure 3 A schematic diagram of the corresponding structure for the middle part of the steps;
[0045] Figure 13 This is a partial stacked diagram of a light-emitting epitaxial wafer provided in an embodiment of this application.
[0046] Figure label:
[0047] 100 - Substrate; 200 - N-type semiconductor layer; 310 - Potential well layer; 320 - Potential barrier layer; 410 - First stress relief layer; 420 - Second stress relief layer; 500 - P-type semiconductor layer; 610 - Buffer layer; 620 - Unintentionally doped layer; Y-direction. Detailed Implementation
[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0049] As described in the background section, semiconductor light-emitting diodes (LEDs) possess advantages such as small size, robustness, high controllability of emission wavelength, high luminous efficiency, low heat loss, low light decay, energy saving, and environmental friendliness. They are widely used in full-color displays, backlights, signal lights, optoelectronic computer interconnection, and short-range communication, and are gradually becoming a research hotspot in the field of electronic power engineering. Gallium nitride (GaN) materials have a series of advantages, including wide bandgap, high electron mobility, high thermal conductivity, and high stability, thus enjoying wide application and a huge market prospect in high-brightness LEDs. The lighting field is placing increasingly higher demands on LEDs, and improving the luminous efficiency of GaN-based LEDs is one of the main research goals for engineers.
[0050] Based on this, the embodiments of this application provide a light-emitting epitaxial wafer and its preparation method, as well as a semiconductor light-emitting device, which effectively solves the technical problems existing in the prior art, ensures the high quality of the prepared light-emitting epitaxial wafer, improves the luminous efficiency and recombination efficiency of the semiconductor light-emitting device, and optimizes the performance of the semiconductor light-emitting device.
[0051] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 13 The technical solutions provided in the embodiments of this application will be described in more detail.
[0052] refer to Figure 1 The diagram shown is a flowchart of a method for preparing a light-emitting epitaxial wafer according to an embodiment of this application. The preparation method includes:
[0053] S11, Provide a substrate.
[0054] S12. An N-type semiconductor layer is grown on one side of the substrate.
[0055] S13. A multi-quantum well layer is grown on the side of the N-type semiconductor layer away from the substrate. The multi-quantum well layer includes a potential well layer and a barrier layer that are grown alternately in a predetermined period. During at least one period of alternating growth of the potential well layer and the barrier layer: a first stress relief layer is grown before and / or after the growth of the potential well layer. The carrier gas during the growth of the first stress relief layer includes at least argon gas.
[0056] S14. A P-type semiconductor layer is grown on the side of the multi-quantum well layer away from the substrate.
[0057] Understandably, the technical solution provided in this application inserts and grows a first stress-relief layer into the multi-quantum-well layer of the light-emitting epitaxial wafer, thereby reducing lattice mismatch and dislocation density through stress relief, ensuring high quality of the prepared light-emitting epitaxial wafer. During the growth of the stress-relief layer, a carrier gas including argon is used. This carrier gas can carry away the hydrogen gas generated during the dissociation of the light-emitting epitaxial wafer during preparation, promoting a positive shift in the ammonia decomposition equilibrium during stress-relief layer growth and suppressing the generation of nitrogen vacancies. Furthermore, argon has a small atomic radius and weak competitive adsorption capacity for surface sites, allowing ammonia molecules to directly contact and decompose on the high-temperature substrate during stress-relief layer growth, further promoting the ammonia decomposition reaction. In addition, during the preparation of the light-emitting epitaxial wafer, a temperature gradient exists in the growth reaction chamber perpendicular to the carrier disk. Due to the relatively low thermal conductivity of argon, the growth of the first stress-relief layer tends to be radial under an argon atmosphere. This facilitates precise control of the stress-relief layer thickness, improving carrier wave function overlap, increasing the recombination efficiency of the semiconductor light-emitting device, and optimizing the performance of the semiconductor light-emitting device.
[0058] In some embodiments, a stress relief layer can be inserted into the multi-quantum well layer of the light-emitting epitaxial wafer provided in this application. Alternatively, a stress relief layer can be inserted between the multi-quantum well layer and the P-type semiconductor layer in the light-emitting epitaxial wafer provided in this application; see details below. Figure 2 The diagram shows a flowchart of another method for preparing a light-emitting epitaxial wafer according to an embodiment of this application. The preparation method provided in this embodiment includes:
[0059] S21, Provide a substrate.
[0060] S22. An N-type semiconductor layer is grown on one side of the substrate.
[0061] S23. A multi-quantum well layer is grown on the side of the N-type semiconductor layer away from the substrate. The multi-quantum well layer includes a potential well layer and a barrier layer that are grown alternately at a predetermined period.
[0062] S24. A second stress relief layer is grown on the side of the multi-quantum well layer away from the substrate, and the carrier gas during the growth of the second stress relief layer includes at least argon gas.
[0063] S25. A P-type semiconductor layer is grown on the side of the second stress relief layer away from the substrate.
[0064] Understandably, the technical solution provided in this application inserts a second stress-relief layer between the multi-quantum-well layer and the P-type semiconductor layer of the light-emitting epitaxial wafer. This reduces lattice mismatch and dislocation density through stress relief, ensuring high quality of the prepared light-emitting epitaxial wafer. Argon is used as a carrier gas during the growth of the stress-relief layer. This allows the carrier gas to remove hydrogen generated during the fabrication of the light-emitting epitaxial wafer, promoting a positive shift in the ammonia decomposition equilibrium during stress-relief layer growth and suppressing nitrogen vacancies. Furthermore, argon's small atomic radius results in weak competitive adsorption at surface sites, allowing ammonia molecules to directly contact and decompose on the high-temperature substrate during stress-relief layer growth, further promoting the ammonia decomposition reaction. Simultaneously, the reduction in hydrogen reduces the formation of -H chemical bonds during P-type doping (e.g., Mg doping reduces Mg-H bond formation during P-type semiconductor layer growth), thereby increasing hole concentration and improving the luminous efficiency of the semiconductor light-emitting device. Furthermore, during the fabrication of the light-emitting epitaxial wafer, there is a temperature gradient in the growth reaction chamber perpendicular to the carrier disk. Since argon has a relatively low thermal conductivity, the growth of the second stress-relieving layer tends to be radial under an argon atmosphere. This is beneficial for precisely controlling the thickness of the stress-relieving layer to improve the wave function overlap of charge carriers, thereby improving the recombination efficiency of the semiconductor light-emitting device and optimizing its performance.
[0065] In the light-emitting epitaxial wafers provided in the above embodiments, a stress-relieving layer can be inserted into the multi-quantum-well layer, or a stress-relieving layer can be inserted between the multi-quantum-well layer and the P-type semiconductor layer. Alternatively, in the light-emitting epitaxial wafers provided in the embodiments of this application, while inserting a stress-relieving layer into the multi-quantum-well layer, a stress-relieving layer can also be inserted between the multi-quantum-well layer and the P-type semiconductor layer; see details below. Figure 3 The diagram shows a flowchart of another method for preparing a light-emitting epitaxial wafer according to an embodiment of this application. The preparation method provided in this embodiment includes:
[0066] S31, Provide a substrate.
[0067] S32. An N-type semiconductor layer is grown on one side of the substrate.
[0068] S33. A multi-quantum well layer is grown on the side of the N-type semiconductor layer away from the substrate. The multi-quantum well layer includes a potential well layer and a barrier layer that are grown alternately in a predetermined period. During at least one period of alternating growth of the potential well layer and the barrier layer: a first stress relief layer is grown before and / or after the growth of the potential well layer. The carrier gas during the growth of the first stress relief layer includes at least argon gas.
[0069] S34. A second stress relief layer is grown on the side of the multi-quantum well layer away from the substrate, and the carrier gas during the growth of the second stress relief layer includes at least argon.
[0070] S35. A P-type semiconductor layer is grown on the side of the second stress relief layer away from the substrate.
[0071] Understandably, the technical solution provided in this application involves inserting a first stress-relief layer into the multi-quantum-well layer of the light-emitting epitaxial wafer, and simultaneously inserting a second stress-relief layer between the multi-quantum-well layer and the P-type semiconductor layer. This stress relief reduces lattice mismatch and dislocation density, ensuring high quality of the prepared light-emitting epitaxial wafer. During the growth of the stress-relief layer, a carrier gas including argon is used. This carrier gas can remove hydrogen generated during the dissociation process of the light-emitting epitaxial wafer, promoting a positive shift in the ammonia decomposition equilibrium during stress-relief layer growth and suppressing nitrogen vacancies. Furthermore, argon's small atomic radius results in weak competitive adsorption at surface sites, allowing ammonia molecules to directly contact and decompose on the high-temperature substrate during stress-relief layer growth, further promoting the ammonia decomposition reaction. Simultaneously, the reduction in hydrogen reduces the formation of -H chemical bonds during P-type doping (e.g., Mg doping reduces Mg-H bond formation during P-type semiconductor layer growth), thereby increasing hole concentration and improving the luminous efficiency of the semiconductor light-emitting device. Furthermore, during the fabrication of the light-emitting epitaxial wafer, a temperature gradient exists in the growth reaction chamber perpendicular to the carrier disk. Due to the relatively low thermal conductivity of argon, the growth of the first and second stress-relief layers tends to be radial under an argon atmosphere. This facilitates precise control of the stress-relief layer thickness, thereby improving the wave function overlap of charge carriers, enhancing the recombination efficiency of the semiconductor light-emitting device, and optimizing its performance.
[0072] The following is combined with Figures 4 to 12 The schematic diagram illustrating the fabrication process of the light-emitting epitaxial wafer provides a more detailed description of the fabrication method of the light-emitting epitaxial wafer provided in this application embodiment. It should be noted that the light-emitting epitaxial wafer provided in this application embodiment may include a GaN-based light-emitting epitaxial wafer, which can be fabricated using MOCVD (Metal-organic Chemical Vapor Deposition) growth equipment. The MO source used includes trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn), magnesium diacene (Cp2Mg), and trimethylaluminum (TMAl), and the gases used include silane (SiH4) and ammonia (NH3). Except for the fabrication of the stress-relieving layer, H2 and N2 can be used as carrier gases, with silane as the N-type doping source and magnesium diacene as the P-type doping source. Firstly, combined with... Figures 4 to 7 right Figure 1 The preparation method of the schematic light-emitting epitaxial wafer is described, wherein... Figures 4 to 7 for Figure 1 The corresponding structural diagrams for each step in the process.
[0073] like Figure 4 As shown, corresponding to step S11, a substrate 100 is provided. The substrate 100 can be a substrate made of materials such as sapphire or SiC. Before growing the structural layer on the substrate 100, the temperature can be increased to perform H-treatment (e.g., the temperature is increased to 1100℃ and H-treatment is performed for 5 minutes) to remove surface impurities of the substrate 100, thereby cleaning the substrate 100.
[0074] like Figure 5 As shown, corresponding to step S12, an N-type semiconductor layer 200 is grown on one side of the substrate 100. The N-type semiconductor layer 200 may include an N-type GaN layer, specifically, TMGa and SiH4 can be introduced into the growth equipment to grow the N-type GaN layer. The thickness of the N-type GaN layer can be 1500-2500 nm (e.g., 2000 nm), the growth temperature can be 1040-1150℃ (e.g., 1085℃), and the concentration of SiH4 can be 2E19 / cm³. 3 .
[0075] like Figure 6 As shown, corresponding to step S13, a multi-quantum well layer is grown on the side of the N-type semiconductor layer 200 away from the substrate 100. The multi-quantum well layer includes a potential well layer 310 and a barrier layer 320 that are grown alternately in a predetermined period. During at least one period of alternating growth of the potential well layer 310 and the barrier layer 320: a first stress relief layer 410 is grown before and / or after the growth of the potential well layer 310. The carrier gas during the growth of the first stress relief layer 410 includes at least argon gas.
[0076] In some embodiments, the growth apparatus can be selected to grow a multi-quantum well layer with a thickness of 120-160 nm (e.g., 140 nm) using TEGa, TMI, TMI, or SiH4. The grown potential well layer 310 can be an InGaN well layer, and the growth temperature for preparing the potential well layer 310 is 700-800 °C (e.g., 780 °C). The grown barrier layer 320 can be a GaN or AlGaN barrier layer, and the growth temperature for the barrier layer 320 can be 800-900 °C (e.g., 890 °C). When growing the multi-quantum well layer, the potential well layer 310 can be grown first and then the barrier layer 320 can be grown in each cycle; or, the barrier layer 320 can be grown first and then the potential well layer 310 can be grown in each cycle. The specific selection needs to be made according to the actual application.
[0077] like Figure 7 As shown, corresponding to step S14, a P-type semiconductor layer 500 is grown on the side of the multi-quantum well layer away from the substrate 100. Specifically, TMGa and Cp2Mg can be introduced into the growth equipment to grow the P-type GaN layer. The thickness of the P-type semiconductor layer 500 can be 20-200 nm (e.g., 100 nm), the growth temperature can be 900-1000 °C (e.g., 965 °C), and the Mg concentration can be 2E19 / cm³. 3 .
[0078] Combination Figures 8 to 10 right Figure 2 The preparation method of the illustrated light-emitting epitaxial wafer is described in detail. Figures 8 to 10 for Figure 2 A structural diagram showing the corresponding steps in the middle section. Among them, Figure 2 The steps S21 and S22 shown are the same as those shown. Figure 1 Steps S11 and S12 are the same as shown in the attached diagram to avoid repetition. Figure 2 Steps S21 and S22 shown can be referred to Figure 4 and Figure 5 The related structures are shown.
[0079] like Figure 4 As shown, corresponding to step S21, a substrate 100 is provided. The substrate 100 can be a substrate made of materials such as sapphire or SiC. Before growing the structural layer on the substrate 100, the temperature can be increased to perform H-treatment (e.g., the temperature is increased to 1100℃ and H-treatment is performed for 5 minutes) to remove surface impurities of the substrate 100, thereby cleaning the substrate 100.
[0080] like Figure 5 As shown, corresponding to step S22, an N-type semiconductor layer 200 is grown on one side of the substrate 100. The N-type semiconductor layer 200 may include an N-type GaN layer, specifically, TMGa and SiH4 can be introduced into the growth equipment to grow the N-type GaN layer. The thickness of the N-type GaN layer can be 1500-2500 nm (e.g., 2000 nm), the growth temperature can be 1040-1150 °C (e.g., 1085 °C), and the concentration of SiH4 can be 2E19 / cm³. 3 .
[0081] like Figure 8In step S23, a multi-quantum well layer is grown on the side of the N-type semiconductor layer 200 away from the substrate 100. The multi-quantum well layer includes a potential well layer 310 and a barrier layer 320 that are grown alternately at a predetermined period. Specifically, TEGa, TMI, TMI, and SiH4 can be selected in the growth equipment to grow a multi-quantum well layer with a thickness of 120-160 nm (e.g., 140 nm). The grown potential well layer 310 can be an InGaN well layer, and the growth temperature for preparing the potential well layer 310 is 700-800℃ (e.g., 780℃). The grown barrier layer 320 can be a GaN or AlGaN barrier layer, and the growth temperature for the barrier layer 320 can be 800-900℃ (e.g., 890℃). When growing multiple quantum well layers, in each cycle, the potential well layer 310 can be grown first and then the barrier layer 320 can be grown; or, in each cycle, the barrier layer 320 can be grown first and then the potential well layer 310 can be grown. The specific choice needs to be made according to the actual application.
[0082] like Figure 9 As shown, corresponding to step S24, a second stress relief layer 420 is grown on the side of the multi-quantum well layer away from the substrate 100, and the carrier gas during the growth of the second stress relief layer 420 includes at least argon gas.
[0083] like Figure 10 As shown, corresponding to step S25, a P-type semiconductor layer 500 is grown on the side of the second stress relief layer 420 facing away from the substrate. Specifically, TMGa and Cp2Mg can be introduced into the growth equipment to grow a P-type GaN layer. The thickness of the P-type semiconductor layer 500 can be 20-200 nm (e.g., 100 nm), the growth temperature can be 900-1000℃ (e.g., 965℃), and the Mg concentration can be 2E19 / cm³. 3 .
[0084] Combination Figure 11 and Figure 12 right Figure 3 The preparation method of the illustrated light-emitting epitaxial wafer is described in detail. Figure 11 and Figure 12 for Figure 3 A structural diagram showing the corresponding steps in the middle section. Among them, Figure 3 The steps S31 to S33 shown are... Figure 1 Steps S11 to S13 are the same as shown in the accompanying drawings to avoid repetition. Figure 3 Steps S31 to S33 shown can also be referred to. Figures 4 to 6 The related structures are shown.
[0085] like Figure 4As shown, corresponding to step S31, a substrate 100 is provided. The substrate 100 can be a substrate made of materials such as sapphire or SiC. Before growing the structural layer on the substrate 100, the temperature can be increased to perform H-treatment (e.g., the temperature is increased to 1100℃ and H-treatment is performed for 5 minutes) to remove surface impurities of the substrate 100, thereby cleaning the substrate 100.
[0086] like Figure 5 As shown, corresponding to step S32, an N-type semiconductor layer 200 is grown on one side of the substrate 100. The N-type semiconductor layer 200 may include an N-type GaN layer, specifically, TMGa and SiH4 can be introduced into the growth equipment to grow the N-type GaN layer. The thickness of the N-type GaN layer can be 1500-2500 nm (e.g., 2000 nm), the growth temperature can be 1040-1150 °C (e.g., 1085 °C), and the concentration of SiH4 can be 2E19 / cm³. 3 .
[0087] like Figure 6 As shown, corresponding to step S33, a multi-quantum well layer is grown on the side of the N-type semiconductor layer 200 away from the substrate 100. The multi-quantum well layer includes a potential well layer 310 and a barrier layer 320 that are grown alternately in a predetermined period. During at least one period of alternating growth of the potential well layer 310 and the barrier layer 320: a first stress relief layer 410 is grown before and / or after the growth of the potential well layer 310. The carrier gas during the growth of the first stress relief layer 410 includes at least argon gas.
[0088] In some embodiments, the growth apparatus can be selected to grow a multi-quantum well layer with a thickness of 120-160 nm (e.g., 140 nm) using TEGa, TMI, TMI, or SiH4. The grown potential well layer 310 can be an InGaN well layer, and the growth temperature for preparing the potential well layer 310 is 700-800 °C (e.g., 780 °C). The grown barrier layer 320 can be a GaN or AlGaN barrier layer, and the growth temperature for the barrier layer 320 can be 800-900 °C (e.g., 890 °C). When growing the multi-quantum well layer, the potential well layer 310 can be grown first and then the barrier layer 320 can be grown in each cycle; or, the barrier layer 320 can be grown first and then the potential well layer 310 can be grown in each cycle. The specific selection needs to be made according to the actual application.
[0089] like Figure 11 As shown, corresponding to step S34, a second stress relief layer 420 is grown on the side of the multi-quantum well layer away from the substrate 100, and the carrier gas during the growth of the second stress relief layer 420 includes at least argon gas.
[0090] like Figure 12 As shown, corresponding to step S35, a P-type semiconductor layer 500 is grown on the side of the second stress relief layer 420 facing away from the substrate. Specifically, TMGa and Cp2Mg can be introduced into the growth equipment to grow the P-type GaN layer. The thickness of the P-type semiconductor layer 500 can be 20-200 nm (e.g., 100 nm), the growth temperature can be 900-1000℃ (e.g., 965℃), and the Mg concentration can be 2E19 / cm³. 3 .
[0091] In some embodiments, the growth of the first stress relief layer 410 and the growth of the second stress relief layer 420 provided in this application embodiment are: the growth of an AlInN stress relief layer; that is, when the method for preparing the light-emitting epitaxial wafer includes the growth of the first stress relief layer 410, the growth of the first stress relief layer 410 can be the growth of an AlInN stress relief layer; when the method for preparing the light-emitting epitaxial wafer includes the growth of the second stress relief layer 420, the growth of the second stress relief layer 420 can be the growth of an AlInN stress relief layer. Optionally, the carrier gas used for growing the first stress relief layer 410 in this embodiment is argon or a mixture of argon and nitrogen; the carrier gas used for growing the second stress relief layer 420 is argon or a mixture of argon and nitrogen; that is, when the method for preparing the light-emitting epitaxial wafer includes growing the first stress relief layer 410, the carrier gas used for growing the first stress relief layer 410 is argon or a mixture of argon and nitrogen; when the method for preparing the light-emitting epitaxial wafer includes growing the second stress relief layer 420, the carrier gas used for growing the second stress relief layer 420 is argon or a mixture of argon and nitrogen. Furthermore, in the embodiments of this application, when growing the first stress-relief layer 410 and the second stress-relief layer 420, the growth temperature is 750-800℃, the growth pressure is 300-500 Torr, and the argon gas flow rate is 30-80 slm. This application does not impose specific limitations on these aspects. That is, when the method for preparing the light-emitting epitaxial wafer includes growing the first stress-relief layer 410, the growth temperature for growing the first stress-relief layer 410 is 750-800℃, the growth pressure is 300-500 Torr, and the argon gas flow rate is 30-80 slm; when the method for preparing the light-emitting epitaxial wafer includes growing the second stress-relief layer 420, the growth temperature for growing the second stress-relief layer 420 is 750-800℃, the growth pressure is 300-500 Torr, and the argon gas flow rate is 30-80 slm.
[0092] Furthermore, to optimize the growth quality of the light-emitting epitaxial wafer, some optimized structural layers can be grown during the fabrication process. In some embodiments, the technical solution provided in this application, after providing the substrate 100 and before growing the N-type semiconductor layer 200, further includes: sequentially growing at least one of a buffer layer and an unintentionally doped layer along the direction from the substrate 100 to the N-type semiconductor layer 200.
[0093] Specifically, the light-emitting epitaxial wafer provided in this application embodiment may include at least one of a buffer layer and an unintentionally doped layer; wherein when the light-emitting epitaxial wafer includes a buffer layer and an unintentionally doped layer, the unintentionally doped layer is located between the buffer layer and the N-type semiconductor layer 200. The buffer layer, also known as a buffer layer, can buffer mismatch stress for the growth of subsequent structural layers, thereby improving the crystal growth quality of the light-emitting epitaxial wafer; in some embodiments, at least TMGa can be introduced into the growth equipment to grow a GaN buffer layer or an AlN buffer layer, and the growth thickness of the buffer layer can be 15-40 nm (e.g., 25 nm), and the growth temperature can be 800-950 °C (e.g., 850 °C). The unintentionally doped layer can be a U-shaped gallium nitride layer. This unintentionally doped layer may include a 3D layer (three-dimensional growth layer) and a GR layer (gradient layer) sequentially stacked along the direction from the substrate 100 to the N-type semiconductor layer 200. The 3D layer grows in a three-dimensional island pattern and then gradually merges, thereby blocking dislocations extending upwards from the substrate 100 and reducing crystal defect density. In some embodiments, at least TMGa can be introduced into the growth apparatus to grow the GaN three-dimensional growth layer. The growth thickness of the 3D layer can be 1200-2000 nm (e.g., 1500 nm), and the growth temperature can be 1000-1100 °C (e.g., 1070 °C). The GR layer can be further heated to gradually transform the GaN from three-dimensional growth to two-dimensional growth, making the epitaxial layer more flat. In some embodiments, at least TMGa can be introduced into the growth apparatus to grow the GR layer. The growth thickness can be 600-2300 nm (e.g., 800 nm), and the growth temperature can be 1080-1200 °C (e.g., 1125 °C). In some embodiments, the N-type semiconductor layer 200 further includes a low-doped LD layer, wherein the low-doped LD layer is located between the N-type GaN layer and the multiple quantum well layer, and the doping concentration of the low-doped LD layer is less than that of the N-type GaN layer; that is, when growing the N-type semiconductor layer 200, a low-doped LD layer can be grown after the growth of the N-type GaN layer and before the growth of the multiple quantum wells. The low-doped LD layer is a low-defect layer, and the doping concentration of the low-doped LD layer is less than that of the N-type GaN layer. The low-defect layer can provide a higher quality crystal platform for the growth of the active region (multiple quantum well layer) and increase the current expansion. In some embodiments, at least TMGa and SiH4 can be introduced into the growth equipment to grow the GaN low-defect layer or the AlGaN low-defect layer. The growth thickness of the low-defect layer can be 200-400 nm (e.g., 150 nm), and the growth temperature can be 1040-1150 °C (e.g., 1085 °C).
[0094] It should be noted that the optimized structural layers provided in the embodiments of this application are not limited to the buffer layer, unintentionally doped layer and low-defect layer shown above; in some embodiments, this application may also grow other functional structures in the light-emitting epitaxial wafer to improve the quality and performance of the light-emitting epitaxial wafer, and this application does not make specific limitations in this regard.
[0095] Based on the same inventive concept, this application also provides a light-emitting epitaxial wafer, which can be prepared using the preparation method provided in any of the above embodiments. (Reference) Figure 7 As shown in the embodiment of this application, a light-emitting epitaxial wafer includes: a substrate 100; an N-type semiconductor layer 200 located on one side of the substrate 100; a multi-quantum well layer located on the side of the N-type semiconductor layer 200 facing away from the substrate 100, the multi-quantum well layer including a potential well layer 310 and a barrier layer 320 stacked alternately with a predetermined period; wherein, in at least one of the periodically stacked potential well layer 310 and barrier layer 320: a first stress relief layer 410 is formed on the side of the potential well layer 310 facing away from the barrier layer 320, and / or a first stress relief layer 410 is formed on the side of the potential well layer 310 facing the barrier layer 320; and a P-type semiconductor layer 500 is located on the side of the multi-quantum well layer facing away from the substrate 100. The first stress relief layer 410 is formed based on a carrier gas including at least argon.
[0096] In some embodiments, the light-emitting epitaxial wafer provided in this application can be as follows: Figure 7 The illustration shows the insertion of a first stress-relief layer 410 into the multi-quantum-well layer. Alternatively, in the light-emitting epitaxial wafer provided in this embodiment, a second stress-relief layer 420 may be inserted between the multi-quantum-well layer and the P-type semiconductor layer 500; see details below. Figure 10 As shown in the embodiment of this application, another light-emitting epitaxial wafer includes: a substrate 100; an N-type semiconductor layer 200 located on one side of the substrate 100; a multi-quantum well layer located on the side of the N-type semiconductor layer 200 opposite to the substrate 100, the multi-quantum well layer including a potential well layer 310 and a barrier layer 320 stacked alternately with a predetermined period; a second stress relief layer 420 located on the side of the multi-quantum well layer opposite to the substrate 100; and a P-type semiconductor layer 500 located on the side of the second stress relief layer 420 opposite to the substrate 100. The second stress relief layer 420 is formed based on a carrier gas including at least argon.
[0097] The light-emitting epitaxial wafer provided in the above embodiments can be as follows: Figure 7 The first stress-relieving layer 410 is intentionally inserted into the multi-quantum-well layer, or it can be prepared as follows: Figure 10 The illustration shows a second stress-relief layer 420 inserted between the multi-quantum-well layer and the P-type semiconductor layer 500. Alternatively, in the light-emitting epitaxial wafer provided in this embodiment, not only can a first stress-relief layer 410 be inserted into the multi-quantum-well layer, but a second stress-relief layer 420 can also be inserted between the multi-quantum-well layer and the P-type semiconductor layer 500 simultaneously; see details below. Figure 12As shown in the embodiment of this application, another type of light-emitting epitaxial wafer includes: a substrate 100; an N-type semiconductor layer 200 located on one side of the substrate 100; a multi-quantum well layer located on the side of the N-type semiconductor layer 200 facing away from the substrate 100, the multi-quantum well layer including a potential well layer 310 and a barrier layer 320 stacked alternately with a predetermined period; wherein, in at least one of the periodically stacked potential well layer 310 and barrier layer 320: a first stress relief layer 410 is formed on the side of the potential well layer 310 facing away from the barrier layer 320, and / or a first stress relief layer 410 is formed on the side of the potential well layer 310 facing the barrier layer 320; a second stress relief layer 420 is formed on the side of the multi-quantum well layer facing away from the substrate 100, and a P-type semiconductor layer 500 is formed on the side of the second stress relief layer 420 facing away from the substrate 100. The first stress relief layer 410 and the second stress relief layer 420 are formed based on a carrier gas including at least argon.
[0098] In some embodiments, the first stress relief layer 410 and the second stress relief layer 420 provided in this application can be AlInN stress relief layers; that is, when the light-emitting epitaxial wafer includes the first stress relief layer 410, the first stress relief layer 410 can be an AlInN stress relief layer; when the light-emitting epitaxial wafer includes the second stress relief layer 420, the second stress relief layer 420 can be an AlInN stress relief layer. Optionally, the thickness of the first stress relief layer 410 and the second stress relief layer 420 provided in this application can be 2-10 nm, and this application does not limit the specific value; that is, when the light-emitting epitaxial wafer includes the first stress relief layer 410, the thickness of the first stress relief layer 410 can be 2-10 nm; when the light-emitting epitaxial wafer includes the second stress relief layer 420, the thickness of the second stress relief layer 420 can be 2-10 nm.
[0099] Furthermore, to optimize the growth quality of light-emitting epitaxial wafers, some optimized structural layers can be grown during the fabrication process. (Reference) Figure 13 The diagram shows a partial stacked structure of a light-emitting epitaxial wafer according to an embodiment of this application. The light-emitting epitaxial wafer further includes: at least one of a buffer layer 610 and an unintentionally doped layer 620, sequentially stacked between the substrate 100 and the N-type semiconductor layer 200 along a direction Y from the substrate 100 to the N-type semiconductor layer 200; and / or, a low-defect layer located between the N-type GaN layer and the multiple quantum well layer. It is understood that the light-emitting epitaxial wafer provided in this application may include at least one of a buffer layer 610, an unintentionally doped layer 620, and a low-defect layer.
[0100] Based on the same inventive concept, embodiments of this application also provide a semiconductor light-emitting device, which includes the light-emitting epitaxial wafer provided in any of the above embodiments. Optionally, the semiconductor light-emitting device provided in embodiments of this application can be a semiconductor light-emitting diode.
[0101] In summary, this application provides a light-emitting epitaxial wafer, its fabrication method, and a semiconductor light-emitting device. A first stress-relief layer is grown within the multi-quantum-well layer of the light-emitting epitaxial wafer, and / or a second stress-relief layer is grown between the multi-quantum-well layer and the P-type semiconductor layer. This stress relief reduces lattice mismatch and dislocation density, ensuring high quality of the fabricated light-emitting epitaxial wafer. Argon is used as a carrier gas during the growth of the stress-relief layer. This carrier gas carries away hydrogen generated during the fabrication of the light-emitting epitaxial wafer, promoting a positive shift in the ammonia decomposition equilibrium during stress-relief layer growth and suppressing nitrogen vacancy generation. Furthermore, argon's small atomic radius results in weak competitive adsorption at surface sites, allowing ammonia molecules to directly contact and decompose on the high-temperature substrate during stress-relief layer growth, further promoting the ammonia decomposition reaction. Simultaneously, the reduction in hydrogen reduces the formation of -H chemical bonds in the dopant element during P-type doping, thereby increasing hole concentration and improving the luminous efficiency of the semiconductor light-emitting device. Furthermore, during the fabrication of the light-emitting epitaxial wafer, a temperature gradient exists in the growth reaction chamber perpendicular to the carrier disk. Due to the relatively low thermal conductivity of argon, the growth of the first and second stress-relief layers tends to be radial under an argon atmosphere. This facilitates precise control of the stress-relief layer thickness, thereby improving the wave function overlap of charge carriers, enhancing the recombination efficiency of the semiconductor light-emitting device, and optimizing its performance.
[0102] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0104] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0105] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0106] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0107] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A light-emitting epitaxial wafer, characterized in that, The light-emitting epitaxial wafer includes: Substrate; An N-type semiconductor layer located on one side of the substrate; A multi-quantum well layer located on the side of the N-type semiconductor layer away from the substrate, the multi-quantum well layer comprising a potential well layer and a barrier layer stacked alternately in a predetermined period; wherein, in at least one of the periodically stacked potential well layer and the barrier layer: on the side of the potential well layer away from the barrier layer, and / or on the side of the potential well layer facing the barrier layer, a first stress relief layer is formed based on a carrier gas comprising at least argon; A P-type semiconductor layer located on the side of the multi-quantum-well layer facing away from the substrate; Alternatively, the light-emitting epitaxial wafer may include: Substrate; An N-type semiconductor layer located on one side of the substrate; A multi-quantum well layer located on the side of the N-type semiconductor layer away from the substrate, the multi-quantum well layer comprising a potential well layer and a barrier layer stacked alternately at a predetermined period; Located on the side of the multi-quantum-well layer opposite to the substrate, a second stress-relieving layer is formed based on a carrier gas including at least argon. A P-type semiconductor layer located on the side of the second stress relief layer facing away from the substrate; Alternatively, the light-emitting epitaxial wafer may include: Substrate; An N-type semiconductor layer located on one side of the substrate; A multi-quantum well layer located on the side of the N-type semiconductor layer away from the substrate, the multi-quantum well layer comprising a potential well layer and a barrier layer stacked alternately in a predetermined period; wherein, in at least one of the periodically stacked potential well layer and the barrier layer: on the side of the potential well layer away from the barrier layer, and / or on the side of the potential well layer facing the barrier layer, a first stress relief layer is formed based on a carrier gas comprising at least argon; A second stress-relieving layer is formed on the side of the multi-quantum well layer opposite to the substrate, based on a carrier gas including at least argon. The P-type semiconductor layer located on the side of the second stress relief layer opposite to the substrate.
2. The light-emitting epitaxial wafer according to claim 1, characterized in that, When the light-emitting epitaxial wafer includes the first stress relief layer, the first stress relief layer is an AlInN stress relief layer; When the light-emitting epitaxial wafer includes the second stress-relieving layer, the second stress-relieving layer is an AlInN stress-relieving layer.
3. The light-emitting epitaxial wafer according to claim 1, characterized in that, When the light-emitting epitaxial wafer includes the first stress-relieving layer, the thickness of the first stress-relieving layer is 2-10 nm; When the light-emitting epitaxial wafer includes the second stress-relieving layer, the thickness of the second stress-relieving layer is 2-10 nm.
4. The light-emitting epitaxial wafer according to claim 1, characterized in that, The carrier gas is argon, or a mixture of argon and nitrogen.
5. The light-emitting epitaxial wafer according to claim 1, characterized in that, The light-emitting epitaxial wafer also includes: At least one of a buffer layer and an unintentionally doped layer is sequentially stacked between the substrate and the N-type semiconductor layer, and along the direction from the substrate to the N-type semiconductor layer.
6. The light-emitting epitaxial wafer according to claim 5, characterized in that, The unintentionally doped layer includes: A 3D layer and a GR layer are sequentially stacked along the direction from the substrate to the N-type semiconductor layer.
7. The light-emitting epitaxial wafer according to claim 1, characterized in that, The N-type semiconductor layer includes an N-type GaN layer.
8. The light-emitting epitaxial wafer according to claim 7, characterized in that, The N-type semiconductor layer further includes a low-doped LD layer, wherein the low-doped LD layer is located between the N-type GaN layer and the multiple quantum well layer, and the doping concentration of the low-doped LD layer is less than the doping concentration of the N-type GaN layer.
9. The light-emitting epitaxial wafer according to claim 1, characterized in that, The light-emitting epitaxial wafer includes a GaN-based light-emitting epitaxial wafer.
10. A semiconductor light-emitting device, characterized in that, The semiconductor light-emitting device includes the light-emitting epitaxial wafer as described in any one of claims 1-9.