A gold wire bonding region structure for WLED multi-chip package

Abstract

The utility model relates to a gold wire bonding area structure for WLED multi-chip package, the utility model effectively solves the problem that traditional multi-chip parallel connection package structure has increased short circuit risk, uneven current distribution, influences device overall life and reliability. The gold wire bonding area structure for WLED multi-chip package is provided with the gold wire limiting frame with the clamping slot, the connecting gold wire of connecting chip and auxiliary pad is physically isolated and forcedly limited, fundamentally eliminates the "spider web" effect, greatly reduces the short circuit risk caused by gold wire contact, improves the reliability of package structure, and through the composite bonding mechanism, the current is first evenly distributed to the auxiliary pads of each row, and then distributed to each chip in the row, effectively reducing the uneven current caused by path resistance difference, making each chip emit light uniformly, color temperature uniform, and delaying light decay, improving the overall life of the device, effectively improving the production yield and quality, and suitable for mass production.

Description

Technical Field

[0001] This utility model belongs to the field of chip packaging technology, specifically relating to a gold wire bonding region structure for WLED multi-chip packaging. Background Technology

[0002] White light-emitting diodes (WLEDs) are increasingly widely used in the lighting field, and multi-chip integrated packaging is the mainstream technology for improving the luminous flux of a single device. In this type of packaging, gold wire bonding is a key process for achieving electrical interconnection between the chip electrodes and external circuitry.

[0003] However, traditional multi-chip parallel packaging structures have significant drawbacks: First, when there are many chips and they are densely arranged, the gold wires leading from each chip are very likely to cross and overlap, forming a so-called "spider web" effect. This not only increases the risk of short circuits, but also the gold wires that are bonded later during the wire bonding process may damage the gold wires that were bonded earlier, resulting in a decrease in product yield. At the same time, in traditional direct parallel structures, the phenomenon of uneven current distribution is prominent. Chips closer to the power input point have a large current, while chips farther away have a small current, resulting in uneven light emission, inconsistent color temperature, and accelerated light decay of some chips, affecting the overall lifespan and reliability of the device. Utility Model Content

[0004] To address the above issues and overcome the shortcomings of existing technologies, this invention provides a gold wire bonding area structure for WLED multi-chip packaging. This structure ensures that each connecting gold wire is bonded within a preset path and channel, fundamentally eliminating the "spider web" effect, greatly reducing the risk of short circuits caused by gold wire contact, and improving the reliability of the packaging structure. It also effectively reduces current unevenness caused by differences in path resistance, resulting in consistent light emission and color temperature across all chips, delaying light decay, and extending the overall lifespan of the device.

[0005] A gold wire bonding area structure for WLED multi-chip packaging includes an insulating substrate, a metal-based printed circuit board disposed on the upper surface of the insulating substrate, a plurality of positioning grooves for mounting WLED chips being formed on the upper surface of the metal-based printed circuit board, and copper foil lines embedded inside the metal-based printed circuit board, with the copper foil lines respectively connected to the inner bottom wall of each positioning groove.

[0006] The positioning groove is internally equipped with a chip array mechanism consisting of multiple WLED chips;

[0007] A composite bonding mechanism is provided on one side of the upper surface of the insulating substrate. A gold wire module is provided between the composite bonding mechanism and the chip array mechanism. The gold wire module includes a strip pad embedded in the main bonding area, an auxiliary pad embedded in the auxiliary bonding area, and connecting gold wires.

[0008] The strip pads and auxiliary pads are bonded together by connecting gold wires, and the auxiliary pads are also bonded to the negative terminals of each WLED chip in the corresponding row by connecting gold wires.

[0009] The top of the gold wire limiting frame has multiple slots for engaging and disengaging the gold wire.

[0010] Preferably, the composite bonding mechanism includes a gold wire limiting frame, an auxiliary bonding area, and a main bonding area arranged sequentially from the side closest to the chip array mechanism to the side furthest away, and the three are arranged in a stepped manner.

[0011] Preferably, the multiple WLED chips in the chip array mechanism are arranged in a rectangular array, and each WLED chip is die-bonded in a positioning groove.

[0012] Preferably, the number of auxiliary pads is the same as the number of rows of WLED chips in the chip array structure, with each auxiliary pad corresponding to one row of WLED chips.

[0013] Preferably, the gold wires connecting the auxiliary pads and the negative terminals of each WLED chip are threaded through corresponding slots on the gold wire limiting frame.

[0014] Preferably, the gold wire limiting frame, the auxiliary bonding area, and the main bonding area have a height difference in the vertical direction, forming a stepped structure for optimizing the curvature of the connected gold wire.

[0015] The beneficial effects of the above technical solution are as follows:

[0016] This gold wire bonding area structure for WLED multi-chip packaging uses a gold wire limiting frame with slots to physically isolate and forcibly limit the connecting gold wires between the chips and auxiliary pads. This ensures that each connecting gold wire bonds within a preset path and channel, fundamentally eliminating the "spider web" effect and greatly reducing the risk of short circuits caused by gold wire contact, thus improving the reliability of the packaging structure. Furthermore, the composite bonding mechanism ensures that the current is first evenly distributed to the auxiliary pads of each row, and then distributed to each chip within that row. Compared to all chips being directly connected in parallel to a single pad, this effectively reduces current unevenness caused by differences in path resistance, resulting in consistent light emission and color temperature across all chips, delaying light decay, and improving the overall lifespan of the device. This effectively improves production yield and quality, making it suitable for mass production. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0018] Figure 2 This is a schematic diagram of the chip array mechanism of this utility model in its disassembled state;

[0019] Figure 3 This is a top view of the present invention.

[0020] In the diagram: 1. Insulating substrate; 2. Metal-based printed circuit board; 3. Positioning groove; 4. Chip array mechanism; 5. Copper foil circuit; 6. Negative terminal connector; 7. Composite bonding mechanism; 701. Main bonding area; 702. Auxiliary bonding area; 703. Gold wire limiting frame; 8. Gold wire module; 801. Strip pad; 802. Auxiliary pad; 803. Connecting gold wire; 9. Slot; 10. Positive terminal connector. Detailed Implementation

[0021] The foregoing and other technical contents, features and effects of this utility model are described in conjunction with the appendix below. Figures 1 to 3 The embodiments are described in detail below.

[0022] This embodiment provides a gold wire bonding region structure for WLED multi-chip packaging, as shown in the attached figure. Figure 1-3 As shown, it includes an insulating substrate 1, with a metal-based printed circuit board 2 containing circuits embedded in the upper surface of the insulating substrate 1. The upper surface of the metal-based printed circuit board 2 has a positioning groove 3 for mounting WLED chips. The interior of the metal-based printed circuit board 2 has embedded copper foil lines 5, and the copper foil lines 5 are respectively connected to the inner bottom wall of each positioning groove 3. The metal-based printed circuit board 2 can be electrically connected to the WLED chips inside the positioning groove 3 through the copper foil lines.

[0023] The positioning groove 3 contains a chip array mechanism 4 composed of multiple WLED chips. The chip array mechanism 4 includes multiple WLED chips arranged in a rectangular array, and each WLED chip is die-bonded in a positioning groove 3. The positioning groove 3 serves to limit and fix the WLED chips, ensuring that the multiple WLED chips maintain a consistent relative spacing when fixed. Each WLED chip has a positive terminal connector 10 fixedly installed on its side, which can be electrically connected to the copper foil circuit 5. The positive terminal connector 10 of each WLED chip is electrically connected to the copper foil circuit in its corresponding positioning groove 3, thereby forming a closed circuit for the WLED chips and ensuring normal use after the WLED chips are powered on.

[0024] The number of positioning slots 3 is the same as the number of WLED chips, and a negative terminal connector 6 that can be electrically connected to the metal-based printed circuit board 2 is fixedly installed on the same side of each WLED chip. A composite bonding mechanism 7 that can be electrically connected to the WLED chip is provided on the same side of the upper surface of the insulating substrate 1 as the negative terminal connector 6. The composite bonding mechanism 7 includes a main bonding area 701, an auxiliary bonding area 702, and a gold wire limiting frame 703. The gold wire limiting frame 703 is fixedly connected to the upper surface of the insulating substrate 1. 3 is made of insulating material and is integrally formed or fixedly connected to the insulating substrate 1; the main bonding area 701 and the auxiliary bonding area 702 are both opened at the end of the upper surface of the insulating substrate 1. The auxiliary bonding area 702 is opened on the side of the gold wire limiting frame 703 away from the chip array mechanism 4, and the main bonding area 701 is opened on the side of the auxiliary bonding area 702 away from the gold wire limiting frame 703. The gold wire limiting frame 703, the auxiliary bonding area 702 and the main bonding area 701 are arranged in a stepped manner to optimize the connection curvature of the gold wire.

[0025] A gold wire module 8, capable of electrical connection, is provided between the composite bonding mechanism 7 and the chip array mechanism 4. The gold wire module 8 includes strip pads 801, auxiliary pads 802, and connecting gold wires 803. The strip pads 801 are embedded in the inner bottom wall of the main bonding area 701, and the auxiliary pads 802 are embedded in the inner bottom wall of the auxiliary bonding area 702. The number of auxiliary pads 802 is the same as the number of rows of WLED chips in the chip array mechanism 4, with each auxiliary pad 802 corresponding to one column of WLED chips. The strip pads 801 and... Each auxiliary pad 802 is bonded with a connecting gold wire 803, and each auxiliary pad 802 is bonded with a connecting gold wire 803 to the negative terminal 6 on each WLED chip in its corresponding column. The row-level parallel architecture ensures that after the current flows in from the main bonding area 701, it is first distributed to the auxiliary bonding areas 702 of each row, and then evenly distributed to each WLED chip in that row. This results in a more uniform current distribution than all chips being directly connected in parallel on a single pad, thereby improving luminous uniformity and device lifespan.

[0026] The top of the gold wire limiting bracket 703 is provided with slots 9 at equal intervals for locking the gold wires 803. The gold wires 803 connecting the auxiliary pads 802 and the negative terminals 6 of each WLED chip are all passed through the corresponding slots 9 on the gold wire limiting bracket 703. This can limit and fix the gold wires 803 on each WLED chip and prevent them from interfering with each other. It forcibly limits the bonding path of the gold wires 803, so that the gold wires 803 can bond at different physical heights and planar areas, fundamentally eliminating the "spider web" effect and greatly reducing the risk of short circuit.

[0027] The number of slots 9 depends on the number of rows of WLED chips in the chip array mechanism 4 and the number of WLED chips in each row. If there are several WLED chips in each row, then the top of the gold wire limiting frame 703, corresponding to the WLED chips in that row, will have the same number of slots 9 as the row of WLED chips. In addition, according to the number of rows of WLED chips, the top of the gold wire limiting frame 703, corresponding to each row, will have the same number of slots 9 as the row of WLED chips. That is to say, the number of slots 9 is the same as the number of WLED chips, and the connecting gold wires 803 bonded to the negative electrode of the WLED chips are respectively passed through a separate slot 9, which can ensure that each connecting gold wire 803 is separated from each other and does not cross each other.

[0028] In summary, the steps for using this gold wire bonding region structure for WLED multi-chip packaging are as follows:

[0029] 1. Multiple WLED chips are die-bonded one by one into the corresponding positioning slots 3 on the metal-based printed circuit board 2 according to the designed matrix layout, and then fixed with conductive adhesive, so that the positive terminal 10 of each chip can be reliably electrically connected to the copper foil line 5 on the bottom wall of the positioning slot 3, thereby completing the common connection of the positive terminals of all chips.

[0030] 2. On the insulating substrate 1, on the side pointed to by the negative terminal 6 of the chip array, a composite bonding mechanism 7 is installed, ensuring that the mechanism consists of, from near to far, the following components: gold wire limiting frame 703, auxiliary bonding area 702, and main bonding area 701, and that the three are arranged in a stepped manner.

[0031] 3. Take a gold wire 803 and bond one end of it to the negative terminal 6 of a WLED chip in the row. Then, thread the gold wire 803 into the slot 9 at the top of the gold wire limiting bracket 703 that corresponds to the chip position. Next, bond the other end of the gold wire to the auxiliary pad 802 corresponding to the row.

[0032] 4. Repeat step 3 until all the negative terminals 6 of all chips are bonded to the auxiliary pads 802 shared by this row through independent connecting gold wires 803.

[0033] 5. Use an automatic wire bonding machine to connect the strip pad 801 to each auxiliary pad 802 with connecting gold wires 803, and then perform subsequent packaging.

[0034] The above description is only for illustrating the present utility model. It should be understood that the present utility model is not limited to the above embodiments, and various modifications that conform to the concept of the present utility model are within the protection scope of the present utility model.

Claims

1. A gold wire bonding region structure for WLED multi-chip packaging, comprising an insulating substrate (1), characterized in that: The upper surface of the insulating substrate (1) is provided with a metal-based printed circuit board (2). The upper surface of the metal-based printed circuit board (2) is provided with multiple positioning slots (3) for mounting WLED chips. The metal-based printed circuit board (2) is embedded with copper foil lines (5) and the copper foil lines (5) are respectively connected to the inner bottom wall of each positioning slot (3). The positioning groove (3) is internally provided with a chip array mechanism (4) composed of multiple WLED chips; A composite bonding mechanism (7) is provided on one side of the upper surface of the insulating substrate (1). A gold wire module (8) is provided between the composite bonding mechanism (7) and the chip array mechanism (4). The gold wire module (8) includes a strip pad (801) embedded in the main bonding area (701), an auxiliary pad (802) embedded in the auxiliary bonding area (702), and connecting gold wires (803). The strip pad (801) and the auxiliary pad (802) are bonded together by connecting gold wire (803), and the auxiliary pad (802) is also bonded to the negative terminal (6) of each WLED chip in the corresponding row by connecting gold wire (803). The top of the gold wire limiting frame (703) is provided with multiple slots (9) for engaging and disengaging the gold wire (803).

2. The gold wire bonding region structure for WLED multi-chip packaging according to claim 1, characterized in that: The composite bonding mechanism (7) includes a gold wire limiting frame (703), an auxiliary bonding area (702) and a main bonding area (701) arranged sequentially from the side closest to the chip array mechanism (4) to the side furthest away, and the three are arranged in a stepped manner.

3. The gold wire bonding region structure for WLED multi-chip packaging according to claim 1, characterized in that: The multiple WLED chips in the chip array mechanism (4) are arranged in a rectangular array, and each WLED chip is die-bonded in a positioning groove (3).

4. The gold wire bonding region structure for WLED multi-chip packaging according to claim 1, characterized in that: The number of auxiliary pads (802) is the same as the number of rows of WLED chips in the chip array mechanism (4), with each auxiliary pad (802) corresponding to a row of WLED chips.

5. The gold wire bonding region structure for WLED multi-chip packaging according to claim 1, characterized in that: The gold wires (803) connecting the auxiliary pads (802) and the negative terminals (6) of each WLED chip are all threaded through the corresponding slots (9) on the gold wire limiting frame (703).

6. The gold wire bonding region structure for WLED multi-chip packaging according to claim 1, characterized in that: The gold wire limiting frame (703), auxiliary bonding area (702) and main bonding area (701) have a height difference in the vertical direction, forming a stepped structure for optimizing the curvature of the connecting gold wire (803).

Images