Display device and electronic device

Abstract

The utility model discloses display device and electronic device. An embodiment of the utility model discloses a display device, include: display area, realize visible light on the substrate, and peripheral area, configure in at least one side of the display area, and have non - display area, the display device includes: scanning clock wiring part, including the multiple scanning clock wiring of the configuration in turn to one direction, sensing clock wiring part, including the multiple sensing clock wiring of the configuration in turn to the direction different from one direction, stage part, including the multiple stage of the multiple scanning clock wiring and the multiple sensing clock wiring connection, and insulating pattern part, configuration is overlapped with scanning clock wiring part or sensing clock wiring part.

Description

Technical Field

[0001] Embodiments of this utility model relate to a display device and an electronic device including the same. Background Technology

[0002] The applications of display devices have recently become more diverse. In addition, due to the thinner and lighter thickness of display devices, their use is becoming more widespread.

[0003] Furthermore, with the increasing application areas of display devices and the development of technologies that utilize display devices, the image quality and high resolution characteristics required by display devices have improved.

[0004] On the other hand, as display devices become thinner in form, similar to flat panels, the trend is towards an increase in the number of manufacturing steps and the complexity of the manufacturing process.

[0005] This limits the ability to achieve high-definition display devices through stable manufacturing processes. Utility Model Content

[0006] Embodiments of this utility model provide a display device with improved image quality characteristics and an electronic device including the same.

[0007] An embodiment of this utility model discloses a display device, including: a display area that realizes visible light on a substrate; and a peripheral area disposed on at least one side of the display area and having a non-display area. The display device includes: a scanning clock wiring section including a plurality of scanning clock wirings arranged sequentially in one direction; a sensing clock wiring section including a plurality of sensing clock wirings arranged sequentially in a direction different from the first direction; a stage section including a plurality of stages connected to the plurality of scanning clock wirings and the plurality of sensing clock wirings; and an insulating pattern section configured to overlap with the scanning clock wiring section or the sensing clock wiring section.

[0008] In this embodiment, the scanning clock wiring section and the sensing clock wiring section may be arranged along one direction, the plurality of sensing clock wirings of the sensing clock wiring section may be arranged sequentially along the one direction, and the plurality of scanning clock wirings of the scanning clock wiring section may be arranged sequentially along the opposite direction of the one direction.

[0009] In this embodiment, the scanning clock wiring section and the sensing clock wiring section may be arranged along one direction, the first sensing clock wiring to the Nth sensing clock wiring of the plurality of sensing clock wirings may be arranged sequentially along the one direction, and the first scanning clock wiring to the Nth scanning clock wiring of the plurality of scanning clock wirings may be arranged sequentially along the opposite direction of the one direction.

[0010] In this embodiment, the arrangement of the plurality of sensing clock wirings of the sensing clock wiring section in sequence may be symmetrical to the arrangement of the plurality of scanning clock wirings of the scanning clock wiring section in sequence.

[0011] In this embodiment, the distance between a scan clock wiring and a sensing clock wiring connected to one of the plurality of stages may have a different value than the distance between a scan clock wiring and a sensing clock wiring connected to another of the plurality of stages.

[0012] In this embodiment, the insulating pattern portion may be configured to correspond to the central region between the scan clock wiring portion and the sensing clock wiring portion, and may be configured to overlap with at least a portion of the scan clock wiring and at least a portion of the sensing clock wiring among the plurality of scan clock wiring and sensing clock wiring.

[0013] In this embodiment, the center of the insulating pattern portion may be configured to be offset from the central region between the scanning clock wiring portion and the sensing clock wiring portion.

[0014] In this embodiment, one or more insulating layers may be disposed between the scanning clock wiring portion and the sensing clock wiring portion and the insulating pattern portion.

[0015] In this embodiment, each of the plurality of stages of the stage may transmit one or more scan signals and sensing signals to the pixels of the display area using signals received through the plurality of sensing clock wirings and the plurality of scanning clock wirings.

[0016] Another embodiment of this utility model discloses an electronic device, including: a controller that generates one or more signals; and a display device that receives one or more signals from the controller and displays information; the display device includes: a scanning clock wiring section, a sensing clock wiring section, and a stage section, configured to receive signals from the controller and transmit signals for displaying information of the display device; the scanning clock wiring section includes a plurality of scanning clock wirings arranged sequentially in one direction; the sensing clock wiring section includes a plurality of sensing clock wirings arranged sequentially in a direction different from the one direction; the stage section includes a plurality of stages connected to the plurality of scanning clock wirings and the plurality of sensing clock wirings; and the display device includes an insulating pattern section configured to overlap with the scanning clock wiring section or the sensing clock wiring section.

[0017] Another embodiment of this utility model discloses an electronic device, including: a controller that generates one or more signals; and a display device that receives one or more signals from the controller and displays information; the display device includes: a scan clock wiring section, a sensing clock wiring section, and a stage section, configured to receive signals from the controller and transmit signals for displaying information of the display device, the scan clock wiring section includes a plurality of scan clock wirings arranged sequentially in one direction, the sensing clock wiring section includes a plurality of sensing clock wirings arranged sequentially in the one direction, the stage section includes a plurality of stages connected to the plurality of scan clock wirings and the plurality of sensing clock wirings, the display device includes an insulating pattern section configured to overlap with the scan clock wiring section or the sensing clock wiring section, and at least in the region overlapping with the insulating pattern section, a sensing clock wiring is arranged between two adjacent scan clock wirings among the plurality of scan clock wirings.

[0018] Another embodiment of the present invention discloses a display device, comprising: a display area that realizes visible light on a substrate; and a peripheral area disposed on at least one side of the display area and having a non-display area. The display device includes: a scanning clock wiring portion including a plurality of scanning clock wirings arranged sequentially in one direction; a sensing clock wiring portion including a plurality of sensing clock wirings arranged sequentially in the one direction; a stage portion including a plurality of stages connected to the plurality of scanning clock wirings and the plurality of sensing clock wirings; and an insulating pattern portion configured to overlap with the scanning clock wiring portion or the sensing clock wiring portion, wherein at least in the region overlapping with the insulating pattern portion, a sensing clock wiring is disposed between two adjacent scanning clock wirings among the plurality of scanning clock wirings.

[0019] In this embodiment, at least in the area overlapping with the insulating pattern portion, a scan clock wire may be configured between two adjacent sensing clock wires among the plurality of sensing clock wires.

[0020] In this embodiment, at least in the area overlapping with the insulating pattern portion, each of the plurality of scan clock wires of the scan clock wiring portion and each of the plurality of sensing clock wires of the sensing clock wiring portion may be arranged alternately with each other in sequence.

[0021] In this embodiment, the scanning clock wiring section and the sensing clock wiring section may be configured along the direction, and the first sensing clock wiring to the Nth sensing clock wiring of the plurality of sensing clock wirings and the first scanning clock wiring to the Nth scanning clock wiring of the plurality of scanning clock wirings may be configured alternately with each other along the direction.

[0022] In this embodiment, the insulating pattern portion may be configured to correspond to the central region between the scan clock wiring portion and the sensing clock wiring portion, and may be configured to overlap with at least a plurality of scan clock wirings and at least a plurality of sensing clock wirings.

[0023] In this embodiment, the center of the insulating pattern portion may be configured to be offset from the central region between the scanning clock wiring portion and the sensing clock wiring portion.

[0024] In this embodiment, the plurality of scanning clock wiring units and the plurality of sensing clock wiring units may be arranged alternately with each other along the one direction.

[0025] In this embodiment, each of the plurality of stages of the stage may transmit one or more scan signals and sensing signals to the pixels of the display area using signals received through the plurality of sensing clock wirings and the plurality of scanning clock wirings.

[0026] In this embodiment, the pixel may include one or more organic light-emitting elements that realize visible light.

[0027] Other aspects, features, and advantages, besides those described above, will become clear from the accompanying drawings, claims, and detailed description of the utility model.

[0028] The display device and electronic device including the present invention can easily achieve high image quality characteristics. Attached Figure Description

[0029] Figure 1 This is a plan view of a display device that briefly illustrates an embodiment of the present invention.

[0030] Figure 2 It is along Figure 1 A simplified cross-sectional view of the K region taken from line II-II.

[0031] Figure 3 It is used for explanation Figure 2 A simplified block diagram of its structure.

[0032] Figure 4 as well as Figure 5 It is shown Figure 2 A simplified cross-sectional view of a deformed example of the structure.

[0033] Figure 6 This is a plan view of a display device that briefly illustrates another embodiment of the present invention.

[0034] Figure 7 It is along Figure 6 A simplified cross-sectional view of the K region taken from line VII-VII.

[0035] Figure 8 as well as Figure 9 It is shown Figure 7 A simplified cross-sectional view of a selective embodiment of the structure.

[0036] Figure 10 This is a plan view of a display device that briefly illustrates yet another embodiment of the present invention.

[0037] Figure 11 It is along Figure 10 A simplified cross-sectional view of the K region taken from line XI-XI.

[0038] Figure 12 This is a plan view of a display device that briefly illustrates yet another embodiment of the present invention.

[0039] Figure 13 It is a brief illustration Figure 12 A block diagram of the display device.

[0040] Figure 14 It is a brief illustration Figure 12 The circuit diagram of a sub-pixel of the display device.

[0041] Figure 15 It is along Figure 12 A simplified cross-sectional view of the K region taken from line XXV-XXV.

[0042] Figure 16 It is along Figure 12 A simplified cross-sectional view of the region P, taken from line XXVI-XXVI.

[0043] Figure 17 This is a plan view of a display device that briefly illustrates yet another embodiment of the present invention.

[0044] Figure 18 It is along Figure 17 A simplified cross-sectional view of the K region taken from line XVIII-XVIII.

[0045] Figure 19 This is a cross-sectional view of a display device according to yet another embodiment of the present invention.

[0046] (Explanation of reference numerals in the attached diagram)

[0047] 101, 201, 301, 401, 501, 601: substrate

[0048] 110, 210, 310, 410, 510, 610: Scan clock wiring section

[0049] 120, 220, 320, 420, 520, 620: Sensing clock wiring section

[0050] 130, 230, 330, 430, 530, 630: Grade level

[0051] 140, 240, 340, 440, 540, 640: Insulating pattern section Detailed Implementation

[0052] This invention can be modified in various ways and can have various embodiments. Specific embodiments will be illustrated in the accompanying drawings and described in detail below. The effects, features, and methods of implementing this invention will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, this invention is not limited to the embodiments disclosed below, but can be implemented in various forms.

[0053] In the following embodiments, the terms "first," "second," etc., are not intended to be limiting, but are used to distinguish one constituent element from other constituent elements.

[0054] In the following embodiments, singular expressions include plural expressions unless explicitly indicated in the context.

[0055] In the following embodiments, terms such as "including" or "having" mean the presence of the features or constituent elements described in the specification, and do not preclude the possibility of additional features or constituent elements beyond one other.

[0056] In the following embodiments, when a membrane, region, constituent element, or other part is described as being located on or above other parts, this includes not only the case where it is directly located on other parts, but also the case where other membranes, regions, constituent elements, etc., are located in between.

[0057] In the accompanying drawings, the dimensions of the constituent elements may be enlarged or reduced for ease of explanation. For example, the dimensions and thicknesses of the various components shown in the drawings are arbitrarily depicted for clarity; therefore, this invention is not necessarily limited to the depicted configuration.

[0058] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system, but can be interpreted in a general sense. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0059] When an embodiment can be implemented in different forms, the specific process sequence can also be performed differently from the described sequence. For example, two processes described consecutively can be performed substantially simultaneously, or they can be performed in the reverse order of the described sequence.

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing the invention with reference to the drawings, the same or corresponding constituent elements will be given the same reference numerals and repeated descriptions thereof will be omitted.

[0061] Figure 1 This is a plan view of a display device that briefly illustrates an embodiment of the present invention. Figure 2 It is along Figure 1 A simplified cross-sectional view of the K region taken from line II-II. Figure 3 It is used for explanation Figure 2 A simplified block diagram of its structure.

[0062] The display device 100 may include a scanning clock wiring section 110, a sensing clock wiring section 120, a stage section 130, and an insulating pattern section 140.

[0063] The insulating pattern portion 140 can serve various functions, such as supporting a manufacturing apparatus (e.g., a mask component) for forming one or more layers of the display device 100, and for this purpose, it can be configured to have a set height. Alternatively, as another example, the insulating pattern portion 140 can also be used for other functions, such as serving as a partition wall that restricts the formation of adjacent layers (e.g., insulating material or encapsulating material).

[0064] Reference Figure 1 The display device 100 may include a display area DA and a peripheral area PA defined on the substrate 101.

[0065] The display area DA can have more than one display element, such as an organic light-emitting element, to display images. Alternatively, as another example, the display element can include one of various other types, such as a quantum dot light-emitting element or a liquid crystal display element. This embodiment illustrates the case where the display element is an organic light-emitting element, but other different types of display elements can certainly be applied as well.

[0066] In addition, multiple pixels can be configured in the display area DA, and each pixel can include multiple sub-pixels. More than one display element can be configured in such a sub-pixel.

[0067] A peripheral region PA can be formed around the display area DA. The peripheral region PA may include a non-display area; for example, the non-display area may be formed to surround the display area DA. Alternatively, as another optional embodiment, the peripheral region PA or the non-display area of ​​the peripheral region PA may be formed to be adjacent only to one or both sides of the display area DA.

[0068] In the peripheral region PA, a drive circuit section can be configured to generate various signals for the operation of pixels in the display region DA. This drive circuit section can have one or more drive circuit sections. Specifically, a scan clock wiring section (e.g., Figure 2 110), sensing clock wiring section (e.g., Figure 2 120), level (e.g., Figure 2 130) and insulating pattern portion (e.g., Figure 2 (140) can be configured in the surrounding PA area.

[0069] Furthermore, although not illustrated, the display area DA can configure not only sub-pixels, but also the scan signal wiring connected to the sub-pixels (e.g., Figure 3 SCL1 to SCL6), sensing signal wiring (e.g., Figure 3 (SSL1 to SSL6). In addition, more than one data routing and more than one drive voltage routing can be configured in a subpixel.

[0070] Additionally, the scan clock wiring section 110, the sensing clock wiring section 120, and the stage section 130 may be included in the scan signal driving section.

[0071] The substrate 101 may include various materials. Specifically, the substrate 101 may be formed of other materials such as glass, metal, or organic materials.

[0072] As an alternative embodiment, substrate 101 may be formed of a flexible material. For example, substrate 101 may be formed to be easily bent, folded, rolled, or bent.

[0073] As an alternative embodiment, substrate 101 may be made of ultrathin glass, metal, or plastic. For example, when plastic is used, substrate 101 may contain polyimide (PI). As other specific examples, substrate 101 may contain at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polycarbonate, tricellulose acetate, and cellulose acetate propionate.

[0074] Alternatively, the substrate 101 may have one or more layers, such as a multi-layer structure. For example, the substrate 101 may include an organic layer (e.g., a resin-based material) and an inorganic layer, or more specifically, an inorganic layer disposed between two organic layers.

[0075] Reference Figure 2 The scan clock wiring section 110 may include a plurality of scan clock wirings, for example, it may include first to sixth scan clock wirings 111 to 116. Such a number of six is ​​exemplary, and there may be fewer or more of them.

[0076] The sensing clock wiring section 120 may include a plurality of sensing clock wirings, for example, it may include first to sixth sensing clock wirings 121 to 126. Such a number of six is ​​exemplary, and there may be fewer or more such wirings.

[0077] The scanning clock wiring section 110 and the sensing clock wiring section 120 can be arranged along a direction (e.g., the X-axis direction). For example, the scanning clock wiring section 110 and the sensing clock wiring section 120 can be separated along the width direction of each wiring section and arranged along a direction (e.g., the X-axis direction).

[0078] Each of the first to sixth sensing clock wirings 121 to 126 of the sensing clock wiring section 120 can be arranged along a direction. For example, the first to sixth sensing clock wirings 121 to 126 can be arranged in one direction (the positive direction of the X-axis or the direction of the X-axis). Figure 2 Based on the left-to-right direction, the configuration is arranged sequentially.

[0079] As another way of putting it, the first sensing clock wiring 121, the second sensing clock wiring 122, the third sensing clock wiring 123, the fourth sensing clock wiring 124, the fifth sensing clock wiring 125, and the sixth sensing clock wiring 126 can be arranged in one direction (the positive direction of the X-axis or...) Figure 2 (Based on the left-to-right direction) are arranged sequentially with each other spaced apart from the other.

[0080] Each of the first to sixth scan clock wirings 111 to 116 of the scan clock wiring section 110 can be arranged along a direction. For example, the first to sixth scan clock wirings 111 to 116 can be arranged in one direction (the negative direction of the X-axis or the direction of the X-axis). Figure 2 Based on the reference direction from right to left, configure sequentially.

[0081] As another way of putting it, the first scan clock wiring 111, the second scan clock wiring 112, the third scan clock wiring 113, the fourth scan clock wiring 114, the fifth scan clock wiring 115, and the sixth scan clock wiring 116 can be in one direction (the negative direction of the X-axis or...) Figure 2 (Based on the direction from right to left) are arranged sequentially with each other spaced apart from the other.

[0082] In other words, the first to sixth sensing clock wirings 121 to 126 of the sensing clock wiring section 120 and the first to sixth scanning clock wirings 111 to 116 of the scanning clock wiring section 110 can be arranged in a left-right symmetrical manner based on the attached drawings.

[0083] Furthermore, as another way of putting it, the distance between clock lines connected to the first stage of stage 130 may be different from the distance between clock lines connected to another stage. For example, the interval d1 between the first sensing clock line 121 and the first scan clock line 111, the interval d2 between the second sensing clock line 122 and the second scan clock line 112, the interval d3 between the third sensing clock line 123 and the third scan clock line 113, the interval d4 between the fourth sensing clock line 124 and the fourth scan clock line 114, the interval d5 between the fifth sensing clock line 125 and the fifth scan clock line 115, and the interval d6 between the sixth sensing clock line 126 and the sixth scan clock line 116 may be different.

[0084] For example, interval d6 can be greater than interval d1. As a specific example, intervals d1, d2, d3, d4, d5, and d6 can have successively larger values.

[0085] Alternatively, as an alternative embodiment, although not shown, it is also possible that the first to sixth sensing clock wirings 121-126 are arranged sequentially from right to left, and the first to sixth scanning clock wirings 111-116 of the scanning clock wiring section 110 are arranged sequentially from left to right. In this case, the interval d6 can be smaller than the interval d1. As a specific example, the intervals d1, d2, d3, d4, d5, and d6 can also have successively smaller values.

[0086] Reference Figure 3 , level (e.g., Figure 2 The 130 can be configured to be separated from the scan clock wiring section 110 and the sensing clock wiring section 120, and connected by one or more connecting lines.

[0087] For example, stage 130, scan clock wiring 110, and sensing clock wiring 120 can be arranged along a direction (e.g., the X-axis direction). As a specific example, as shown in the figures, stage 130 can be configured to face the side of sensing clock wiring 120 opposite to the side facing scan clock wiring 110. As another example, stage 130 can also be configured on at least one side of scan clock wiring 110 and sensing clock wiring 120.

[0088] Although not shown, stage 130 may include multiple stages, for example, six stages. Figure 3 For ease of explanation, three levels are shown, for example, level 131, level 2132 and level 6136 are shown, while level 3, 4 and 5 are omitted (not shown).

[0089] The first stage 131 can output the first scan signal to the first scan signal wiring SCL1 and output the first sensing signal to the first sensing signal wiring SSL1.

[0090] The second stage 132 can output the second scan signal to the second scan signal wiring SCL2 and output the second sensing signal to the second sensing signal wiring SSL2.

[0091] The sixth level 136 can output the sixth scan signal to the sixth scan signal wiring SCL6 and output the sixth sensing signal to the sixth sensing signal wiring SSL6.

[0092] Each of these output signals can be transmitted to the pixels of the display area DA.

[0093] Each of the stages included in the stage 130 can be connected to the wiring of the scan clock wiring section 110 and the wiring of the sensing clock wiring section 120.

[0094] In the first stage 131, the first scan clock wiring 111 of the scan clock wiring section 110 and the first sensing clock wiring 121 of the sensing clock wiring section 120 can be electrically connected, and can be connected through each conductive connection line.

[0095] In the second stage 132, the second scan clock wiring 112 of the scan clock wiring section 110 and the second sensing clock wiring 122 of the sensing clock wiring section 120 can be electrically connected, and can be connected through each conductive connection line.

[0096] In the sixth stage 136, the sixth scan clock wiring 116 of the scan clock wiring section 110 and the sixth sensing clock wiring 126 of the sensing clock wiring section 120 can be electrically connected, and can be connected through each conductive connection line.

[0097] Although not shown, as an alternative embodiment, it may also include one or more clock wiring sections electrically connected to the stage 130. For example, it may include a carry clock wiring section and a global clock wiring section. Each of the one or more clock wiring sections may include multiple clock wirings, and such multiple clock wirings are respectively connected to multiple stages 131, 132, 136 of each stage 130.

[0098] Each of the multiple stages of such stage 130 can be connected to at least one scan signal wiring to apply a scan signal, and connected to a sensing signal wiring to apply a sensing signal.

[0099] For example, the first stage 131 of stage 130 can output a first scan signal to the first scan signal wiring SCL1 and a first sensing signal to the first sensing signal wiring SSL1 based on the first sensing clock signal received through the first sensing clock wiring 121 and the first scan clock signal received through the first scan clock wiring 111. Alternatively, as an optional embodiment, the first stage 131 can be connected to a carry clock wiring section and a global clock wiring section. In this case, the first scan signal and the first sensing signal can be output based on the first sensing clock signal, the first scan clock signal, and one or more carry clock signals or one or more global clock signals.

[0100] Alternatively, as a specific example, the first stage 131 may also output the first sensing signal to the first sensing signal wiring SSL1 based on the first sensing clock signal received through the first sensing clock wiring 121, and output the first scanning signal to the first scanning signal wiring SCL1 based on the first scanning clock signal received through the first scanning clock wiring 111.

[0101] Alternatively, for example, the second stage 132 of stage 130 can output a second scan signal to the second scan signal wiring SCL2 and output a second sensing signal to the second sensing signal wiring SSL2 based on the second sensing clock signal received through the second sensing clock wiring 122 and the second scan clock signal received through the second scan clock wiring 112. Alternatively, as an alternative embodiment, the second stage 132 can be connected to a carry clock wiring section and a global clock wiring section. In this case, the second scan signal and the second sensing signal can be output based on the second sensing clock signal, the second scan clock signal, and one or more carry clock signals or one or more global clock signals.

[0102] Alternatively, as a specific example, the second stage 132 may also output the second sensing signal to the second sensing signal wiring SSL2 based on the second sensing clock signal received through the second sensing clock wiring 122, and output the second scanning signal to the second scanning signal wiring SCL2 based on the second scanning clock signal received through the second scanning clock wiring 112.

[0103] Additionally, for example, the sixth stage 136 of stage 130 can output a sixth scan signal to the sixth scan signal wiring SCL6 and a sixth sensing signal to the sixth sensing signal wiring SSL6 based on the sixth sensing clock signal received through the sixth sensing clock wiring 126 and the sixth scan clock signal received through the sixth scan clock wiring 116. Alternatively, as an optional embodiment, the sixth stage 136 can be connected to a carry clock wiring unit and a global clock wiring unit. In this case, the sixth scan signal and the sixth sensing signal can be output based on the sixth sensing clock signal, the sixth scan clock signal, and one or more carry clock signals or one or more global clock signals.

[0104] Alternatively, as a specific example, the sixth level 136 can also output the sixth sensing signal to the sixth sensing signal wiring SSL6 based on the sixth sensing clock signal received through the sixth sensing clock wiring 126, and output the sixth scanning signal to the sixth scanning signal wiring SCL6 based on the sixth scanning clock signal received through the sixth scanning clock wiring 116.

[0105] Although levels three through five are not illustrated, their structure can be understood by referring to levels one, two, and six, 131, 132, and 136, so specific explanations are omitted.

[0106] Reference Figure 2 The insulating pattern portion 140 may be configured to overlap with at least one area of ​​the scanning clock wiring portion 110 or the sensing clock wiring portion 120.

[0107] As an alternative embodiment, the insulating layer NCI can be formed on the scan clock wiring portion 110 and the sensing clock wiring portion 120. Through the insulating layer NCI, the insulating pattern portion 140 can be insulated from the scan clock wiring portion 110 and the sensing clock wiring portion 120.

[0108] On the other hand, as an alternative embodiment, the insulating layer NCI may also be formed to cover the stage 130 on the stage 130.

[0109] As an alternative embodiment, another insulating layer may also be formed on the insulating layer NCI, which is formed to correspond at least to one side or top of the insulating pattern portion 140.

[0110] The insulating pattern portion 140 may be configured to overlap with at least one area of ​​the scanning clock wiring portion 110 or the sensing clock wiring portion 120.

[0111] The insulating pattern portion 140 can serve various functions, such as supporting a manufacturing apparatus (e.g., a mask component) for forming one or more layers of the display device 100, and for this purpose, it can be configured to have a set height. Alternatively, as another example, the insulating pattern portion 140 can also be used for other functions, such as serving as a partition wall that restricts the formation of adjacent layers (e.g., insulating material or encapsulating material).

[0112] The insulating pattern portion 140 may contain various insulating materials, such as organic materials. Furthermore, the insulating pattern portion 140 may be formed as a single layer or multiple layers.

[0113] Reference Figure 2 The insulating pattern portion 140 can be configured to overlap with the first to third scan clock wirings 111 to 113 of the scan clock wiring portion 110 and the first to third sensing clock wirings 121 to 123 of the sensing clock wiring portion 120.

[0114] In this embodiment, the direction in which the first to sixth scan clock wirings 111 to 116 of the scan clock wiring section 110 are sequentially arranged is opposite to the direction in which the first to sixth sensing clock wirings 121 to 126 of the sensing clock wiring section 120 are sequentially arranged.

[0115] For example, the configuration of the first to sixth scan clock wirings 111 to 116 of the scan clock wiring section 110 in this embodiment can be symmetrical to the configuration of the first to sixth sensing clock wirings 121 to 126 of the sensing clock wiring section 120.

[0116] In this way, when the display device 100 is used to offset the changes in image quality characteristics (e.g., increased brightness) of the first to sixth scan clock lines 111 to 116 of the scan clock wiring section 110 and the changes in image quality characteristics (e.g., decreased brightness) of the first to sixth sensing clock lines 121 to 126 of the sensing clock wiring section 120, the uneven brightness defects caused by changes due to external or internal environmental problems can be reduced.

[0117] On the other hand, when the display device 100 is used in environments with high temperature and high humidity, moisture may flow in through the edges. Since the insulating pattern portion 140 is closer to the edge area than the center of the display device 100, it may curl up or down in the area adjacent to the insulating pattern portion 140. Due to such curling up or down, the capacitance in the area adjacent to the insulating pattern portion 140 may change. For example, the capacitance of the scan clock wiring portion 110 or the sensing clock wiring portion 120 may increase.

[0118] Alternatively, as a specific example, if the capacitance increases in the region adjacent to each scan clock line of the scan clock wiring section 110, the voltage applied to the gate of the transistor driving the pixel through the scan signal wiring increases, thereby increasing the brightness of the display element. Alternatively, as another specific example, if the capacitance increases in the region adjacent to each sensing clock line of the sensing clock wiring section 120, the voltage applied to the gate of the transistor related to the initialization of the connected pixel increases, thereby decreasing the brightness of the display element.

[0119] Furthermore, the increase or decrease in brightness of such clock wiring can vary depending on its sequence. For example, the increase in brightness can be greater with the sequence of the first to sixth scan clock wirings 111-116 of the scan clock wiring section 110, and the decrease in brightness can be greater with the sequence of the first to sixth sensing clock wirings 121-126 of the sensing clock wiring section 120. In this case, when the sixth scan clock wiring 116 and the first sensing clock wiring 121 are adjacent, the brightness change increases, and the occurrence of image quality defects on the screen may increase. In this embodiment, the first to sixth scan clock wirings 111-116 of the scan clock wiring section 110 can be arranged sequentially in one direction, and the first to sixth sensing clock wirings 121-126 of the sensing clock wiring section 120 can be arranged in the opposite direction. Thus, the first scan clock wiring 111 and the first sensing clock wiring 121 can be configured to be adjacent.

[0120] As a result, the brightness characteristics can be improved by reducing the increase in brightness caused by the increased capacitance of the first to sixth scan clock lines 111 to 116 of the scan clock wiring section 110 and the decrease in brightness caused by the increased capacitance of the first to sixth sensing clock lines 121 to 126 of the sensing clock wiring section 120.

[0121] On the other hand, Figure 2 The first to third scan clock wirings 111 to 113 of the intermediate scan clock wiring section 110 and the first to third sensing clock wirings 121 to 123 of the sensing clock wiring section 120 can be configured to overlap with the insulating pattern section 140. As a specific example, the insulating pattern section 140 can be configured to overlap with the central region between the scan clock wiring section 110 and the sensing clock wiring section 120.

[0122] In this way, the capacitance changes of the first to third scanning clock wirings 111 to 113, which overlap with the insulating pattern portion 140, are relatively large, and the capacitance changes of the first to third sensing clock wirings 121 to 123 are also relatively large. This allows areas with large increases in brightness and areas with large decreases in brightness to overlap together, thereby reducing uneven brightness in the pixels of the display device 100, such as defects like stripes.

[0123] Figure 4 as well as Figure 5 It is shown Figure 2 A simplified cross-sectional view of a deformed example of the structure.

[0124] Reference Figure 4 The display device 100' is configured with the insulating pattern section 140'. Figure 2 Different. For example, the insulating pattern portion 140' may also be configured to overlap with the first to sixth scan clock lines 111 to 116 of the scan clock line portion 110. As a specific example, the center of the insulating pattern portion 140' may be configured to be offset from the central region between the scan clock line portion 110 and the sensing clock line portion 120.

[0125] At this time, the first sensing clock wiring 121 in the sensing clock wiring section 120 can be made to be adjacent to the insulating pattern section 140'. This reduces the unevenness of the increase in brightness of the scanning clock wiring section 110. The first sensing clock wiring 121, which has the smallest decrease in brightness in the sensing clock wiring section 120, is adjacent to the insulating pattern section 140', thereby controlling the brightness decrease to be small even if the capacitance of the first sensing clock wiring 121 increases.

[0126] Reference Figure 5 The display device 100” is configured with the insulating pattern section 140”. Figure 2 Different. For example, the insulating pattern portion 140” can also be configured to overlap with the first to sixth sensing clock wirings 121 to 126 of the sensing clock wiring portion 120.

[0127] The first to sixth sensing clock wirings 121-126 overlap with the insulating pattern portion 140”, thus reducing or preventing uneven brightness increases caused by capacitance changes in the first to sixth scanning clock wirings 111-116 due to vertical warping caused by external environmental factors, thereby reducing the visibility of brightness defects. This improves the image quality characteristics of the display device. Furthermore, the wiring of the scanning clock wiring portion 110 most adjacent to the insulating pattern portion 140” can be made the first scanning clock wiring 111, thereby reducing the magnitude of brightness increases and improving image quality characteristics.

[0128] Reference Figures 1 to 5 The display devices 100, 100', and 100" in this embodiment may include a circuit region for driving scan signals disposed in the peripheral region PA, specifically including a scan clock wiring section 110, a sensing clock wiring section 120, and a stage section 130. In addition, the display devices 100, 100', and 100" may include insulating pattern sections 140, 140', and 140" that overlap with the scan clock wiring section 110 or the sensing clock wiring section 120.

[0129] The stage 130 may include multiple stages 131, 132, and 136, each stage sequentially connecting multiple wirings of the scan clock wiring section and sequentially connecting wirings of the sensing clock wiring section. In this case, the scan clock wiring section and the sensing clock wiring section may be arranged in one direction, and the multiple wirings in each scan clock wiring section and the sensing clock wiring section may also be arranged in one direction. Specifically, the multiple scan clock wirings of the scan clock wiring section may be arranged in one direction in a specific order, i.e., in the order of the sixth to the first scan clock wirings, while the multiple sensing clock wirings of the sensing clock wiring section may be arranged in the opposite order, i.e., in the order of the first to the sixth sensing clock wirings.

[0130] When warping occurs due to moisture or other factors that increase with usage time caused by external or internal environments, the capacitance in the scan clock wiring or sensing clock wiring may change, for example, increase. This can lead to an increase or decrease in brightness in at least one area of ​​the display device 100. In this case, the order of the multiple sensing clock wirings and the multiple scan clock wirings can be reversed, for example, the wirings can be configured symmetrically. This prevents the brightness increase and decrease areas from being too close due to the proximity of adjacent areas, such as the sixth scan clock wiring and the first sensing clock wiring, which would reduce the recognizability of uneven brightness changes.

[0131] Figure 6 This is a plan view of a display device that briefly illustrates another embodiment of the present invention. Figure 7 It is along Figure 6 A simplified cross-sectional view of the K region taken from line VII-VII.

[0132] The display device 200 may include a substrate 201, a scanning clock wiring section 210, a sensing clock wiring section 220, a stage section 230, and an insulating pattern section 240.

[0133] Reference Figure 6 The display device 200 may include a display area DA and a peripheral area PA. For ease of explanation, the description will focus on the differences from the aforementioned embodiments.

[0134] Reference Figure 7 The scan clock wiring section 210 may include a plurality of scan clock wirings, for example, it may include first to sixth scan clock wirings 211 to 216. Such a number of six is ​​exemplary, and there may be fewer or more of them.

[0135] The sensing clock wiring section 220 may include a plurality of sensing clock wirings, for example, it may include first to sixth sensing clock wirings 221 to 226. Such a number of six is ​​exemplary, and there may be fewer or more such wirings.

[0136] The scanning clock wiring section 210 and the sensing clock wiring section 220 can be arranged along a direction (e.g., the X-axis direction). For example, the scanning clock wiring section 210 and the sensing clock wiring section 220 can be separated along the width direction of each wiring section and arranged along a direction (e.g., the X-axis direction).

[0137] Each of the first to sixth sensing clock wirings 221 to 226 of the sensing clock wiring section 220 can be arranged along a direction. For example, the first to sixth sensing clock wirings 221 to 226 can be arranged in one direction (the positive direction of the X-axis or the direction of the X-axis). Figure 7 Based on the left-to-right direction, the configuration is arranged sequentially.

[0138] As another way of putting it, the first sensing clock wiring 221, the second sensing clock wiring 222, the third sensing clock wiring 223, the fourth sensing clock wiring 224, the fifth sensing clock wiring 225, and the sixth sensing clock wiring 226 can be in one direction (the positive direction of the X-axis or...) Figure 7 (Based on the left-to-right direction) are arranged sequentially with each other spaced apart from the other.

[0139] Each of the first to sixth scan clock wirings 211 to 216 of the scan clock wiring section 210 can be arranged along a direction. For example, the first to sixth scan clock wirings 211 to 216 can be arranged in one direction (the positive direction of the X-axis or the direction of the X-axis). Figure 7 Based on the left-to-right direction, the configuration is arranged sequentially.

[0140] As another way of putting it, the first scan clock wiring 211, the second scan clock wiring 212, the third scan clock wiring 213, the fourth scan clock wiring 214, the fifth scan clock wiring 215, and the sixth scan clock wiring 216 can be in one direction (the positive direction of the X-axis or...) Figure 7 (Based on the left-to-right direction) are arranged sequentially with each other spaced apart from the other.

[0141] To be more specific, each of the first to sixth sensing clock wires 221 to 226 of the sensing clock wiring section 220 and each of the first to sixth scanning clock wires 211 to 216 of the scanning clock wiring section 210 can be configured to be adjacent to each other.

[0142] As another expression, a sensing clock line can be configured between two adjacent scanning clock lines, and a scanning clock line can be configured between two adjacent sensing clock lines.

[0143] As another expression, each of the first to sixth sensing clock wires 221 to 226 of the sensing clock wiring section 220 and each of the first to sixth scanning clock wires 211 to 216 of the scanning clock wiring section 210 can be arranged alternately with each other in sequence.

[0144] As yet another expression, along a direction (e.g.) Figure 7 The positive direction of the X-axis, Figure 7 (From left to right), for example, the direction in which the scan clock wiring section 210 and the sensing clock wiring section 220 are arranged, the first scan clock wiring 211, the first sensing clock wiring 221, the second scan clock wiring 212, the second sensing clock wiring 222, the third scan clock wiring 213, the third sensing clock wiring 223, the fourth scan clock wiring 214, the fourth sensing clock wiring 224, the fifth scan clock wiring 215, the fifth sensing clock wiring 225, the sixth scan clock wiring 216, and the sixth sensing clock wiring 226 can be arranged sequentially.

[0145] As another alternative embodiment, the first sensing clock wiring 221 can be configured instead of the first scanning clock wiring 211.

[0146] Additionally, as another alternative embodiment, in the opposite direction (e.g.) Figure 7 The negative direction of the X-axis Figure 7 Each of the first to sixth sensing clock wires 221 to 226 of the sensing clock wiring section 220 (from right to left) and each of the first to sixth scanning clock wires 211 to 216 of the scanning clock wiring section 210 can also be arranged alternately with each other.

[0147] Stage 230 can be configured to be spaced apart from scan clock wiring section 210 and sensing clock wiring section 220, and connected via one or more connecting lines. Although not shown, stage 230 may include multiple stages, for example, six stages, each of which can output a scan signal to scan signal wiring and a sensing signal to sensing signal wiring.

[0148] Each stage included in stage 230 can be connected to the wiring of scan clock wiring section 210 and the wiring of sensing clock wiring section 220. For example, in the first stage (not shown), the first scan clock wiring 211 of scan clock wiring section 210 and the first sensing clock wiring 221 of sensing clock wiring section 220 can be electrically connected via respective conductive connection lines. Similarly, in the second stage (not shown), the second scan clock wiring 212 of scan clock wiring section 210 and the second sensing clock wiring 222 of sensing clock wiring section 220 can be electrically connected via respective conductive connection lines. In this way, each of the multiple stages of stage 230 can be electrically connected to its corresponding (e.g., the same number) scan clock wiring and sensing clock wiring.

[0149] The insulating pattern portion 240 may be configured to overlap with at least one area of ​​the scanning clock wiring portion 210 or the sensing clock wiring portion 220.

[0150] As an alternative embodiment, the insulating layer NCI can be formed on the scan clock wiring portion 210 and the sensing clock wiring portion 220. Through the insulating layer NCI, the insulating pattern portion 240 can be insulated from the scan clock wiring portion 210 and the sensing clock wiring portion 220.

[0151] On the other hand, as an alternative embodiment, the insulating layer NCI may also be formed to cover the stage 230.

[0152] As an alternative embodiment, another insulating layer may also be formed on the insulating layer NCI, which is formed to correspond at least to one side or top of the insulating pattern portion 240.

[0153] The insulating pattern portion 240 may be configured to overlap with at least one area of ​​the scanning clock wiring portion 210 or the sensing clock wiring portion 220.

[0154] Reference Figure 7 The insulating pattern portion 240 may be configured to overlap with the third and fourth scan clock wirings 213 and 214 of the scan clock wiring portion 210 and the third and fourth sensing clock wirings 223 and 224 of the sensing clock wiring portion 220, and may be configured to overlap with at least a portion of the second sensing clock wiring 222 and at least a portion of the fifth scan clock wiring 215.

[0155] In this embodiment, the direction in which the first to sixth scan clock wirings 211 to 216 of the scan clock wiring section 210 are sequentially arranged is the same as the direction in which the first to sixth sensing clock wirings 221 to 226 of the sensing clock wiring section 220 are sequentially arranged.

[0156] Alternatively, a sensing clock line can be configured between two adjacent scanning clock lines, and a scanning clock line can be configured between two adjacent sensing clock lines. For example, each of the first to sixth sensing clock lines 221 to 226 of the sensing clock line section 220 and each of the first to sixth scanning clock lines 211 to 216 of the scanning clock line section 210 can be configured alternately with each other in sequence.

[0157] In this way, when the display device 200 is used to offset the changes in image quality characteristics (e.g., increased brightness) of the first to sixth scan clock lines 211 to 216 of the scan clock line section 210 and the changes in image quality characteristics (e.g., decreased brightness) of the first to sixth sensing clock lines 221 to 226 of the sensing clock line section 220, the uneven brightness defects caused by changes due to external or internal environmental problems can be reduced.

[0158] On the other hand, when the display device 200 is used in environments with high temperature and high humidity, moisture may flow in through the edges. Since the insulating pattern portion 240 is closer to the edge area than the center of the display device 200, it may curl up or down in the area adjacent to the insulating pattern portion 240. Due to such curling up or down, the capacitance in the area adjacent to the insulating pattern portion 240 may change. For example, the capacitance of the scan clock wiring portion 210 or the sensing clock wiring portion 220 may increase.

[0159] Alternatively, as a specific example, if the capacitance increases in the region adjacent to each scan clock line of the scan clock wiring section 210, the voltage applied to the gate of the transistor driving the pixel through the scan signal wiring increases, thereby increasing the brightness of the display element. Alternatively, as another specific example, if the capacitance increases in the region adjacent to each sensing clock line of the sensing clock wiring section 220, the voltage applied to the gate of the transistor related to the initialization of the connected pixel increases, thereby decreasing the brightness of the display element.

[0160] Furthermore, the increase or decrease in brightness of such clock wiring can vary depending on its sequence. For example, the increase in brightness can be greater with the sequence of the first to sixth scan clock wirings 211 to 216 of the scan clock wiring section 210. Conversely, the decrease in brightness can be greater with the sequence of the first to sixth sensing clock wirings 221 to 226 of the sensing clock wiring section 220.

[0161] In this embodiment, each of the first to sixth sensing clock wires 221 to 226 of the sensing clock wiring section 220 and each of the first to sixth scanning clock wires 211 to 216 of the scanning clock wiring section 210 are arranged alternately with each other in sequence. For example, the first scanning clock wire 211 and the first sensing clock wire 221 are arranged adjacent to each other, and the second scanning clock wire 212 and the second sensing clock wire 222 are arranged adjacent to each other. This makes it easy to counteract the increase and decrease of brightness. In this way, the image quality non-uniformity recognition caused by uneven brightness can be reduced, and the image quality characteristics of the display device 200 can be improved.

[0162] On the other hand, Figure 7 The insulating pattern portion 240 can be arranged in the central region along the width direction of the scanning clock wiring portion 210 and the sensing clock wiring portion 220, thereby reducing the occurrence of abrupt brightness changes in the first or sixth scanning clock wiring or the first or sixth sensing clock wiring.

[0163] Figure 8 as well as Figure 9 It is shown Figure 7 A simplified cross-sectional view of a selective embodiment of the structure.

[0164] Reference Figure 8 The display device 200' is configured with the insulating pattern section 240'. Figure 7 Different. For example, the insulating pattern portion 240' may also be configured to overlap with the first scan clock wiring 211, the first sensing clock wiring 221, the second scan clock wiring 212, the second sensing clock wiring 222, the third scan clock wiring 213, and the third sensing clock wiring 223.

[0165] The pairs (e.g., three pairs) of the scan clock wiring and sensing clock wiring connected at the same level overlap with the insulating pattern section 240', so that unevenness in brightness increase or decrease can be precisely controlled due to the problem of increased capacitance caused by the warping between upper and lower layers caused by the external environment.

[0166] Reference Figure 9 The display device 200” is configured with the insulating pattern section 240”. Figure 7 Different. For example, the insulating pattern portion 240” can also be configured to overlap with the fourth scan clock wiring 214, the fourth sensing clock wiring 224, the fifth scan clock wiring 215, the fifth sensing clock wiring 225, the sixth scan clock wiring 216, and the sixth sensing clock wiring 226.

[0167] The pairs (e.g., three pairs) of the scan clock wiring and sensing clock wiring connected at the same level overlap with the insulating pattern section 240”, so that unevenness in brightness increase or decrease can be precisely controlled due to capacitance increase caused by the warping between upper and lower layers caused by the external environment.

[0168] Reference Figures 6 to 9 The display devices 200, 200', and 200" in this embodiment may include a circuit region for driving scan signals disposed in the peripheral region PA, specifically including a scan clock wiring section 210, a sensing clock wiring section 220, and a stage section 230. In addition, the display devices 200, 200', and 200" may include insulating pattern sections 240, 240', and 240" that overlap with the scan clock wiring section 210 and the sensing clock wiring section 220.

[0169] The stage 230 may include multiple stages, in which multiple wirings of the scan clock wiring section are sequentially connected, and wirings of the sensing clock wiring section are sequentially connected. In this case, the scan clock wiring section and the sensing clock wiring section may be arranged along one direction, and the multiple wirings included in each stage may also be arranged in one direction. Specifically, the multiple scan clock wirings of the scan clock wiring section and the multiple sensing clock wirings of the sensing clock wiring section may be arranged alternately in sequence.

[0170] This makes it easy to counteract areas of increased and decreased brightness in the display device, thereby reducing the recognizability of uneven brightness variations.

[0171] Figure 10 This is a plan view of a display device that briefly illustrates yet another embodiment of the present invention. Figure 11 It is along Figure 10 A simplified cross-sectional view of the K region taken from line XI-XI.

[0172] The display device 300 may include a substrate 301, a scanning clock wiring section 310, a sensing clock wiring section 320, a stage section 330, and an insulating pattern section 340.

[0173] Reference Figure 10 The display device 300 may include a display area DA and a peripheral area PA. For ease of explanation, the description will focus on the differences from the aforementioned embodiments.

[0174] Reference Figure 11 The scan clock wiring section 310 may include multiple scan clock wirings, such as first to sixth scan clock wirings 311 to 316.

[0175] The sensing clock wiring section 320 may include multiple sensing clock wirings, such as first to sixth sensing clock wirings 321 to 326.

[0176] The scanning clock wiring section 310 and the sensing clock wiring section 320 can be arranged along a direction (e.g., the X-axis direction). For example, the scanning clock wiring section 310 and the sensing clock wiring section 320 can be separated along the width direction of each wiring section and arranged along a direction (e.g., the X-axis direction).

[0177] Each of the first to sixth sensing clock wirings 321 to 326 of the sensing clock wiring section 320 can be arranged along a direction. For example, the first to sixth sensing clock wirings 321 to 326 can be arranged in one direction (the positive direction of the X-axis or the direction of the X-axis). Figure 11 Based on the left-to-right direction, the configuration is arranged sequentially.

[0178] Each of the first to sixth scan clock wirings 311 to 316 of the scan clock wiring section 310 can be arranged along a direction. For example, the first to sixth scan clock wirings 311 to 316 can be arranged in one direction (the positive direction of the X-axis or the direction of the X-axis). Figure 11 Based on the left-to-right direction, the configuration is arranged sequentially.

[0179] To be more specific, each of the first to sixth sensing clock wires 321 to 326 of the sensing clock wiring section 320 and each of the first to sixth scanning clock wires 311 to 316 of the scanning clock wiring section 310 can be configured to be adjacent to each other at least in the area overlapping with the insulating pattern section 340.

[0180] As another expression, a sensing clock line may be configured between two adjacent scanning clock lines in the area overlapping with the insulating pattern portion 340.

[0181] As another expression, in the area overlapping with the insulating pattern portion 340, each of the first to sixth sensing clock wires 321 to 326 of the sensing clock wire portion 320 and each of the first to sixth scanning clock wires 311 to 316 of the scanning clock wire portion 310 can be arranged alternately with each other in sequence.

[0182] As another expression, it can be, along a direction (e.g.) Figure 11 The positive direction of the X-axis, Figure 11 The first scan clock wiring 311, the second scan clock wiring 312, and the third scan clock wiring 313 of the scan clock wiring section 310 are arranged in the direction from left to right. In addition, the first sensing clock wiring 321, the second sensing clock wiring 322, and the third sensing clock wiring 323 are arranged in the same direction.

[0183] Additionally, the fourth scan clock wiring 314, the fourth sensing clock wiring 324, the fifth scan clock wiring 315, the fifth sensing clock wiring 325, the sixth scan clock wiring 316, and the sixth sensing clock wiring 326 may be arranged in the area overlapping with the insulating pattern portion 340.

[0184] In this embodiment, at least in the area overlapping with the insulating pattern portion, a sensing clock line can be configured between two adjacent scanning clock lines. By configuring a scanning clock line between two adjacent sensing clock lines, the unevenness of brightness increase or decrease can be offset, thereby reducing the brightness unevenness defect of the display device.

[0185] This reduces the inconsistency in image quality caused by uneven brightness, thereby improving the image quality characteristics of the display device 300.

[0186] The insulating pattern portion 340 is shown in the accompanying drawings as being offset to the right, but it could also be centrally located or offset to the left.

[0187] Figure 12 This is a plan view of a display device that briefly illustrates yet another embodiment of the present invention. Figure 13 It is a brief illustration Figure 12 A block diagram of the display device. Figure 14 It is a brief illustration Figure 12 The circuit diagram of a sub-pixel of the display device. Figure 15 It is along Figure 12 A simplified cross-sectional view of the K region taken from line XXV-XXV. Figure 16 It is along Figure 12 A simplified cross-sectional view taken from line XXVI-XXVI.

[0188] The display device 400 may include a display area DA and a peripheral area PA.

[0189] The display area DA can have more than one display element (e.g., Figure 16 For example, an organic light-emitting diode (OLED) can be used to display images. Alternatively, as another example, the display element can include one of various other types, such as quantum dot light-emitting elements or liquid crystal display elements. This embodiment illustrates the case where the display element is an organic light-emitting element, but other different types of display elements can certainly be applied as well.

[0190] In addition, multiple pixels can be configured in the display area DA, and more than one display element can be configured in a pixel.

[0191] A peripheral region PA can be formed around the display area DA. The peripheral region PA may include a non-display area; for example, the non-display area may be formed to surround the display area DA. Alternatively, as another optional embodiment, the peripheral region PA or the non-display area of ​​the peripheral region PA may be formed to be adjacent only to one or both sides of the display area DA.

[0192] The peripheral area PA can be configured with a drive circuit section area that generates various signals for the operation of pixels in the display area DA, and the drive circuit section area can have one or more drive circuit sections.

[0193] Figure 13 It is a brief illustration Figure 12 A block diagram of the display device will be provided in reference. Figures 12 to 14 At the same time, briefly describe the display device.

[0194] The display area DA can be configured not only with sub-pixels SP, but also with scan signal wiring SCL, sensing signal wiring SSL, data wiring DL, and first drive voltage wiring VDDL connected to the sub-pixels SP. The scan signal wiring SCL and sensing signal wiring SSL can extend in the display area DA in a first direction (e.g., the X-axis direction). The data wiring DL can extend in the display area DA in a second direction (e.g., the Y-axis direction) intersecting the first direction (e.g., the X-axis direction). The first drive voltage wiring VDDL can extend in the display area DA in, for example, the second direction (Y-axis direction).

[0195] Each sub-pixel SP can be connected to any of the scan signal wirings SCL, any of the data wirings DL, and any of the sensing signal wirings SSL. Figure 13 The example illustrates that each subpixel SP is connected to a scan signal routing SCL, a data routing DL, and a sensing signal routing SSL, but is not limited thereto.

[0196] Subpixels SP can be connected together to the first drive voltage wiring VDDL.

[0197] Additionally, each sub-pixel SP may include a driving transistor, at least one transistor, a display element, and a capacitor. For example, the transistor may be turned on when a scan signal is applied from the scan signal wiring SCL, thereby applying the data voltage of the data wiring DL to the gate electrode of the first transistor T1. The first transistor T1 can emit light by supplying a driving current to the light-emitting element (or display element) according to the data voltage applied to its gate electrode. The first transistor T1 and at least one switching transistor may be thin-film transistors. The display element is, for example, an organic light-emitting element (e.g., an organic light-emitting element). Figure 16(480) can emit light according to the driving current of the first transistor T1.

[0198] The capacitor can stably maintain the data voltage applied to the gate electrode of the first transistor T1.

[0199] A scan signal drive unit SA can be configured in the peripheral area PA. The scan signal drive unit SA can apply a scan signal to the scan signal wiring SCL and a sensing signal to the sensing signal wiring SSL.

[0200] For example, the scan signal driving unit SA can receive a scan control signal from the timing control unit TC. The scan control signal may include multiple clock signals, sensing control signals, gate on-voltage, and gate off-voltage.

[0201] The scan signal driver unit SA can output scan signals and sensing signals to the scan signal wiring SCL and the sensing signal wiring SSL.

[0202] exist Figure 13 The illustration shows a scan signal driving unit SA formed on one side of the display area DA, such as the peripheral area PA on the left side of the display area DA, but it is not limited thereto. For example, the scan signal driving unit SA may also be disposed on one side or both sides of the display area DA.

[0203] The timing control unit TC can be configured separately from the display device 400, or it can be integrally formed with the display device 400. The timing control unit TC may include an integrated circuit, for example, capable of receiving digital video data and timing signals from the system-on-a-chip on a system circuit board. The timing control unit TC can generate control signals for controlling the data driving unit DD and scan control signals for controlling the timing of the scan signal driving unit SA based on the timing signals. As an alternative embodiment, the timing control unit TC can output the scan control signals to the scan signal driving unit SA and output digital video data and source control signals to the data driving unit DD.

[0204] The power supply unit PS can be configured separately from the display device 400, or it can be integrally formed with the display device 400. The power supply unit PS can generate a first driving voltage and supply it to the first driving voltage wiring VDDL. In addition, the power supply unit PS can generate a second driving voltage and supply it to the cathode electrode of the display element of each sub-pixel SP. As an alternative embodiment, the power supply unit PS can generate a reference voltage and supply it to the reference voltage wiring connected to each sub-pixel SP.

[0205] Figure 14 It is a brief illustration Figure 12 The circuit diagram of a sub-pixel of the display device.

[0206] Reference Figure 14 Subpixels (e.g., Figure 13 The SP may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor Cst.

[0207] The light-emitting element EL emits light according to the current Id supplied through the first transistor T1. The light-emitting element EL can be an organic light-emitting element (e.g., Figure 16 (e.g., 480), but not limited to this. For example, the light-emitting element EL can also be a quantum dot light-emitting diode, an inorganic light-emitting diode, or an ultra-miniature light-emitting diode. When the light-emitting element EL is an organic light-emitting element (e.g., ... Figure 16 The specific details of (480) will be provided in reference. Figure 16 This will be discussed later.

[0208] As an example, the pixel electrode of the light-emitting element EL can be connected to a connection electrode of the first transistor T1, and the counter electrode opposite to the pixel electrode can be connected to the second driving voltage wiring VSSL.

[0209] The first transistor T1 can adjust the current Id flowing from the first driving voltage wiring VDDL, which supplies the first power supply voltage, to the light-emitting element EL based on the voltage difference between its gate electrode and a connection electrode. Alternatively, the gate electrode of the first transistor T1 can be connected to a connection electrode of the second transistor T2, one connection electrode of the first transistor T1 can be connected to the pixel electrode of the light-emitting element EL, and the other connection electrode of the first transistor T1 can be connected to the first driving voltage wiring VDDL.

[0210] The second transistor T2 can connect the data route DL to the gate electrode of the first transistor T1 by turning on the scan signal of the scan signal route SCL. Alternatively, the gate electrode of the second transistor T2 can be connected to the scan signal route SCL, one connection electrode of the second transistor T2 can be connected to the gate electrode of the first transistor T1, and the other connection electrode of the second transistor T2 can be connected to the data route DL.

[0211] The third transistor T3 connects the reference voltage wiring VL to a connection electrode of the first transistor T1 by turning on the sensing signal of the sensing signal wiring SSL. Alternatively, the gate electrode of the third transistor T3 can be connected to the sensing signal wiring SSL, one connection electrode of the third transistor T3 can be connected to the reference voltage wiring VL, and the other connection electrode of the third transistor T3 can be connected to a connection electrode of the first transistor T1.

[0212] A capacitor Cst is formed between the gate electrode of the first transistor T1 and a connection electrode. The capacitor Cst stores the voltage corresponding to the difference between the gate voltage of the first transistor T1 and the voltage of the connection electrode.

[0213] The first to third transistors T1, T2, and T3 can be formed using thin-film transistors. Alternatively, they can be formed using P-type transistors. As another example, they can also be formed using N-type transistors.

[0214] Figure 15 It is along Figure 12 A simplified cross-sectional view of the K region taken from line XXV-XXV.

[0215] Reference Figure 15 The display device 400 may include a substrate 401, a scanning clock wiring section 410, a sensing clock wiring section 420, a stage section 430, and an insulating pattern section 440.

[0216] The scan clock wiring section 410, the sensing clock wiring section 420, and the stage section 430 may be included in the scan signal driving section SA.

[0217] The substrate 401 can be adapted to the same or similar scope as described above, therefore specific details are omitted.

[0218] As an alternative embodiment, one or more buffer layers 402 may be disposed between the substrate 401 and the scan signal driving unit SA.

[0219] A buffer layer 402 may be disposed on a substrate 401. The buffer layer 402 may reduce or prevent impurities from being injected or diffused through the substrate 401.

[0220] The buffer layer 402 can contain various materials, such as inorganic materials. Specifically, it can contain silicon-based materials. As an alternative embodiment, the buffer layer 402 can contain silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y At least one of them.

[0221] As another example, buffer layer 402 may contain oxides; specifically, it may contain aluminum oxide (AlO2). x At least one of the following metal oxides:

[0222] Alternatively, as an alternative embodiment, the buffer layer 402 may also include a multilayer structure with at least two layers.

[0223] The scan clock wiring section 410 may include multiple scan clock wirings, such as first to sixth scan clock wirings 411 to 416.

[0224] The sensing clock wiring section 420 may include multiple sensing clock wirings, such as first to sixth sensing clock wirings 421 to 426.

[0225] The scanning clock wiring section 410 and the sensing clock wiring section 420 can be arranged along a direction (e.g., the X-axis direction). For example, the scanning clock wiring section 410 and the sensing clock wiring section 420 can be separated along the width direction of each wiring section and arranged along a direction (e.g., the X-axis direction).

[0226] The specific arrangement of each of the first to sixth sensing clock wires 421 to 426 of the sensing clock wiring section 420 and the arrangement of each of the first to sixth scanning clock wires 411 to 416 of the scanning clock wiring section 410 are similar to those in the aforementioned embodiments, for example, with... Figure 2 The same applies as shown, so specific details are omitted.

[0227] The stage 430 can be configured to be separated from the scan clock wiring section 410 and the sensing clock wiring section 420, and connected by one or more connecting lines.

[0228] For example, stage 430, scan clock wiring 410, and sensing clock wiring 420 can be arranged along a direction (e.g., the X-axis direction). As a specific example, as shown in the figures, they can be configured to face the side of the sensing clock wiring 420 that does not face the scan clock wiring 410. As an example, stage 430 can also be configured on at least one side of the scan clock wiring 410 or the sensing clock wiring 420.

[0229] Although not illustrated, stage 430 may include multiple stages, for example, it may include six stages (see reference for a specific example). Figure 3 ).

[0230] Although not shown, as an alternative embodiment, the scan signal driving unit SA may also include more than one clock routing unit, such as a carry clock routing unit, a global clock routing unit, or multiple clock routing units including multiple clock routings, which are respectively connected to multiple stages of the stage unit 430.

[0231] Each of the multiple stages of such stage 430 can be wired with at least one scan signal (e.g., Figure 14 The scan signal is applied by connecting the SCL (Sensor Logic Controller) to the sensing signal wiring (e.g., Figure 14 The sensing signal is applied through the SSL connection.

[0232] The insulating pattern portion 440 may be configured to overlap with at least one area of ​​the scanning clock wiring portion 410 or the sensing clock wiring portion 420.

[0233] As an alternative embodiment, the first insulating layer NCI1 can be formed on the scan clock wiring portion 410 and the sensing clock wiring portion 420, and the insulating pattern portion 440 can be insulated from the scan clock wiring portion 410 and the sensing clock wiring portion 420 through the first insulating layer NCI1.

[0234] On the other hand, as an alternative embodiment, the first insulating layer NCI1 may also be formed to cover the stage 430 on the stage 430.

[0235] As an alternative embodiment, the second insulating layer NCI2 may be formed on the first insulating layer NCI1. As one example, the second insulating layer NCI2 may be formed to contact the insulating pattern portion 440; more specifically, it may be formed to correspond to one side or the top of the insulating pattern portion 440. As an alternative embodiment, the second insulating layer NCI2 may also be formed to cover the insulating pattern portion 440.

[0236] The insulating pattern portion 440 may be configured to overlap with at least one area of ​​the scanning clock wiring portion 410 or the sensing clock wiring portion 420.

[0237] The insulating pattern portion 440 can serve various functions, such as supporting a manufacturing apparatus (e.g., a mask component) for forming one or more layers of the display device 400, and for this purpose, it can be configured to have a set height. Alternatively, as another example, the insulating pattern portion 440 can also be used for other functions, such as serving as a partition wall that restricts the formation of adjacent layers (e.g., insulating layers or encapsulation portions).

[0238] The insulating pattern portion 440 may contain various insulating materials, such as organic materials. Furthermore, the insulating pattern portion 440 may be formed as a single layer or multiple layers.

[0239] Reference Figure 15 The insulating pattern portion 440 can be configured to overlap with the first to third scan clock wirings 411 to 413 of the scan clock wiring portion 410 and the first to third sensing clock wirings 421 to 423 of the sensing clock wiring portion 420.

[0240] The content related to the configuration of such insulating pattern section 440, scanning clock wiring section 410, and sensing clock wiring section 420 is as described above. Figure 2 The content described in both structures is essentially the same, so specific explanations are omitted.

[0241] When the display device 400 is used to offset the changes in image quality characteristics (e.g., increased brightness) of the first to sixth scan clock wirings 411 to 416 of the scan clock wiring section 410 in this embodiment and the changes in image quality characteristics (e.g., decreased brightness) of the first to sixth sensing clock wirings 421 to 426 of the sensing clock wiring section 420, the uneven brightness defects caused by changes due to external or internal environmental problems can be reduced.

[0242] On the other hand, when the display device 400 is used in environments with high temperature and high humidity, moisture may flow in through the edges. Since the insulating pattern portion 440 is closer to the edge area than the center of the display device 400, it may curl up or down in the area adjacent to the insulating pattern portion 440. Due to such curling up or down, the capacitance in the area adjacent to the insulating pattern portion 440 may change. For example, the capacitance of the scan clock wiring portion 410 or the sensing clock wiring portion 420 may increase.

[0243] Additionally, as a specific example, if capacitance increases in the region adjacent to each scan clock wiring of the scan clock wiring section 410, it will be applied to the first transistor (e.g., through the scan signal wiring) via the scan signal wiring. Figure 14 The voltage at the gate of (T1) increases, thereby activating the light-emitting element (e.g., Figure 14 The brightness of the EL increases. Alternatively, as another specific example, if the capacitance increases in the region adjacent to each sensing clock wiring of the sensing clock wiring section 420, then an increase in capacitance is applied to the connected third transistor (e.g., Figure 14 The voltage at the gate of (T3) increases, thereby activating the light-emitting element (e.g., Figure 14 The brightness of the EL (Electroluminescence) decreases.

[0244] Furthermore, the increase or decrease in brightness of such clock wiring can vary depending on its sequence. For example, the increase in brightness can be greater with the sequence of the first to sixth scan clock wirings 411-416 of the scan clock wiring section 410. Conversely, the decrease in brightness can be greater with the sequence of the first to sixth sensing clock wirings 421-426 of the sensing clock wiring section 420. In this case, when the sixth scan clock wiring 416 and the first sensing clock wiring 421 are adjacent, the brightness change increases, potentially increasing the occurrence of image quality defects. In this embodiment, the first to sixth scan clock wirings 411-416 of the scan clock wiring section 410 can be arranged sequentially in one direction, while the first to sixth sensing clock wirings 421-426 of the sensing clock wiring section 420 can be arranged in the opposite direction. Thus, the first scan clock wiring 411 and the first sensing clock wiring 421 can be configured to be adjacent.

[0245] As a result, the brightness characteristics can be improved by reducing the increase in brightness caused by the increased capacitance of the first to sixth scan clock lines 411 to 416 of the scan clock wiring section 410 and the decrease in brightness caused by the increased capacitance of the first to sixth sensing clock lines 421 to 426 of the sensing clock wiring section 420.

[0246] Although not illustrated, the foregoing may be selectively applied as an alternative embodiment. Figure 4 as well as Figure 5 Any one of the structures.

[0247] Figure 16 It is along Figure 12 A simplified cross-sectional view of region P, taken from line XVI-XVI. For example, Figure 16 It can be shown that the sub-pixel is shown (e.g., Figure 13 At least one region of the SP.

[0248] The substrate 401 may include various materials. Specifically, the substrate 401 may be formed of other materials such as glass, metal, or organic materials. The content related to the substrate 401 is substantially the same as the specific content described in the foregoing embodiments, therefore, detailed description is omitted.

[0249] As an alternative embodiment, the buffer layer 402 may be disposed on the substrate 401.

[0250] One or more thin-film transistors can be disposed on substrate 401. The thin-film transistor may include an active layer 451 and a gate electrode 452. Additionally, the thin-film transistor may include a first connection electrode 454 and a second connection electrode 455.

[0251] The active layer 451 can be configured on the buffer layer 402.

[0252] In one embodiment, the active layer 451 may contain a semiconductor material. For example, it may contain a silicon-based semiconductor material, and as a specific example, it may contain a polycrystalline silicon-based material. As another example, the active layer 451 may contain an oxide semiconductor.

[0253] The gate electrode 452 can be configured to overlap with the active layer 451, for example, it can be configured above the active layer 451 with reference to the thickness direction of the substrate 401.

[0254] The gate insulating film 453 can be configured to insulate between the active layer 451 and the gate electrode 452. As a specific example, the gate insulating film 453 can be disposed on the active layer 451. The gate insulating film 453 can contain an insulating material, such as silicon oxide, silicon nitride, silicon oxide nitride, etc., which can be contained individually or in combination with each other.

[0255] The gate electrode 452 can be disposed on the gate insulating film 453, configured to overlap with the active layer 451. The gate electrode 452 can contain a conductive material, such as a metal, alloy, conductive metal oxide, transparent conductive material, etc. As specific examples, the gate electrode 452 can contain conductive materials such as molybdenum (Mo), aluminum (Al), silver (Ag), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc., and can contain alloys of the aforementioned conductive materials. In addition, the gate electrode 452 can include a single layer or multiple layers containing the aforementioned materials.

[0256] The interlayer insulating layer 461 can be configured to insulate between the gate electrode 452 and the first connection electrode 454 and the second connection electrode 455. For example, the interlayer insulating layer 461 can be formed to cover the gate electrode 452 and the active layer 451 over the gate electrode 452 and the active layer 451.

[0257] Additionally, interlayer insulation layer 461 may be disposed on buffer layer 402. Interlayer insulation layer 461 may contain insulating material.

[0258] The first connecting electrode 454 and the second connecting electrode 455 can be disposed on the interlayer insulating layer 461. The first connecting electrode 454 and the second connecting electrode 455 can respectively contact the active layer 451 through the contact holes of the interlayer insulating layer 461.

[0259] Based on the signal applied to the gate electrode 452, the first connection electrode 454 and the second connection electrode 455 can be electrically connected.

[0260] The first connecting electrode 454 and the second connecting electrode 455 may contain one or more of various conductive materials, such as metals, alloys, conductive metal oxides, transparent conductive materials, etc. For specific examples, they may contain silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0261] As an alternative embodiment, a conductive pattern portion 477 may also be configured.

[0262] As an example, the conductive pattern portion 477 may have a region that overlaps with the active layer 451 and is disposed between the substrate 401 and the buffer layer 402.

[0263] The conductive pattern portion 477 can be used as a light-shielding component to protect the active layer 451 or the thin-film transistor therein by reducing or blocking light that can enter the substrate 401. For this purpose, the conductive pattern portion 477 may contain light-shielding and / or light-absorbing materials, for example, it may contain an opaque metal layer.

[0264] Alternatively, as an alternative embodiment, the conductive pattern portion 477 can also be electrically connected to the first connection electrode 454 or the second connection electrode 455 through contact holes that sequentially penetrate the interlayer insulating layer 461 and the buffer layer 402. This can improve various electrical control characteristics; for example, it can expand the driving range of the predetermined voltage supplied to the gate electrode 452 of the thin-film transistor. Another example is that it can stabilize the channel region of the active layer 451.

[0265] As an alternative embodiment, the conductive pattern portion 477 may comprise various metals, and may be formed as a single layer composed of a suitable (or selected) single or mixture thereof from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag) and their alloys, or as a two- or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or silver (Ag) as low-resistance materials in order to reduce wiring resistance.

[0266] One or more protective insulating layers 471 and 472 may be disposed on the interlayer insulating layer 461. For example, a first protective insulating layer 471 may be disposed on the interlayer insulating layer 461, and a second protective insulating layer 472 may be disposed on the first protective insulating layer 471. The first protective insulating layer 471 and the second protective insulating layer 472 may contain an insulating material. For example, they may be formed from various substances, and may be formed by organic or inorganic materials alone or together, and may include a single layer or multiple layers containing organic materials.

[0267] As a specific example, the first protective insulation layer 471 may contain inorganic materials, and the second protective insulation layer 472 may contain organic materials.

[0268] As an alternative embodiment, the second protective insulating layer 472 may be formed with a flat surface in at least one region, which may reduce or prevent defects in the display element 480 due to unevenness underneath.

[0269] The display element 480 may be disposed above the second protective insulating layer 472. As previously mentioned, the display element 480 may be one of various types, for example, it may include an organic light-emitting element, which is illustrated below.

[0270] The display element 480 includes a first electrode 481, a second electrode 482, and an intermediate layer 483 between the two electrodes.

[0271] The first electrode 481 can be connected to the circuit below, such as a thin-film transistor. For example, it can be connected to... Figure 16 The second connection electrode 455 of the thin-film transistor shown below is electrically connected.

[0272] The first electrode 481 can have various forms; for example, it can be patterned in the form of islands.

[0273] The first electrode 481 may contain various conductive materials. For example, the first electrode 481 may contain at least one material selected from the group consisting of transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Alternatively, the first electrode 481 may contain a metal with high reflectivity such as silver (Ag).

[0274] Alternatively, the intermediate layer 483 may include an organic light-emitting layer, which uses a low-molecular-weight organic compound or a polymeric organic compound. As an alternative embodiment, the intermediate layer 483 may, together with the organic light-emitting layer, include at least one selected from the group consisting of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0275] On the other hand, the organic light-emitting layer can be formed individually for each organic light-emitting element. In this case, red, green, and blue light can be emitted separately for each organic light-emitting element. However, the present invention is not limited to this; the organic light-emitting layers can be formed collectively on the organic light-emitting element as a whole. For example, multiple organic light-emitting layers emitting red, green, and blue light can be vertically stacked or mixed to emit white light. Of course, the combination of colors used to emit white light is not limited to the above. On the other hand, in this case, a color conversion layer or color filter that converts the emitted white light into a predetermined color can be separately provided.

[0276] The second electrode 482 can be formed of various conductive materials. For example, the second electrode 482 can contain lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or silver (Ag), and can be formed from at least one of the materials as a single layer or multiple layers, and can contain an alloy material containing at least two of the materials.

[0277] Alternatively, a pixel defining film (PDL) may be disposed on the second protective insulating layer 472. After the pixel defining film (PDL) is configured not to cover a predetermined area of ​​the first electrode 481, an intermediate layer 483 may be disposed on the area of ​​the first electrode 481 not covered by the pixel defining film (PDL), and a second electrode 482 may be disposed on the intermediate layer 483.

[0278] Pixel defining film (PDL) can be formed from various insulating materials. For example, PDL can contain organic matter. As a specific example, it can be formed by spin coating or other methods from one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0279] As an alternative embodiment, a functional layer (not shown) having one or more layers may also be configured on the second electrode 482. For example, at least one layer of the functional layer may reduce contamination of the second electrode 482 during subsequent processes, and another layer of the functional layer may improve the efficiency of visible light extracted from the intermediate layer 483.

[0280] The encapsulation portion 490 can be configured to protect the display element 480. For example, an encapsulation portion 490 having one or more encapsulation layers can be configured on the second electrode 482 to block or reduce the penetration of moisture or other foreign matter into the display element 480.

[0281] As an example, the encapsulation portion 490 may have two or more encapsulation layers. As an alternative embodiment, the encapsulation portion 490 may include one or more inorganic layers or one or more organic layers. As an example, it may also include a structure in which inorganic and organic layers are alternately stacked one or more times. As a specific example, it may also include a structure in which inorganic and organic layers are alternately stacked multiple times.

[0282] On the other hand, as an alternative embodiment, the aforementioned first insulating layer (e.g., Figure 15 The NCI1 can also be related to the display area (e.g., Figure 12 The insulating layer of the DA) is a first insulating layer formed simultaneously from the same material. For example, the first insulating layer NCI1 may be formed from the same material as the interlayer insulating layer 461.

[0283] Additionally, the insulating pattern portion (e.g., Figure 15 The insulating pattern portion 440 can also be formed simultaneously with the insulating layer of the display area DA from the same material. For example, the insulating pattern portion 440 can be formed from the same material as at least one of the protective insulating layers 471, 472 or the pixel defining film PDL.

[0284] Reference Figures 12 to 16Alternatively, the display device 400 in this embodiment may include a scan signal driving unit SA disposed in the peripheral region PA. The scan signal driving unit SA includes a scan clock wiring unit 410, a sensing clock wiring unit 420, and a stage unit 430. In addition, the display device 400 may include an insulating pattern portion 440 that overlaps with the scan clock wiring unit 410 or the sensing clock wiring unit 420.

[0285] The stage may include multiple stages, with multiple wires of the scan clock wiring section and multiple wires of the sensing clock wiring section connected sequentially in each stage. In this case, the scan clock wiring section and the sensing clock wiring section may be arranged in one direction, and the multiple wires included in each stage may also be arranged in one direction. Specifically, the multiple scan clock wires of the scan clock wiring section may be arranged in one direction in a specific order, i.e., in the order of the sixth to the first scan clock wires, while the multiple sensing clock wires of the sensing clock wiring section may be arranged in the opposite order, i.e., in the order of the first to the sixth sensing clock wires.

[0286] When warping occurs due to moisture or other factors that increase with usage time caused by external or internal environments, the capacitance in the scan clock wiring or sensing clock wiring may change, for example, increase. This can lead to an increase or decrease in brightness in at least one area of ​​the display device 400. In this case, the order of the multiple sensing clock wirings and the multiple scan clock wirings can be reversed, for example, the wirings can be configured symmetrically. This prevents the brightness increase and decrease areas from being too close due to the proximity of adjacent areas, such as the sixth scan clock wiring and the first sensing clock wiring, thus reducing the recognizability of uneven brightness changes.

[0287] Although not illustrated, the aforementioned can be considered... Figures 6 to 11 The structure is selectively applied to the display device 400 of this embodiment.

[0288] Figure 17 This is a plan view of a display device that briefly illustrates yet another embodiment of the present invention. Figure 18 It is along Figure 17 A simplified cross-sectional view of the K region taken from line XVIII-XVIII.

[0289] The display device 500 may include a display area DA and a peripheral area PA. For ease of explanation, it will be compared with the display device of the foregoing embodiment (e.g., Figure 12 The differences between the 400 and the 400 are explained in detail. The descriptions related to the scanning clock wiring section 510, the sensing clock wiring section 520, the stage section 530, and the insulating pattern section 540 are omitted.

[0290] Reference Figure 18The display device 500 may also include a substrate 503.

[0291] The substrates 503 and 501 can be joined by a sealing member SLT, and the space created by the joining can be filled by filler JCL.

[0292] A light conversion layer (FTL) may be disposed on one side of the substrate 503, such as the side facing the substrate 501. The light conversion layer (FTL) is a layer that improves the purity of the light drawn from the display device 500, and may include, for example, a color filter.

[0293] As an alternative embodiment, a low refractive index layer (LRL) can be disposed on one side of the light conversion layer (FTL). The low refractive index layer (LRL) can contain organic or inorganic materials with low refractive index.

[0294] As an alternative embodiment, one or more capping layers (CPLs) can be disposed on one side of the low refractive index layer (LRL). The capping layer (CPL) can precisely control optical properties or protect the low refractive index layer (LRL) and may contain inorganic insulating materials.

[0295] Figure 19 This is a cross-sectional view of a display device according to yet another embodiment of the present invention.

[0296] For ease of explanation, the description will focus on the differences from the aforementioned embodiments.

[0297] The display device 600 may include a display area DA and a peripheral area PA.

[0298] Additionally, the display device 600 may include a substrate 601, a scanning clock wiring section 610, a sensing clock wiring section 620, a stage section 630, and an insulating pattern section 640.

[0299] As an alternative embodiment, a buffer layer 602 may be disposed on the substrate 601.

[0300] Referring to the display area DA, one or more thin-film transistors can be disposed on the substrate 601. The thin-film transistor may include an active layer 651 and a gate electrode 652. Additionally, the thin-film transistor may include a first connection electrode 654 and a second connection electrode 655.

[0301] Additionally, the gate insulating film 653 can be configured to insulate between the active layer 651 and the gate electrode 652.

[0302] The interlayer insulating layer 661 may be configured to insulate between the gate electrode 652 and the first connection electrode 654 and the second connection electrode 655. For example, the interlayer insulating layer 661 may be formed to cover the gate electrode 652 and the active layer 651 above the gate electrode 652 and the active layer 651.

[0303] Interlayer insulation layer 661 can be disposed on buffer layer 602.

[0304] The first connecting electrode 654 and the second connecting electrode 655 can be disposed on the interlayer insulating layer 661. The first connecting electrode 654 and the second connecting electrode 655 can respectively contact the active layer 651 through the contact holes of the interlayer insulating layer 661.

[0305] Based on the signal applied to the gate electrode 652, the first connection electrode 654 and the second connection electrode 655 can be electrically connected.

[0306] As an alternative embodiment, the display device 600 may also be configured with a conductive pattern portion 677.

[0307] As an example, the conductive pattern portion 677 may have a region that overlaps with the active layer 651 and is disposed between the substrate 601 and the buffer layer 602.

[0308] One or more protective insulating layers 671 and 672 may be disposed on the interlayer insulating layer 661. For example, the first protective insulating layer 671 may be disposed on the interlayer insulating layer 661, and the second protective insulating layer 672 may be disposed on the first protective insulating layer 671.

[0309] The display element 680 may be disposed above the second protective insulating layer 672. As previously mentioned, the display element 680 may be one of various types, for example, it may include an organic light-emitting element, which is illustrated below.

[0310] The display element 680 includes a first electrode 681, a second electrode 682, and an intermediate layer 683 between the two electrodes.

[0311] The first electrode 681 can be connected to the circuit below, such as a thin-film transistor. For example, it can be electrically connected to the second connection electrode 655 of the thin-film transistor.

[0312] Alternatively, the intermediate layer 683 may include an organic light-emitting layer, which uses a low-molecular-weight organic compound or a polymeric organic compound. As an alternative embodiment, the intermediate layer 683 may, together with the organic light-emitting layer, include at least one selected from the group consisting of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0313] The second electrode 682 can be formed from various conductive materials.

[0314] Alternatively, a pixel defining film (PDL) may be disposed on the second protective insulating layer 672. After the pixel defining film (PDL) is configured not to cover a predetermined area of ​​the first electrode 681, an intermediate layer 683 may be disposed on the area of ​​the first electrode 681 not covered by the pixel defining film (PDL), and a second electrode 682 may be disposed on the intermediate layer 683.

[0315] The encapsulation portion 690 can be configured to protect the display element 680. For example, an encapsulation portion 690 having one or more encapsulation layers can be configured on the second electrode 682 to block or reduce the penetration of moisture or other foreign matter into the display element 680.

[0316] As an example, the encapsulation section 690 may include a first inorganic encapsulation layer 691, a second inorganic encapsulation layer 692, and an organic encapsulation layer 693, with the organic encapsulation layer 693 disposed between the first inorganic encapsulation layer 691 and the second inorganic encapsulation layer 692.

[0317] The scan clock wiring section 610 configured in the peripheral area PA may include multiple scan clock wirings, such as first to sixth scan clock wirings 611 to 616.

[0318] The sensing clock wiring section 620 configured in the peripheral area PA may include multiple sensing clock wirings, such as first to sixth sensing clock wirings 621 to 626.

[0319] The arrangement of each of the first to sixth sensing clock wires 621 to 626 of the specific sensing clock wiring section 620 and the arrangement of each of the first to sixth scanning clock wires 611 to 616 of the scanning clock wiring section 610 can be the same as one of the foregoing embodiments, for example... Figure 2 The same as shown.

[0320] Furthermore, the first to sixth sensing clock wirings 621 to 626 of the sensing clock wiring section 620 and the first to sixth scanning clock wirings 611 to 616 of the scanning clock wiring section 610 can be formed of the same material as one or more conductive layers of the display area DA. For example, they can be formed of the same material as one of the electrodes of the thin film transistor disposed in the display area DA. As a specific example, they can be formed of the same material as the first connection electrode 654 and the second connection electrode 655.

[0321] As an alternative embodiment, a structure electrically connected to the lower wiring may also be provided below the first to sixth sensing clock wirings 621 to 626 of the sensing clock wiring section 620 and the first to sixth scanning clock wirings 611 to 616 of the scanning clock wiring section 610.

[0322] The stage 630 can be configured to be separated from the scan clock wiring section 610 and the sensing clock wiring section 620, and connected by one or more connecting lines.

[0323] Although not illustrated, stage 630 may include multiple stages, for example, it may include six stages (see reference for a specific example). Figure 3 ).

[0324] As an alternative embodiment, stage 630 may include one or more conductive layers. For example, it may include layers formed of the same material as one or more conductive layers of display area DA. Specifically, it may include layers formed of the same material as the first connection electrode 654 and the second connection electrode 655, layers formed of the same material as the gate electrode 652, or layers formed of the same material as the conductive pattern portion 677. Specifically, it may also include one or more thin-film transistors.

[0325] One or more insulating layers may be disposed between the insulating pattern section 640 and the stage section 630, the scanning clock wiring section 610 and the sensing clock wiring section 620, for example, a first protective insulating layer 671 for the display area DA may be disposed.

[0326] Alternatively, the insulating pattern portion 640 may also be an insulating pattern portion formed simultaneously with the insulating layer of the display area DA using the same material. For example, the insulating pattern portion 640 may be formed using the same material as the pixel defining film PDL or the second protective insulating layer 672.

[0327] As an alternative embodiment, the insulating pattern portion 640 may further include a lower layer portion 640a made of the same material as the second protective insulating layer 672 and an upper layer portion 640b made of the same material as the pixel defining film PDL.

[0328] As an alternative embodiment, one or more dams DM1, DM2, and DM3 may be configured in the surrounding area PA. For example, dams DM1, DM2, and DM3 may include a first dam DM1, a second dam DM2, and a third dam DM3. Specifically, a second dam DM2 may be configured between the first dam DM1 and the third dam DM3.

[0329] The first dam DM1, the second dam DM2, and the third dam DM3 can be formed using various insulating materials. For example, one or more dams can be formed of the same material as the pixel defining film PDL or the second protective insulating layer 672. As a specific example, it can also include a lower layer of the same material as the second protective insulating layer 672 and an upper layer of the same material as the pixel defining film PDL.

[0330] Additionally, the display device 600 may also include a substrate 603.

[0331] The substrates 603 and 601 can be joined by a sealing member SLT, and the space created by the joining can be filled by filler JCL.

[0332] A light conversion layer (FTL) may be disposed on one side of the substrate 603, such as the side facing the substrate 601. The light conversion layer (FTL) is a layer that improves the purity of the light drawn from the display device 600, and may include, for example, a color filter.

[0333] As an alternative embodiment, a low refractive index layer (LRL) can be disposed on one side of the light conversion layer (FTL). The low refractive index layer (LRL) can contain organic or inorganic materials with low refractive index.

[0334] As an alternative embodiment, one or more capping layers (CPLs) can be disposed on one side of the low refractive index layer (LRL). The capping layer (CPL) can precisely control optical properties or protect the low refractive index layer (LRL) and may contain inorganic insulating materials.

[0335] On the other hand, at least one of the display devices described in the foregoing embodiments can be applied to electronic devices.

[0336] For example, such an electronic device may include more than one display device and other accessories.

[0337] As a specific example, the electronic device in this embodiment may include at least one of the aforementioned display devices, and additionally include a processor, a memory, an input module, a power module, a built-in module, and an external module.

[0338] A processor can run software to control at least one other component (e.g., hardware or software component) of an electronic device connected to the processor, and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operation, the processor can store commands or data received from other components (e.g., input modules, sensor modules, or communication modules) in volatile memory, process the commands or data stored in volatile memory, and store the result data in non-volatile memory.

[0339] As an alternative embodiment, such a processor may include a main processor and auxiliary processors. The main processor may include one or more of a central processing unit (CPU) or an application processor (AP). The main processor may also include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor may also include a neural processing unit (NPU). The neural processing unit acts as a processor specialized for processing artificial intelligence models, which can be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the foregoing examples. In addition to hardware architecture, artificial intelligence models may additionally or alternatively include software architecture. The aforementioned processing device and at least two of the processors can be implemented as a unified structure (e.g., a single chip) or as independent structures (e.g., multiple chips).

[0340] The auxiliary processor may include a controller, which may include interface conversion circuitry and timing control circuitry. The controller receives image signals from the main processor, converts the image signal data format to match the interface specifications of the display device, and outputs the image data. The controller can output various control signals required for driving the display device.

[0341] Additionally, as an alternative embodiment, the auxiliary processor may further include a controller, a data conversion circuit, a gamma correction circuit, a rendering circuit, etc. The data conversion circuit receives image data from the controller and compensates the image data according to the characteristics of the electronic device or user settings to display the image at the desired brightness, or converts the image data for purposes such as reducing power consumption or compensating for image retention. The gamma correction circuit can convert image data or gamma reference voltage, etc., to give the image displayed on the electronic device the desired gamma characteristics. The rendering circuit receives image data from the controller and renders the image data considering the pixel configuration of the display device suitable for the electronic device.

[0342] The input module can receive commands or data from outside the electronic device (e.g., from a user or an external electronic device) that will be used on the components of the electronic device (e.g., a processor, sensor module, or audio output module).

[0343] The input module may include a first input module for receiving commands or data from a user and a second input module for receiving commands or data from an external electronic device. The first input module may include a microphone, mouse, keyboard, keys (e.g., buttons), or a pen (e.g., a passive or active pen). The second input module may support a specified protocol for wired or wireless connection to an external electronic device. According to one embodiment, the second input module may include an HDMI (High Definition Multimedia Interface), USB (Universal Serial Bus) interface, SD card interface, or audio interface. The second input module may include a connector for physical connection to an external electronic device, such as an HDMI connector, USB connector, SD card connector, or audio connector (e.g., a headphone connector).

[0344] On the other hand, the display device may also include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal required for the display device to emit light, in response to a control signal received from the controller. The light-emitting driver may be formed separately from the scan driver or integrated into the scan driver.

[0345] Additionally, the display device may include a scan driver that receives a control signal from a controller and outputs a scan signal in response to the control signal.

[0346] Additionally, the display device may include a data driver that receives control signals from a controller and, in response to the control signals, converts image data into analog voltages for output.

[0347] The electronic device may also include built-in modules and external modules. Built-in modules may include sensor modules, antenna modules, and audio output modules. External modules may include camera modules, lighting modules, and communication modules.

[0348] The sensor module can sense input through the user's body or through an input module, and generate an electrical signal or data value corresponding to the input. The sensor module may also include at least one of a fingerprint sensor, an input sensor, and a digitizer. In addition, the sensor module may also include a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or a brightness sensor.

[0349] Input modules, sensor modules, camera modules, etc., can be linked with the processor to control the operation of the display device.

[0350] The electronic device can be of various forms. It may include at least one of, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. The electronic device according to embodiments herein is not limited to the foregoing devices.

[0351] The present invention has been described above with reference to an embodiment shown in the accompanying drawings, but this is merely exemplary. Those skilled in the art will understand that various modifications and variations of the embodiments can be made based on this description. Therefore, the true scope of protection of the present invention should be determined by the technical concept of the appended claims.

Claims

1. A display device, characterized in that, include: The display area enables visible light to be emitted on the substrate. In addition to the surrounding area, it is disposed on at least one side of the display area and has a non-display area. The display device includes: The scan clock routing section includes multiple scan clock routings arranged sequentially in one direction; The sensing clock wiring section includes a plurality of sensing clock wirings arranged sequentially in a direction different from the said direction; The stage includes multiple stages connected to the plurality of scan clock wirings and the plurality of sensing clock wirings; and An insulating pattern portion is configured to overlap with the scanning clock wiring portion or the sensing clock wiring portion.

2. The display device according to claim 1, characterized in that, The scanning clock wiring section and the sensing clock wiring section are arranged along one direction. The first to Nth sensing clock wirings of the plurality of sensing clock wirings are arranged sequentially along the said direction. The first scan clock wiring to the Nth scan clock wiring of the plurality of scan clock wirings are arranged sequentially in the opposite direction of the first direction.

3. The display device according to claim 1, characterized in that, The arrangement of the plurality of sensing clock wirings in the sensing clock wiring section is symmetrical to the arrangement of the plurality of scanning clock wirings in the scanning clock wiring section.

4. The display device according to claim 1, characterized in that, The insulating pattern portion is configured to correspond to the central region between the scan clock wiring portion and the sensing clock wiring portion, and is configured to overlap with at least a portion of the scan clock wiring and at least a portion of the sensing clock wiring among the plurality of scan clock wiring and sensing clock wiring.

5. The display device according to claim 1, characterized in that, The center of the insulating pattern portion is configured to be offset from the central region between the scanning clock wiring portion and the sensing clock wiring portion.

6. An electronic device, characterized in that, include: The controller generates one or more signals; The display device receives one or more signals from the controller and displays information. The display device includes a scanning clock wiring section, a sensing clock wiring section, and a stage section, configured to receive signals from the controller and transmit signals for displaying information of the display device. The scan clock wiring section includes a plurality of scan clock wirings arranged sequentially in one direction. The sensing clock wiring section includes a plurality of sensing clock wirings arranged sequentially in a direction different from the first direction. The stage includes multiple stages connected to the plurality of scan clock wirings and the plurality of sense clock wirings. The display device includes an insulating pattern portion configured to overlap with the scanning clock wiring portion or the sensing clock wiring portion.

7. A display device, characterized in that, include: The display area enables visible light to be emitted on the substrate. as well as The surrounding area is located on at least one side of the display area and includes a non-display area. The display device includes: The scan clock routing section includes multiple scan clock routings arranged sequentially in one direction; The sensing clock wiring section includes a plurality of sensing clock wirings arranged sequentially in the said one direction; The stage includes multiple stages connected to the plurality of scan clock wirings and the plurality of sensing clock wirings; and The insulating pattern portion is configured to overlap with the scanning clock wiring portion or the sensing clock wiring portion. At least in the area overlapping with the insulating pattern portion, a sensing clock wire is configured between two adjacent scanning clock wires among the plurality of scanning clock wires.

8. The display device according to claim 7, characterized in that, At least in the area overlapping with the insulating pattern portion, a scan clock wire is configured between two adjacent sensing clock wires among the plurality of sensing clock wires.

9. The display device according to claim 7, characterized in that, At least in the area overlapping with the insulating pattern portion, each of the plurality of scan clock wires of the scan clock wiring portion and each of the plurality of sensing clock wires of the sensing clock wiring portion are arranged alternately with each other in sequence.

10. The display device according to claim 7, characterized in that, The insulating pattern portion is configured to correspond to the central region between the scan clock wiring portion and the sensing clock wiring portion, and is configured to overlap with at least a plurality of scan clock wirings and at least a plurality of sensing clock wirings.

Images