Display device

Abstract

The present disclosure relates to a display device capable of improving the recognition rate of an alignment key, and the display device includes a substrate, a first electrode on the substrate, a pixel definition layer above the first electrode, a light emitting stack above the first electrode and the pixel definition layer, a second electrode above the light emitting stack, and an alignment key in a non-display area of the substrate and including an external pattern layer above the substrate, an internal pattern layer inside a through hole of the external pattern layer, and a dummy layer between the external pattern layer and the internal pattern layer. The display device is capable of improving the recognition rate of the alignment key.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0122801, filed on September 10, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and an optical device capable of improving the recognition rate of alignment keys. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet, and focused in front of the user's eyes at a distance relatively close to the eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays use multiple lenses to magnify and display images from small display devices. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with a resolution of approximately 3000 pixels per inch (PPI) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), as small organic light-emitting display devices with high resolution, have been used in head-mounted displays. OLEDoS is a device that displays images by arranging organic light-emitting diodes (OLEDs) on a semiconductor silicon wafer substrate on which complementary metal-oxide-semiconductor (CMOS) semiconductors are positioned. Utility Model Content

[0005] The purpose of this invention is to provide a display device and an optical device that can improve the recognition rate of alignment keys.

[0006] According to an aspect of this disclosure, a display device is provided, the display device comprising: a substrate; a first electrode on the substrate; a pixel defining layer above the first electrode; a light-emitting stack above the first electrode and the pixel defining layer; a second electrode above the light-emitting stack; and an alignment key in a non-display area of ​​the substrate, and including an outer pattern layer above the substrate, an inner pattern layer inside a via of the outer pattern layer, and a dummy layer between the outer pattern layer and the inner pattern layer.

[0007] The outer pattern layer and the inner pattern layer may include metals, while the dummy layer includes non-metals.

[0008] In a planar view, an inner pattern layer can be surrounded by an outer pattern layer.

[0009] The outer pattern layer may include a first sub-outer pattern layer and a second sub-outer pattern layer above the first sub-outer pattern layer.

[0010] An internal pattern layer may include a first sub-internal pattern layer and a second sub-internal pattern layer above the first sub-internal pattern layer.

[0011] A virtual layer may include a first sub-virtual layer, a second sub-virtual layer above the first sub-virtual layer, a third sub-virtual layer above the second sub-virtual layer, and a fourth sub-virtual layer above the third sub-virtual layer.

[0012] The first sub-dummy layer can be at least partially above the outer pattern layer and the inner pattern layer.

[0013] The fourth sub-dummy layer can be above the outer pattern layer and the inner pattern layer.

[0014] Through-holes and internal patterned layers can have the same shape.

[0015] A dummy layer can have through holes that overlap with the inner pattern layer.

[0016] Additionally, according to an aspect of this disclosure, an optical device is provided, comprising: a light path changing member; and a display device below the light path changing member, including a substrate, a first electrode above the substrate, a pixel defining layer above the first electrode, a light-emitting stack above the first electrode and the pixel defining layer, a second electrode above the light-emitting stack, and an alignment key in a non-display area of ​​the substrate, wherein the alignment key includes an outer pattern layer above the substrate, an inner pattern layer inside a via of the outer pattern layer, and a dummy layer between the outer pattern layer and the inner pattern layer.

[0017] The outer pattern layer and the inner pattern layer may include metals, while the dummy layer includes non-metals.

[0018] In a planar view, an inner pattern layer can be surrounded by an outer pattern layer.

[0019] The outer pattern layer may include a first sub-outer pattern layer and a second sub-outer pattern layer above the first sub-outer pattern layer.

[0020] An internal pattern layer may include a first sub-internal pattern layer and a second sub-internal pattern layer above the first sub-internal pattern layer.

[0021] A virtual layer may include a first sub-virtual layer, a second sub-virtual layer above the first sub-virtual layer, a third sub-virtual layer above the second sub-virtual layer, and a fourth sub-virtual layer above the third sub-virtual layer.

[0022] The first sub-dummy layer can be at least partially above the outer pattern layer and the inner pattern layer.

[0023] The fourth sub-dummy layer can be above the outer pattern layer and the inner pattern layer.

[0024] Through-holes and internal patterned layers can have the same shape.

[0025] Additionally, according to an aspect of this disclosure, an electronic device is provided, comprising a display device including: a screen; a substrate; a first electrode above the substrate; a pixel defining layer above the first electrode; a light-emitting stack above the first electrode and the pixel defining layer; a second electrode above the light-emitting stack; and an alignment key in a non-display area of ​​the substrate, and including an outer pattern layer above the substrate, an inner pattern layer inside a via of the outer pattern layer, and a dummy layer between the outer pattern layer and the inner pattern layer.

[0026] The recognition rate of the alignment key can be improved by adjusting the display device.

[0027] It should be noted that the disclosed aspects are not limited to those described above, and other disclosed aspects will become apparent from the following description. Attached Figure Description

[0028] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments; Figure 2 This is a block diagram illustrating a display device according to one or more embodiments; Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments; Figure 4 This is a layout diagram illustrating a display panel according to one or more embodiments; Figure 5 It is shown Figure 4 Layout diagram of the display area; Figure 6 This illustrates one or more other embodiments. Figure 4 Layout diagram of the display area; Figure 7 It shows along Figure 5 A cross-sectional view of the display panel taken by line I1-I1'; Figure 8 It is shown Figure 4 The layout diagram of the first pad (or "solder pad") portion; Figure 9 It shows along Figure 8 A cross-sectional view of the display panel taken by line I2-I2'; Figure 10 yes Figure 4A plan view of the alignment key; Figure 11 It shows along Figure 10 A cross-sectional view of the display panel taken by line I3-I3'; Figure 12 It shows along Figure 10 A cross-sectional view of the display panel taken by line I4-I4'; Figure 13 This is a perspective view showing a head-mounted display device according to one or more embodiments; Figure 14 It is shown Figure 13 Exploded perspective view of a head-mounted display device; Figure 15 This is a perspective view illustrating a head-mounted display device according to one or more other embodiments; Figure 16 It is a block diagram of an electronic device according to one or more embodiments; and Figure 17 , Figure 18 and Figure 19 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0029] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential to a full understanding of aspects of this disclosure for those skilled in the art, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0030] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can," "may," or "may not" in describing embodiments corresponds to one or more embodiments of this disclosure.

[0031] It will be understood by those skilled in the art that, in view of the whole of this disclosure, various suitable features of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, the various embodiments may be implemented independently of each other or in combination with each other in any suitable way.

[0032] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description, the disclosure is not limited thereto. Additionally, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities and / or any other characteristics, properties, etc., of the elements shown.

[0033] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes shown in the illustrations will be anticipated due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown for elements, layers, or regions, but will include deviations in shape due to factors such as manufacturing processes.

[0034] For example, an injection region shown as rectangular will typically have circular or curved features at its edges and / or an injection concentration gradient, rather than a binary variation from the injection region to the non-injection region. Similarly, a buried region formed by injection can result in some injection in the region between the buried region and the surface through which the injection occurs.

[0035] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “upper,” “above,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) are used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another (other) element or feature. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” another element or feature will subsequently be positioned “above” said other element or feature. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0036] Furthermore, the phrase "in a plan view" refers to the view of an object portion from above, and the phrase "in a schematic sectional view" refers to the view of a schematic section taken by vertically cutting through an object portion from the side. The terms "overlapping" or "overlapping" indicate that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping" may include stacking, facing or oriented, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" may include meanings such as "spaced apart from," "separated from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" may indicate that the first object may be directly or indirectly opposite the second object. In cases where a third object is located between the first and second objects, although the first and second objects still face each other, they may be understood as being indirectly opposite each other.

[0037] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, that component, layer, region, or assembly may be directly formed on, directly on, directly connected to, or directly incorporated into, the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into, the other component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may exist. Furthermore, this can collectively refer to direct or indirect incorporation or connection, as well as integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, that layer, region, or component may be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, connections are not limited to those shown in the accompanying drawings or detailed descriptions, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on" means that one component is directly connected to or directly bonded to another component, or directly on another component, without any intermediate components.

[0038] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components (such as "between," "immediately between," "adjacent to," and "directly adjacent to") can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0039] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying any individual elements within that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ) or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple (species / beings)”, “one of…”, and other prepositional phrases follow (before) a list of elements, they modify the entire list of elements, not individual elements within that list. When stated as “C to D”, unless otherwise specified, it means C or greater and D or less.

[0040] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are used only to distinguish one element, component, assembly, area, layer, section, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, area, layer, or part described below may be referred to as a second element, component, area, layer, or part. Describing an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or groups of elements. For brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0041] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0042] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when the terms “comprising,” “having,” “including,” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0043] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and indicates that, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system), it falls within an acceptable deviation range for the particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range acceptable to one of ordinary skill in the art. Other expressions may also omit “substantially.”

[0044] In some embodiments, well-known structures and arrangements may be described in conjunction with one or more functional blocks (e.g., block diagrams), units, and / or modules in the accompanying drawings to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software to perform the various functions discussed herein, which may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing functions different from those of the dedicated hardware. Furthermore, without departing from the scope of this disclosure, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of this disclosure, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0046] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments.

[0047] Reference Figure 1 and Figure 2 The display device 10 according to one or more embodiments is a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Optionally, the display device 10 according to one or more embodiments can be applied to smartwatches, watch phones, or head-mounted displays (HMDs) for implementing virtual reality and augmented reality.

[0048] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0049] The display panel 100 may have a shape similar to a rectangle in a plan view. For example, the display panel 100 may have a shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded with a curvature (e.g., a predetermined curvature) or formed at a right angle. The shape of the display panel 100 in a plan view is not limited to a rectangular shape, and may be similar to other polygonal shapes, circular shapes, or elliptical shapes. The shape of the display device 10 in a plan view may follow the shape of the display panel 100 in a plan view, but this disclosure is not limited thereto.

[0050] The display panel 100 includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), multiple data lines (DL), a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 2 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0051] Multiple pixels (PX) can be located within the display area (DAA). These multiple pixels (PX) can be arranged in a matrix along the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and be arranged along the first direction (DR1).

[0052] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0053] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 3 The multiple pixel transistors shown can be formed using semiconductor processes and can be located on a semiconductor substrate SSUB (see...). Figure 7 For example, the multiple pixel transistors of multiple sub-pixels SP1, SP2 and SP3 can be formed by complementary metal-oxide semiconductor (CMOS), but this disclosure is not limited thereto.

[0054] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emitt control line ECL1, a second emitt control line ECL2, and a data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0055] The scan driver 610, the transmit driver 620, and the data driver 700 can be located in the non-display area NDA.

[0056] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor data]). Figure 7For example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS, but this disclosure is not limited thereto.

[0057] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400, and may sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and may sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output the bias scan signal to the bias scan line GBL.

[0058] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and can sequentially output the first transmit control signal to the first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and can sequentially output the second transmit control signal to the second transmit control line ECL2.

[0059] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 For example, multiple data transistors can be formed using CMOS, but this disclosure is not limited thereto.

[0060] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and can output the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0061] The heat dissipation layer 200 may be stacked on the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100, for example, on its rear surface. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al), or graphite.

[0062] Circuit board 300 can be electrically connected to the first pad portion PDA1 of display panel 100 (see [link to PDA1]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be located on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion PDA1 of the display panel 100 (see Figure 1) using conductive adhesive members. Figure 4 Multiple first pads PD1 (see) Figure 4 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0063] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0064] The power supply circuit 500 can generate multiple panel driving voltages based on an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and can supply these three voltages to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0065] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and can be attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0066] Optionally, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by semiconductor processes and may be formed on a semiconductor substrate SSUB (see [link to semiconductor substrate]). Figure 7 On the data driver 700. For example, multiple timing transistors and multiple power transistors can be formed as CMOS, but this disclosure is not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be located in the data driver 700 and the first pad portion PDA1 (see...). Figure 4 )between.

[0067] Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments.

[0068] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, the second drive voltage line VDL, and the third drive voltage line VIL. The first drive voltage line VSL is applied with a first drive voltage VSS corresponding to a low potential voltage; the second drive voltage line VDL is applied with a second drive voltage VDD corresponding to a high potential voltage; and the third drive voltage line VIL is applied with a third drive voltage VINT corresponding to an initialization voltage.

[0069] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0070] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode; in this case, the light-emitting element LE can be a micro light-emitting diode.

[0071] The first transistor T1 may be a driving transistor that controls the source-drain current (hereinafter referred to as the "driving current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode.

[0072] The second transistor T2 can be located between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1.

[0073] The third transistor T3 can be located between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. Therefore, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode.

[0074] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE.

[0075] The fifth transistor T5 can be located between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0076] The sixth transistor T6 can be located between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0077] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0078] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0079] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0080] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0081] Figure 4 This is a layout diagram illustrating a display panel according to one or more embodiments.

[0082] Reference Figure 4The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0083] The scan driver 610 can be located on a first side of the display area DAA, and the transmit driver 620 can be located on a second side of the display area DAA. For example, the scan driver 610 can be located on one side of the display area DAA in a first direction DR1, and the transmit driver 620 can be located on the other side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and both the scan driver 610 and the transmit driver 620 can be located on either the first or the second side of the display area DAA.

[0084] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by conductive adhesive members. The first pad portion PDA1 may be located on the third side of the display area DAA. For example, the first pad portion PDA1 may be located on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be located outside the data driver 700 in the second direction DR2.

[0085] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to fixtures or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0086] The second pad portion PDA2 can be located on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be located on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be located outside the second distribution circuit 720 in the second direction DR2.

[0087] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one of the first pads PD1 in the first pad portion PDA1 to P data lines DL (P is a positive integer of 2 or greater), thus reducing the number of multiple first pads PD1. The first distribution circuit 710 can be located on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be located on one side of the display area DAA in the second direction DR2.

[0088] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be located on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2.

[0089] The cathode connection portion (CCA) can be the display element layer (EML) (see...). Figure 7 The second electrode CAT (see) Figure 7 The region connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection portion CCA may be located outside at least one side of the display area DAA. For example, the cathode connection portion CCA may be located outside at least one side of the display area DAA. Optionally, the cathode connection portion CCA may be as follows: Figure 4 The positioning shown is around the display area DAA to reduce or minimize the deviation of the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA.

[0090] like Figure 4 As shown, multiple alignment keys AK can be located at the edge of the display panel 100. For example, alignment keys AK can be used for alignment between the first pad PD1 and the circuit board 300 or for alignment between the second pad PD2 and the circuit board used for inspection.

[0091] Figure 5 It is shown Figure 4 The layout diagram of the display area. Figure 6 This illustrates one or more other embodiments. Figure 4 The layout diagram of the display area.

[0092] Reference Figure 5 and Figure 6 Each of the pixels PX includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0093] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can be arranged as follows in the plan view: Figure 5 and Figure 6The quadrilateral or hexagonal shape shown is not the only one described herein. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than quadrilaterals or hexagons in the plan view.

[0094] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other.

[0095] Optionally, such as Figure 6 As shown, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. In this case, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent or aligned in the second direction DR2. Additionally, the first emission region EA1 and the second emission region EA2 can be adjacent in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second diagonal direction DD2. Furthermore, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be a direction substantially perpendicular to the first diagonal direction DD1.

[0096] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0097] Each of the multiple pixels PX can include, for example Figure 5The three launch regions EA1, EA2, and EA3 shown may include, for example, Figure 6 The four emission regions EA1, EA2, EA3, and EA4 are shown. In this case, the fourth emission region EA4 can emit the same second light as the second emission region EA2, but this disclosure is not limited thereto.

[0098] The emission regions of multiple pixels PX can be arranged in a strip structure along the first direction DR1, such as... Figure 6 The emission areas EA1, EA2, EA3, and EA4 shown are arranged in a diamond-shaped PenTile. ® / PENTILE ® Structure (PenTile) ® and Pentile ® (It is a registered trademark of Samsung Display Co., Ltd. of South Korea), or a hexagonal structure with the emission area arranged in a hexagonal shape.

[0099] Figure 7 It shows along Figure 5 The cross-sectional view of the display panel is taken by line I1-I1'.

[0100] Reference Figure 7 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0101] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) having multiple pixel transistors (PTRs), multiple semiconductor insulating layers covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference... Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0102] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the top surface of the semiconductor substrate SSUB (as used herein, "located on" can mean "above"). The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0103] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0104] The lower insulating layer BINS can be located between the gate electrode GE and the well region WA. The side insulating layer SINS can be located on the side surface of the gate electrode GE. The side insulating layer SINS can be located on the lower insulating layer BINS.

[0105] Each of the source region SA and drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can be stacked with the gate electrode GE on the third direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0106] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. Due to the lower insulating layer BINS, the first low-concentration impurity region LDD1 can be a region with a lower impurity concentration than the source region SA. Due to the lower insulating layer BINS, the second low-concentration impurity region LDD2 can be a region with a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2; therefore, the length of the channel region CH in each of the pixel transistors PTR can be increased.

[0107] The first semiconductor insulating layer SINS1 can be located on the semiconductor substrate SSUB. The second semiconductor insulating layer SINS2 can be located on the first semiconductor insulating layer SINS1.

[0108] Multiple contact terminals (CTEs) may be located on the second semiconductor insulating layer (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating layer (SINS1) and the second semiconductor insulating layer (SINS2). The multiple contact terminals (CTEs) may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0109] The third semiconductor insulating layer (SINS3) may be located on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) may be exposed and not covered by the third semiconductor insulating layer (SINS3).

[0110] Each of the first semiconductor insulating layer SINS1, the second semiconductor insulating layer SINS2, and the third semiconductor insulating layer SINS3 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0111] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate (such as polyimide). In this case, the thin-film transistor can be located on either the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0112] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS10.

[0113] The first insulating layers INS1 to the eighth insulating layers INS8 are used to insulate the first conductive layers ML1 to the eighth conductive layers ML8. The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 3 The circuit of the first sub-pixel SP1 shown.

[0114] For example, transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the connection between transistors T1 to T6 and the first capacitor CP1 and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0115] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first insulating layers INS1 to INS8 can be formed of substantially the same material. The first insulating layers INS1 to INS8 can be made of silicon oxide (SiO2).x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0116] The ninth insulating layer INS9 can be located on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0117] Each of the ninth vias VA9 can penetrate the tenth insulating layer INS10 and the ninth insulating layer INS9, and can connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0118] The display element layer (EML) can be located on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include an eleventh insulating layer (INS11) and a twelfth insulating layer (INS12), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining layer (PDL), and multiple trenches (TRC).

[0119] The reflective electrode RL may be located on the tenth insulating layer INS10. The reflective electrode RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode RL may include, for instance... Figure 7 The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 are shown in the figure.

[0120] The first reflective electrode RL1 can be located on the tenth insulating layer INS10 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be located on the corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be located on the corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be located on the corresponding third reflective electrode RL3.

[0121] Because the second reflective electrode RL2 is essentially the electrode that reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0122] Each of the first reflective electrodes RL1 to the fourth reflective electrodes RL4 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or compounds thereof. For example, each of the first reflective electrodes RL1 may include titanium nitride (TiN), each of the second reflective electrodes RL2 may include aluminum (Al), each of the third reflective electrodes RL3 may include titanium nitride (TiN), and each of the fourth reflective electrodes RL4 may include titanium (Ti).

[0123] The eleventh insulating layer INS11 may be located on the tenth insulating layer INS10. The eleventh insulating layer INS11 may be located between adjacent reflective electrodes RL. The eleventh insulating layer INS11 may be a film used to flatten the step caused by the reflective electrode RL. The twelfth insulating layer INS12 may be located on the eleventh insulating layer INS11 and the reflective electrode RL.

[0124] The eleventh insulating layer INS11 and the twelfth insulating layer INS12 can be formed of silicon oxide (SiO2). x This disclosure includes inorganic membranes, but is not limited thereto.

[0125] The twelfth insulating layer INS12 can be an optical auxiliary layer used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixels SP1, SP2, and SP3. The thickness of the twelfth insulating layer INS12 can be different in the first sub-pixels SP1, SP2, and SP3. That is, in order to adjust the distance from the reflective electrode RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first sub-pixels SP1, SP2, and SP3, the thickness of the twelfth insulating layer INS12 can be set (e.g., set differently) in each of the first sub-pixels SP1, SP2, and SP3.

[0126] For example, such as Figure 7As shown, the thickness of the twelfth insulating layer INS12 in the first sub-pixel SP1 can be greater than the thickness of the twelfth insulating layer INS12 in the second sub-pixel SP2. The thickness of the twelfth insulating layer INS12 in the second sub-pixel SP2 can be greater than the thickness of the twelfth insulating layer INS12 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 can be greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0127] Each of the tenth vias VA10 can penetrate the twelfth insulating layer INS12 and can be connected to the exposed fourth reflective electrode RL4. The tenth vias VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0128] The first electrode AND of each of the light-emitting elements LE can be located on the twelfth insulating layer INS12 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth via VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or compounds thereof. For example, the first electrode AND of each of the light-emitting elements LE can be made of titanium nitride (TiN).

[0129] The pixel defining layer (PDL) may be located on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL may cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL may separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be a region of the light-emitting element (LE) with the first electrode AND, the light-emitting stack IL, and the second electrode CAT positioned thereon.

[0130] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0131] The pixel definition layer (PDL) may include a first pixel definition layer (PDL1), a second pixel definition layer (PDL2), and a third pixel definition layer (PDL3). The first pixel definition layer (PDL1) may be located on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel definition layer (PDL2) may be located on the first pixel definition layer (PDL1), and the third pixel definition layer (PDL3) may be located on the second pixel definition layer (PDL2). The first pixel definition layer (PDL1), the second pixel definition layer (PDL2), and the third pixel definition layer (PDL3) may be made of silicon oxide (SiO2). x An inorganic film of the form of silicon nitride (SiN) can be formed. Optionally, the first pixel defining layer PDL1 and the third pixel defining layer PDL3 can be formed of silicon nitride (SiN). x An inorganic layer of type ) is formed, while the second pixel defining layer PDL2 can be formed of silicon oxide (SiO2). x ( ) Formation of inorganic films. The first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 can each have a thickness of approximately 500 Å.

[0132] To reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which the film is coated on the flat portion. The lower the step coverage, the easier it is for the film to be cut at the inclined portion.

[0133] Each of the plurality of trench TRCs can penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. In each of the plurality of trench TRCs, the twelfth insulating film INS12 can have a shape in which at least a portion of the twelfth insulating film INS12 is slotted.

[0134] At least one trench TRC can be located between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Two trench TRCs are shown located between adjacent sub-pixels SP1, SP2 and SP3, but this disclosure is not limited thereto.

[0135] The light-emitting stack IL can include multiple stacked layers IL1, IL2, and IL3. [This is already in progress / is being studied / implemented]. Figure 7 The diagram illustrates a light-emitting stack IL having a triple-tandem structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, the light-emitting stack IL may have a double-tandem structure comprising two stacked layers.

[0136] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 for emitting different colors of light. For example, the light-emitting stack IL may include a first stacked layer IL1 for emitting light of a first color, a second stacked layer IL2 for emitting light of a second color, and a third stacked layer IL3 for emitting light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0137] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer for emitting light of a first color, and a first electron transport layer are stacked in sequence. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer for emitting light of a second color, and a second electron transport layer are stacked in sequence. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer for emitting light of a third color, and a third electron transport layer are stacked in sequence.

[0138] A first charge generation layer for supplying holes to the second stacked layer IL2 and for supplying electrons to the first stacked layer IL1 may be located between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0139] A second charge generation layer for supplying holes to the third stacked layer IL3 and for supplying electrons to the second stacked layer IL2 may be located between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0140] A first stacked layer IL1 may be located on the first electrode AND and the pixel defining layer PDL, and the residual film RIL on the bottom surface of the trench TRC in each trench TRC may be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 may be located on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space may be located between the residual film RIL and the third stacked layer IL3. The third stacked layer IL3 may be located on the second stacked layer IL2. The third stacked layer IL3 may not be disconnected by the trench TRC and may be positioned to cover the second stacked layer IL2 in each trench TRC.

[0141] In a three-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the first charge generation layer, the second charge generation layer, and the first hole transport layer to the third hole transport layer of each of the first stacked layers IL1 to IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. Alternatively, in a two-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the charge generation layer and the lower stacked layer located between the lower stacked layer and the upper stacked layer.

[0142] To stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To disconnect the charge generation layer of the display element layer EML and the hole transport layer of the light-emitting stack IL between adjacent sub-pixels SP1, SP2, and SP3, other structures can exist instead of trench TRCs. For example, instead of trench TRCs, a partition wall with an inverted conical shape can be located on the pixel defining layer PDL.

[0143] Already Figure 7The diagram shows a light-emitting stack IL completely located within the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, this disclosure is not limited thereto. For example, instead of the light-emitting stack IL, the first light-emitting layer may be located in the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Similarly, the second light-emitting layer may be located in the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Furthermore, the third light-emitting layer may be located in the third emission region EA3 and may be omitted from both the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0144] The second electrode CAT can be located on the light-emitting stack IL. The second electrode CAT can be located on the third stack IL3 in each of the multiple trench TRCs. The second electrode CAT can be made of a transparent conductive material (TCO) (such as indium tin oxide (ITO) or indium zinc oxide (IZO) capable of transmitting light through it) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the second electrode CAT is made of a semi-transmissive conductive material, the luminous efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be increased through the microcavity.

[0145] The encapsulation layer TFE can be located on the display element layer EML. The encapsulation layer TFE may include at least one encapsulation inorganic film TFE1 and TFE3 to reduce or prevent oxygen or moisture penetration into the display element layer EML. For example, the first encapsulation inorganic film TFE1 may be located on the second electrode CAT, and the second encapsulation inorganic film TFE3 may be located on the first encapsulation inorganic film TFE1. Each of the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed in which silicon nitride (SiN) is extracted. x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and aluminum oxide (AlO) x A multilayer of alternating stacks of one or more inorganic membranes selected from )

[0146] Additionally, the encapsulation layer TFE may include at least one encapsulation organic film TFE2 to protect the display element layer EML from foreign matter such as dust. For example, the encapsulation organic film TFE2 may be located between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. Optionally, the encapsulation organic film TFE2 may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0147] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Alternatively, the adhesive layer ADL can be a transparent adhesive component such as a transparent adhesive or a transparent adhesive resin.

[0148] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the adhesive layer ADL.

[0149] A first color filter CF1 may be superimposed on a first emission region EA1 of a first sub-pixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light in the blue band). The blue band may be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color emitted from the first emission region EA1.

[0150] The second color filter CF2 can be superimposed on the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (e.g., light in the green band). The green band can be from approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0151] The third color filter CF3 can be superimposed on the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color (e.g., light in the red band). The red band can be from about 600 nm to about 750 nm. Therefore, the third color filter CF3 can transmit light of a third color emitted from the third emission region EA3.

[0152] Multiple lenses LNS can be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed to the front of the display device 10. Each of the multiple lenses LNS can have a profile shape that convexes in the upward direction.

[0153] The filler layer (FIL) can be located on multiple lens lenses (LNS). The filler layer (FIL) can have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens lenses (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0154] The cover layer CVL can be located on the filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0155] The polarizer POL can be located on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizer POL can be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0156] Figure 8 It is shown Figure 4 The layout diagram of the first pad of the first pad part. Figure 9 It shows along Figure 8 The cross-sectional view of the display panel is taken by line I2-I2'.

[0157] Reference Figure 8 and Figure 9 Each of the first pads PD1 includes a first sub-pad BPD and a second sub-pad IPD. Both the first sub-pad BPD and the second sub-pad IPD can be electrically connected to the pads or bumps of the circuit board 300 via conductive adhesive members. Additionally, the second sub-pad IPD can be a pad that is connected to a fixture or probe pin or the circuit board for inspection during the inspection process.

[0158] The area of ​​the first sub-pad BPD can be larger than the area of ​​the second sub-pad IPD. The width of the first sub-pad BPD in the first direction DR1 can be substantially the same as the width of the second sub-pad IPD in the first direction DR1. The length of the first sub-pad BPD in the second direction DR2 can be longer than the length of the second sub-pad IPD in the second direction DR2.

[0159] Each of the first sub-pad BPD and the second sub-pad IPD may include a pad conductive layer PML. The pad conductive layer PML may include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or compounds thereof. The second sub-pad conductive layer SPML2 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or compounds thereof. For example, the first sub-pad conductive layer SPML1 may be made of aluminum (Al).

[0160] The thickness of the first sub-pad conductive layer SPML1 can be greater than the thickness of the reflective electrode RL. For example, the first sub-pad conductive layer SPML1 can have a thickness of approximately 10,000 Å or greater (e.g., 12,000 Å or greater). Additionally, the second sub-pad conductive layer SPML2 can be made of titanium nitride (TiN) and can have a thickness of approximately 1,000 Å or less (e.g., approximately 600 Å). Because the first sub-pad conductive layer SPML1 is formed to have a thickness of approximately 10,000 Å or greater, damage to the pad conductive layer PML can be reduced or prevented even when pressure is applied to the fixtures or probe pins in the pad conductive layer PML during inspection processes.

[0161] The pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD can be positioned separately from each other, but can be connected to the eighth conductive layer ML8 through the ninth via VA9 penetrating the ninth insulating layer INS9. For example, the first sub-pad conductive layer SPML1 of the first sub-pad BPD and the first sub-pad conductive layer SPML1 of the second sub-pad IPD can be connected to the eighth conductive layer ML8 through the ninth via VA9 penetrating the ninth insulating layer INS9. Therefore, the pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD can have substantially the same potential.

[0162] like Figure 8 and Figure 9As shown, when the pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD are separated or distinguished from each other, even if the pad conductive layer PML of the second sub-pad IPD is damaged or destroyed by the fixture or probe pins during the inspection process, the pad conductive layer PML of the first sub-pad BPD will not be damaged or destroyed. That is, by physically separating the first sub-pad BPD connected to the circuit board 300 and the second sub-pad IPD used in the inspection process, even if the pad conductive layer PML of the second sub-pad IPD is damaged, the pad conductive layer PML of the first sub-pad BPD can still be stably connected to the circuit board 300.

[0163] Figure 10 yes Figure 4 A plan view of the alignment key. Figure 11 It shows along Figure 10 The cross-sectional view of the display panel is taken by line I3-I3'. Figure 12 It shows along Figure 10 The cross-sectional view of the display panel is taken by line I4-I4'.

[0164] like Figure 10 and Figure 11 As shown, the alignment key AK may include an outer pattern layer 21, an inner pattern layer 22, and a dummy layer 23. For example... Figure 11 and Figure 12 As shown, the alignment key AK can be located on or above the ninth insulating layer INS9. The alignment key AK can be stacked on the third-direction DR3 above the substrate (e.g., semiconductor substrate SSUB) with the first semiconductor insulating layers SINS1 to SINS3 of the semiconductor backplane SBP and the first insulating layers INS1 to INS9 of the light-emitting element backplane EBP. In this case, the alignment key AK can be stacked on the third-direction DR3 without being stacked with other metal layers.

[0165] exist Figure 10 In the plan view shown, the outer pattern layer 21 may have a quadrilateral shape. However, the shape of the outer pattern layer 21 is not limited to this and can be varied in various shapes. The outer pattern layer 21 may have a through-hole 11. For example, the through-hole 11 may be defined by the outer pattern layer 21. The through-hole 11 may penetrate the outer pattern layer 21 in a third direction DR3. In the plan view, the through-hole 11 may have a cross shape. However, the shape of the through-hole 11 is not limited to this and can be varied in various shapes. The outer pattern layer 21 may include a first sub-outer outer pattern layer 21a and a second sub-outer outer pattern layer 21b located on different layers.

[0166] The first sub-outer pattern layer 21a of the outer pattern layer 21 may be located on the ninth insulating layer INS9, and the second sub-outer pattern layer 21b of the outer pattern layer 21 may be located on the first sub-outer pattern layer 21a. The first sub-outer pattern layer 21a and the second sub-outer pattern layer 21b may be stacked on each other on the third-direction DR3 and may be in contact with each other.

[0167] The outer pattern layer 21 can be made of the same material as the first pad PD1 described above. For example, the outer pattern layer 21 can be made of the same material as the pad conductive layer PML of the first pad PD1. For example, the first sub-outer pattern layer 21a of the outer pattern layer 21 can be made of the same material as the first sub-pad conductive layer SPML1 described above, and the second sub-outer pattern layer 21b of the outer pattern layer 21 can be made of the same material as the second sub-pad conductive layer SPML2. The outer pattern layer 21 and the pad conductive layer PML can be formed together using the same process.

[0168] The inner pattern layer 22 may be located inside the through-hole 11 of the outer pattern layer 21. For example, in a plan view, the inner pattern layer 22 may be surrounded by the edge of the outer pattern layer 21 (or the through-hole 11 of the outer pattern layer 21). In a plan view, the inner pattern layer 22 may have the same shape as the through-hole 11. For example, the inner pattern layer 22 may have a cross shape. However, the shape of the inner pattern layer 22 is not limited to this and can be changed in various shapes. The inner pattern layer 22 may include a first sub-inner pattern layer 22a and a second sub-inner pattern layer 22b located on different layers.

[0169] The first sub-internal pattern layer 22a of the internal pattern layer 22 can be located on the ninth insulating layer INS9 inside the through-hole 11, and the second sub-internal pattern layer 22b of the internal pattern layer 22 can be located on the first sub-internal pattern layer 22a. The first sub-internal pattern layer 22a and the second sub-internal pattern layer 22b can be stacked on each other on the third-direction DR3 and can be in contact with each other.

[0170] The inner patterned layer 22 can be made of the same material as the outer patterned layer 21. For example, the first sub-inner patterned layer 22a of the inner patterned layer 22 can be made of the same material as the first sub-outer patterned layer 21a described above, and the second sub-inner patterned layer 22b of the inner patterned layer 22 can be made of the same material as the second sub-outer patterned layer 21b described above. The inner patterned layer 22 and the outer patterned layer 21 can be formed together using the same process (one or more of the same processes). The thickness of the inner patterned layer 22 on the third-direction DR3 and the thickness of the outer patterned layer 21 on the third-direction DR3 can be the same.

[0171] Dummy layer 23 may be located between outer pattern layer 21 and inner pattern layer 22. For example, dummy layer 23 may be located on the ninth insulating layer INS9 in a via 11 of outer pattern layer 21. A portion of dummy layer 23 may be located inside via 11. Dummy layer 23 may extend on third-direction DR3 to be located on outer pattern layer 21 and inner pattern layer 22 (e.g., partially on or above outer pattern layer 21 and inner pattern layer 22).

[0172] The dummy layer 23 may have a through-hole 12. The through-hole 12 of the dummy layer 23 may be located on the inner pattern layer 22 to overlap with the inner pattern layer 22. The through-hole 12 of the dummy layer 23 may have the same shape as the inner pattern layer 22. For example, the through-hole 12 of the dummy layer 23 may have a cross shape.

[0173] The virtual layer 23 may include a first sub-virtual layer 23a, a second sub-virtual layer 23b, a third sub-virtual layer 23c, and a fourth sub-virtual layer 23d.

[0174] The first sub-dummy layer 23a of dummy layer 23 may be located on the ninth insulating layer INS9 between the via 11 and the inner patterned layer 22 (e.g., between the outer patterned layer 21 and the inner patterned layer 22). A portion of the first sub-dummy layer 23a may be located inside the via 11. The first sub-dummy layer 23a may extend on the third-direction DR3 to be located on the outer patterned layer 21 and the inner patterned layer 22. The first sub-dummy layer 23a may, for example, be made of the same material as the tenth insulating layer INS10. The first sub-dummy layer 23a and the tenth insulating layer INS10 may be manufactured together using the same process.

[0175] The second sub-dummy layer 23b of dummy layer 23 can be located on the first sub-dummy layer 23a. The second sub-dummy layer 23b can be stacked on the first sub-dummy layer 23a on the third-direction DR3 and can be in contact with each other. The second sub-dummy layer 23b can be made of the same material as the first pixel-defining layer PDL1 described above. The second sub-dummy layer 23b and the first pixel-defining layer PDL1 can be formed together using the same process.

[0176] The third sub-dummy layer 23c of dummy layer 23 can be located on the second sub-dummy layer 23b. The third sub-dummy layer 23c can be stacked on the second sub-dummy layer 23b on the third-direction DR3 and can be in contact with each other. The third sub-dummy layer 23c can be made of the same material as the second pixel-defining layer PDL2 described above. The third sub-dummy layer 23c and the second pixel-defining layer PDL2 can be formed together using the same process.

[0177] The fourth sub-dummy layer 23d of dummy layer 23 can be located on the third sub-dummy layer 23c, the outer pattern layer 21, and the inner pattern layer 22. The fourth sub-dummy layer 23d can be stacked on the third sub-dummy layer 23c on the third-direction DR3 and can be in contact with each other. Additionally, the fourth sub-dummy layer 23d can be located on the side surface of the first sub-dummy layer 23a (e.g., on a portion of the side surface of the first sub-dummy layer 23a), the side surface of the second sub-dummy layer 23b, and the side surface of the third sub-dummy layer 23c. The fourth sub-dummy layer 23d can be made of the same material as the third pixel defining layer PDL3 described above. The fourth sub-dummy layer 23d and the third pixel defining layer PDL3 can be formed using the same process. In one or more embodiments, the fourth sub-dummy layer 23d and the third pixel defining layer PDL3 can be joined together to be integrally formed.

[0178] The thickness of the first sub-dummy layer 23a on the third-direction DR3 may be greater than the thickness of the outer pattern layer 21 on the third-direction DR3. In one or more embodiments, the thickness of the first sub-dummy layer 23a on the third-direction DR3 may be greater than the thickness of the inner pattern layer 22 on the third-direction DR3. In one or more embodiments, the thickness of the first sub-dummy layer 23a on the third-direction DR3 may be greater than the thickness of the second sub-dummy layer 23b on the third-direction DR3. In one or more embodiments, the thickness of the first sub-dummy layer 23a on the third-direction DR3 may be greater than the thickness of the third sub-dummy layer 23c on the third-direction DR3. In one or more embodiments, the thickness of the first sub-dummy layer 23a on the third-direction DR3 may be greater than the thickness of the fourth sub-dummy layer 23d on the third-direction DR3.

[0179] For example, the alignment key AK can be captured or detected by an optical device. In this case, the alignment key AK can be identified (or detected) due to the outer pattern layer 21 and the inner pattern layer 22 (each of which can be formed of metal), and due to the dummy layer 23 located between the outer pattern layer 21 and the inner pattern layer 22 (the dummy layer 23 can be formed of non-metal). For example, the cross-shaped through-hole 11 can be clearly identified (or detected) as the shape of the alignment key AK due to the difference in reflectivity between the metal and non-metal in the relevant region. The optical device described above can capture an image of the alignment key AK in the region of the alignment key AK. For example, during the capture of the alignment key AK, the alignment key AK can be located between the optical device and the ninth insulating layer INS9.

[0180] Furthermore, during the manufacturing process of the display device 10, since the outer pattern layer 21 and the inner pattern layer 22 can be covered (or protected) by the fourth sub-dummy layer 23d of the dummy layer 23, damage to the outer pattern layer 21 and the inner pattern layer 22 can be reduced or prevented during the manufacturing process of the display device 10. Therefore, the possibility of visual errors in the alignment key AK due to damage to the outer pattern layer 21 or the inner pattern layer 22 can be reduced or prevented.

[0181] Figure 13 This is a perspective view showing a head-mounted display device according to one or more embodiments. Figure 14 It is shown Figure 13 An exploded perspective view of a head-mounted display device.

[0182] Reference Figure 13 and Figure 14 A head-mounted display device 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0183] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 can be combined with... Figures 1 to 12 The display devices 10 described are essentially the same, so the descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0184] The first optical component 1510 may be located between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be located between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0185] The intermediate frame 1400 can be located between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2 and the control circuit board 1600.

[0186] The control circuit board 1600 can be located between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0187] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0188] The display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is positioned to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned at the user's left eye and a second eyepiece 1220 positioned at the user's right eye. Figure 13 and Figure 14 The first eyepiece 1210 and the second eyepiece 1220 are shown positioned separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0189] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0190] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned on the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display device 1000 can be configured as follows: Figure 15 The eyeglass frame shown is used instead of the headband 1300.

[0191] Figure 15 This is a perspective view illustrating a head-mounted display device according to one or more other embodiments.

[0192] Reference Figure 15 The head-mounted display device 1000_1 according to one or more embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to one or more embodiments may include a display device 10_4, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0193] The display device housing 1200_1 can accommodate the display device 10_4, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 10_4 can be magnified by the optical component 1060, the light path can be converted by the light path changing component 1070, and provided to the user's right eye through the right eye lens 1020. Therefore, the user can view an augmented reality image in which the virtual image displayed on the display device 10_4 as seen through his / her right eye is combined with the real image seen through the right eye lens 1020.

[0194] exist Figure 15 The display device housing 1200_1 has been shown located at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030, and in this case, the image displayed on the display device 10_4 may be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 10_4 through both his / her left and right eyes.

[0195] Display devices can be applied to various electronic devices. An electronic device according to one or more embodiments includes the display device described above, and may also include modules or devices with additional functions in addition to the display device.

[0196] Figure 16 This is a block diagram of an electronic device according to one or more embodiments. (Refer to...) Figure 16 The electronic device 50 according to one or more embodiments may include a display module 18, a processor 19, a memory 13, and a power module 14. The electronic device 50 may also include an input module 15, an output module 16, and / or a communication module 17.

[0197] Electronic device 50 can output various information in the form of images through display module 18. When processor 19 executes an application stored in memory 13, the image information provided by the application can be provided to the user through display module 18. Power module 14 may include a power supply module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of electronic device 50. Input module 15 can provide input information to processor 19 and / or display module 18. Output module 16 can receive information other than images (such as sound, touch, and light) sent from processor 19 and provide that information to the user. Communication module 17 is responsible for sending and receiving information between electronic device 50 and external devices, and may include a receiving unit and a sending unit.

[0198] At least one of the components of the electronic device 50 described above may be included in the display device according to the embodiments described above. Additionally, some modules that are functionally included in a single module may be included in the display device, while other modules may be disposed separately from the display device. For example, the display device includes a display module 18, and the processor 19, memory 13, and power module 14 may be disposed within the electronic device 50 as other devices besides the display device.

[0199] Figure 17 , Figure 18 and Figure 19 These are schematic diagrams of electronic devices according to various embodiments. Figures 17 to 19 Examples of various electronic devices that utilize a display device according to an embodiment are shown.

[0200] Figure 17 Examples of electronic devices are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0201] In addition to the display module 18, the smartphone 10_1a may also include input modules such as a touch sensor and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0202] In the case of tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e, they may also include a display module and input module similar to those of smartphone 10_1a, and in some cases may additionally include a communication module.

[0203] Figure 18The illustration shows an electronic device, including a display module, used in a wearable electronic device. The wearable electronic device can be smart glasses 10_2a, a head-mounted display 10_2b, a smartwatch 10_2c, etc.

[0204] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0205] The smartwatch 10_2c includes a biometric sensor as an input device and can provide the user with biometric information identified by the biometric sensor through a display module.

[0206] Figure 19 The illustration shows an application of an electronic device, including a display module, in a vehicle. For example, the display device 10_3 can be applied to the vehicle's dashboard, central instrument panel, etc., or it can be applied to a CID (Central Information Display) placed on the vehicle's dashboard, or an interior mirror display that replaces the side mirrors.

[0207] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the aspects of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, characterized in that, The display device includes: Base; The first electrode is on the substrate; A pixel-defining layer is located above the first electrode; A light-emitting stack above the first electrode and the pixel defining layer; The second electrode is located above the light-emitting stack; and The alignment key is located in a non-display area of ​​the substrate and includes: an outer pattern layer above the substrate; an inner pattern layer inside a through-hole in the outer pattern layer; and a dummy layer between the outer pattern layer and the inner pattern layer.

2. The display device according to claim 1, characterized in that, The outer pattern layer and the inner pattern layer are metal layers, and The dummy layer is a non-metallic layer.

3. The display device according to claim 1, characterized in that, The inner pattern layer is surrounded by the outer pattern layer in the plan view.

4. The display device according to claim 1, characterized in that, The outer pattern layer includes: First sub-outer pattern layer; and The second sub-outer pattern layer is located above the first sub-outer pattern layer.

5. The display device according to claim 1, characterized in that, The internal pattern layer includes: The first sub-internal pattern layer; and The second sub-internal pattern layer is located above the first sub-internal pattern layer.

6. The display device according to claim 1, characterized in that, The virtual layer includes: First sub-virtual layer; The second sub-virtual layer is located above the first sub-virtual layer; The third sub-virtual layer is located above the second sub-virtual layer; and The fourth sub-virtual layer is located above the third sub-virtual layer.

7. The display device according to claim 6, characterized in that, The first sub-dummy layer is at least partially above the outer pattern layer and the inner pattern layer.

8. The display device according to claim 6, characterized in that, The fourth sub-dummy layer is above the outer pattern layer and the inner pattern layer.

9. The display device according to claim 1, characterized in that, The through-hole and the internal pattern layer have the same shape.

10. The display device according to claim 1, characterized in that, The dummy layer has through holes that overlap with the inner pattern layer.

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