Josephson junction and semiconductor device

Abstract

The utility model provides a kind of Josephson junction and semiconductor device, comprising: semiconductor substrate, the semiconductor substrate has two adjacent grooves and the fin portion between two adjacent grooves, the two adjacent grooves are spaced by the fin portion;First metal electrode and second metal electrode are filled in two adjacent grooves respectively, the first metal electrode, the second metal electrode and the fin portion between two adjacent grooves constitute fin type vertical stack structure. To improve the quantum decoherence time of Josephson junction and improve the integrated density of Josephson junction.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a Josephson junction and semiconductor device. Background Technology

[0002] The traditional Josephson junction, also known as a superconducting tunnel junction, is generally a structure consisting of two superconductors sandwiching a very thin barrier layer.

[0003] Please refer to Figure 1 A traditional Josephson junction, from bottom to top, includes a substrate 10, a first electrode 20, a barrier layer 30, and a second electrode 40. The traditional Josephson junction is a planar structure with low integration density. The barrier layer 30 of the traditional Josephson junction is usually made of aluminum oxide. Since aluminum oxide has an amorphous structure and high interface defects between aluminum oxide and aluminum, the quantum decoherence time of the Josephson junction is limited.

[0004] Therefore, improving the quantum decoherence time and increasing the integration density of Josephson junctions have become urgent technical problems that need to be solved by existing technologies. Utility Model Content

[0005] This invention provides a Josephson junction and semiconductor device that improves the quantum decoherence time and integration density of the Josephson junction.

[0006] According to a first aspect of the present invention, the present invention provides a Josephson knot, comprising: A semiconductor substrate having two adjacent grooves and a fin located between the two adjacent grooves, the two adjacent grooves being spaced apart by the fin; The first metal electrode and the second metal electrode are respectively filled in two adjacent grooves, and the first metal electrode, the second metal electrode, and the fin between the two adjacent grooves form a fin-type vertical stacking structure.

[0007] Optionally, the semiconductor substrate is made of single-crystal silicon.

[0008] Optionally, the semiconductor substrate is made of a Si and Ge composite layer or a Si and AlN composite layer.

[0009] Optionally, the material of the first metal electrode is Al; The material of the second metal electrode is AL.

[0010] Optionally, in the fin-type vertical stacked structure, the thickness of the fin between the first metal electrode and the second metal electrode is 12nm-15nm.

[0011] Optionally, the semiconductor substrate is a P-type semiconductor substrate.

[0012] According to a second aspect of the present invention, the present invention also provides a semiconductor device, including the Josephson junction described above.

[0013] Compared with the prior art, the technical solution of this utility model embodiment has the following beneficial effects: In the Josephson junction and semiconductor device of this invention, the semiconductor substrate has two adjacent grooves and fins located between them. The adjacent grooves are separated by the fins, resulting in a relatively ordered interface of the semiconductor material. Therefore, by using the fins formed on the semiconductor substrate between the two grooves as a barrier layer, the barrier layer becomes more ordered, thereby improving the quantum decoherence time of the formed Josephson junction. Furthermore, since the first metal electrode and the second metal electrode are located in two adjacent grooves, the first metal electrode, the second metal electrode, and the fins between the two adjacent grooves constitute a fin-type vertical stacked structure. Therefore, the three-dimensional structure of the formed fin-type vertical stacked structure has a high integration density. At the same time, the thickness of the fins, i.e., the barrier layer of the Josephson junction, is easier to control, making the interface of the formed fins more ordered, thus resulting in more stable junction parameters of the formed Josephson junction. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a Josephson knot. Figure 2 This is a schematic diagram of the Josephson knot in one embodiment of the present invention. Detailed Implementation

[0016] As described in the background section, traditional Josephson junctions have low integration density and long quantum decoherence times. A detailed explanation follows with reference to the accompanying drawings.

[0017] In view of this, the present invention provides a Josephson junction, which has two adjacent grooves in a semiconductor substrate and fins located between the two adjacent grooves, with the two adjacent grooves separated by the fins; a first metal electrode and a second metal electrode are respectively filled in the two adjacent grooves, and the first metal electrode, the second metal electrode, and the fins between the two adjacent grooves constitute a fin-type vertical stacked structure. This improves the quantum decoherence time of the Josephson junction and increases its integration density.

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0019] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] The technical solution of this utility model will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0021] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0022] Please refer to Figure 2 An embodiment of this utility model proposes a Josephson junction, comprising: A semiconductor substrate 100 having two adjacent grooves and a fin 200 located between the two adjacent grooves, the two adjacent grooves being spaced apart by the fin 200.

[0023] The first metal electrode 300 and the second metal electrode 400 are respectively filled in two adjacent grooves, and the first metal electrode 300, the second metal electrode 400, and the fin 200 between the two adjacent grooves constitute a fin-type vertical stacking structure.

[0024] In this embodiment, since the semiconductor substrate 100 has two adjacent grooves and a fin 200 located between the two adjacent grooves, and the two adjacent grooves are separated by the fin 200, the interface of the semiconductor material is relatively ordered. Therefore, by using the fin 200 formed on the semiconductor substrate 100 between the two grooves as a barrier layer, the barrier layer is made more ordered, thereby improving the quantum decoherence time of the formed Josephson junction. Furthermore, since the first metal electrode 300 and the second metal electrode 400 are located in two adjacent grooves, the first metal electrode 300, the second metal electrode 400, and the fin 200 between the two adjacent grooves constitute a fin-type vertical stacked structure. Therefore, the three-dimensional structure of the formed fin-type vertical stacked structure has a high integration density. At the same time, by forming the fin 200 in the groove, the thickness of the fin 200, i.e., the barrier layer, is easier to control, making the interface of the formed fin 200 more ordered, thereby making the junction parameters of the formed Josephson junction more stable.

[0025] As an example, the semiconductor substrate 100 is made of single-crystal silicon.

[0026] Using the monocrystalline silicon as the semiconductor material, and the fin 200 also being made of monocrystalline silicon, the interface defects between monocrystalline silicon and aluminum are lower. Therefore, the quantum decoherence time is higher in this embodiment.

[0027] As another example, the semiconductor substrate 100 is made of a Si and Ge composite layer or a Si and AlN composite layer.

[0028] Specifically, the material of the first metal electrode 300 is AL.

[0029] The material of the second metal electrode 400 is AL.

[0030] Al is a superconducting material. Al has good interface compatibility with single-crystal silicon. Using Al as the material for the first metal electrode 300 and the second metal electrode 400 helps to reduce defects at the interface, thereby reducing losses and low decoherence time caused by interface problems.

[0031] Of course, this invention is not limited thereto. As an example, the materials of the first metal electrode 300 and the second metal electrode 400 can also be Nb, TiN, NbN, YBa2Cu3O. δIt can be any of the following superconducting materials: Bi2Sr2CaCu2O8, where δ≥7 and δ is a positive integer.

[0032] In one embodiment, the fin thickness between the first metal electrode 300 and the second metal electrode 400 in the fin vertical stacking structure is 12nm-15nm.

[0033] Since the thickness of the fin between the two metal electrodes in the fin-type vertical stacked structure is 12nm-15nm, under the same process precision, the small change in thickness in a thicker barrier has a relatively low impact on the junction parameters of the Josephson junction.

[0034] As an example, the semiconductor substrate 100 is a P-type semiconductor substrate.

[0035] The dielectric loss and charge noise of the semiconductor substrate 100 are important factors affecting quantum decoherence. These negative effects of P-type semiconductor substrates can be reduced by optimizing doping and surface treatment.

[0036] In traditional Josephson junctions, the barrier layer of alumina is an amorphous thin film formed by the thermal oxidation of aluminum. The thermal oxidation process is difficult to control precisely, resulting in uneven alumina thickness and structural and chemical defects, leading to a rough and disordered interface. In this embodiment, however, the barrier layer is formed from a semiconductor material through anisotropic etching. The crystal planes formed by the etching process have atomic-level flatness and parallelism, exhibiting better ordering compared to alumina. The high lattice matching between aluminum and the semiconductor material allows for a low-defect interface to be achieved through surface cleaning (such as HF etching) and high-temperature annealing, resulting in a Josephson junction with a more ordered atomic arrangement at the interface.

[0037] In traditional Josephson junctions, the amorphous structure and interface defects of alumina significantly shorten the coherence time. However, the Josephson junction of this invention uses a semiconductor material, such as single-crystal silicon, for its fin 200, i.e., the barrier layer, reducing interface defects and improving the quantum decoherence time.

[0038] In traditional Josephson junctions, the high dielectric loss of aluminum oxide and the additional losses of the Al and Si substrates 100 lead to an increase in total loss. In this embodiment, the semiconductor material used for the fins 200, i.e., the barrier layer, has extremely low dielectric loss, and the capacitor of the fin-type vertical stacked structure reduces the contact area with the substrate 100, thereby reducing the loss of the Josephson junction.

[0039] In traditional Josephson junctions, the barrier layer, made of alumina, is only 1.9 nm to 2.1 nm thick. Even a small change in the thickness of this barrier layer can cause an exponential change in the critical current of the Josephson junction, leading to a significant dispersion in the frequency of the qubits and increasing the difficulty of integrating the Josephson junction into circuits. In this embodiment, a fin 200 formed by etching the semiconductor substrate 100 serves as the barrier layer, allowing the thickness of the barrier layer to be controlled within 12 nm to 15 nm. Under the same process precision, with a thicker barrier layer in the Josephson junction, small changes in the barrier layer thickness have a relatively lower impact on device performance.

[0040] In addition, the present invention also proposes a semiconductor device including the Josephson junction described above.

[0041] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A Josephson knot, characterized in that, include: A semiconductor substrate having two adjacent grooves and a fin located between the two adjacent grooves, the two adjacent grooves being spaced apart by the fin; The first metal electrode and the second metal electrode are respectively filled in two adjacent grooves, and the first metal electrode, the second metal electrode, and the fin between the two adjacent grooves form a fin-type vertical stacking structure.

2. The Josephson knot as described in claim 1, characterized in that, The semiconductor substrate is made of single-crystal silicon.

3. The Josephson knot as described in claim 1, characterized in that, The semiconductor substrate is made of a Si and Ge composite layer or a Si and AlN composite layer.

4. The Josephson knot as described in claim 2 or 3, characterized in that, The material of the first metal electrode is Al; The material of the second metal electrode is AL.

5. The Josephson knot as described in claim 1, characterized in that, In the fin-type vertical stacked structure, the thickness of the fin between the first metal electrode and the second metal electrode is 12nm-15nm.

6. The Josephson knot as described in claim 1, characterized in that, The semiconductor substrate is a P-type semiconductor substrate.

7. A semiconductor device, characterized in that, The Josephson knot as described in any one of claims 1-6.

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