A silicon wafer etching circuit

Abstract

The utility model relates to a kind of silicon wafer detection equipment, especially a kind of silicon wafer etching circuit, comprising: first working electrode, for abutting on silicon wafer;Second working electrode, for abutting on silicon wafer;High voltage circuit, respectively with the first working electrode and the second working electrode opposite arrangement;And switching circuit, with the first working electrode and the second working electrode connection, and respectively with the high voltage circuit and measurement circuit opposite arrangement, for making the first working electrode and the second working electrode simultaneously with the high voltage circuit or the measurement circuit conduction.The utility model provides a kind of silicon wafer etching circuit adopts two working electrodes, when contact is bad, to the two working electrodes between instantaneous high voltage is applied, to the surface of semiconductor silicon wafer forms ablation point, reduces the ohmic contact resistance of working electrode and semiconductor silicon wafer, avoids to etching and CV measurement to cause influence, reduces use cost, improves production efficiency.

Description

Technical Field

[0001] This utility model relates to a silicon wafer inspection device, and more particularly to a silicon wafer etching circuit. Background Technology

[0002] ECV (Electrochemical Capacitance-Voltage) is a semiconductor-specific testing instrument. It uses an electrolyte to form a potential barrier and applies bias voltage (p-type) and light to the semiconductor (n-type requires both bias voltage and light) to etch the semiconductor surface. The etching depth can be obtained by integrating the etching current. After reaching the etching depth, a DC voltage is superimposed with a small-signal AC voltage to measure the CV (capacitance voltage method). The carrier concentration at the corresponding depth is obtained according to the Mott-Schottky equation. The "etch-measurement" cycle is repeated automatically to obtain the concentration-depth curve.

[0003] When performing etching and CV measurements in ECV testing, a single working electrode is typically used in electrochemical testing. However, excessive contact resistance between the working electrode and the semiconductor silicon wafer can negatively impact accurate etching and CV measurements. Utility Model Content

[0004] To solve the above problems, this utility model provides a silicon wafer etching circuit, the specific technical solution of which is as follows: A silicon wafer etching circuit includes: a first working electrode for contacting a silicon wafer; a second working electrode for contacting a silicon wafer; a high-voltage circuit disposed opposite to the first working electrode and the second working electrode; and a switching circuit connected to the first working electrode and the second working electrode, and disposed opposite to the high-voltage circuit and the measurement circuit, for simultaneously enabling the first working electrode and the second working electrode to be connected to the high-voltage circuit or the measurement circuit.

[0005] Preferably, the following components are included: a high-voltage input terminal HV; a high-voltage ground HV_GND; a capacitor C1, the positive and negative terminals of which are connected to the high-voltage input terminal HV and the high-voltage ground HV_GND, respectively; a resistor R1, which is connected to the capacitor C1 and the high-voltage input terminal HV; a relay K1, which is connected to the second working electrode, the negative terminal of the capacitor C1, and the measurement circuit; and a relay K2, which is connected to the first working electrode, the positive terminal of the capacitor C1, and the measurement circuit, respectively.

[0006] Furthermore, the switching circuit includes a relay controller SW1, which is connected to the relay K1 and the relay K2 respectively.

[0007] Furthermore, it also includes a charging and discharging circuit, which is connected to the high-voltage input terminal HV and the resistor R1, respectively.

[0008] Furthermore, the charging and discharging circuit includes: a relay K3, which is connected to the resistor R1 and the high-voltage input terminal HV respectively; and a relay controller SW2, which is connected to the relay K3.

[0009] Furthermore, the capacitor C1 is a high-voltage capacitor.

[0010] Furthermore, the high voltage at the high voltage input terminal HV is a DC voltage greater than 40V.

[0011] Compared with the prior art, the present invention has the following beneficial effects: The silicon wafer etching circuit provided by this utility model uses two working electrodes. When there is poor contact, a momentary high voltage is applied between the two working electrodes to form an ablation point on the surface of the semiconductor silicon wafer. This reduces the ohmic contact resistance between the working electrodes and the semiconductor silicon wafer, avoids affecting etching and CV measurement, reduces the cost of use, and improves production efficiency.

[0012] In addition, it also solves the problem of slow detection efficiency caused by coating the working electrode contact point with liquid metal in the existing technology. Attached Figure Description

[0013] Figure 1 This is a circuit schematic diagram of Embodiment 1 of this application; Figure 2 This is a circuit schematic diagram of Embodiment 2 of this application. Detailed Implementation

[0014] The present invention will now be further described with reference to the accompanying drawings.

[0015] Example 1 like Figure 1 As shown, a silicon wafer etching circuit includes a first working electrode, a second working electrode, a high-voltage circuit, and a switching circuit. The first and second working electrodes are both abutted against the silicon wafer. The high-voltage circuit is respectively disposed opposite to the first and second working electrodes. The switching circuit is connected to the first and second working electrodes and is respectively disposed opposite to the high-voltage circuit and the measurement circuit, for enabling the first and second working electrodes to be simultaneously connected to the high-voltage circuit or the measurement circuit.

[0016] Specifically, the high-voltage circuit includes a high-voltage input terminal HV, a high-voltage ground HV_GND, a capacitor C1, a resistor R1, a relay K1, and a relay K2; the positive and negative terminals of the capacitor C1 are connected to the high-voltage input terminal HV and the high-voltage ground HV_GND, respectively; the resistor R1 is connected to the capacitor C1 and the high-voltage input terminal HV; the relay K1 is connected to the second working electrode, the negative terminal of the capacitor C1, and the second measuring terminal of the measuring circuit; the relay K2 is connected to the first working electrode, the positive terminal of the capacitor C1, and the first measuring terminal of the measuring circuit.

[0017] The switching circuit includes a relay controller SW1, which is connected to the relay K1 and the relay K2 respectively.

[0018] Capacitor C1 is a high-voltage capacitor, and resistor R1 is a charging current-limiting resistor.

[0019] The measurement circuit uses relays to isolate it from the high-voltage circuit.

[0020] The high voltage at the high voltage input terminal HV is a DC voltage greater than 40V.

[0021] When power is applied, both relays K1 and K2 are in the off state, and there is no voltage on capacitor C1.

[0022] The etching process is as follows: Step 1: The measurement circuit is cut off from the first and second measurement terminals via relays K1 and K2. Voltage is applied between the normally closed contacts of relays K1 and K2 and between the first and second working electrodes and the two contact points on the silicon wafer. The voltage and current are recorded. The voltage is applied multiple times at different values, and the resulting IV curves are linearly fitted to obtain the ohmic resistance R. If the resistance R is greater than the required value (e.g., 1K), proceed to the next step.

[0023] Step 2: Relays K1 and K2 are closed, and high voltage is applied between the two contact points of the silicon wafer through the two working electrodes.

[0024] Step 3: Relays K1 and K2 are turned off, and the two working electrodes are connected to the measuring terminals. The etching apparatus applies voltage from the first and second measuring terminals through the normally closed contacts of relays K1 and K2, and between the first and second working electrodes, to the two contact points of the silicon wafer, recording the voltage and current. The voltage is applied multiple times at different values, and the resulting IV curves are linearly fitted to obtain the ohmic resistance R. If the obtained ohmic resistance R is less than or equal to the required value, the ablation process ends. If it is greater than the specified upper limit (e.g., 1K), steps 2 and 3 are repeated multiple times. If it is less than the specified value, the ablation step is complete.

[0025] Example 2 like Figure 2 As shown, based on Embodiment 1, the silicon wafer etching circuit further includes a charge / discharge circuit. The charge / discharge circuit is connected to the high-voltage input terminal HV and the resistor R1, respectively. Specifically, the charge / discharge circuit includes a relay K3 and a relay controller SW2. The relay K3 is connected to the resistor R1 and the high-voltage input terminal HV, respectively; the relay controller SW2 is connected to the relay K3.

[0026] The etching process is as follows: Step 1: The measuring circuit applies voltage to the two contact points of the silicon wafer through the normally closed contacts of relays K1 and K2, as well as the first and second working electrodes, from the first and second measuring terminals, and records the voltage and current. The voltage is applied multiple times at different values, and the resulting IV curves are used to obtain the ohmic resistance R by linear fitting of the IV curves. If the resistance R is greater than the required value (e.g., 1K), proceed to the next step.

[0027] Step 2: Relay K3 closes, charging capacitor C1 to high voltage.

[0028] Step 3: Relay K3 is turned off, and relays K1 and K2 are closed, applying high voltage between the two contact points of the silicon wafer through the two working electrodes.

[0029] Step 4: Relays K1, K2, and K3 are all off, and the two working electrodes are connected to the measuring terminals. The etching apparatus applies voltage from the first and second measuring terminals through the normally closed contacts of relays K1 and K2, and through the first and second working electrodes, to the two contact points of the silicon wafer, recording the voltage and current. The voltage is applied multiple times at different values, and the resulting IV curves are linearly fitted to obtain the ohmic resistance R. If the obtained ohmic resistance R is less than or equal to the required value, the ablation process ends. If it is greater than the specified upper limit (e.g., 1K), steps 2 and 3 are repeated multiple times. If it is less than the specified value, the ablation step is complete.

[0030] The technical principles of this utility model have been described above with reference to specific embodiments. These descriptions are merely for explaining the principles of this utility model and should not be construed as limiting the scope of protection of this utility model in any way. Based on this explanation, those skilled in the art can readily conceive of other specific embodiments of this utility model without inventive effort, and these embodiments will all fall within the protection scope of the claims of this utility model.

Claims

1. A silicon wafer etching circuit, characterized in that, include: The first working electrode is used to press against the silicon wafer; The second working electrode is used to press against the silicon wafer; A high-voltage circuit is respectively positioned opposite to the first working electrode and the second working electrode; as well as A switching circuit is connected to the first working electrode and the second working electrode, and is respectively disposed opposite to the high-voltage circuit and the measuring circuit, for enabling the first working electrode and the second working electrode to be simultaneously connected to the high-voltage circuit or the measuring circuit.

2. The silicon wafer etching circuit according to claim 1, characterized in that, The high-voltage circuit includes: High voltage input terminal HV; High voltage ground HV_GND; Capacitor C1, the positive and negative terminals of which are connected to the high voltage input terminal HV and the high voltage ground HV_GND, respectively; Resistor R1 is connected to capacitor C1 and high voltage input terminal HV respectively; Relay K1 is connected to the second working electrode, the negative terminal of capacitor C1, and the measuring circuit, respectively; and Relay K2 is connected to the first working electrode, the positive terminal of capacitor C1, and the measurement circuit, respectively.

3. The silicon wafer etching circuit according to claim 2, characterized in that, The switching circuit includes a relay controller SW1, which is connected to the relay K1 and the relay K2 respectively.

4. A silicon wafer etching circuit according to claim 2, characterized in that, Also includes: The charging and discharging circuits are connected to the high-voltage input terminal HV and the resistor R1, respectively.

5. A silicon wafer etching circuit according to claim 4, characterized in that, The charge / discharge circuit includes: Relay K3, which is connected to both resistor R1 and the high-voltage input terminal HV; and Relay controller SW2 is connected to relay K3.

6. A silicon wafer etching circuit according to claim 2, characterized in that, The capacitor C1 is a high-voltage capacitor.

7. A silicon wafer etching circuit according to claim 2, characterized in that, The high voltage at the high voltage input terminal HV is a DC voltage greater than 40V.

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