Packaging structure, circuit board assembly, and electronic device

Abstract

The present disclosure relates to a packaging structure, a circuit board assembly and an electronic device. The packaging structure comprises a packaging substrate, a first chip, a second chip and a heat dissipation member. The first chip is arranged on the packaging substrate and electrically connected with the packaging substrate. The second chip is arranged above the first chip and electrically connected with the first chip and the packaging substrate. At least part of the projection of the second chip on the packaging substrate is within the projection range of the first chip on the packaging substrate. The heat dissipation member is arranged on the first chip, and the projection of the heat dissipation member on the packaging substrate is within the projection range of the first chip on the packaging substrate. The packaging structure simultaneously realizes the stacked packaging of the first chip and the second chip and the heat dissipation of the first chip, ensures that the packaging structure can simultaneously consider high integration and good heat dissipation capacity, and improves the overall performance of the packaging structure.

Description

Technical Field

[0001] This disclosure relates to the field of packaging, specifically a packaging structure, circuit board assembly, and electronic device. Background Technology

[0002] In recent years, with the rapid development of packaging technology and the continuous iteration of semiconductor devices, the performance requirements for packaging structures have been increasing. Integration density and heat dissipation capability, as important evaluation indicators of packaging structures, have gradually become key factors affecting the performance, product yield, and lifespan of packaging structures. Utility Model Content

[0003] To overcome the problems existing in the related technologies, this disclosure provides a packaging structure, a circuit board assembly, and an electronic device.

[0004] According to a first aspect of the present disclosure, a packaging structure is provided, characterized in that the packaging structure includes: Packaging substrate; A first chip is disposed on the packaging substrate and is electrically connected to the packaging substrate. The second chip is disposed above the first chip and is electrically connected to both the first chip and the packaging substrate. At least a portion of the projection of the second chip onto the packaging substrate is located within the projection range of the first chip onto the packaging substrate. A heat sink is disposed on the first chip, and the projection of the heat sink on the packaging substrate is located within the projection range of the first chip on the packaging substrate.

[0005] In this embodiment, a first chip is disposed on a packaging substrate, and a second chip is disposed above the first chip, such that at least a portion of the projection of the second chip on the packaging substrate overlaps with the projection of the first chip on the packaging substrate, thereby achieving stacked packaging of the first chip and the second chip. This saves the overall space occupied by the first chip and the second chip in the horizontal direction. A heat sink is disposed on the first chip, and the projection of the heat sink on the packaging substrate is located within the projection range of the first chip on the packaging substrate, thereby achieving heat dissipation of the first chip. This ensures that the packaging structure can simultaneously achieve high integration and good heat dissipation capabilities, thereby improving the overall performance of the packaging structure.

[0006] In some embodiments of this disclosure, the projection of the second chip on the packaging substrate is located within the projection range of the first chip on the packaging substrate; A first electrical connector is provided between the first chip and the second chip. The first electrical connector is used to support the second chip and electrically connect the first chip and the second chip.

[0007] In this embodiment, the projection of the second chip on the packaging substrate is configured to fall within the projection range of the first chip on the packaging substrate, which maximizes the use of horizontal space and further improves the integration of the packaging structure. By setting a first electrical connector between the first chip and the second chip, the stacking and electrical connection between the first chip and the second chip can be achieved using the first electrical connector, ensuring the reliability of the packaging structure and signal interaction, and improving the overall performance of the packaging structure.

[0008] In some embodiments of this disclosure, a portion of the projection of the second chip onto the packaging substrate is located within the projection range of the first chip onto the packaging substrate; A second electrical connector is provided between the first chip and the second chip. The second electrical connector is used to support the second chip and electrically connect the first chip and the second chip. A third electrical connector is provided between the second chip and the packaging substrate. The third electrical connector is used to support the second chip and electrically connect the second chip and the packaging substrate.

[0009] In this embodiment, the projection of the second chip onto the packaging substrate is configured to fall within the projection range of the first chip onto the packaging substrate. This reduces the area of ​​the second chip covering the first chip while still allowing the second chip to be stacked with the first chip. This facilitates further improvement in the heat dissipation capacity of the first chip by increasing the coverage area of ​​the heat sink. By providing a second electrical connector between the first and second chips, and a third electrical connector between them, electrical connections can be established between the second chip and the first chip and the packaging substrate, respectively. The second and third electrical connectors also work together to provide fixed support for the second chip, ensuring the reliability of the packaging structure and signal interaction, and improving the overall performance of the packaging structure.

[0010] In some embodiments of this disclosure, a passive device is further disposed between the second chip and the packaging substrate, and the third electrical connector passes through the passive device.

[0011] In this embodiment, by setting a passive device between the second chip and the packaging substrate, and allowing the third electrical connector to pass through the passive device, the space between the second chip and the packaging substrate is fully utilized while ensuring the electrical connection between the second chip and the packaging substrate. This is beneficial to further improve the integration of the packaging structure and the support stability of the second chip, thereby improving the overall performance of the packaging structure.

[0012] In some embodiments of this disclosure, the first chip includes a system-on-a-chip, and the second chip includes at least one of a central processing unit chip, a graphics processing unit chip, and a memory chip.

[0013] In this embodiment, a system-on-a-chip (SoC) is used as the first chip, and at least one of the central processing unit (CPU) chip, graphics processing unit (GPU) chip, and memory chip is used as the second chip. This achieves the integration of at least one of the CPU chip, GPU chip, and memory chip with the SoC, and ensures that the larger chip size of the SoC and the higher signal interaction stability requirements of the SoC can be matched with the first chip. This further improves the rationality of the packaging structure and is conducive to more stable and efficient functional implementation of the first and second chips.

[0014] In some embodiments of this disclosure, a connection layer is provided between the heat sink and the first chip.

[0015] In this embodiment, by providing a connection layer between the heat sink and the first chip, the heat sink and the first chip can be fixed through the connection layer, and the heat generated by the first chip can be conducted to the heat sink. This helps to improve the structural stability and heat dissipation effect of the heat sink, thereby improving the overall performance of the packaging structure.

[0016] In some embodiments of this disclosure, a redistribution layer is provided in the packaging substrate, and the redistribution layer is electrically connected to both the first chip and the second chip. A fourth electrical connector is provided on the bottom surface of the packaging substrate, and the fourth electrical connector is electrically connected to the redistribution layer.

[0017] In this embodiment, a redistribution layer is provided in the packaging substrate, and the redistribution layer is electrically connected to both the first chip and the second chip. A fourth electrical connector is provided on the bottom surface of the packaging substrate, and the fourth electrical connector is electrically connected to the redistribution layer. Signal interaction between the inside and outside of the packaging structure can be realized through the redistribution layer and the fourth electrical connector. Furthermore, by planning and designing the routing of the redistribution layer, the routing rationality of the redistribution layer can be improved, thereby optimizing signal integrity, electromagnetic compatibility, and thermal management efficiency, which is beneficial to further improving the overall performance of the semiconductor structure.

[0018] In some embodiments of this disclosure, a fifth electrical connector is provided between the first chip and the packaging substrate, and the fifth electrical connector electrically connects the first chip and the packaging substrate.

[0019] In this embodiment, a fifth electrical connector is provided between the first chip and the packaging substrate, and the fifth electrical connector is electrically connected to the first chip and the packaging substrate. The fifth electrical connector enables signal interaction between the inside and outside of the packaging structure, which helps to improve the stability of signal interaction between the first chip and the packaging substrate.

[0020] In some embodiments of this disclosure, an underfill material is further provided between the first chip and the packaging substrate, the underfill material filling the gap between the first chip and the packaging substrate.

[0021] In this embodiment, a bottom filler is provided between the first chip and the packaging substrate, which can ensure the connection strength between the first chip and the packaging substrate and achieve isolation protection for the fifth electrical connector, which is beneficial to further improve the reliability of the packaging structure.

[0022] In some embodiments of this disclosure, the packaging structure further includes an encapsulating material for encapsulating the first chip, the second chip, and the heat sink on the packaging substrate.

[0023] In this embodiment, the first chip, the second chip, and the heat sink are encapsulated on the packaging substrate using encapsulating material, thereby achieving overall encapsulation of the packaging structure. The encapsulating material is used to fix and protect the first chip and the second chip, which helps to improve the integrity and reliability of the packaging structure.

[0024] In some embodiments of this disclosure, the top surface of the encapsulant is flush with the top surface of the heat sink and / or the top surface of the second chip.

[0025] In this embodiment, the top surface of the encapsulant is configured to be flush with the top surface of at least one of the heat sink and the second chip, which helps to further improve the heat dissipation effect of the encapsulation structure and further improve the reliability of the encapsulation structure, thus ensuring the overall performance of the encapsulation structure.

[0026] In some embodiments of this disclosure, the top surface of the encapsulant is higher than the top surface of the heat sink and / or the top surface of the second chip.

[0027] In this embodiment, the top surface of the encapsulant is configured to be higher than the top surface of at least one of the heat sink and the second chip, which helps to further improve the isolation and protection effect of the encapsulation structure, thereby increasing the service life of the encapsulation structure and ensuring the overall performance of the encapsulation structure.

[0028] According to a second aspect of the present disclosure, a circuit board assembly is provided, the circuit board assembly including the packaging structure as described in the first aspect, the circuit board assembly further including a circuit board, the packaging structure being disposed on the circuit board, and the circuit board being electrically connected to a fourth electrical connector of the packaging structure.

[0029] According to a third aspect of the present disclosure, an electronic device is provided, the electronic device including the packaging structure as described in the first aspect, or the electronic device including the circuit board assembly as described in the second aspect.

[0030] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: a first chip is disposed on a packaging substrate, a second chip is disposed above the first chip, and at least a portion of the projection of the second chip on the packaging substrate overlaps with the projection of the first chip on the packaging substrate, thereby realizing the stacked packaging of the first chip and the second chip, saving the overall space occupied by the first chip and the second chip in the horizontal direction; a heat sink is disposed on the first chip, and the projection of the heat sink on the packaging substrate is located within the projection range of the first chip on the packaging substrate, thereby realizing heat dissipation of the first chip, ensuring that the packaging structure can simultaneously take into account high integration and good heat dissipation capacity, and improving the overall performance of the packaging structure.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0033] Figure 1 This is a schematic diagram of a packaging structure.

[0034] Figure 2 This is a schematic diagram of another packaging structure.

[0035] Figure 3 This is a schematic diagram of the packaging structure according to an exemplary embodiment.

[0036] Figure 4 This is a schematic diagram of the structure of a circuit board assembly according to an exemplary embodiment.

[0037] Figure 5 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0038] Figure 6 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0039] Figure 7 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0040] Figure 8 This is a schematic diagram of the packaging structure according to another exemplary embodiment.

[0041] In the picture: 10-Packaging substrate; 11-Rewiring layer; 20-First chip; 30-Second chip; 40-Heat sink; 51-First electrical connector; 52-Second electrical connector; 53-Third electrical connector; 54-Fourth electrical connector; 55-Fifth electrical connector; 60-Passive device; 70-Connection layer; 80-Bottom filler; 90-Encapsulation material; 100-Circuit board; 110-Chip. Detailed Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0043] In recent years, with the rapid development of packaging technology and the continuous iteration of semiconductor devices, the performance requirements for packaging structures have become increasingly stringent. Integration density and heat dissipation capability, as important evaluation indicators of packaging structures, have gradually become key factors affecting packaging structure performance, product yield, and lifespan.

[0044] In one exemplary embodiment, a packaging structure is provided for implementing board-level packaging of multiple chips. The packaging structure may be disposed in a circuit board assembly and embedded in an electronic device such as a mobile phone, tablet computer, or smart band.

[0045] In one embodiment, such as Figure 1 As shown, multiple chips 110 can be arranged horizontally on the packaging substrate 10, such as... Figure 2 As shown, multiple chips 110 can also be stacked sequentially along the vertical direction on the packaging substrate 10 to achieve integrated packaging of multiple chips 110.

[0046] For example Figure 1 The packaging structure shown occupies a large amount of space horizontally due to the arrangement of multiple chips 110, which is not conducive to the miniaturization and high integration requirements of the packaging structure. Figure 2 The packaging structure shown, even with a heat sink placed above the top chip 110, cannot guarantee effective heat dissipation for the bottom chip 110, resulting in an excessively high temperature gradient between the chips 110 and causing thermal interference. Therefore, the aforementioned packaging structures cannot simultaneously achieve both high integration and effective heat dissipation, thus limiting the overall performance of the packaging structure.

[0047] In another embodiment, reference Figure 3As shown, the packaging structure includes a packaging substrate 10, a first chip 20, a second chip 30, and a heat sink 40. The first chip 20 is disposed on the packaging substrate 10 and is electrically connected to the packaging substrate 10. The second chip 30 is disposed above the first chip 20 and is electrically connected to both the first chip 20 and the packaging substrate 10. At least a portion of the projection of the second chip 30 onto the packaging substrate 10 lies within the projection range of the first chip 20 onto the packaging substrate 10. The heat sink 40 is disposed on the first chip 20, and its projection onto the packaging substrate 10 lies within the projection range of the first chip 20 onto the packaging substrate 10.

[0048] The packaging substrate 10 provides functions such as load-bearing, electrical connection, and protection for the packaging structure, and realizes the purposes of multi-input / output, overall packaging, and device modularization of the packaging structure. (Reference) Figure 4 As shown, when the packaging structure is disposed in the circuit board assembly, the packaging substrate 10 can be disposed on the circuit board 100 in the circuit board assembly and electrically connected to the circuit board 100 through electrical connectors such as bumps or ball grid arrays.

[0049] The first chip 20 is disposed on the packaging substrate 10 and electrically connected to the packaging substrate 10 to realize the internal and external transmission of electrical signals of the first chip 20. For example, the first chip 20 can be mounted on the packaging substrate 10 using a surface mount process. The first chip 20 can be electrically connected to the packaging substrate 10 using electrical connectors such as bumps or ball grid arrays, and the gap between the first chip 20 and the packaging substrate 10 is filled by an underfill material 80.

[0050] The second chip 30 is disposed above the first chip 20, and is electrically connected to both the first chip 20 and the packaging substrate 10. The second chip 30 can interact with the first chip 20 via its electrical connection, and also interact with the first chip 20 and external circuits or devices via its electrical connection to the packaging substrate 10. At least a portion of the projection of the second chip 30 onto the packaging substrate 10 lies within the projection range of the first chip 20 onto the packaging substrate 10. That is, the entire or partial structure of the second chip 30 overlaps with the first chip 20 in the horizontal direction (X-direction). This overlapping portion is the stacked portion of the first chip 20 and the second chip 30 in the vertical direction (Y-direction). This vertical stacking of the first chip 20 and the second chip 30 reduces the space occupied in the horizontal direction, allowing for a greater number of first chips 20 and second chips 30 to be placed within a limited space, thus meeting the requirements of miniaturization and high integration in the packaging structure.

[0051] For example, the second chip 30 may be a chip of a different type, function, or size than the first chip 20. The type, function, size, and quantity of the first chip 20 and the second chip 30 can be selected according to requirements. The first chip 20 and the second chip 30 may be indirectly electrically connected, for example, through electrical connectors such as bumps or ball grid arrays. The first chip 20 and the second chip 30 may also be directly electrically connected through methods such as hybrid bonding (HB). The second chip 30 and the packaging substrate 10 may be electrically connected through electrical connectors such as metal pillars.

[0052] A heat sink 40 is disposed on the first chip 20, such that the projection of the heat sink 40 on the packaging substrate 10 is within the projection range of the first chip 20 on the packaging substrate 10. That is, the entire heat sink 40 overlaps with the first chip 20 in the horizontal direction (X direction), causing a portion of the first chip 20 to be covered by at least a portion of the second chip 30 in the vertical direction (Y direction) to achieve stacking. Another portion of the first chip 20 is covered by the heat sink 40 in the vertical direction (Y direction) to achieve heat dissipation for the first chip 20, ensuring good heat dissipation for both the bottom first chip 20 and the top second chip 30. Exemplarily, the material of the heat sink 40 may include silicon, metal, or graphene, and the heat sink 40 may be in the form of a sheet, column, or block.

[0053] In this embodiment, a first chip 20 is disposed on the packaging substrate 10, and a second chip 30 is disposed above the first chip 20, such that at least a portion of the projection of the second chip 30 on the packaging substrate 10 overlaps with the projection of the first chip 20 on the packaging substrate 10, thereby achieving stacked packaging of the first chip 20 and the second chip 30, saving the overall space occupied by the first chip 20 and the second chip 30 in the horizontal direction. A heat sink 40 is disposed on the first chip 20, and the projection of the heat sink 40 on the packaging substrate 10 is located within the projection range of the first chip 20 on the packaging substrate 10, thereby achieving heat dissipation of the first chip 20, ensuring that the packaging structure can simultaneously achieve high integration and good heat dissipation capability, and improving the overall performance of the packaging structure.

[0054] In some embodiments, the projection of the second chip 30 on the packaging substrate 10 is located within the projection range of the first chip 20 on the packaging substrate 10, and a first electrical connector 51 is provided between the first chip 20 and the second chip 30. The first electrical connector 51 is used to support the second chip 30 and electrically connect the first chip 20 and the second chip 30.

[0055] refer to Figure 5As shown, the entire projection of the second chip 30 onto the packaging substrate 10 lies within the projection range of the first chip 20 onto the packaging substrate 10. That is, the overall structure of the second chip 30 overlaps with the first chip 20 in the horizontal direction, and the entire second chip 30 is stacked on top of the first chip 20. In this case, a first electrical connector 51 is provided between the first chip 20 and the second chip 30. The first electrical connector 51 supports the second chip 30 and electrically connects the first chip 20 and the second chip 30. In other words, the first electrical connector 51 simultaneously provides the functions of carrying and electrical connection for the second chip 30, enabling the stacking of the second chip 30 and the first chip 20. This allows the second chip 30 to interact with the first chip 20 via the first electrical connector 51, and also interacts with the packaging substrate 10 via the first electrical connector 51 and the first chip 20. For example, the first electrical connector 51 may include bumps or a ball grid array.

[0056] In this embodiment, the projection of the second chip 30 onto the packaging substrate 10 is configured to fall within the projection range of the first chip 20 onto the packaging substrate 10, maximizing the use of horizontal space and further improving the integration of the packaging structure. By providing a first electrical connector 51 between the first chip 20 and the second chip 30, the first electrical connector 51 can be used to achieve stacking and electrical connection between the first chip 20 and the second chip 30, ensuring the reliability of the packaging structure and signal interaction, and improving the overall performance of the packaging structure.

[0057] In other embodiments, a portion of the projection of the second chip 30 onto the packaging substrate 10 is located within the projection range of the first chip 20 onto the packaging substrate 10. A second electrical connector 52 is provided between the first chip 20 and the second chip 30. The second electrical connector 52 is used to support the second chip 30 and electrically connect the first chip 20 and the second chip 30. A third electrical connector 53 is provided between the second chip 30 and the packaging substrate 10. The third electrical connector 53 is used to support the second chip 30 and electrically connect the second chip 30 and the packaging substrate 10.

[0058] like Figure 3As shown, a portion of the projection of the second chip 30 onto the packaging substrate 10 lies within the projection range of the first chip 20 onto the packaging substrate 10. That is, a portion of the structure of the second chip 30 overlaps with the first chip 20 in the horizontal direction. A portion of the second chip 30 is stacked on the first chip 20, and another portion of the second chip 30 is located outside the first chip 20. In this case, a second electrical connector 52 is provided between the first chip 20 and the second chip 30, and a third electrical connector 53 is provided between the second chip 30 and the packaging substrate 10. The second electrical connector 52 supports the second chip 30 and electrically connects the first chip 20 and the second chip 30. Specifically, the second electrical connector 52 provides support and electrical connection for a portion of the second chip 30, enabling the stacking of a portion of the second chip 30 with the first chip 20 and allowing the second chip 30 to interact with the first chip 20 via the second electrical connector 52. The third electrical connector 53 supports the second chip 30 and electrically connects the second chip 30 and the packaging substrate 10. That is, the third electrical connector 53 provides a carrier and electrical connection for another part of the second chip 30, ensuring the overall structural stability of the second chip 30 and enabling the second chip 30 to interact with the packaging substrate 10 via the third electrical connector 53. For example, the second electrical connector 52 may include bumps or a ball grid array, and the third electrical connector 53 may include metal columnar structures such as through-silicon vias (TSVs) or through-interposer vias (TIVs).

[0059] In this embodiment, the projection of the second chip 30 onto the packaging substrate 10 is configured to fall within the projection range of the first chip 20 onto the packaging substrate 10. This reduces the coverage area of ​​the second chip 30 on the first chip 20 while still allowing the second chip 30 to be stacked with the first chip 20. This facilitates further improvement of the heat dissipation capacity of the first chip 20 by increasing the coverage area of ​​the heat sink 40 on the first chip 20. By providing a second electrical connector 52 between the first chip 20 and the second chip 30, and a third electrical connector 53 between the first chip 20 and the second chip 30, electrical connections between the second chip 30 and the first chip 20 and the packaging substrate 10 can be achieved using the second electrical connector 52 and the third electrical connector 53, respectively. The second electrical connector 52 and the third electrical connector 53 also work together to fix and support the second chip 30, ensuring the reliability of the packaging structure and signal interaction, and improving the overall performance of the packaging structure.

[0060] In some embodiments, a passive device 60 is further disposed between the second chip 30 and the packaging substrate 10, and a third electrical connector 53 passes through the passive device 60.

[0061] It is understandable that when a portion of the projection of the second chip 30 onto the packaging substrate 10 is within the projection range of the first chip 20 onto the packaging substrate 10, a portion of the second chip 30 is stacked on the first chip 20, and another portion of the second chip 30 is located outside the first chip 20, so that there is a large amount of usable space between the other portion of the second chip 30 and the packaging substrate 10, in addition to the third electrical connector 53 that needs to be provided.

[0062] like Figure 6 As shown, passive devices such as silicon wafers and capacitors can be placed between the second chip 30 and the packaging substrate 10, and the third electrical connector 53 can pass through the passive device 60 to electrically connect the second chip 30 and the packaging substrate 10. This can make full use of the space between the second chip 30 and the packaging substrate 10 to further improve the integration of the packaging structure, and the passive device 60 can provide more stable support for the second chip 30.

[0063] In this embodiment, by setting a passive device 60 between the second chip 30 and the packaging substrate 10, and making the third electrical connector 53 pass through the passive device 60, the space between the second chip 30 and the packaging substrate 10 is fully utilized while ensuring the electrical connection between the second chip 30 and the packaging substrate 10. This is beneficial to further improve the integration of the packaging structure and the support stability of the second chip 30, thereby improving the overall performance of the packaging structure.

[0064] In some embodiments, the first chip 20 includes a system-on-a-chip, and the second chip 30 includes at least one of a central processing unit chip, a graphics processing unit chip, and a memory chip.

[0065] Since at least a portion of the second chip 30 and the heat sink 40 need to cover the first chip 20, and the first chip 20 is closer to the packaging substrate 10 than the second chip 30, the first chip 20 typically has a larger chip size and a shorter signal interaction path between itself and the packaging substrate 10. Therefore, a system-on-chip (SOC) can be used as the first chip 20, and at least one of a central processing unit (CPU), a graphics processing unit (GPU), and a dynamic random access memory (DRAM) can be used as the second chip 30. This allows the larger chip size of the SOC and the higher signal interaction stability requirements of the SOC to match the first chip 20, ensuring the rationality of the chip placement while achieving multi-functional chip integration.

[0066] In this embodiment, a system-on-a-chip (SoC) is used as the first chip 20, and at least one of the central processing unit (CPU) chip, graphics processing unit (GPU) chip, and memory chip is used as the second chip 30. This achieves the integration of at least one of the CPU chip, GPU chip, and memory chip with the SoC, and ensures that the large chip size of the SoC and the high signal interaction stability requirements of the SoC can be matched with the first chip 20. This further improves the rationality of the packaging structure and is conducive to the more stable and efficient functional implementation of the first chip 20 and the second chip 30.

[0067] In some embodiments, a connection layer 70 is provided between the heat sink 40 and the first chip 20.

[0068] like Figure 3 As shown, a connection layer 70 is provided between the heat sink 40 and the first chip 20. The connection layer 70 can achieve a tight bond between the first chip 20 and the heat sink 40 through its good flexibility and interface adaptability, and conducts the heat generated by the first chip 20 to the heat sink 40 through its good thermal conductivity, thereby improving the structural stability and heat dissipation effect of the heat sink 40. For example, the connection layer 70 may include a die-attach film (DAF), graphene, thermal interface materials (TIM), conductive silver paste, or solder paste, etc.

[0069] In this embodiment, by providing a connection layer 70 between the heat sink 40 and the first chip 20, the heat sink 40 and the first chip 20 can be fixed through the connection layer 70, and the heat generated by the first chip 20 can be conducted to the heat sink 40, which is beneficial to improving the structural stability and heat dissipation effect of the heat sink 40, thereby improving the overall performance of the packaging structure.

[0070] In some embodiments, a redistribution layer 11 is provided in the packaging substrate 10, and the redistribution layer 11 is electrically connected to both the first chip 20 and the second chip 30. A fourth electrical connector 54 is provided on the bottom surface of the packaging substrate 10, and the fourth electrical connector 54 is electrically connected to the redistribution layer 11.

[0071] like Figure 3 and Figure 4 As shown, a redistribution layer (RDL) 11 can be provided in the packaging substrate 10. The redistribution layer 11 is electrically connected to both the first chip 20 and the second chip 30, enabling the first chip 20 and the second chip 30 to interact with the packaging substrate 10 or the circuit board 100 through the redistribution layer 11. By planning and designing the redistribution layer 11, effects such as reducing crosstalk and noise coupling, shortening the critical path length, and controlling impedance continuity can be achieved.

[0072] A fourth electrical connector 54 is provided on the bottom surface of the packaging substrate 10, and the fourth electrical connector 54 is electrically connected to the redistribution layer 11, providing an interface for the electrical connection between the packaging structure and external devices or external circuits. This allows the first chip 20 and the second chip 30 to interact with external devices or external circuits through the electrical connection path of the redistribution layer 11 and the fourth electrical connector 54. For example, when the packaging structure is disposed in a circuit board assembly, the circuit board 100 of the circuit board assembly can be electrically connected to the redistribution layer 11 through the fourth electrical connector 54 to meet the electrical interconnection requirements of the circuit board assembly.

[0073] In this embodiment, a redistribution layer 11 is provided in the packaging substrate 10, and the redistribution layer 11 is electrically connected to both the first chip 20 and the second chip 30. A fourth electrical connector 54 is provided on the bottom surface of the packaging substrate 10, and the fourth electrical connector 54 is electrically connected to the redistribution layer 11. Signal interaction between the inside and outside of the packaging structure can be realized through the redistribution layer 11 and the fourth electrical connector 54. Furthermore, by planning and designing the routing of the redistribution layer 11, the routing rationality of the redistribution layer 11 can be improved, thereby optimizing signal integrity, electromagnetic compatibility, and thermal management efficiency, which is beneficial to further improving the overall performance of the semiconductor structure.

[0074] In some embodiments, the first chip 20 is mounted on the packaging substrate 10 using a hybrid bonding process and is directly electrically connected to the packaging substrate 10.

[0075] In some other embodiments, a fifth electrical connector 55 is provided between the first chip 20 and the packaging substrate 10, and the fifth electrical connector 55 is electrically connected to the first chip 20 and the packaging substrate 10.

[0076] like Figure 3 As shown, a fifth electrical connector 55 can be provided between the first chip 20 and the packaging substrate 10 to achieve electrical connection between the first chip 20 and the packaging substrate 10, thereby ensuring signal interaction between the first chip 20 and the packaging substrate 10, as well as with external circuits or external devices outside the packaging structure. For example, the active surface of the first chip 20 is disposed opposite to the packaging substrate 10, and the fifth electrical connector 55 can be disposed on the active surface of the first chip 20. The fifth electrical connector 55 includes bumps or a ball grid array, one end of the fifth electrical connector 55 is electrically connected to the first chip 20, and the other end of the fifth electrical connector 55 is electrically connected to the redistribution layer 11 of the packaging substrate 10.

[0077] In this embodiment, a fifth electrical connector 55 is provided between the first chip 20 and the packaging substrate 10, and the fifth electrical connector 55 is electrically connected to the first chip 20 and the packaging substrate 10. The fifth electrical connector 55 enables signal interaction between the inside and outside of the packaging structure, which is beneficial to improving the stability of signal interaction between the first chip 20 and the packaging substrate 10.

[0078] In some embodiments, a bottom filler 80 is further provided between the first chip 20 and the packaging substrate 10, and the bottom filler 80 fills the gap between the first chip 20 and the packaging substrate 10.

[0079] like Figure 3 As shown, when a fifth electrical connector 55 is provided between the first chip 20 and the packaging substrate 10, a bottom filler 80 can be provided between the first chip 20 and the packaging substrate 10 to fill the gap formed between the first chip 20 and the packaging substrate 10.

[0080] In this embodiment, a bottom filler 80 is provided between the first chip 20 and the packaging substrate 10, which can ensure the connection strength between the first chip 20 and the packaging substrate 10 and realize the isolation protection of the fifth electrical connector 55, which is conducive to further improving the reliability of the packaging structure.

[0081] In some embodiments, the packaging structure further includes a packaging material 90, which is used to encapsulate the first chip 20, the second chip 30 and the heat sink 40 on the packaging substrate 10.

[0082] The packaging structure also includes a packaging material 90, which can fill the gaps between the first chip 20, the second chip 30, the heat sink 40 and the packaging substrate 10, so as to encapsulate the first chip 20, the second chip 30 and the heat sink 40 on the packaging substrate 10, thereby fixing and protecting the first chip 20 and the second chip 30, and ensuring the integrity and reliability of the packaging structure.

[0083] In this embodiment, the first chip 20, the second chip 30, and the heat sink 40 are encapsulated on the packaging substrate 10 by the encapsulation material 90, thereby realizing the overall encapsulation of the packaging structure. The encapsulation material 90 is used to fix and protect the first chip 20 and the second chip 30, which helps to improve the integrity and reliability of the packaging structure.

[0084] In some embodiments, the top surface of the encapsulant 90 is flush with the top surface of the heat sink 40, or the top surface of the encapsulant 90 is flush with the top surface of the second chip 30, or the top surface of the encapsulant 90 is flush with the top surface of the heat sink 40 and the top surface of the second chip 30.

[0085] The top surface of the encapsulant 90 can be configured to be flush with the top surface of the heat sink 40, exposing the top surface of the heat sink 40. This improves the heat dissipation effect of the heat sink 40 and ensures the overall height consistency of the encapsulation structure, thus enhancing its reliability. Alternatively, the top surface of the encapsulant 90 can be configured to be flush with the top surface of the second chip 30, exposing the top surface of the second chip 30. This also improves the heat dissipation effect of the second chip 30, ensures the overall height consistency of the encapsulation structure, and enhances its reliability. For example, as... Figure 3 As shown, the top surface of the encapsulation material 90 can be flush with the top surface of the heat sink 40 and also flush with the top surface of the second chip 30, as... Figure 7 As shown, the top surface of the encapsulant 90 can be flush with the top surface of the heat sink 40 and higher than the top surface of the second chip 30.

[0086] In this embodiment, the top surface of the encapsulation material 90 is configured to be flush with the top surface of at least one of the heat sink 40 and the second chip 30, which is beneficial to further improve the heat dissipation effect of the encapsulation structure and further improve the reliability of the encapsulation structure, thus ensuring the overall performance of the encapsulation structure.

[0087] In other embodiments, the top surface of the encapsulant 90 is higher than the top surface of the heat sink 40, or the top surface of the encapsulant 90 is higher than the top surface of the second chip 30, or the top surface of the encapsulant 90 is higher than the top surface of the heat sink 40 and the top surface of the second chip 30.

[0088] The top surface of the encapsulant 90 can be configured to be higher than the top surface of the heat sink 40, so that the encapsulant 90 completely encapsulates the heat sink 40. This further enhances the isolation and protection effect of the heat sink 40, preventing damage to the heat sink 40 during subsequent transfer, storage, and use. The good thermal conductivity of the encapsulant 90 itself also ensures the heat dissipation effect of the heat sink 40. Alternatively, the top surface of the encapsulant 90 can be configured to be higher than the top surface of the second chip 30, so that the encapsulant 90 completely encapsulates the heat sink 40. This further enhances the isolation and protection effect of the second chip 30, preventing damage to the second chip 30 during subsequent transfer, storage, and use. The good thermal conductivity of the encapsulant 90 itself also ensures the heat dissipation effect of the second chip 30. For example, as... Figure 7 As shown, the top surface of the encapsulation material 90 can be flush with the top surface of the heat sink 40 and higher than the top surface of the second chip 30, as... Figure 8 As shown, the top surface of the encapsulant 90 can be higher than the top surface of the heat sink 40 and higher than the top surface of the second chip 30.

[0089] In this embodiment, the top surface of the encapsulation material 90 is configured to be higher than the top surface of at least one of the heat sink 40 and the second chip 30, which helps to further improve the isolation and protection effect of the encapsulation structure, thereby increasing the service life of the encapsulation structure and ensuring the overall performance of the encapsulation structure.

[0090] In one exemplary embodiment, a circuit board assembly is provided, the circuit board assembly including the packaging structure as described above, the circuit board assembly further including a circuit board 100, the packaging structure being disposed on the circuit board 100, and the circuit board 100 being electrically connected to a fourth electrical connector 54 of the packaging structure.

[0091] like Figure 4 As shown, the circuit board assembly includes a circuit board 100 and the packaging structure shown in the above embodiments. The packaging structure is disposed on the circuit board 100. The circuit board 100 can provide support for the packaging structure and is electrically connected to the packaging substrate 10 of the packaging structure through the fourth electrical connector 54 of the packaging structure to meet the electrical interconnection requirements of the circuit board assembly.

[0092] In this embodiment, the circuit board assembly has the same advantages because its packaging structure has the advantages of both integration and heat dissipation.

[0093] In one exemplary embodiment, an electronic device is provided, which includes at least one of the packaging structure and circuit board assembly as described above. The electronic device may be, for example, a mobile phone, a tablet computer, a wristband, etc.

[0094] In this embodiment, since the packaging structure and circuit board assembly of the electronic device have the advantages of both integration and heat dissipation, the electronic device has the same advantages.

[0095] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered illustrative only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0096] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: Packaging substrate; A first chip is disposed on the packaging substrate and is electrically connected to the packaging substrate. The second chip is disposed above the first chip and is electrically connected to both the first chip and the packaging substrate. At least a portion of the projection of the second chip onto the packaging substrate is located within the projection range of the first chip onto the packaging substrate. A heat sink is disposed on the first chip, and the projection of the heat sink on the packaging substrate is located within the projection range of the first chip on the packaging substrate.

2. The packaging structure according to claim 1, characterized in that, The projection of the second chip on the packaging substrate is within the projection range of the first chip on the packaging substrate; A first electrical connector is provided between the first chip and the second chip. The first electrical connector is used to support the second chip and electrically connect the first chip and the second chip.

3. The packaging structure according to claim 1, characterized in that, The projection of the second chip onto the packaging substrate is located within the projection range of the first chip onto the packaging substrate; A second electrical connector is provided between the first chip and the second chip. The second electrical connector is used to support the second chip and electrically connect the first chip and the second chip. A third electrical connector is provided between the second chip and the packaging substrate. The third electrical connector is used to support the second chip and electrically connect the second chip and the packaging substrate.

4. The packaging structure according to claim 3, characterized in that, A passive device is also disposed between the second chip and the packaging substrate, and the third electrical connector passes through the passive device.

5. The packaging structure according to claim 1, characterized in that, The first chip includes a system-on-a-chip, and the second chip includes at least one of a central processing unit chip, a graphics processing unit chip, and a memory chip.

6. The packaging structure according to any one of claims 1 to 5, characterized in that, A connection layer is provided between the heat sink and the first chip.

7. The packaging structure according to any one of claims 1 to 5, characterized in that, The packaging substrate is provided with a redistribution layer, which is electrically connected to both the first chip and the second chip. A fourth electrical connector is provided on the bottom surface of the packaging substrate, and the fourth electrical connector is electrically connected to the redistribution layer.

8. The packaging structure according to any one of claims 1 to 5, characterized in that, A fifth electrical connector is provided between the first chip and the packaging substrate, and the fifth electrical connector electrically connects the first chip and the packaging substrate.

9. The packaging structure according to claim 8, characterized in that, An underfill material is also provided between the first chip and the packaging substrate, and the underfill material fills the gap between the first chip and the packaging substrate.

10. The packaging structure according to any one of claims 1 to 5, characterized in that, The packaging structure also includes a packaging material, which is used to encapsulate the first chip, the second chip and the heat sink on the packaging substrate.

11. The packaging structure according to claim 10, characterized in that, The top surface of the encapsulant is flush with the top surface of the heat sink and / or the top surface of the second chip.

12. The packaging structure according to claim 10, characterized in that, The top surface of the encapsulant is higher than the top surface of the heat sink and / or the top surface of the second chip.

13. A circuit board assembly, characterized in that, The circuit board assembly includes the packaging structure as described in any one of claims 1 to 12, the circuit board assembly further includes a circuit board, the packaging structure is disposed on the circuit board, and the circuit board is electrically connected to a fourth electrical connector of the packaging structure.

14. An electronic device, characterized in that, The electronic device includes the packaging structure as described in any one of claims 1 to 12, or the electronic device includes the circuit board assembly as described in claim 13.

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