Chip and package structure

Abstract

The utility model relates to a kind of chip and packaging structure, relate to the field of semiconductor technology, in the chip, since multiple first conductive structure surrounds function area, so when the function area in chip produces electromagnetic radiation, first conductive structure can directly absorb or reflect electromagnetic radiation effectively, so that it will not interfere with other structures, reduce the interference of electromagnetic radiation.In the packaging structure, since the chip in the application is used, electromagnetic interference will not occur between multiple chips, reducing the electromagnetic interference in packaging structure. Since the first conductive structure for shielding is arranged inside the chip, it is not necessary to set a separate Faraday cage, which not only reduces the thickness of the packaging structure, but also reduces the footprint of the chip on the first substrate, further miniaturizing the packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its packaging structure. Background Technology

[0002] With the continuous improvement of packaging technology and signal speed, electromagnetic compatibility issues are becoming increasingly serious. In some packaging structures, multiple components are integrated on the same substrate. In this case, various radiations and interferences are generated inside the substrate. The internal metals can cause electromagnetic waves to oscillate back and forth, which cannot be processed in time, seriously affecting the quality of high-speed signals and power supplies. Utility Model Content

[0003] Therefore, it is necessary to provide a chip and a packaging structure for reducing electromagnetic radiation in the packaging structure.

[0004] To achieve the above objectives, on the one hand, this utility model provides a chip, comprising:

[0005] A substrate, the substrate including a functional region and an edge region surrounding the functional region;

[0006] A plurality of first shielding structures are located within the substrate of the edge region and surround the functional region, the first shielding structures being used to reflect or absorb radiated interference.

[0007] In one embodiment, the chip further includes:

[0008] A first wiring structure is located on a first side of the substrate. The first wiring structure includes a first ground layer, which is electrically connected to the first shielding structure.

[0009] In one embodiment, the first shielding structure extends through the substrate, and the chip further includes:

[0010] The second conductive layer is located on the second side of the substrate and is connected to the first shielding structure;

[0011] Solder balls are located on the side of the second conductive layer away from the substrate.

[0012] In one embodiment, the spacing between two adjacent first conductive structures is less than or equal to λ / 10, where λ is the minimum shielding wavelength.

[0013] In one embodiment, the arrangement of the first conductive structure in the edge region includes a single-layer ring or multiple-layer rings.

[0014] On the other hand, this application also provides a packaging structure, including:

[0015] First substrate;

[0016] Multiple chips as described above, wherein the multiple chips are located on one side of the first substrate.

[0017] In one embodiment, the chip includes a plurality of first shielding structures extending through a substrate, a second conductive layer located on a second side of the substrate, and solder balls located on the side of the second conductive layer away from the substrate. The package structure further includes:

[0018] The filler layer includes an insulating adhesive layer and an absorbent adhesive layer. The insulating adhesive layer is located between the chip and the first substrate and wraps the second conductive layer of the chip and the solder balls. The absorbent adhesive layer surrounds the insulating adhesive layer.

[0019] In one embodiment, the packaging structure further includes:

[0020] A thermal pad, the thermal pad being located on the side of the chip away from the first substrate;

[0021] The packaging structure further includes:

[0022] A radiation-absorbing layer is located on the side of the chip away from the first substrate;

[0023] And / or, the packaging structure further includes:

[0024] Multiple absorbing structures are located on the sidewall of the thermal pad, and the multiple absorbing structures surround the thermal pad.

[0025] In one embodiment, the chip includes a plurality of first shielding structures penetrating a substrate, a second conductive layer located on a second side of the substrate, and solder balls located on the side of the second conductive layer away from the substrate. The first substrate includes:

[0026] The second ground layer is located on the side of the first substrate closer to the chip, and the first shielding structure is connected to the second ground layer through the solder balls;

[0027] The second wiring layer is located on the side of the first substrate away from the chip;

[0028] The side of the first substrate away from the chip further includes:

[0029] Multiple functional components, the chip being interconnected with the functional components via the second wiring layer;

[0030] Multiple pads are located between the second wiring layer and the functional component, connecting the second wiring layer and the functional component.

[0031] In one embodiment, the chip includes a first chip, and the packaging structure further includes:

[0032] A second substrate is located on one side of the first substrate and surrounds the first chip. The second substrate includes at least one grounding structure that penetrates the second substrate and is connected to the second grounding layer of the first substrate.

[0033] Compared with existing technologies, the above technical solution has the following advantages:

[0034] In this chip, the substrate includes a functional region and an edge region surrounding the functional region. Multiple first conductive structures are disposed in the edge region surrounding the functional region. Because the multiple first conductive structures surround the functional region, when the functional region within the chip generates electromagnetic radiation, the first conductive structures can directly and effectively absorb or reflect the electromagnetic radiation, preventing it from interfering with other structures and reducing electromagnetic radiation interference.

[0035] In the packaging structure, multiple chips are disposed on the substrate. Since these chips are the chips described in this application, and each chip has a first conductive structure inside to prevent electromagnetic interference, electromagnetic interference will not occur between the multiple chips, thus reducing electromagnetic interference in the packaging structure. Because the first conductive structure for shielding is disposed inside the chip, there is no need to provide a separate Faraday cage, which not only reduces the thickness of the packaging structure but also reduces the area occupied by the chip on the first substrate, further miniaturizing the packaging structure. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic flowchart illustrating a chip fabrication method provided in an embodiment of this application;

[0038] Figure 2 This application provides a partial structural schematic diagram of a chip as an embodiment;

[0039] Figure 3 This application provides a partial structural schematic diagram of a chip forming a first wiring structure according to an embodiment of the present application;

[0040] Figure 4 This application provides another partial structural diagram of a chip forming a first wiring structure according to an embodiment of the present application;

[0041] Figure 5 This application provides a partial three-dimensional structural diagram of a chip forming a first wiring structure according to an embodiment of the present application;

[0042] Figure 6 This application provides a partial structural diagram of a chip after the formation of the first trench;

[0043] Figure 7 This application provides a partial structural diagram of a chip after the formation of an insulating layer;

[0044] Figure 8 This application provides a partial structural diagram of a chip after the formation of its initial conductive structure.

[0045] Figure 9 This is a partial structural diagram of a chip after substrate thinning, provided in an embodiment of this application.

[0046] Figure 10 This application provides a partial structural diagram of a chip after the formation of a first shielding structure and a second conductive layer;

[0047] Figure 11 This is a schematic diagram of the fabrication process of a packaging structure provided in an embodiment of this application;

[0048] Figure 12 This is a schematic diagram of a packaging structure provided in an embodiment of this application;

[0049] Figure 13 This is another partial structural schematic diagram of a packaging structure provided in an embodiment of this application;

[0050] Figure 14 for Figure 12 A schematic diagram of the 3D disassembled structure within the dashed box.

[0051] Explanation of reference numerals in the attached figures: 01-Substrate; 011-Functional area; 012-Edge area; 013-First shielding structure; 0131-Initial conductive structure; 02-First wiring structure; 021-First ground layer; 022-First wiring layer; 023-First conductive structure; 03-First trench; 04-Insulating layer; 05-Second conductive layer; 06-Solder ball; 10-First substrate; 11-Chip; 12-Fill layer; 121-Insulating adhesive layer; 122-Absorbing adhesive layer; 13-Radiation absorbing layer; 14-Provides thermal pad; 15-Second ground layer; 16-Second substrate; 161-Grounding structure; 17-Heat dissipation layer; 18-Optical chip; 19-Optical fiber; 20-Solder pad; 21-Functional component. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when a layer is described as "adjacent to" or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is described as "directly adjacent to" or "directly connected to" other layers, there are no intervening layers.

[0055] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0056] Based on the background information, the Central Processing Unit (CPU) typically operates in the S-band, with a wavelength of approximately 10 cm. Even after the number of CPU cores reaches a certain level, further increases in clock speed are considered. Simultaneously, the Deep Computing Unit (DCU), optoelectronic co-package, and connectors are integrated onto a single substrate, achieving a large substrate package. This is equivalent to combining different chip packaging substrates with a motherboard, eliminating the need for a separate motherboard for power and signals. In this case, various forms of radiation and interference are generated within the substrate. The internal metal causes electromagnetic waves to oscillate, which cannot be processed in a timely manner, severely impacting the quality of high-speed signals and power.

[0057] In integrated packaging technology, to prevent electromagnetic interference between adjacent chips, Faraday cages are placed in the gaps around the chips to shield electromagnetic interference. However, since Faraday cages require a certain amount of space, they not only occupy more substrate area but also increase the thickness of the packaging structure, making the integrated packaging structure more complex and increasing the packaging thickness, which is not conducive to the miniaturization of the packaging structure.

[0058] Based on this, this application provides a chip and a packaging structure. In the chip, the substrate includes a functional region and an edge region surrounding the functional region. Multiple first conductive structures are disposed in the edge region surrounding the functional region. Because the multiple first conductive structures surround the functional region, when the functional region within the chip generates electromagnetic radiation, the first conductive structures can directly and effectively absorb or reflect the electromagnetic radiation, preventing it from interfering with other structures and reducing electromagnetic radiation interference.

[0059] In the packaging structure, multiple chips are disposed on the substrate. Since these chips are the chips described in this application, and each chip has a first conductive structure inside to prevent electromagnetic interference, electromagnetic interference will not occur between the multiple chips, thus reducing electromagnetic interference in the packaging structure. Because the first conductive structure for shielding is disposed inside the chip, there is no need to provide a separate Faraday cage, which not only reduces the thickness of the packaging structure but also reduces the area occupied by the chip on the first substrate, further miniaturizing the packaging structure.

[0060] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] refer to Figure 1 , Figure 1 This application provides a schematic flowchart of a chip fabrication method according to an embodiment; see reference. Figure 2 , Figure 2 This application provides a partial structural schematic diagram of a chip; the method for fabricating the chip includes:

[0062] A substrate 01 is provided, the substrate 01 including a functional region 011 and an edge region 012 surrounding the functional region 011;

[0063] Multiple first shielding structures 013 are formed within the substrate 01 of the edge region 012, surrounding the functional region 011. The first shielding structures 013 are used to reflect or absorb radiation interference.

[0064] Specifically, substrate 01 includes a silicon substrate, such as a bare silicon wafer. Substrate 01 includes a functional region 011 for fabricating functional devices, where transistors and other device structures are fabricated. An edge region 012 surrounds the functional region 011, and multiple first shielding structures 013 are formed within the substrate 01 of the edge region 012, forming a shielding wall around the functional region 011. When electromagnetic radiation is generated within the functional region 011, the first shielding structures 013 reflect or absorb the electromagnetic radiation generated within the chip, preventing electromagnetic radiation within the chip from interfering with other structures.

[0065] It should be noted that the first shielding structure 013 is grounded to achieve effective electromagnetic shielding. The material of the first shielding structure 013 can be a conductive metal, such as copper, and is not specifically limited. It should also be noted that the fabrication of the functional region 011 and the edge region 012 is not specifically limited and can be fabricated in steps as needed, for example, the functional region 011 can be fabricated first, and then the edge region 012 can be fabricated.

[0066] In this embodiment, since multiple first shielding structures 013 surround the functional area 011, when the functional area 011 inside the chip generates electromagnetic radiation, the first shielding structures 013 can directly and effectively absorb or reflect the electromagnetic radiation, so that it will not interfere with other structures and reduce the interference of electromagnetic radiation.

[0067] In another embodiment of this application, reference is made to Figure 3 , Figure 3 This application provides a partial structural diagram of a chip forming a first wiring structure; after forming a plurality of first shielding structures 013 surrounding the functional region 011 within the substrate 01 of the edge region 012, the chip includes:

[0068] A first wiring structure 02 is formed on the first side of the substrate 01. The first wiring structure 02 includes a first ground layer 021, which is electrically connected to the first shielding structure 013.

[0069] Specifically, the first wiring structure 02 may include multiple first wiring layers to realize the transmission of electrical signals (not shown in the figure). The first wiring structure 02 may include a first ground layer 021. It should be noted that the first ground layer 021 may be a metal material layer, such as a copper metal layer.

[0070] In this embodiment, the first ground layer 021 is connected to the first shielding structure 013 so that the shielding wall formed by the first shielding structure 013 forms a global network connection with the functional area 011 of the chip, thereby better achieving electromagnetic radiation shielding of the chip.

[0071] In another embodiment of this application, such as Figure 3 As shown, a first wiring structure 02 is formed on the first side of the substrate 01, including:

[0072] A first ground layer 021 is formed on the first side of the substrate 01, covering the first shielding structure 013.

[0073] Specifically, when forming the first wiring structure 02, the first ground layer 021 can be located at the bottom layer of the first wiring structure 02. At this time, the first ground layer 021 is directly formed on the substrate 01. The first ground layer 021 can directly cover the first shielding structure 013, thereby being electrically connected to the first shielding structure 013.

[0074] In this embodiment, the first grounding layer 021 is directly connected to the first shielding structure 013, which can reduce the need for conductive structures and save costs.

[0075] In another embodiment of this application, reference is made to Figure 4 , Figure 4 This application provides a schematic diagram of another part of the structure for forming a first wiring structure of a chip, as shown in the embodiments of this application; see reference. Figure 5 , Figure 5 This application provides a partial three-dimensional structural diagram of a chip forming a first wiring structure according to an embodiment of the present application; a first wiring structure 02 is formed on a first side of a substrate 01, including:

[0076] A first wiring layer 022 is formed on a first side of substrate 01. The first wiring layer 022 includes a first conductive layer and a dielectric layer.

[0077] Multiple first through holes are formed in the first wiring layer 022 of the edge region 012, surrounding the functional region 011, and the first through holes expose the first shielding structure 013;

[0078] A first conductive structure 023 is formed within the first through hole;

[0079] A first ground layer 021 is formed on the side of the first wiring layer 022 away from the substrate 01, covering the first conductive structure 023.

[0080] Specifically, in some chip designs, the first ground layer 021 cannot be directly connected to the first shielding structure 013. In this case, a first wiring layer 022 can be first set on the first side of the substrate 01. The first wiring layer 022 of the functional area 011 may include a dielectric layer and a first conductive layer. The first conductive layer is used for signal transmission, and the dielectric layer is used for planarization and to achieve line isolation. It should be noted that the first conductive layer may not be set in the dielectric layer of the edge area 012 at this time.

[0081] Next, the first wiring layer 022 of the edge region 012 is processed. For example, a patterned mask layer is formed on the first wiring layer 022 of the edge region 012, followed by photolithography to form a plurality of first vias surrounding the functional region 011. It should be noted that at least part of the first shielding structure 013 is exposed in the first vias.

[0082] After forming the first through hole, a first conductive structure 023 can be filled into the first through hole. It should be noted that the first conductive structure 023 can be configured in a one-to-one correspondence with the first shielding structure 013 to achieve electrical connection between the first shielding structure 013 and the first conductive structure 023, without any specific limitation. Alternatively, only partial connection is possible, in which case the first shielding structures 013 are connected in series and the first conductive structures 023 are connected in series to form a shielding network.

[0083] Then, a first ground layer 021 is formed on the side of the first wiring layer 022 away from the substrate 01. At this time, the first ground layer 021 covers the first conductive structure 023, thereby connecting with the first conductive structure 023 and connecting with the first shielding structure 013 through the first conductive structure 023, so that the shielding wall is connected to the global network of the chip. At this time, the global network is usually a low impedance network composed of multiple layers of the first conductive layer and the first conductive structure 023, which better achieves the shielding of electromagnetic radiation of the chip.

[0084] In this embodiment, the first wiring structure 02 can be designed according to specific needs, first wiring layer 022 can be designed first, and then the first grounding layer 021 and the first shielding structure 013 can be connected through the first conductive structure 023, which increases the design flexibility.

[0085] In another embodiment of this application, reference is made to Figure 6 , Figure 6 This application provides a partial structural diagram of a chip after the formation of the first trench, as shown in the embodiment of the present application; see reference. Figure 7 , Figure 7 This application provides a partial structural diagram of a chip after the formation of an insulating layer, as shown in the embodiments of the present application; see reference. Figure 8 , Figure 8 This application provides a partial structural diagram of a chip after the initial conductive structure has been formed, according to an embodiment of the present application; see reference. Figure 9 , Figure 9 This application provides a partial structural diagram of a chip after substrate thinning, as shown in the embodiments of the present application; Reference Figure 10 , Figure 10 This application provides a partial structural diagram of a chip after the formation of a first shielding structure and a second conductive layer; a plurality of first shielding structures 013 surrounding the functional region 011 are formed within the substrate 01 of the edge region 012, including:

[0086] Multiple first shielding structures 013 are formed within the substrate 01 of the edge region 012, surrounding the functional region 011. The height of the first shielding structure 013 is less than the thickness of the substrate 01.

[0087] The second side of the substrate 01 is thinned to expose the first shielding structure 013.

[0088] Specifically, the first shielding structure 013 can be formed within the substrate 01 of the edge region 012. For example, a substrate 01 is provided, and the substrate 01 of the edge region 012 is first processed to form a patterned mask layer on the substrate 01 of the edge region 012. Then, alternating etching and passivation processes are performed to etch out multiple first trenches 03 surrounding the functional region 011. It should be noted that transistors can be formed in the functional region 011 first, and then the edge region 012 can be processed (e.g., ...). Figure 6 (As shown).

[0089] In some embodiments, the aspect ratio of the first trench 03 can be 10:1, and is not specifically limited, but can be designed as needed. The depth range of the first trench 03 can be 20μm-100μm, including the endpoint values. For example, the depth of the first trench 03 can be 20μm, or the depth of the first trench 03 can be 60μm, or the depth of the first trench 03 can be 73μm, etc. The thickness of the first trench 03 is less than the thickness of the substrate 01, and the first trench 03 is only a cavity at this time and does not have electrical functions (such as...). Figure 6 (As shown).

[0090] Then, an insulating layer 04 is deposited within the first trench 03 and on the surface of the substrate 01 in the edge region 012. This insulating layer 04 isolates the silicon substrate 01 and improves the reliability of the first trench 03. The insulating layer 04 can be an oxide layer (such as...). Figure 7 (As shown).

[0091] Subsequently, a conductive material layer is formed on the side of the insulating layer 04 away from the substrate 01. This conductive material layer fills the first trench 03 to form multiple initial conductive structures 0131 surrounding the functional region 011. At this time, the conductive material layer also covers the surface of the substrate 01 in the edge region 012, so that the initial conductive structures 0131 form a shielding network. It should be noted that the material of the conductive material layer can be copper or tungsten to ensure compatibility between the silicon substrate 01 and the first wiring layer 022, preventing cracking caused by contamination or thermal expansion coefficient mismatch. The insulating layer 04 can insulate the finally formed first shielding structure 013 from the circuitry inside the chip, for example, by using an oxide layer to avoid short circuits or signal crosstalk (such as...). Figure 8 (As shown).

[0092] Then, the side of substrate 01 away from the first wiring structure 02 is etched, so that the initial conductive structure 0131 protrudes from the surface of substrate 01 (e.g., Figure 9 As shown), the initial conductive structure 0131 is then thinned to flatten the protruding parts of the initial conductive structure 0131, and the remaining initial conductive structure 0131 forms the first shielding structure 013 (as shown). Figure 10 (As shown).

[0093] In this embodiment, the first shielding structure 013 formed in this manner is compatible with through-silicon via (TSV) technology, reducing manufacturing costs.

[0094] In another embodiment of this application, such as Figure 10 As shown, Figure 3 As shown, after forming a plurality of first shielding structures 013 surrounding the functional region 011 within the substrate 01 of the edge region 012, the method includes:

[0095] A second conductive layer 05 is formed on the second side of the substrate;

[0096] Solder balls 06 are formed on the side of the second conductive layer 05 away from the substrate 01.

[0097] Specifically, the material of the second conductive layer 05 can be copper. The material of the solder ball 06 can also be copper.

[0098] After fabricating multiple first shielding structures 013, a second conductive layer 05 is formed on the second side of the substrate 01, and the second conductive layer 05 is connected to the first shielding structures 013. Solder balls 06 are formed on the side of the second conductive layer 05 away from the substrate 01 using a ball-planting process. This second conductive layer 05 can increase the reliability of the solder balls 06 and also serve as a ground on the back of the chip, facilitating the formation of a shielding wall and further expanding the shielding network.

[0099] It should be understood that, unless explicitly stated otherwise in this document, there is no strict order in which these steps are performed; they can be performed in any other order. Furthermore, Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0100] Based on the above chip fabrication method, refer to Figure 2 This application also provides a chip, including:

[0101] Substrate 01, which includes a functional region 011 and an edge region 012 surrounding the functional region 011;

[0102] Multiple first shielding structures 013 are located within the substrate 01 of the edge region 012, and the multiple first shielding structures 013 surround the functional region 011.

[0103] Specifically, substrate 01 includes a silicon substrate, functional region 011 may include transistors, edge region 012 surrounds functional region 011, and multiple first shielding structures 013 within substrate 01 of edge region 012 form a shielding wall. When electromagnetic radiation is generated within functional region 011, the first shielding structure 013 will reflect or absorb the electromagnetic radiation generated within the chip, preventing electromagnetic radiation within the chip from interfering with other structures.

[0104] In another embodiment of this application, such as Figure 3 Or such as Figure 4 Or such as Figure 5 The chip shown also includes:

[0105] The first wiring structure 02 is located on the first side of the substrate 01. The first wiring structure 02 includes a first ground layer 021, which is electrically connected to the first shielding structure 013.

[0106] Specifically, the first wiring structure 02 may include multiple first wiring layers 022 to realize the transmission of electrical signals (not shown). The first wiring structure 02 may include a first ground layer 021. It should be noted that the first ground layer 021 may be a metal material layer, such as a copper metal layer.

[0107] In the first wiring structure 02, the first ground layer 021 can be located at the bottom layer of the first wiring structure 02. In this case, the first ground layer 021 is formed directly on the substrate 01, and the first ground layer 021 covers the first shielding structure 013 and is electrically connected to it.

[0108] In some chip designs, the first ground layer 021 cannot be directly connected to the first shielding structure 013. In this case, a first wiring layer 022 can be first set on the first side of the substrate 01. The first wiring layer 022 of the functional area 011 can include a dielectric layer and a first conductive layer. At this time, the first conductive layer can be omitted from the dielectric layer of the edge area 012. Then, a first conductive structure 023 is formed in the first wiring layer 022 of the edge area 012. Then, a first ground layer 021 is formed on the side of the first wiring layer 022 away from the substrate 01. The first ground layer 021 covers the first conductive structure 023, so that the first ground layer 021 and the first shielding structure 013 are connected through the first conductive structure 023, increasing design flexibility.

[0109] In this embodiment, the first ground layer 021 is connected to the first shielding structure 013 so that the shielding wall formed by the first shielding structure 013 forms a global network connection with the functional area 011 of the chip, thereby better achieving electromagnetic radiation shielding of the chip.

[0110] In another embodiment of this application, such as Figure 3 As shown, the chip also includes:

[0111] The second conductive layer 05 is located on the second side of the substrate 01 and connected to the first shielding structure 013;

[0112] The solder ball 06 is located on the side of the second conductive layer 05 facing away from the substrate 01.

[0113] Specifically, the material of the second conductive layer 05 may be a copper material. The material of the solder ball 06 may also be a copper material. The second conductive layer 05 can improve the reliability of the solder ball 06, and can also serve as a ground on the back side of the chip, so as to form a shielding wall and further expand the shielding network.

[0114] In another embodiment of the present application, the spacing between two adjacent first shielding structures 013 is less than or equal to λ / 10, where λ is the minimum shielding wavelength.

[0115] Specifically, there are a plurality of first shielding structures 013, and the spacing between two directly adjacent first shielding structures 013 may be less than or equal to λ / 10, for example, the spacing between two adjacent first shielding structures 013 may be λ / 11, or the spacing between two adjacent first shielding structures 013 may be λ / 12, which is not specifically limited, and can shield electromagnetic waves of different wavelengths.

[0116] At this time, λ is the minimum shielding wavelength, that is, λ is the minimum wavelength of electromagnetic radiation in the chip. If the spacing is too large, part of the electromagnetic waves cannot be completely shielded. In this embodiment, as the operating frequency continues to increase, the spacing between two adjacent first shielding structures 013 can be designed to be less than or equal to λ / 10, and effective shielding is achieved by reasonably reducing the spacing between two adjacent first shielding structures 013.

[0117] In another embodiment of the present application, the arrangement of the first shielding structures 013 in the edge region 012 includes a single-layer ring shape or a multi-layer ring shape.

[0118] Specifically, the edge region 012 surrounds the functional region 011. At this time, the first shielding structures 013 located in the edge region 012 may form a single-layer ring, for example, a single-layer circular ring or a single-layer square ring. It may also form a multi-layer ring, for example, a shape like a Chinese character "回". Of course, it may also be three layers, four layers, etc. (not shown), which is not specifically limited. The multi-layer ring can further improve the shielding effect of the shielding wall.

[0119] It should be noted that the chip is prepared by the above-mentioned chip preparation method, and the specific contents can be referred to each other, and will not be repeated here.

[0120] Based on the above chip, refer to Figure 11 , Figure 11 is a schematic diagram of a preparation process of a packaging structure provided by the embodiment of the present application; refer to Figure 12 , Figure 12 This application provides a schematic diagram of a packaging structure according to an embodiment of the present application; the present application also provides a method for preparing a packaging structure, including:

[0121] Provide a first substrate 10;

[0122] Multiple chips 11 as described above are mounted on the first substrate 10.

[0123] Specifically, the first substrate 10 provided can be a packaging substrate, etc., and the chip 11 can be a flip chip with a first shielding structure 013. Figure 12 The middle arrow indicates the radiation direction of the electromagnetic waves generated by chip 11.

[0124] In the fabrication method of this packaging structure, multiple chips 11 are mounted on the first substrate 10. These chips 11 are the same chips that are disposed with the first shielding structure 013 as described above. The multiple chips 11 disposed on the same substrate can improve the integration density.

[0125] In this embodiment, multiple chips 11 are disposed on the substrate, which is inevitably subject to electromagnetic interference. However, since the chip 11 is the chip of this application, it has a first shielding structure 013 inside to prevent electromagnetic radiation interference. Therefore, no electromagnetic interference is generated between the multiple chips 11, reducing electromagnetic interference in the packaging structure. Since the first shielding structure 013 for shielding is disposed inside the chip 11, there is no need to set a separate Faraday cage. This not only reduces the thickness of the packaging structure but also reduces the area occupied by the chip 11 on the first substrate 10, further miniaturizing the packaging structure.

[0126] In another embodiment of this application, reference is made to Figure 13 , Figure 13 This is another schematic diagram of a packaging structure provided in an embodiment of this application; after mounting multiple chips 11 on the first substrate 10, it further includes:

[0127] A filler layer 12 is formed on the side of the chip 11 near the first substrate 10.

[0128] Specifically, when the chip 11 is mounted onto the first substrate 10, the filler layer 12 can better encapsulate the chip 11 and improve the reliability of the mounted chip 11.

[0129] In another embodiment of this application, such as Figure 13 As shown, the chip 11 includes a plurality of first shielding structures 013 penetrating the substrate 01, a second conductive layer 05 located on the second side of the substrate 01, and solder balls 06 located on the side of the second conductive layer 05 away from the substrate 01. A filler layer 12 is formed on the side of the chip 11 near the first substrate 10, including:

[0130] An insulating adhesive layer 121 is formed between the chip 11 and the first substrate 10, and the insulating adhesive layer 121 covers the second conductive layer 05 of the chip 11 and the solder balls 06.

[0131] An absorbent layer 122 is formed surrounding the insulating adhesive layer 121.

[0132] Specifically, when mounting the chip 11, its solder balls 06 are located on one side of the first substrate 10. At this time, the filler layer 12 is provided to prevent the solder balls 06 from being corroded by moisture and improve the packaging reliability.

[0133] The filler layer 12 includes an insulating adhesive layer 121 and an absorbent adhesive layer 122. It should be noted that the insulating adhesive layer 121 at least covers the second conductive layer 05 and the solder ball 06 to prevent the second conductive layer 05 and the solder ball 06 from forming a short circuit with the material in the absorbent adhesive layer 122, so as to ensure the reliability of the solder ball 06.

[0134] An absorbent layer 122 is disposed around the outside of the insulating adhesive layer 121. This absorbent layer 122 can possess both shielding and heat dissipation properties. For example, the absorbent layer 122 can be made of an adhesive material doped with carbon nanotubes, graphene, or silver nanowires, which can form an anisotropic conductive network. This absorbent layer 122 can absorb electromagnetic radiation waves and convert them into heat energy that is diffused away. In some embodiments, boron nitride or aluminum oxide can also be added to the absorbent layer 122 to improve thermal conductivity.

[0135] In this embodiment, the insulating adhesive layer 121 prevents short circuits, and the absorbent adhesive layer 122 prevents obstruction of heat dissipation paths and increases shielding functionality. The design of the filler layer 12 ensures the mechanical reliability of the encapsulation in harsh environments.

[0136] In another embodiment of this application, reference is made to Figure 14 , Figure 14 for Figure 12 A schematic diagram of the three-dimensional split structure within the dashed box; after mounting multiple chips 11 on the first substrate 10, it also includes:

[0137] A radiation absorption layer 13 is formed on the side of the chip 11 away from the first substrate 10.

[0138] Specifically, there will also be electromagnetic radiation leakage on the upper side of the chip 11. At this time, a radiation absorption layer 13 can be formed on the side of the chip 11 away from the first substrate 10. The radiation absorption layer 13 can absorb electromagnetic waves and convert them into heat energy to diffuse away.

[0139] In some embodiments, the radiation absorbing layer 13 is made of a conductive filler and a polymer matrix; wherein the conductive filler is made of one or more of graphene, metal nanowires, and carbon nanotubes, and the polymer is made of one or more of epoxy resin, polyimide, and silicone rubber. This conductive filler can improve heat dissipation performance. For example, graphene has a thermal conductivity exceeding 5000 W / m·K, which is significantly superior to traditional thermally conductive materials such as copper (~400 W / m·K) and aluminum (~235 W / m·K). Simultaneously, graphene has high electrical conductivity and permittivity, effectively absorbing electromagnetic waves and exhibiting broadband absorption characteristics. Its absorption principle is to convert the radiant energy of electromagnetic waves into heat energy and diffuse it away. The conductive filler and polymer matrix form a conductive polymer composite material that can shield the electromagnetic waves of the chip 11 away from the side of the first substrate 10.

[0140] In another embodiment of this application, such as Figure 14 As shown, a radiation-absorbing layer 13 is formed on the side of the chip 11 away from the first substrate 10, comprising:

[0141] Provides thermal pad 14;

[0142] A radiation-absorbing material is coated on at least one side of the thermal pad 14 to form a radiation-absorbing layer 13;

[0143] The thermal pad 14 is placed on the side of the chip 11 away from the first substrate 10.

[0144] Specifically, when forming the radiation absorption layer 13, a thermal pad 14 can be provided first, and an absorbing material can be coated on at least one side of the thermal pad 14. For example, a conductive polymer composite material can be coated on the first side to form the radiation absorption layer 13, or a conductive polymer composite material can be coated on the second side to form the radiation absorption layer 13, or conductive polymer composite materials can be coated on both sides to form the radiation absorption layer 13, etc. Then, the thermal pad 14 is placed on the side of the chip 11 away from the first substrate 10. It should be noted that when coating on one side only, the radiation absorption layer 13 can be disposed on the side facing the chip 11 (not shown) or on the side away from the chip 11 (e.g., ...). Figure 14 As shown), no specific limitations are made.

[0145] In some embodiments, an absorbing structure (not shown) surrounding the thermal pad 14 may also be provided on the sidewall of the thermal pad 14 to absorb electromagnetic waves leaking from the top.

[0146] In this embodiment, the thermal pad 14 can assist in setting the radiation absorption layer 13 to further improve the shielding range.

[0147] In another embodiment of this application, such as Figure 12 As shown, Figure 14As shown, chip 11 includes a first chip, and the first substrate 10 includes a second ground layer 15 disposed on the side close to chip 11 and a second wiring layer disposed on the side away from chip 11; before forming the radiation absorption layer 13 on the side of chip 11 away from the first substrate 10, it includes:

[0148] A second substrate 16 is provided, the second substrate 16 having a hollow region 162, and the second substrate 16 including at least one ground structure 161, the ground structure 161 penetrating the second substrate 16.

[0149] The second substrate 16 is attached to the side of the first substrate 10 where the first chip is disposed. The first chip is located in the hollow area 162 of the second substrate 16. The grounding structure 161 is connected to the second grounding layer 15 of the first substrate 10.

[0150] A plurality of pads 20 are formed on the side of the first substrate 10 away from the chip 11;

[0151] Multiple functional components 21 are mounted on the side of the pad 20 away from the chip 11, and the chip 11 is interconnected with the functional components 21 through the second wiring layer and the pad 20.

[0152] Specifically, the first substrate 10 includes a second ground layer 15, which is located on the side closer to the chip 11 to facilitate grounding of devices in the package structure. In the package structure, the chip 11 may include a first chip. This first chip may be a chip 11 with a fan-out structure.

[0153] The first substrate 10 has a plurality of pads 20 on the side away from the chip 11, which can increase the connection reliability of the functional components 21.

[0154] Multiple functional components 21, including various signals and power supplies in the system, can be mounted on the side of the pad 20 away from the first substrate 10. The second wiring layer and the pad 20 interconnect multiple chips 11 and multiple functional components 21 to form a large substrate package through large-scale integration technology, ensuring signal and power integrity. Since the soldering is completed on the first substrate 10, no separate packaging is required, which also reduces power consumption. At this time, the chip 11 has a first shielding structure 013, and the electromagnetic radiation generated by the functional components 21 will not affect the chip 11, thus increasing the electromagnetic radiation resistance of the entire structure.

[0155] The provided second substrate 16 has a hollow region 162. When the second substrate 16 is mounted onto the first substrate 10, the first chip is located within the hollow region 162 of the second substrate 16. The second substrate 16 surrounds the first chip, and there is no gap between the first chip and the second substrate 16; that is, the first chip and the second substrate 16 are fitted together. The grounding structure 161 in the second substrate 16 is used to implement the circuit network of the chip 11, so as to connect to the second ground layer 15 in the first substrate 10 through the grounding structure 161. It should be noted that the grounding structure 161 can be a conductive metal, such as copper.

[0156] In related technologies, a Faraday cage is required between the second substrate 16 and the chip 11. However, in this application, since the first shielding structure 013 is already provided in the chip 11, there is no need to design a Faraday cage. Therefore, the thickness of the second substrate 16 can be designed to be thinner, and there is no need to provide a gap between the second substrate 16 and the chip 11. This reduces the thickness of the packaging structure and also reduces the area occupied by the first substrate 10 of the packaging structure, thereby improving the miniaturization of the packaging structure.

[0157] It should be understood that, unless explicitly stated otherwise in this document, there is no strict order in which these steps are performed; they can be performed in any other order. Furthermore, Figure 11 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0158] Based on the above-described method for fabricating the encapsulation structure, this application also provides an encapsulation structure, comprising:

[0159] First substrate 10;

[0160] Multiple chips 11 as described above are located on one side of the first substrate 10.

[0161] Specifically, the first substrate 10 can be a packaging substrate, etc., and the chip 11 can be a flip chip.

[0162] In this packaging structure, multiple chips 11 are provided. These chips 11 are the same as those provided in the first shielding structure 013. The types of chips 11 can be different and are not specifically limited. The multiple chips 11 provided on the same substrate can improve the integration density.

[0163] In this embodiment, multiple chips 11 are disposed on the substrate. Since the chips 11 are the chips of this application, each chip 11 has a first shielding structure 013 inside to prevent electromagnetic radiation interference. Therefore, no electromagnetic interference is generated between the multiple chips 11, reducing electromagnetic interference in the packaging structure. Because the first shielding structure 013 for shielding is disposed inside the chip 11, there is no need to set a separate Faraday cage. This not only reduces the thickness of the packaging structure but also reduces the area occupied by the chip 11 on the first substrate 10, further miniaturizing the packaging structure.

[0164] In another embodiment of this application, the chip 11 includes a plurality of first shielding structures 013 penetrating the substrate 01, a second conductive layer 05 located on a second side of the substrate 01, and solder balls 06 located on the side of the second conductive layer 05 away from the substrate 01. The package structure further includes:

[0165] The filler layer 12 includes an insulating adhesive layer 121 and an absorbent adhesive layer 122. The insulating adhesive layer 121 is located between the chip 11 and the first substrate 10 and wraps the second conductive layer 05 and solder balls 06 of the chip 11. The absorbent adhesive layer 122 surrounds the insulating adhesive layer 121.

[0166] Specifically, when mounting the chip 11, its solder balls 06 are located on one side of the first substrate 10. At this time, the filler layer 12 is provided to prevent the solder balls 06 from being corroded by moisture and improve the packaging reliability.

[0167] The filler layer 12 includes an insulating adhesive layer 121 and an absorbent adhesive layer 122. It should be noted that the insulating adhesive layer 121 at least covers the second conductive layer 05 and the solder ball 06, which can prevent the second conductive layer 05 and the solder ball 06 from forming a short circuit with the material in the absorbent adhesive layer 122, so as to ensure the reliability of the solder ball 06.

[0168] An absorbent layer 122 is provided on the side of the insulating adhesive layer 121 away from the first substrate 10. This absorbent layer 122 can combine shielding and heat dissipation properties. In this embodiment, the insulating adhesive can prevent short circuits, and the absorbent layer 122 can avoid blocking the heat dissipation path, thus increasing the shielding function. The design of the filler layer 12 ensures the mechanical reliability of the package under harsh environments.

[0169] In another embodiment of this application, the material of the absorbent layer 122 includes an adhesive material incorporating carbon nanotubes, graphene, or silver nanowires.

[0170] Specifically, the absorbent layer 122 can be made of a material doped with carbon nanotubes, graphene, or silver nanowires, which can form an anisotropic conductive network, providing both adhesive and local electromagnetic shielding functions. This absorbent layer 122 can absorb electromagnetic radiation waves and convert them into heat energy that diffuses away. In some embodiments, boron nitride or aluminum oxide can also be added to the absorbent layer 122 to improve thermal conductivity. The specific materials can be chosen according to actual conditions.

[0171] In another embodiment of this application, such as Figure 12 as well as Figure 14 As shown, the packaging structure also includes:

[0172] Thermal pad 14 is located on the side of chip 11 away from the first substrate 10;

[0173] The packaging structure also includes:

[0174] The radiation absorption layer 13 is located on the side of the chip 11 away from the first substrate 10.

[0175] And / or, the package structure also includes:

[0176] Multiple absorbing structures are located on the sidewall of the thermal pad 14, and the multiple absorbing structures surround the thermal pad 14.

[0177] Specifically, the thermal pad 14 can improve the heat dissipation capacity of the chip 11. In addition, there will be electromagnetic radiation leakage on the upper side of the chip 11. At this time, a radiation absorption layer 13 can be formed on the side of the chip 11 away from the first substrate 10. The radiation absorption layer 13 can absorb electromagnetic waves and convert them into heat energy for diffusion.

[0178] The thermal pad 14 can provide an adhesion base for the radiation absorption layer 13, for example, by coating one side of the thermal pad 14 with a conductive polymer composite material to form the radiation absorption layer 13.

[0179] Furthermore, the absorbing structure may include absorbing devices. In this embodiment, the absorbing structure can be placed on the sidewall of the thermal pad 14 to absorb some of the electromagnetic waves leaking from the upper side of the chip 11. It should be noted that multiple absorbing structures can be arranged around the thermal pad 14 to improve the absorbing performance. The radiation absorption layer 13 and the absorbing structure can both be provided, or only one can be provided; there is no specific limitation.

[0180] In another embodiment of this application, the material of the radiation absorbing layer 13 includes a conductive filler and a polymer matrix; wherein the material of the conductive filler includes one or more combinations of graphene, metal nanowires, and carbon nanotubes, and the material of the polymer includes one or more combinations of epoxy resin, polyimide, and silicone rubber.

[0181] Specifically, the conductive filler and the polymer matrix form a conductive polymer composite material that can shield the electromagnetic waves of the chip 11 away from the side of the first substrate 10. For example, graphene has a thermal conductivity of over 5000 W / m·K, which is significantly superior to traditional thermally conductive materials such as copper (~400 W / m·K) and aluminum (~235 W / m·K). At the same time, graphene has high electrical conductivity and capacitance, which can effectively absorb electromagnetic waves and has broadband absorption characteristics. Its wave absorption principle is to convert the radiation energy of electromagnetic waves into heat energy and diffuse it away.

[0182] In another embodiment of this application, such as Figure 12 as well as Figure 14 As shown, the packaging structure also includes:

[0183] Heat dissipation layer 17 is located on the side of radiation absorption layer 13 away from chip 11.

[0184] Specifically, the heat dissipation layer 17 is located on the side of the radiation absorption layer 13 away from the chip 11, and is used to dissipate heat for the entire package structure.

[0185] In some embodiments, an optical chip 18 may be disposed between the heat dissipation layer 17 and the first substrate 10, and the optical chip 18 is also connected to an optical fiber 19 for transmitting photoelectric signals.

[0186] In another embodiment of this application, such as Figure 12 as well as Figure 14 As shown, the chip 11 includes a plurality of first shielding structures 013 penetrating the substrate 01, a second conductive layer 05 located on the second side of the substrate 01, and solder balls 06 located on the side of the second conductive layer 05 away from the substrate 01. The first substrate 10 includes:

[0187] The second grounding layer 15, the first shielding structure 013 is connected to the second grounding layer 15 through solder balls 06;

[0188] The second wiring layer is located on the side of the first substrate away from the chip;

[0189] The side of the first substrate 10 away from the chip 11 also includes:

[0190] Multiple functional components 21 and multiple chips 11 are interconnected with the multiple functional components 21 through a second wiring layer;

[0191] Multiple pads 20 are located between the second wiring layer and the functional component 21, and the pads 20 connect the second wiring layer and the functional component 21.

[0192] Specifically, the first substrate 10 is also provided with a second grounding layer 15. The second grounding layer 15 is connected to the second conductive layer 05 through solder balls 06 to the first shielding structure 013, thereby realizing the grounding of the first shielding structure 013 and the second conductive layer 05, thus realizing the shielding network and increasing the shielding range.

[0193] The first substrate 10 has a plurality of pads 20 on the side away from the chip 11, which can increase the connection reliability of the functional components 21.

[0194] On the side of the pad 20 away from the chip 11, multiple functional components 21 are also provided, including various signals and power supplies in the system. The second wiring layer interconnects multiple chips 11 and multiple functional components 21 to form an ultra-large substrate package through large-scale integration technology, ensuring signal and power integrity. Furthermore, the soldering is completed on the first substrate 10, eliminating the need for separate packaging and reducing power consumption.

[0195] In another embodiment of this application, such as Figure 12 as well as Figure 14 As shown, chip 11 includes a first chip, and the package structure further includes:

[0196] The second substrate 16 is located on one side of the first substrate 10 and surrounds the first chip. The second substrate 16 includes at least one ground structure 161, which penetrates the second substrate 16 and is connected to the second ground layer 15 of the first substrate 10.

[0197] Specifically, the first substrate 10 includes a second ground layer 15 to facilitate grounding of devices in the package structure. In the package structure, the chip 11 may include a first chip. This first chip may be a chip 11 with a fan-out structure.

[0198] The second substrate 16 has a hollow region 162, and the first chip is located within the hollow region 162 of the second substrate 16, so that the second substrate 16 surrounds the first chip. There is no gap between the first chip and the second substrate 16, that is, the first chip is fitted into the second substrate 16. The grounding structure 161 in the second substrate 16 is used to implement the circuit network of the chip 11, so as to connect to the second ground layer 15 in the first substrate 10 through the grounding structure 161. It should be noted that the grounding structure 161 can be a conductive metal, such as copper.

[0199] It should be noted that the encapsulation structure is prepared by the method described above, and the specific details can be referred to each other, which will not be repeated here.

[0200] The aforementioned packaging structure forms a distributed shielding wall, replacing the external Faraday cage in related technologies. This reduces the packaging thickness and the area of ​​the packaging structure, thereby improving its miniaturization. It should be noted that as the frequency increases, the direction of radiation may change. Therefore, the direction of electromagnetic radiation can be determined through software simulation before effective electromagnetic shielding can be implemented.

[0201] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0202] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip, characterized in that, include: A substrate, the substrate including a functional region and an edge region surrounding the functional region; A plurality of first shielding structures are located within the substrate of the edge region and surround the functional region, the first shielding structures being used to reflect or absorb radiated interference.

2. The chip according to claim 1, characterized in that, The chip also includes: A first wiring structure is located on a first side of the substrate. The first wiring structure includes a first ground layer, which is electrically connected to the first shielding structure.

3. The chip according to claim 1, characterized in that, The first shielding structure penetrates the substrate, and the chip further includes: The second conductive layer is located on the second side of the substrate and is connected to the first shielding structure; Solder balls are located on the side of the second conductive layer away from the substrate.

4. The chip according to claim 1, characterized in that, The spacing between two adjacent first shielding structures is less than or equal to λ / 10, where λ is the minimum shielding wavelength.

5. The chip according to claim 1, characterized in that, The arrangement of the first shielding structure in the edge region includes a single-layer ring or multiple-layer rings.

6. A packaging structure, characterized in that, include: First substrate; A plurality of chips as described in any one of claims 1-5, wherein the plurality of chips are located on one side of the first substrate.

7. The packaging structure according to claim 6, characterized in that, The chip includes multiple first shielding structures penetrating the substrate, a second conductive layer located on a second side of the substrate, and solder balls located on the side of the second conductive layer away from the substrate. The packaging structure further includes: The filler layer includes an insulating adhesive layer and an absorbent adhesive layer. The insulating adhesive layer is located between the chip and the first substrate and wraps the second conductive layer of the chip and the solder balls. The absorbent adhesive layer surrounds the insulating adhesive layer.

8. The packaging structure according to claim 6, characterized in that, The packaging structure further includes: A thermal pad, the thermal pad being located on the side of the chip away from the first substrate; The packaging structure further includes: A radiation-absorbing layer is located on the side of the chip away from the first substrate; And / or, the packaging structure further includes: Multiple absorbing structures are located on the sidewall of the thermal pad, and the multiple absorbing structures surround the thermal pad.

9. The packaging structure according to claim 6, characterized in that, The chip includes a plurality of first shielding structures penetrating the substrate, a second conductive layer located on a second side of the substrate, and solder balls located on the side of the second conductive layer away from the substrate. The first substrate includes: The second ground layer is located on the side of the first substrate closer to the chip, and the first shielding structure is connected to the second ground layer through the solder balls; The second wiring layer is located on the side of the first substrate away from the chip; The side of the first substrate away from the chip further includes: Multiple functional components, the chip being interconnected with the functional components via the second wiring layer; Multiple pads are located between the second wiring layer and the functional component, connecting the second wiring layer and the functional component.

10. The packaging structure according to claim 9, characterized in that, The chip includes a first chip, and the packaging structure further includes: A second substrate is located on one side of the first substrate and surrounds the first chip. The second substrate includes at least one grounding structure that penetrates the second substrate and is connected to the second grounding layer of the first substrate.

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