A semiconductor structure and electronic device

Abstract

The application discloses a semiconductor structure and an electronic device. The semiconductor structure comprises a first wiring structure layer, a second wiring structure layer, a first chip layer and a second chip layer. The second wiring structure layer is arranged opposite to the first wiring structure layer. The first chip layer is arranged between the first wiring structure layer and the second wiring structure layer. The first chip layer comprises a first chip, a first component and a plurality of conductive columns. The first chip is electrically connected to the second wiring structure layer. The first component is a decoupling component. The plurality of conductive columns are used for electrically connecting the first wiring structure layer and the second wiring structure layer. At least part of the conductive columns penetrates the first component. The second chip layer is located on a side of the first wiring structure layer away from the first chip layer and comprises a second chip electrically connected to the first wiring structure layer. The orthographic projection of at least part of the first component and the second chip on the second wiring structure layer overlaps. The orthographic projection of the first chip and the second chip on the second wiring structure layer partially overlaps.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor structure and electronic device. Background Technology

[0002] With the rapid development of fields such as artificial intelligence (AI), high-performance computing (HPC), 5G, and automotive electronics, the demand for high-performance, low-power, and miniaturized chips is constantly increasing. Increased semiconductor speeds, interconnect densities, reduced pad spacing, larger chip sizes, and increased power consumption all pose challenges to chip packaging. Chiplet technology integrates chips and components with different functions or different process technologies through advanced packaging techniques to form a system-on-a-chip (SoC), breaking the limitations of traditional SoC design. This design approach not only reduces dependence on advanced processes but also improves design flexibility and scalability. However, the advanced nature of the chiplet architecture leads to a significant increase in design complexity. Chiplets manufactured using different processes differ in physical size, electrical characteristics, and thermal management, further increasing design complexity and challenges. Utility Model Content

[0003] This application discloses a semiconductor structure, the semiconductor structure comprising:

[0004] First wiring structure layer;

[0005] The second wiring structure layer is disposed opposite to and spaced apart from the first wiring structure layer;

[0006] A first chip layer is disposed between the first wiring structure layer and the second wiring structure layer; the first chip layer includes a first chip spaced apart in a first direction and at least one first component; the first chip is electrically connected to the second wiring structure layer, and the first component is a decoupling component; the first chip layer further includes a plurality of conductive pillars for electrically connecting the first wiring structure layer and the second wiring structure layer, at least a portion of the conductive pillars penetrating the at least one first component.

[0007] The second chip layer is located on the side of the first wiring structure layer away from the first chip layer. The second chip layer includes a second chip, which is electrically connected to the first wiring structure layer. At least a portion of the orthographic projection of the first component on the second wiring structure layer overlaps with the orthographic projection of the second chip on the second wiring structure layer. A portion of the orthographic projection of the first chip on the second wiring structure layer overlaps with a portion of the orthographic projection of the second chip on the second wiring structure layer.

[0008] In one embodiment, the overlapping area of ​​the portion of the first chip projected onto the second wiring structure layer and the portion of the second chip projected onto the second wiring structure layer is less than or equal to 2 mm in the first direction.

[0009] In some embodiments, the plurality of conductive posts include a plurality of first conductive posts that penetrate the at least one first component;

[0010] The second chip has a power signal connection terminal, wherein at least a portion of the plurality of the first conductive pillars are connected to the power signal connection terminal through the wiring structure of the first wiring structure layer.

[0011] In some embodiments, the plurality of conductive pillars further include one or more second conductive pillars located in a region outside all first components, the second conductive pillars penetrating the first chip;

[0012] The second conductive post is electrically connected to the second chip through the wiring structure of the first wiring structure layer.

[0013] In some embodiments, the first chip is at least one of a data processing chip, an input / output chip, and a storage chip, and the second chip is a data processing chip.

[0014] In some embodiments, the second chip layer further includes a second component, which is arranged along a first direction with the second chip, and the first chip is closer to the second component than the first component.

[0015] In some embodiments, the second component is a heat sink or a decoupling component.

[0016] In some embodiments, the orthographic projection of the second component on the second wiring structure layer overlaps with the orthographic projection of the first component on the second wiring structure layer;

[0017] The first chip is connected to the second component through the wiring structure of the first wiring structure layer.

[0018] In some embodiments, the first wiring structure layer is a rewiring layer, and the second wiring structure layer is a rewiring layer.

[0019] In some embodiments, the semiconductor structure further includes a first encapsulation layer and a second encapsulation layer;

[0020] The first encapsulation layer is located between the first wiring structure layer and the second wiring structure layer, and encapsulates the first chip and the first component;

[0021] The second encapsulation layer is located on the side of the first wiring structure layer opposite to the second wiring structure layer, and at least encapsulates the second chip.

[0022] In some embodiments, the decoupling component is an integrated capacitor or a deep trench capacitor;

[0023] Wherein, when at least one of the first components is a single component, the single first component is a deep-groove capacitor; when at least one of the first components is multiple components, each of the first components is an integrated capacitor.

[0024] This application also provides an electronic device, which includes the semiconductor structure described above.

[0025] Compared with related technologies, the semiconductor structure and electronic device provided in this application, by setting the first chip and the second chip to overlap in the orthographic projection portion of the second wiring structure layer, and setting at least one decoupling component that overlaps with the projection of the second chip on the second wiring structure layer, and at least some conductive pillars passing through the at least one decoupling component, improves the chip packaging integration, facilitates the decoupling of the conductive pillar transmission portion, improves the signal integrity of the semiconductor structure, and the setting of the decoupling component can also balance the stress of the first chip layer and reduce the warpage of the semiconductor structure.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0028] Figure 1 This is a cross-sectional view of a semiconductor structure according to an embodiment of this application.

[0029] Figure 2 This is a cross-sectional view of another semiconductor structure in one embodiment of this application. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0031] If the embodiments of this application contain terms relating to directional indications or positional relationships (e.g., up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance. Connections in this application can refer to mechanical connections, electrical connections, or signal connections, etc.

[0032] This application discloses a semiconductor structure comprising a first wiring structure layer, a second wiring structure layer, a first chip layer, and a second chip layer. The second wiring structure layer is disposed opposite to and spaced apart from the first wiring structure layer. The first chip layer is disposed between the first wiring structure layer and the second wiring structure layer. The first chip layer includes a first chip spaced apart in a first direction and at least one first component. The first chip is electrically connected to the second wiring structure layer, and the first component is a decoupling component. The first chip layer further includes a plurality of conductive pillars for electrically connecting the first wiring structure layer and the second wiring structure layer, at least a portion of the conductive pillars penetrating the at least one first component. The second chip layer is located on the side of the first wiring structure layer away from the first chip layer, and includes a second chip electrically connected to the first wiring structure layer. At least a portion of the orthographic projection of the first component on the second wiring structure layer overlaps with the orthographic projection of the second chip on the second wiring structure layer, and a portion of the orthographic projection of the first chip on the second wiring structure layer overlaps with a portion of the orthographic projection of the second chip on the second wiring structure layer.

[0033] In one embodiment of this disclosure, the overlapping area of ​​the first chip and the second chip in the orthographic projection of the second wiring structure layer is less than or equal to 2 mm in the first direction.

[0034] The aforementioned semiconductor structure includes at least one decoupling component that overlaps with the projection of the second chip onto the second wiring structure layer, and at least some conductive pillars penetrate the at least one decoupling component. This not only improves the chip packaging integration but also facilitates the decoupling of the conductive pillar transmission portion, thereby enhancing the signal integrity of the semiconductor structure. Furthermore, the decoupling component can balance the stress of the first chip layer and reduce the warpage of the semiconductor structure.

[0035] In the embodiments of this disclosure, by controlling the size of the overlapping area of ​​the first chip and the second chip in the orthographic projection of the second wiring structure layer in the first direction to be less than or equal to 2 mm, the stress of the first chip layer can be balanced and the warping of the semiconductor structure can be reduced.

[0036] The following is in conjunction with the appendix Figure 1 and Figure 2 The semiconductor structure described above will be described in detail. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] Please refer to Figure 1 This application provides a semiconductor structure 100. The semiconductor structure 100 includes a first wiring structure layer 20, a second wiring structure layer 10, a first chip layer 30, and a second chip layer 40. The second wiring structure layer 10, the first chip layer 30, the first wiring structure layer 20, and the second chip layer 40 are stacked in the thickness direction T of the semiconductor structure 100.

[0038] The second wiring structure layer 10 is opposite to and spaced apart from the first wiring structure layer 20.

[0039] The first wiring structure layer 20 has two opposing surfaces 2021 and 2022. The second wiring structure layer 10 has two opposing surfaces 1021 and 1022. Surface 2022 of the first wiring structure layer 20 faces surface 1021 of the second wiring structure layer 10.

[0040] The first wiring structure layer 20 has a wiring structure 201 and a dielectric layer 202 covering the wiring structure 201. The wiring structure 201 can be a conductive circuit with conductive leads, and the wiring structure 201 is exposed from two surfaces 2021 and 2022 of the first wiring structure layer 20. The wiring structure 201 can protrude from the exposed surfaces or be flush with the exposed surfaces.

[0041] In some embodiments, the first wiring structure layer 20 is a rewiring layer. Of course, in other embodiments, the first wiring structure layer 20 may also be a prefabricated wiring substrate.

[0042] The second wiring structure layer 10 has a wiring structure 101 and a dielectric layer 102 covering the wiring structure 101. The wiring structure 101 is a conductive circuit with conductive leads, and the wiring structure 101 is exposed from two surfaces 1021 and 1022 of the second wiring structure layer 10. The wiring structure 101 may protrude from the exposed surface or be flush with the exposed surface.

[0043] In some embodiments, the second wiring structure layer 10 is a rewiring layer. Of course, in other embodiments, the second wiring structure layer 10 may also be a prefabricated wiring substrate.

[0044] A first chip layer 30 is disposed between the first wiring structure layer 20 and the second wiring structure layer 10. The first chip layer 30 includes a first chip 32 spaced apart in a first direction L and at least one first component 31. The first chip 32 is electrically connected to the second wiring structure layer 10. The first component 31 is a decoupling component. The first chip layer 30 also includes a plurality of conductive posts 33 for electrically connecting the first wiring structure layer 20 and the second wiring structure layer 10, at least a portion of the conductive posts 33 penetrating the at least one first component 31.

[0045] The second chip layer 40 is located on the side of the first wiring structure layer 20 away from the first chip layer 30. The second chip layer 40 includes a second chip 41, which is electrically connected to the first wiring structure layer 20.

[0046] In this process, at least a portion of the orthographic projection of the first component 31 on the second wiring structure layer 10 overlaps with the orthographic projection of the second chip 41 on the second wiring structure layer 10.

[0047] The portion of the first chip 32 projected onto the second wiring structure layer 10 overlaps with the portion of the second chip 41 projected onto the second wiring structure layer 10, and the size L1 of the overlapping area in the first direction L is less than or equal to 2mm, such as 2mm, 1.8mm, 1.5mm, 1.3mm, 1.2mm, 1mm, 0.9mm, 0.8mm, 0.7mm, 0.6mm, etc.

[0048] In some embodiments, the dimension L1 of the overlapping region in the first direction L is less than or equal to 1 mm, such as 1 mm, 0.9 mm, 0.8 mm, 0.7 mm, 0.6 mm, etc.

[0049] In some embodiments, the orthographic projections of all the first components 31 on the second wiring structure layer 10 fall within the orthographic projection of the second chip 41 on the second wiring structure layer 10. In this way, the conductive pillar transmission portion can be decoupled, the signal integrity of the semiconductor structure can be improved, the stress of the first chip layer can be balanced, the warpage of the semiconductor structure can be reduced, and the compactness of the semiconductor structure can be guaranteed without increasing the volume of the semiconductor structure.

[0050] In some embodiments, the plurality of conductive posts 33 include a plurality of first conductive posts 331 extending through the at least one first component 31.

[0051] The second chip 41 has a power signal connection terminal, wherein at least a portion of the plurality of first conductive pillars 331 are connected to the power signal connection terminal through the wiring structure 201 of the first wiring structure layer 20.

[0052] like Figure 1 As shown, the surface of the second chip 41 facing the first wiring structure layer 20 is provided with a plurality of connection terminals (also referred to as pads) 401. Among the plurality of connection terminals 401, there are first type connection terminals 4011 that are connected to the plurality of first conductive posts 331 through the first wiring structure layer 20. At least a portion of the first type of connection terminals 4011 are power signal connection terminals. Accordingly, the wiring structure 201 in the first wiring structure layer 20 includes a first wiring structure 2011 for connecting the first type of connection terminals 4011 and the first conductive posts 331.

[0053] At least a portion of the first conductive post 331 serves as a power signal transmission conductive post. In conjunction with the setting of decoupling components, it can effectively improve the signal integrity of the semiconductor structure, especially signal and power integrity (SIPI).

[0054] In some embodiments, the plurality of conductive posts 33 may further include one or more second conductive posts 332 located outside all the first components 31, the second conductive posts 332 penetrating the first chip 32.

[0055] The second conductive post 332 is electrically connected to the second chip 41 through the wiring structure 201 of the first wiring structure layer 20.

[0056] like Figure 1 As shown, among the plurality of connection terminals 401 disposed on the surface of the second chip 41 facing the first wiring structure layer 20, there are second-type connection terminals 4012 that are connected to the plurality of second conductive posts 332 through the first wiring structure layer 20. At least a portion of these second-type connection terminals 4012 may be data signal connection terminals. Accordingly, the wiring structure 201 of the first wiring structure layer 20 includes a second wiring structure 2012 for connecting the first-type connection terminals 4011 and the second conductive posts 332.

[0057] It is understandable that the wiring structures in the first wiring structure layer 20 can be electrically isolated or electrically connected as needed.

[0058] In some embodiments, the second chip 41 is a data processing chip, such as at least one of a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0059] The first chip 32 is at least one of a data processing chip, an input / output chip (IO chip), and a memory chip (DDR chip). When the first chip 32 is a data processing chip, its processing function may differ from that of the second chip; for example, the first chip 32 may be a neural network processing unit (NPU).

[0060] Please continue to refer to Figure 1 As shown, the second chip layer 40 further includes a second component 42. The second component 42 can be arranged with the second chip 41 along the first direction L, and the first chip 32 is closer to the second component 42 than the first component 31.

[0061] In some embodiments, the second component 42 is a heat sink, such as a silicon chip without circuitry or a heat sink metal component (such as a copper structure).

[0062] It is understandable that when the second component 42 is used as a heat sink, it can guide and dissipate the heat generated during the operation of the first chip 32 and the second chip 41.

[0063] In some other embodiments, the second component 42 is a decoupling component.

[0064] The second component 42 can decouple the electrical signals of the second chip 41.

[0065] In some embodiments, the first chip 32 is connected to the second component 42 through the wiring structure of the first wiring structure layer 20. Accordingly, the wiring structure 201 of the first wiring structure layer 20 includes a third wiring structure 2013 electrically connected to the second component 42.

[0066] When the second component 42 is used as a heat sink, heat dissipation is more effective through the conduction of the wiring structure.

[0067] When the second component 42 is used as a decoupling component, electrical signal decoupling can be better achieved through the transmission of wiring structure.

[0068] In some embodiments, the orthographic projection of the second component 42 on the second wiring structure layer 10 overlaps with the orthographic projection of the first component on the second wiring structure layer 10, which helps to further ensure the compact arrangement of each component in the semiconductor structure.

[0069] In some embodiments, the edge of the second component 42 facing away from the second chip 41 can be flush with or approximately flush with the edge of the first chip 32 facing away from the first component 31, which is more conducive to controlling the volume of the semiconductor structure and ensuring the compactness of the arrangement of each component.

[0070] In some embodiments, the first chip layer 30 further includes a first encapsulation layer 34.

[0071] The first encapsulation layer 34 is located between the first wiring structure layer 20 and the second wiring structure layer 10, and encapsulates the first chip 32 and the first component 31.

[0072] In some embodiments, the first chip layer 30 may include a dielectric layer 36 located on the side of the first chip 32 facing the first wiring structure layer 20.

[0073] The first chip layer 30 may include a dielectric layer 35 located on the side of the first component 31 facing the first wiring structure layer 20.

[0074] Dielectric layers 35 and 36 may have corresponding openings and be filled with conductive material to achieve electrical connection with the wiring structure of the first wiring structure layer 20.

[0075] The dielectric layers 35 and 36, as well as the dielectric layer 202 of the first wiring structure layer 20 and the dielectric layer 102 of the second wiring structure layer 10, can be made of the same or similar dielectric materials. The dielectric materials can be polyimide (PI), benzocyclobutene (BCB), epoxy resin, etc.

[0076] In some embodiments, the first chip layer 30 further includes a soldering structure 37 for connecting the wiring structure 101 of the second wiring structure layer 10 to the solder pads of the first chip 32, and for connecting the wiring structure of the second wiring structure layer 10 to the solder pads of the first component 31. The soldering structure 37 may be a solder ball.

[0077] In some embodiments, the second chip layer 40 further includes a second encapsulation layer 44. The second encapsulation layer is located on the side of the first wiring structure layer 20 opposite to the second wiring structure layer 10, and at least encapsulates the second chip 41.

[0078] like Figure 1 As shown, when the second chip layer 40 includes the second component 42, the second encapsulation layer 44 also encapsulates the second component 42.

[0079] The surfaces of the second chip 41 and the second component 42 facing away from the first wiring structure layer 20 can be flush with the surface of the second encapsulation layer 44 on that side. Correspondingly, the surfaces of the second chip 41 and the second component 42 facing away from the first wiring structure layer 20 are exposed outside the second encapsulation layer 44. For example... Figure 1 As shown. Of course, in some other embodiments, the second encapsulation layer 44 may also cover the surface of the second chip 41 and the second component 42 that is away from the first wiring structure layer 20.

[0080] like Figure 1 As shown, in some embodiments, the second chip layer 40 further includes a soldering structure 45 for connecting the wiring structure 201 of the first wiring structure layer 20 to the solder pads of the second chip 41, and for connecting the wiring structure of the second wiring structure layer 10 to the solder pads of the second component 42. The soldering structure 45 may be a solder ball.

[0081] like Figure 1 As shown, in some embodiments, the second chip layer 40 includes an underfill adhesive 43. The underfill adhesive 43 fills at least the area between the second chip 41 and the first wiring structure layer 20, excluding the soldering structure, and also fills the area between the second component 42 and the first wiring structure layer 20, excluding the soldering structure.

[0082] In some embodiments, the decoupling component is an integrated capacitor or a deep trench capacitor.

[0083] like Figure 1 As shown, there are multiple first components 31, and each first component 31 can be an integrated capacitor, that is, an integrated passive device (IPD).

[0084] like Figure 1 As shown, in some embodiments, the semiconductor structure 100 further includes an external connection key 50 disposed on the side of the second wiring structure layer 10 opposite to the first chip layer 30, for electrically connecting to a structure outside the semiconductor structure 100. This external connection key 50 can be electrically connected to the wiring structure 101 of the second wiring structure layer 10.

[0085] It should be noted that the above semiconductor structure can be sequentially formed on a carrier substrate as a second wiring structure layer 10, a first chip layer 30, a first wiring structure layer 20, and a second chip layer 40. Finally, after removing the carrier substrate, an external connection key 50 is provided. The steps for forming the first chip layer 30 may include: setting a first chip 32 and a first component 31 on the second wiring structure layer 10, then encapsulating and thinning them until the surfaces of the first chip 32 and the first component 31 are exposed away from the second wiring structure layer 10, and then drilling holes to fill conductive material to form conductive pillars. Then, dielectric layers 35 and 36, and the encapsulation material surrounding the dielectric layers 35 and 36, are set to form the first chip layer. Alternatively, dielectric layers 35 and 36 can be first set on the corresponding first chip and first component, and after forming and thinning the first encapsulation layer, holes are drilled to form conductive pillars and conductive material in the dielectric layers 35 and 36. The steps for forming the second chip layer 40 may include: setting a second chip 41, a second component 42, and other devices on the side of the first wiring structure layer 20 opposite to the first chip layer 30, setting an underfill adhesive 43, and thereby forming a second encapsulation layer 44. The fabrication process steps of the first semiconductor structure 100 can be adaptively selected and adjusted as needed, and this application does not limit them.

[0086] Please refer to Figure 2 As shown, this application also provides a semiconductor structure 200, which is substantially the same as the semiconductor structure 100 described above. The similarities are described above and will not be repeated here. The difference lies in that the first component 31 of the semiconductor structure 200 is a single component, which can be a deep trench capacitor (DTC).

[0087] It is understood that in some other embodiments, when there are multiple first components 31 and sufficient space for their placement, at least one of the multiple first components 31 may be a deep-groove capacitor. Alternatively, when there is only one first component 31, that single first component 31 may also be an integrated capacitor.

[0088] It should be noted that the semiconductor structure 100 or semiconductor structure 200 provided in this application can be used as a system on a chip (SoC Die).

[0089] This application also provides an electronic device, which includes the semiconductor structure 100 or 200 or a similar semiconductor structure described above.

[0090] The electronic device may also include a circuit board.

[0091] In the semiconductor structure 100 or 200 or similar semiconductor structure, the side of the second wiring structure layer 10 facing away from the first chip layer 30 faces the circuit board and is electrically connected to the circuit in the circuit board.

[0092] The electronic device can be a mobile phone, a tablet, or other electronic products.

[0093] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0094] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: First wiring structure layer; The second wiring structure layer is disposed opposite to and spaced apart from the first wiring structure layer; A first chip layer is disposed between the first wiring structure layer and the second wiring structure layer; the first chip layer includes a first chip spaced apart in a first direction and at least one first component; the first chip is electrically connected to the second wiring structure layer, and the first component is a decoupling component; the first chip layer further includes a plurality of conductive pillars for electrically connecting the first wiring structure layer and the second wiring structure layer, at least a portion of the conductive pillars penetrating the at least one first component. The second chip layer is located on the side of the first wiring structure layer away from the first chip layer. The second chip layer includes a second chip, which is electrically connected to the first wiring structure layer. At least a portion of the orthographic projection of the first component on the second wiring structure layer overlaps with the orthographic projection of the second chip on the second wiring structure layer. A portion of the orthographic projection of the first chip on the second wiring structure layer overlaps with a portion of the orthographic projection of the second chip on the second wiring structure layer.

2. The semiconductor structure as described in claim 1, characterized in that, The plurality of conductive posts include a plurality of first conductive posts that penetrate the at least one first component; The second chip has a power signal connection terminal, wherein at least a portion of the plurality of the first conductive pillars are connected to the power signal connection terminal through the wiring structure of the first wiring structure layer.

3. The semiconductor structure as described in claim 2, characterized in that, The plurality of conductive pillars also include one or more second conductive pillars located outside all the first components, the second conductive pillars penetrating the first chip; The second conductive post is electrically connected to the second chip through the wiring structure of the first wiring structure layer.

4. The semiconductor structure according to claim 1, characterized in that, The first chip is at least one of a data processing chip, an input / output chip, and a storage chip, and the second chip is a data processing chip.

5. The semiconductor structure according to claim 1, characterized in that, The second chip layer also includes a second component, which is arranged along the first direction with the second chip, and the first chip is closer to the second component than the first component.

6. The semiconductor structure according to claim 5, characterized in that, The second component is a heat sink or a decoupling component.

7. The semiconductor structure according to claim 5, characterized in that, The orthographic projection of the second component on the second wiring structure layer overlaps with the orthographic projection of the first component on the second wiring structure layer; The first chip is connected to the second component through the wiring structure of the first wiring structure layer.

8. The semiconductor structure as described in claim 1, characterized in that, The first wiring structure layer is a rewiring layer, and the second wiring structure layer is a rewiring layer.

9. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a first encapsulation layer and a second encapsulation layer; The first encapsulation layer is located between the first wiring structure layer and the second wiring structure layer, and encapsulates the first chip and the first component; The second encapsulation layer is located on the side of the first wiring structure layer opposite to the second wiring structure layer, and at least encapsulates the second chip.

10. The semiconductor structure according to any one of claims 1 to 9, characterized in that, The decoupling components are integrated capacitors or deep-groove capacitors. Wherein, when at least one of the first components is a single component, the single first component is a deep-groove capacitor; when at least one of the first components is multiple components, each of the first components is an integrated capacitor.

11. The semiconductor structure according to any one of claims 1 to 9, characterized in that, The overlapping area of ​​the portion of the first chip projected onto the second wiring structure layer and the portion of the second chip projected onto the second wiring structure layer in the first direction is less than or equal to 2 mm.

12. An electronic device, characterized in that, The electronic device includes the semiconductor structure according to any one of claims 1-11.

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