Memory chip package and memory device having the same

Abstract

The application discloses a storage chip package and a storage device with the same. The storage chip package comprises a substrate, a solder joint and a plurality of storage chips. The substrate has a first surface and a second surface. The substrate also has a plurality of grooves which are opened in a first direction. The first direction is perpendicular to the thickness direction of the substrate. The grooves penetrate through the first surface and the second surface of the substrate. The solder joint is arranged on the first surface of the substrate and is arrayed on both sides of the grooves. Each storage chip is arranged in a corresponding chip placement area on the second surface. The grooves are in or pass through the chip placement area. The storage chips are electrically connected to the first surface of the substrate through wires which pass through the grooves. The storage chips are electrically connected to the first surface of the substrate through wires which pass through the grooves. The problems of poor heat dissipation caused by the mutual stacking of the storage chips and the problem of large delay caused by the long signal wiring length are solved. The read-write speed is improved while the capacity is increased.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a memory chip package and a storage device having the same. Background Technology

[0002] With the increasing application of memory chips, mobile devices, and consumer electronics products, WindowBallGridArray (WBGA) packaged products are also becoming more common.

[0003] In existing WBGA packages, the number of memory chips that can be installed is limited due to the fixed PCB area. The capacity of traditional single-chip packages is limited by the chip's own capacity and packaging technology. To increase the capacity of memory modules, under current conditions, increasing the capacity of each memory chip requires increasing the number of chips within the chip. The traditional solution involves mounting the bottom chip normally and flip-chip mounted on the back of the bottom chip. The top chip is connected to a conductive structure at the edge of the substrate via long gold wires and then led out through through-holes in the substrate. However, chip stacking leads to heat transfer between chips, resulting in poor heat dissipation. The operating temperature of the top chip is higher than that of the bottom chip, which affects operation during high-speed read / write operations. Furthermore, the long signal wiring length results in large parasitic inductance and impedance discontinuities, leading to significant delays at high speeds, making it difficult to meet speed requirements.

[0004] Therefore, how to increase read and write speeds while increasing capacity has become an urgent problem to be solved. Utility Model Content

[0005] This application provides at least one memory chip package and a memory device having the same, so as to improve read and write speeds while increasing capacity.

[0006] The first aspect of this application provides a memory chip package, including a substrate, solder joints, and a plurality of memory chips; the substrate has a first surface and a second surface, and the substrate also has a plurality of trenches formed along a first direction, the first direction being perpendicular to the thickness direction of the substrate, and the trenches penetrating the first surface and the second surface of the substrate; the solder joints are disposed on the first surface of the substrate and are arrayed on both sides of the trenches; each memory chip is disposed side by side in a corresponding chip placement area on the second surface, the trenches are in or through the chip placement area, and the memory chips are electrically connected to the first surface of the substrate through wires passing through the trenches.

[0007] A second aspect of this application provides a storage device including the storage chip package described in the first aspect above.

[0008] The above solution, by setting multiple memory chips on the second surface of the substrate and having multiple trenches penetrating the first and second surfaces, and electrically connecting the memory chips to the first surface of the substrate through wires passing through the trenches, alleviates the problems of poor heat dissipation caused by stacking memory chips and large delay caused by long signal wiring length, thereby improving both capacity and read / write speed.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0011] Figure 1 These are schematic diagrams of the structure of some embodiments of the memory chip package of this application; Figure 2 These are cross-sectional structural schematic diagrams of some embodiments of the memory chip package of this application; Figure 3 These are schematic diagrams of the structure of some other embodiments of the memory chip package of this application; Figure 4 This is a schematic diagram of the framework of the storage device in some embodiments of this application. Detailed Implementation

[0012] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0013] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0014] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "many" in this document means two or more. Moreover, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0015] Please see Figure 1The first aspect of this application provides a memory chip package 100, including a substrate 110, solder joints 120, and a plurality of memory chips 130; the substrate 110 has a first surface 111 and a second surface 112, and the substrate 110 also has a plurality of trenches 150 formed along a first direction (marked as X in the figure), the first direction being perpendicular to the thickness direction of the substrate 110, and the trenches 150 penetrating the first surface 111 and the second surface 112 of the substrate 110; the solder joints 120 are disposed on the first surface 111 of the substrate 110 and are arrayed on both sides of the trenches 150; each of the memory chips 130 is arranged side by side in a corresponding chip placement area on the second surface 112, the trenches 150 are in or through the chip placement area, and the memory chips 130 are electrically connected to the first surface 111 of the substrate 110 through wires 240 passing through the trenches 150.

[0016] The memory chip 130 may include dynamic random access memory (DRAM), static random access memory (SRAM), etc., such as double data rate synchronous dynamic random access memory (DDR SDRAM), etc. This application does not limit the type of memory chip 130.

[0017] The first direction can be parallel to the direction of one side of the substrate 110, such as... Figure 1 As shown. This application does not limit the extension direction of the trench 150.

[0018] It is worth mentioning that the solder joint 120 and the memory chip 130 are respectively disposed on different surfaces of the substrate 110, and the memory chip 130 is disposed above the trench 150. Figure 1 This is observed from above the memory chip package 100 in some embodiments of this application, and the memory chip package 100 is made transparent in order to show the bottom structure of the memory chip package 100.

[0019] Please combine Figure 2 .from Figure 2 As can be seen, multiple memory chips 130 are disposed on the substrate 110, and each memory chip 130 is disposed in parallel on the second surface 112 of the substrate 110 without being stacked on top of each other, thereby improving heat dissipation; the memory chips 130 are electrically connected to the first surface 111 of the substrate 110 through wires 240 passing through the trench 150, without having to go around the edge of the substrate 110, thereby shortening the trace length and reducing latency.

[0020] The above solution, by setting multiple memory chips 130 on the second surface 112 of the substrate 110, and the substrate 110 having multiple trenches 150 penetrating the first surface 111 and the second surface 112, allows the memory chips 130 to be electrically connected to the first surface 111 of the substrate 110 via wires 240 passing through the trenches 150. This shortens the signal path length, reduces parasitic inductance, and helps meet the latency requirements of DDR5 at a speed of 6.4Gbps, alleviating the high signal latency problem caused by long gold wires in traditional chip stacking solutions. Furthermore, the parallel arrangement of the memory chips 130 allows each chip to dissipate heat independently, resulting in a more balanced operating temperature, improving the heat dissipation efficiency and reliability of the package, and supporting the integration of multiple memory chips 130 on the same substrate 110 to increase capacity, thereby improving read and write speeds while increasing capacity.

[0021] In some embodiments, multiple chips can be connected via a fly-by topology.

[0022] Please refer to Figure 3 , Figure 3 An exemplary diagram illustrates the structure of a memory chip package 100 within the memory chip placement area 140, featuring a trench 150. Compared to Figure 1 The memory chip package 100 shown is... Figure 3 The trench 150 is covered by the storage chip placement area 140.

[0023] In some embodiments, please continue to refer to Figure 2 The substrate 110 also includes conductive terminals 220, which are disposed on the first surface 111 where a groove 150 is formed, thereby exposing the conductive terminals 220 through the groove 150, and electrically connecting the conductive terminals 220 to the solder joints 120 on both sides of the corresponding groove 150; the memory chip 130 is connected to the conductive terminals 220 through wires 240 passing through the groove 150 to electrically connect to the substrate 110.

[0024] Please combine Figure 1 ,from Figure 1 As can be seen, the first surface 111 of the substrate 110 has arrayed solder points 120 on both sides of the two trenches 150. The memory chip 130 can be connected to the conductive terminal 220 of the first surface 111 through the trench 150 below it, and electrically connected to the solder points 120 through the wiring, thereby bringing out the signal of the memory chip 130.

[0025] The conductive terminal 220 can be a gold finger or the like, and this application does not impose any restrictions.

[0026] The above solution, through the trench 150 design, allows the conductor 240 to directly pass through the trench 150 and connect to the conductive terminal 220, significantly shortening the signal path length, reducing parasitic inductance, meeting the latency requirements of DDR5 at a rate of 6.4Gbps, and avoiding the signal integrity problems caused by long gold wires in traditional chip stacking solutions. Simultaneously, the parallel arrangement of chips allows for independent heat dissipation of each chip, resulting in a more uniform operating temperature, improving the heat dissipation efficiency and reliability of the package, and supporting the integration of multiple chips on the same substrate 110 to increase capacity and achieve high-performance, high-density packaging.

[0027] In some embodiments, the memory chip 130 has pads, and when the memory chip 130 is disposed on the substrate 110, the pads are exposed through a trench 150, and the pads are electrically connected to the substrate 110 through a wire 240 passing through the trench 150.

[0028] like Figure 2 As shown, the surface of the memory chip 130 near the substrate 110 may have pads, and when the memory chip 130 is disposed on the substrate 110, the pads are exposed due to the presence of the trench 150 on the substrate 110, thereby connecting the pads on the memory chip 130 and the conductive terminals 220 exposed through the trench 150 on the first surface 111 of the substrate 110 through the wire 240, thus realizing the electrical connection between the memory chip 130 and the substrate 110.

[0029] When the memory chip 130 is mounted on the second surface 112 of the substrate 110, its pads are exposed inside the trench 150. The wire 240 can be gold wire, copper wire, etc., and this application does not limit the material of the wire 240.

[0030] The above solution, by exposing the pads in the trench 150 and allowing the conductors 240 to pass through the trench 150, significantly shortens the signal path and reduces parasitic inductance. This enables DDR5 to meet the high-speed read and write requirements at a latency of 6.4Gbps, and alleviates the signal quality degradation caused by long gold wires in traditional chip stacking solutions, as well as the poor heat dissipation caused by chip stacking.

[0031] In some embodiments, the substrate 110 further has a plurality of conductive vias 230, each conductive via 230 extending from the first surface 111 to the second surface 112; the solder joint 120 is electrically connected to the corresponding conductive via 230.

[0032] In some embodiments, the trench 150 passes through the memory chip placement area 140, and each trench 150 passes through two memory chip placement areas 140.

[0033] Combination Figure 1Each trench 150 passes through two memory chip placement areas 140, allowing the two memory chips 130 to be arranged side-by-side on the second surface 112 of the substrate 110 with the trench 150. The memory chips 130 can be electrically connected to the first surface 111 of the substrate 110 via wires 240 passing through the trench 150. Therefore, this solution significantly shortens the signal path and reduces parasitic inductance by exposing the pads in the trench 150 and allowing the wires 240 to pass through it. This enables DDR5 to meet high-speed read / write requirements at a latency of 6.4Gbps, alleviating the signal quality degradation caused by long gold wires and the poor heat dissipation caused by chip stacking in traditional chip stacking solutions.

[0034] In some embodiments, the substrate 110 has two trenches 150 formed along a first direction.

[0035] In some embodiments, the groove 150 is filled with molding material 260. Please refer to... Figure 2 The trench 150 may be filled with a molding material 260, such as epoxy resin or ceramic, and this application does not impose any restrictions on this. By molding the trench 150, the insulation between adjacent conductive structures can be improved, preventing short circuits.

[0036] In some embodiments, the memory chip 130 is bonded to the second surface 112 of the substrate 110. Figure 2 An adhesive 210 is provided between the memory chip 130 and the second surface 112 of the substrate 110, and the memory chip 130 can be bonded to the second surface 112 of the substrate 110 by the adhesive 210. The adhesive 210 can be conventional chip bonding adhesives in the art, and this application is not limited thereto.

[0037] In some embodiments, the memory chip package 100 may include four memory chips 130, which are respectively disposed in four chip placement areas on the second surface 112, and the chip placement areas are respectively penetrated by two rows of trenches 150.

[0038] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0039] A second aspect of this application provides a storage device 40, please refer to... Figure 4 The storage device 40 includes the storage chip package 100 in any of the above embodiments.

[0040] The storage device 40 may be a memory module, hard disk, etc., and the storage device 40 may have multiple storage chip packages 100. This application does not impose any restrictions.

[0041] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0042] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0043] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0044] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0045] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A memory chip package, characterized in that, include: A substrate has a first surface and a second surface, and the substrate also has a plurality of grooves formed along a first direction, the first direction being perpendicular to the thickness direction of the substrate, and the grooves penetrating the first surface and the second surface of the substrate. Solder joints are disposed on the first surface of the substrate and are arrayed on both sides of the trench; Multiple memory chips are arranged side-by-side in a corresponding chip placement area on the second surface. The trench is located in or through the chip placement area, and the memory chips are electrically connected to the first surface of the substrate via wires passing through the trench.

2. The memory chip package according to claim 1, characterized in that, The substrate further includes conductive terminals disposed on the first surface where the trench is formed, thereby exposing the conductive terminals through the trench and electrically connecting the conductive terminals to the solder joints on both sides of the corresponding trench. The memory chip is connected to the conductive terminal via a wire passing through the trench to be electrically connected to the substrate.

3. The memory chip package according to claim 1, characterized in that, The memory chip has pads, and when the memory chip is disposed on the substrate, the pads are exposed through the trenches, and the pads are electrically connected to the substrate through wires passing through the trenches.

4. The memory chip package according to claim 1, characterized in that, The substrate also has a plurality of conductive vias, each of which extends from the first surface to the second surface; the solder joints are electrically connected to the corresponding conductive vias.

5. The memory chip package according to claim 1, characterized in that, The trenches pass through the memory chip placement areas, and each trench passes through two memory chip placement areas.

6. The memory chip package according to claim 1, characterized in that, The substrate has two grooves formed along a first direction.

7. The memory chip package according to claim 1, characterized in that, The groove is filled with molding material.

8. The memory chip package according to claim 1, characterized in that, The memory chip is bonded to the second surface of the substrate.

9. The memory chip package according to claim 1, characterized in that, It includes four memory chips, which are respectively disposed in four chip placement areas on the second surface, and the chip placement areas are respectively penetrated by two columns of trenches.

10. A storage device, characterized in that, The memory chip package includes any one of claims 1 to 9.

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