Packaging structure

Abstract

The application discloses a packaging structure, which comprises an interposer, a plurality of chips connected by the interposer, the plurality of chips being located above the interposer, a bottom filling material layer filling gaps between the plurality of chips and between the plurality of chips and the interposer, and a mold sealing layer sealing the interposer, the plurality of chips and the bottom filling material layer, wherein the upper surface of the interposer is provided with a hole, and the bottom filling material layer and / or the mold sealing layer is formed with a protrusion matched with the hole, so as to enhance the bonding force between the layer provided with the protrusion in the bottom filling material layer and the mold sealing layer and the interposer. The packaging structure is provided to at least increase the bonding force of the packaging structure and avoid warping or delamination of the packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to a packaging structure. Background Technology

[0002] Figure 1 and Figure 2 A cross-sectional schematic diagram of a prior art packaging structure (hereinafter referred to as the first packaging structure 90 for ease of explanation) is shown. See also Figure 1 After wafer molding, a first package structure 90 is formed on the stage 100. The first package structure 90 includes: an interposer 210 and a plurality of chips 220 connected through the interposer 210, the plurality of chips 220 being located above the interposer 210; an underfill material layer 230 filling the gaps between the plurality of chips 220 and between the plurality of chips 220 and the interposer 210; and a molding layer 240 encapsulating the interposer 210, the plurality of chips 220, and the underfill material layer 230. See also Figure 2 After removing the de-carrier 100, the resulting first package structure 90 may experience warpage and delamination. However, in general, the wafer warpage needs to be controlled to <2mm during the manufacturing process. Therefore, the first package structure 90 needs to be processed to reduce warpage. Generally speaking, warpage behavior can be divided into convex warpage and concave warpage. Concave warpage can be understood as the two sides of the package structure curving downwards while the middle bulges upwards, while concave warpage is the middle of the package structure concave downwards while the two sides curve upwards. Different processing methods are required for these two different types of warpage. Figure 3 A schematic diagram of the prior art for processing the warped crying face is shown. Figure 4 This diagram illustrates a prior art method for addressing smile face warping. Currently, in the manufacturing process, during the removal of... Figure 1 After the stage 100 is used, a de-warp test is performed on the first package structure 90. If a teardrop warp is detected, it is adjusted by heating. See details below. Figure 3 A heat plate is placed below the first package structure 90, and a mass block 110 is placed above the first package structure 90 to reduce warpage. Figure 3 The diagram shows the heat 120 generated by the hot plate located below the first package structure 90. Typically, the mass block 110 will remain stationary above the first package structure 90 for up to one week. If a smiley face warping is measured, then... Figure 4 As shown, a balance film 130 is attached to the back of the first encapsulation structure 90 to reduce warpage. Utility Model Content

[0003] To address the above issues, this application proposes a packaging structure that at least increases the bonding strength of the packaging structure and prevents warping or delamination of the packaging structure.

[0004] The technical solution of this application is implemented as follows:

[0005] According to one aspect of this application, a packaging structure is provided, comprising: an interposer layer and a plurality of chips connected through the interposer layer, the plurality of chips being located above the interposer layer; an underfill material layer for filling the gaps between the plurality of chips and between the plurality of chips and the interposer layer; and a molding layer for encapsulating the interposer layer, the plurality of chips, and the underfill material layer; wherein, an aperture is provided on the upper surface of the interposer layer, and the underfill material layer and / or the molding layer are formed with protrusions that mate with the apertures to enhance the bonding force between the underfill material layer and the layer with protrusions in the molding layer and the interposer layer.

[0006] In some embodiments, the packaging structure further includes a redistribution layer disposed in an interposer layer, the redistribution layer being located beneath the plurality of chips.

[0007] In some embodiments, the packaging structure further includes a carrier disposed below the intermediary layer.

[0008] In some embodiments, the encapsulation structure further includes a release film disposed below the intermediary layer, and the molding layer further encapsulates the release film.

[0009] In some embodiments, the redistribution layer includes conductive vias and wires disposed in the intermediary layer.

[0010] In some embodiments, the plurality of chips includes a first chip and a second chip, and the vias laterally space a first wire electrically connected to the first chip and a second wire electrically connected to the second chip.

[0011] In some embodiments, there are multiple holes, and the holes are respectively arranged laterally on both sides of the redistribution layer.

[0012] In some embodiments, holes are disposed between multiple chips and accommodate protrusions in the bottom filler material layer.

[0013] In some embodiments, the hole is a blind hole that does not penetrate the interlayer.

[0014] In some embodiments, there are multiple holes, which are arranged laterally on both sides of the multiple chips and accommodate protrusions of the molding layer.

[0015] In some embodiments, the hole is a blind hole that does not penetrate the interlayer.

[0016] In some embodiments, the hole is a through-hole that penetrates the intermediary layer.

[0017] In some embodiments, the depth of the pore is in the range of 3 μm to 30 μm.

[0018] In some embodiments, the width of the hole gradually widens and then narrows from top to bottom.

[0019] In some embodiments, the width of the hole gradually narrows from top to bottom.

[0020] In some embodiments, the hole is a laser-cut hole.

[0021] In some embodiments, the opening formed by the hole on the upper surface of the intermediary layer is an elliptical opening.

[0022] In some embodiments, the opening formed by the hole on the upper surface of the intermediary layer is a circular opening.

[0023] In some embodiments, a wire is disposed below the hole.

[0024] According to another aspect of this application, a packaging structure is provided, comprising: an interposer layer and a plurality of chips connected through the interposer layer, the plurality of chips being located above the interposer layer; an underfill material layer for filling the gaps between the plurality of chips and between the plurality of chips and the interposer layer; and a molding layer for encapsulating the interposer layer, the plurality of chips, and the underfill material layer; wherein, an aperture is provided on the upper surface of the interposer layer, and the underfill material layer and / or the molding layer are embedded in the aperture.

[0025] The beneficial effects of the above technical solution include at least: increasing the bonding force of the packaging structure and preventing the packaging structure from warping or delaminating. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 and Figure 2 A cross-sectional schematic diagram of a prior art packaging structure is shown.

[0028] Figure 3 A schematic diagram of the prior art for processing the warped crying face is shown.

[0029] Figure 4 A schematic diagram of the prior art's method for handling smiley face warping is shown.

[0030] Figure 5 and Figure 6A cross-sectional schematic diagram of a packaging structure according to some embodiments of this application is shown.

[0031] Figure 7 and Figure 8 A cross-sectional schematic diagram of the packaging structure according to other embodiments of this application is shown.

[0032] Figure 9 A top view schematic diagram of a packaging structure according to some embodiments of this application is shown.

[0033] Figure 10 The packaging structure is shown in Figure 9 A schematic diagram of the cross-section in section AA.

[0034] Figure 11 and Figure 12 The packaging structure is shown in Figure 9 A schematic diagram of the cross-section in the BB section.

[0035] Figure 13 The packaging structure is shown in Figure 9 A schematic diagram of the cross-section in the CC section.

[0036] Figure 14 and Figure 15 A top view schematic diagram of a packaging structure according to some embodiments of this application is shown.

[0037] Figure 16 A top view schematic diagram of a packaging structure according to some embodiments of this application is shown.

[0038] Figure 17 and Figure 18 The packaging structure is shown in Figure 16 A schematic diagram of the cross-section in the DD section.

[0039] Figure 19 , Figure 20 , Figure 21 and Figure 22 The packaging structure is shown in Figure 16 A schematic diagram of the cross-section in the EE section.

[0040] Figure 23 and Figure 24 A top view schematic diagram of a packaging structure according to some embodiments of this application is shown.

[0041] Figure 25 , Figure 26 , Figure 27 , Figure 28 as well as Figure 29 A cross-sectional schematic diagram of the manufacturing process of a packaging structure according to some embodiments of this application is shown.

[0042] Figure 30 , Figure 31 , Figure 32 , Figure 33 as well as Figure 34 A cross-sectional schematic diagram of the manufacturing process of a packaging structure according to some embodiments of this application is shown.

[0043] Figure 35 , Figure 36 , Figure 37 , Figure 38 ,as well as Figure 39 A cross-sectional schematic diagram of the manufacturing process of a packaging structure according to some embodiments of this application is shown.

[0044] Figure 40 , Figure 41 , Figure 42 ,as well as Figure 43 A cross-sectional schematic diagram of the manufacturing process of a packaging structure according to some embodiments of this application is shown. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0046] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0047] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] Figure 5 and Figure 6 A cross-sectional schematic diagram of a packaging structure 200 according to some embodiments of this application is shown. See also Figure 5 and Figure 6The package structure 200 includes: an interposer 210 and a plurality of chips 220 connected through the interposer 210, the plurality of chips 220 being located above the interposer 210; an underfill material layer 230 filling the gaps between the plurality of chips 220 and between the plurality of chips 220 and the interposer 210; and a molding layer 240 encapsulating the interposer 210, the plurality of chips 220, and the underfill material layer 230; wherein, the upper surface of the interposer 210 is provided with a hole 211, and the underfill material layer 230 and / or the molding layer 240 are formed with protrusions that mate with the hole 211 to enhance the bonding force between the underfill material layer 230 and the layer with protrusions in the molding layer 240 and the interposer 210. Figure 5 This illustrates a case where the bottom filling material layer 230 has protrusions that mate with the holes 211, and Figure 6 The diagram illustrates a case where the molding layer 240 has protrusions that mate with the via 211. It is understood that by forming the via 211 in the interposer layer 210, some of the stress present in the interposer layer 210 can be released. Since the warpage of the package structure 200 largely originates from the interposer layer 210, forming the via 211 can correspondingly reduce the overall warpage of the package structure 200. Furthermore, because the underfill material layer 230 and / or the molding layer 240 have protrusions that mate with the via 211, the overall bonding strength of the package structure 200 can be improved, better suppressing delamination of the package structure 200. Generally, the location of the via 211 can be flexibly selected based on the wiring configuration in the interposer layer 210. In some embodiments, both the underfill material layer 230 and the molding layer 240 may also have protrusions that mate with the via 211.

[0049] See also Figure 5 and Figure 6 In some embodiments, the package structure 200 further includes a redistribution layer 250 disposed in the interposer layer 210. The redistribution layer 250 is located beneath the plurality of chips 220 and is electrically connected to the chips 220 via pads 280 located beneath the chips 220. The redistribution layer 250 may include conductive vias 251 and wires 253 disposed in the interposer layer 210. In some embodiments, the package structure 200 further includes a carrier 260 carrying the interposer layer 210, and the molding layer 240 further encapsulates the carrier 260. The carrier 260 may be disposed beneath the interposer layer 210 to enhance the overall rigidity of the package structure 200. Figure 7 and Figure 8 A cross-sectional schematic diagram of a packaging structure 200 according to other embodiments of this application is shown. Different from... Figure 5 and Figure 6 The package structure 200 shown is... Figure 7 and Figure 8In the encapsulation structure 200, the medium used to carry the interposer 210 is not the carrier 260, but a release film 270. Similarly, the molding layer 240 also encapsulates the release film 270. In some embodiments, the depth of the hole 211 is in the range of 3 μm to 30 μm, and the hole 211 may be a laser-cut hole. See also Figure 5 and Figure 7 Hole 211 is disposed between multiple chips 220 and accommodates a protrusion of the underfill material layer 230. Preferably, hole 211 is configured as a blind via that does not penetrate the interposer layer 210. See also... Figure 6 and Figure 8 This illustrates multiple holes 211, which are laterally disposed on both sides of the redistribution layer 250. Specifically, the holes 211 are laterally disposed on both sides of multiple chips 220 and accommodate protrusions of the molding layer 240. This can be illustrated as follows: Figure 6 and Figure 8 As shown, the holes 211 located on both sides of the multiple chips 220 are configured as through holes that penetrate the interposer layer 210, which can also be similar to Figure 5 and Figure 7 The holes 211 located on both sides of the multiple chips 220 are configured as blind vias that do not penetrate the interposer layer 210. Whether the holes 211 are configured to penetrate the interposer layer 210 or not will be described in detail later.

[0050] Figure 9 A top view of a package structure 200 according to some embodiments of this application is shown. For ease of understanding, the bottom filler layer 230 and the molding layer 240 above the interposer layer 210 are omitted, and the conductor 253 located in the interposer layer 210 is shown. Figure 10 The package structure 200 is shown in Figure 9 A schematic diagram of the cross-section in section AA. Figure 11 and Figure 12 The package structure 200 is shown in Figure 9 A schematic diagram of the cross-section in the BB section. Figure 13 The package structure 200 is shown in Figure 9 A schematic cross-sectional view of the CC section. See also: [link to CC section diagram]. Figure 9 Two chips 220 are shown (for ease of understanding, they will be shown in the image). Figures 10-13 (Illustrated as first chip 221 and second chip 222). See also Figure 9 In some embodiments, the via 211 spaces the two chips 220 and arranges them in a row. The opening formed by the via 211 on the upper surface of the interposer 210 can be an elliptical opening or a circular opening. See also Figure 9 and Figure 10A wire 253 may be disposed below the hole 211. In some embodiments, the width of the hole 211 gradually narrows from top to bottom. Preferably, the hole 211 does not pass through the wire 253 located between the first chip 221 and the second chip 222 to avoid damaging the circuit. See also Figure 9 and Figure 11 In some embodiments, the width of the hole 211 gradually narrows from top to bottom and can be deeper, for example, than... Figure 10 The hole 211 shown is deep, and the bottom of the hole 211 may extend beyond the first wire 2531 electrically connected to the first chip 221 and the second wire 2532 electrically connected to the second chip 222, and laterally space the first wire 2531 and the second wire 2532. See also Figure 9 and Figure 12 In some embodiments, even in cross-section, there is no wire 253 (e.g., connecting the first chip 221 and the second chip 222) below the hole 211. Figure 10 As shown in the diagram (wire 253), the lower boundary of the hole 211 may still not exceed the first wire 2531 and the second wire 2532 located below the first chip 221 and the second chip 222, respectively. See also Figure 9 and Figure 13 In some embodiments, the width of the hole 211 gradually widens and then narrows from top to bottom to provide better adhesion, for example, to allow the bottom filling material layer 230 to better adhere to the protrusions of the hole 211. Furthermore, when the hole 211... Figure 9 As illustrated, when a protrusion is positioned between two chips 220 and accommodates the underfill material layer 230, it is preferable that the via 211 does not penetrate the interposer layer 210 to avoid open circuits between the chips 220. Furthermore, it is understood that the depth and shape of the via 211 depend on the degree of warpage of the interposer layer 210 in which the via 211 is located. When the measured warpage of the interposer layer 210 is greater in that region, the via 211 can be configured to have a greater width and depth, while when the measured warpage of the interposer layer 210 is smaller in that region, the via 211 can be configured to have a smaller width and depth.

[0051] Figure 14 and Figure 15 A top view of a packaging structure 200 according to some embodiments of this application is shown. For ease of understanding, the bottom filler layer 230 and the molding layer 240 above the interposer layer 210 are omitted. See also Figure 14 In some embodiments, when viewed from above, the holes 211 may be formed as circular openings on the upper surface of the interposer layer 210 and disposed between the chips 220, and arranged in a regular vertical column. See also Figure 15In some embodiments, when viewed from above, the hole 211 may be formed as an integral rectangular opening on the upper surface of the interposer layer 210 and disposed between the chips 220.

[0052] Figure 16 A top view of a package structure 200 according to some embodiments of this application is shown. For ease of understanding, the bottom filler layer 230 and the molding layer 240 above the interposer layer 210 are omitted, and the conductor 253 located in the interposer layer 210 is shown. Figure 17 and Figure 18 The package structure 200 is shown in Figure 16 A schematic diagram of the cross-section in the DD section. Figure 19 , Figure 20 , Figure 21 and Figure 22 The package structure 200 is shown in Figure 16 A schematic cross-sectional view of the EE section. See also: [link to cross-section diagram]. Figure 16 Two chips 220 are shown (for ease of understanding, they will be shown in the image). Figures 17-22 (Illustrated as first chip 221 and second chip 222). See also Figure 16 In some embodiments, the holes 211 are located on both sides of the two chips 220 and arranged in two rows. The openings formed by the holes 211 on the upper surface of the interposer layer 210 can be elliptical or circular. See also Figure 17 and Figure 18 The diagram shows protrusions 211 for accommodating the molding layer 240, respectively disposed on both sides of the first chip 221 and the second chip 222. As previously described, the holes 211 can have different shapes, widths, and depths depending on the degree of warpage in different regions of the interposer layer 210. Furthermore, since it is not necessary to consider the wires 253 located between the first chip 221 and the second chip 222, the holes 211 can be similar to... Figure 6 and Figure 8 It penetrates the intermediary layer 210. See also... Figure 19 , Figure 20 , Figure 21 and Figure 22 Even if the conductor 253 located between the first chip 221 and the second chip 222 is not shown in the cross-section, the holes 211 respectively disposed on both sides of the first chip 221 and the second chip 222 can similarly have different shapes, widths, and depths to accommodate different degrees of warping of the interposer layer 210. Furthermore, the holes 211 can also similarly... Figure 6 and Figure 8 , penetrating the intermediary layer 210. Regarding Figure 19 , Figure 20 , Figure 21 and Figure 22 The setting of hole 211 can also be applied to the same way. Figure 16The setting of hole 211 in the FF section is not described in detail here.

[0053] Figure 23 and Figure 24 A top view of a packaging structure 200 according to some embodiments of this application is shown. For ease of understanding, the bottom filler layer 230 and the molding layer 240 above the interposer layer 210 are omitted. See also Figure 23 In some embodiments, when viewed from above, the holes 211 can be formed as circular openings on the upper surface of the interposer 210 and located on both sides of the chip 220, arranged in a regular vertical column. See also Figure 24 In some embodiments, when viewed from above, the hole 211 may be formed as an integral rectangular opening on the upper surface of the interposer layer 210 and located on both sides of the chip 220.

[0054] Embodiments of this application also provide a packaging structure 200, which can be referred to Figure 6 and Figure 7 To understand this, the package structure 200 includes: an interposer 210 and a plurality of chips 220 connected through the interposer 210, the plurality of chips 220 being located above the interposer 210; an underfill material layer 230 filling the gaps between the plurality of chips 220 and between the plurality of chips 220 and the interposer 210; and a molding layer 240 encapsulating the interposer 210, the plurality of chips 220, and the underfill material layer 230; wherein, the upper surface of the interposer 210 is provided with a hole 211, and the underfill material layer 230 and / or the molding layer 240 are embedded in the hole 211.

[0055] Figure 25 , Figure 26 , Figure 27 , Figure 28 as well as Figure 29 A schematic cross-sectional view of the packaging structure 200 according to some embodiments of this application is shown during the manufacturing process. See also Figure 25 An intermediary layer 210 is provided above the carrier 260, and a redistribution layer 250 is present within the intermediary layer 210. In some embodiments, the intermediary layer 210 may be similar to Figure 7 It is set on the release film 270. Figure 26 This illustrates connecting chip 220 to redistribution layer 250 via pads 280. Figure 27In this process, a stencil 400 is provided, and a laser 500 forms holes 211 on the interposer 210. It is understood that while it is preferable that the holes 211 do not penetrate the interposer 210, holes 211 formed in areas between chips 220 where there are no conductors 253 can penetrate the interposer 210 to further reduce warpage of the interposer 210. Of course, setting all holes 211 formed between chips 220 to not penetrate the interposer 210 improves process consistency and reduces the risk of open circuits. See now. Figure 28 An underfill material layer 230 is formed below and between chip 220, and in the hole 211. Figure 29 In the process, a molding layer 240 is formed to encapsulate the chip 220 to form a package structure 200.

[0056] Figure 30 , Figure 31 , Figure 32 , Figure 33 as well as Figure 34 A schematic cross-sectional view of the packaging structure 200 according to some embodiments of this application is shown during the manufacturing process. See also Figure 30 An intermediary layer 210 is provided above the carrier 260, and a redistribution layer 250 is present within the intermediary layer 210. In some embodiments, the intermediary layer 210 may be similar to Figure 7 It is set on the release film 270. Figure 31 This illustrates connecting chip 220 to redistribution layer 250 via pads 280. Figure 32 In this process, an underfill material layer 230 is formed below and between chip 220 and chip 220. See also Figure 33 A mask 400 is provided, and a hole 211 is formed on the interposer layer 210 by a laser 500. The hole 211 is formed on both sides of the chip 220. Figure 34 In the process, a molding layer 240 is formed to encapsulate the chip 220 and fill the vias 211 to form a package structure 200.

[0057] Figure 35 , Figure 36 , Figure 37 , Figure 38 ,as well as Figure 39 A schematic cross-sectional view of the packaging structure 200 according to some embodiments of this application is shown during the manufacturing process. See also Figure 35 An intermediary layer 210 is provided above the carrier 260, and a redistribution layer 250 is provided within the intermediary layer 210. Figure 36 A mask 400 is shown to form a hole 211 in the middle portion of the interposer layer 210. Figure 37 This illustrates connecting chip 220 to redistribution layer 250 via pads 280. Figure 38In this process, an underfill material layer 230 is formed below and between chips 220 and within holes 211. See also Figure 39 A molding layer 240 is formed to encapsulate the chip 220 to form a package structure 200.

[0058] Figure 40 , Figure 41 , Figure 42 ,as well as Figure 43 A schematic cross-sectional view of the packaging structure 200 according to some embodiments of this application is shown during the manufacturing process. See also Figure 40 An intermediary layer 210 is provided above the carrier 260, and a redistribution layer 250 is provided within the intermediary layer 210. Figure 41 A mask 400 is shown to form holes 211 on both sides of the interposer layer 210. Figure 42 This illustrates connecting chip 220 to redistribution layer 250 via pads 280, and forming an underfill material layer 230 beneath and between chips 220. See also Figure 43 A molding layer 240 is formed to encapsulate the chip 220 and fill the vias 211 to form a package structure 200.

[0059] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A packaging structure, characterized in that, include: An intermediary layer, and a plurality of chips connected through the intermediary layer, the plurality of chips being located above the intermediary layer; A bottom filling material layer fills the gaps between the plurality of chips and between the plurality of chips and the interposer layer; A molding layer encapsulates the interposer layer, the plurality of chips, and the underfill material layer. The upper surface of the intermediate layer is provided with a hole, and the bottom filling material layer and / or the molding layer are formed with protrusions that cooperate with the hole, so as to enhance the bonding force between the bottom filling material layer and the layer with the protrusion in the molding layer and the intermediate layer.

2. The packaging structure according to claim 1, characterized in that, It also includes a redistribution layer disposed in the intermediary layer, the redistribution layer being located beneath the plurality of chips.

3. The packaging structure according to claim 1, characterized in that, It also includes a carrier disposed below the intermediary layer.

4. The packaging structure according to claim 1, characterized in that, It also includes a release film disposed below the intermediate layer, and the sealing layer further encapsulates the release film.

5. The packaging structure according to claim 1, wherein, The plurality of chips includes a first chip and a second chip, and the hole laterally separates a first wire electrically connected to the first chip and a second wire electrically connected to the second chip.

6. The packaging structure according to claim 2, wherein, There are multiple holes, and the holes are respectively arranged laterally on both sides of the redistribution layer.

7. The packaging structure according to claim 1, wherein, The hole is a blind hole that does not penetrate the intermediate layer.

8. The packaging structure according to claim 1, wherein, There are multiple holes, and the holes are respectively arranged laterally on both sides of the multiple chips and accommodate the protrusions of the molding layer.

9. The packaging structure according to claim 8, wherein, The hole is a through-hole that penetrates the intermediary layer.

10. The packaging structure according to claim 1, wherein, The width of the hole gradually narrows from top to bottom.

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