Integrated circuit and integrated device

Abstract

The utility model provides an integrated circuit and integrated device, integrated circuit includes: substrate, including top surface, semiconductor device is on the substrate, interconnect structure covers the substrate and is coupled to semiconductor device, first conductive pad is coupled to interconnect structure, wherein first conductive pad has first upper surface, is located at higher than the first height of substrate top surface, and second upper surface, is located at higher than the second height of substrate top surface, wherein first height is greater than second height.

Description

Technical Field

[0001] This utility model relates to an integrated circuit and an integrated device. Background Technology

[0002] The semiconductor industry continuously improves the processing power and power consumption of integrated chips by shrinking the smallest feature size. Functional integrated chips can have widths of less than 10 micrometers. However, due to the shrinking feature size and the increased possibility of damaging smaller features, testing integrated chips becomes more difficult. Utility Model Content

[0003] This utility model provides an integrated circuit, including: a substrate having a top surface; a semiconductor device on the substrate; an interconnect structure covering the substrate and coupled to the semiconductor device; and a first conductive pad coupled to the interconnect structure, wherein the first conductive pad has a first upper surface at a first height above the top surface of the substrate and a second upper surface at a second height above the top surface of the substrate, wherein the first height is greater than the second height.

[0004] This utility model provides an integrated device, including: a substrate; a plurality of semiconductor devices above the substrate; an interconnect structure coupled to the plurality of semiconductor devices; an interlayer dielectric layer surrounding the interconnect structure, the interlayer dielectric layer including a first surface at a first height above the substrate, a second surface at a second height above the substrate, and a third surface at a third height above the substrate, the second height being smaller than the first height and the third height; and a first conductive pad including a lower surface conforming to the first surface, second surface, and third surface of the interlayer dielectric layer, and coupled to the interconnect structure through the first surface of the interlayer dielectric layer. Attached Figure Description

[0005] The best understanding of all aspects of this utility model can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E Cross-sectional views illustrating some embodiments of integrated circuits with conductive pads having upper surfaces of different heights.

[0007] Figure 2A , Figure 2B , Figure 2C and Figure 2D This diagram illustrates a top view of the redistribution layer as an intermediate step in a known-good-die (KGD) method for testing multiple integrated circuits at once.

[0008] Figure 3 Explanation after test Figure 2A The top view shows the conductive pads of multiple integrated circuits.

[0009] Figure 4 Cross-sectional views illustrating some embodiments of an integrated circuit coupled to a second integrated circuit via conductive pads.

[0010] Figure 5 Cross-sectional views illustrating some embodiments of through-holes coupled to conductive pads of an integrated device.

[0011] Figure 6 A top view illustrating some embodiments of the trenches introduced during the patterning of the conductive pads and redistribution layers of the integrated device.

[0012] Figures 7-9 , Figures 10A-10B , Figures 11-21 A series of cross-sectional views illustrating some embodiments of a method for forming an integrated device using the known-good-die (KGD) method.

[0013] Figure 22 The flowchart illustrates some embodiments of a method for forming an integrated device using the known-good-die (KGD) method. Detailed Implementation

[0014] This utility model provides many different embodiments or examples to implement different features of the utility model. Specific examples of components and configurations are described below to simplify the utility model. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of the utility model. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0016] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers for ease of explanation to distinguish different components of a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the components, and are not intended to describe corresponding components in different illustrated examples and / or examples not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in examples not shown.

[0017] With the development of integrated circuit technology, the compactness of circuits and features has been improved in various ways. The reduction in the size of circuit components leads to a reduction in the size of the formed circuits and semiconductor dies. The reduction in semiconductor die size increases the yield per wafer and improves the efficiency of the manufacturing process. However, testing a larger number of semiconductor dies becomes more time-consuming. Testing individual semiconductor dies produced from a single wafer can take several days, significantly reducing manufacturing throughput. There is a need for methods to test multiple semiconductor dies simultaneously to reduce the time required to test the formed integrated circuits, thereby improving the efficiency of the manufacturing process.

[0018] This invention provides a method for simultaneously testing multiple semiconductor dies. In the manufacturing process, circuit components and interconnect structures of multiple semiconductor dies are formed on a substrate. The interconnect structure includes multiple vias on the top surface of an interlayer dielectric layer. After forming the interconnect structure (and the surrounding interlayer dielectric layer), a redistribution layer is formed and patterned to couple the vias to multiple metal pads. The redistribution layer includes multiple conductors that couple corresponding vias of portions of the semiconductor dies (e.g., vias coupled to the same components of the semiconductor dies) together, allowing those portions of the semiconductor dies to be tested in parallel. Electrical tests (e.g., circuit probing tests) are then performed on the semiconductor dies using the metal pads and the conductors of the redistribution layer to determine if any coupled semiconductor dies have damaged or missing connections. If the tests show damaged connections or voltage or current higher than expected, that portion of the semiconductor die is not used to form the final circuit. In this way, hundreds of semiconductor dies can be coupled together and tested simultaneously, reducing the time to test a single semiconductor die wafer from days to hours, greatly increasing the throughput of the manufacturing process. The cost is that additional semiconductor dies are discarded when tests fail.

[0019] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E Cross-sectional views 100a, 100b, 100c, 100d, and 100e illustrate some embodiments of integrated circuits with conductive pads on upper surfaces of different heights.

[0020] Multiple semiconductor devices 104 are located on substrate 102. The multiple semiconductor devices 104 include one or more transistors (e.g., planar field-effect transistors, fin field-effect transistors, gate-all-around (GAA) devices, etc.), circuit components (e.g., resistors, capacitors, diodes, etc.), or similar components. The multiple semiconductor devices 104 are coupled to an interconnect structure 106. The interconnect structure 106 includes multiple line layers 108 and multiple via layers 110. In some embodiments, multiple contacts 112 couple the multiple semiconductor devices 104 to the interconnect structure 106. The interconnect structure is surrounded by an interlayer dielectric layer 114. In some embodiments, the multiple semiconductor devices 104 and the interconnect structure 106 are configured to form a light-emitting diode (LED) driving circuit.

[0021] Multiple conductive pads 116 are coupled to the interconnect structure through the uppermost via layer of multiple via layers 110. In some embodiments, some of the multiple conductive pads 116 are coupled to the interconnect structure through four or more vias. The multiple conductive pads 116 have a first upper surface 118 located at a first height 119 above the top surface 102a of the substrate 102, a second upper surface 120 located at a second height 121 above the top surface 102a of the substrate 102, and a third upper surface 122 located at a third height 123 above the top surface 102a of the substrate 102. In some embodiments, the first height 119 and the third height 123 are substantially the same. The second height 121 is smaller than the first height 119 and the third height 123. In some embodiments, the conductive pads 116 are coupled to the interconnect structure 106 at a first lower surface directly below the first upper surface 118 and a second lower surface directly below the third upper surface 122.

[0022] Multiple conductive pads 116 conform to the upper surface of the interlayer dielectric layer 114. Electrical testing (e.g., probe testing) of the integrated device (before the conductive pads are formed) using a known-good-die (KGD) method results in multiple trenches 124 extending between the uppermost vias 110a, and multiple protrusions 126 through which the uppermost vias 110a extend. The multiple conductive pads 116 extend to cover and conform to portions of the trenches 124, resulting in multiple conductive pads 116 having multiple upper surfaces of different heights (e.g., a first upper surface 118, a second upper surface 120, and a third upper surface 122).

[0023] like Figure 1B As shown in the cross-sectional view 100b, in some embodiments, a first conductive pad 116a of a plurality of conductive pads 116 may conform to the upper surface of a first trench 124a of a plurality of trenches 124, while a second conductive pad 116b of a plurality of conductive pads 116 may conform to the upper surfaces of a second trench 124b and a third trench 124c of a plurality of trenches 124. The conductive pads of the plurality of conductive pads 116 extend to cover and conform to the upper surfaces of any number of trenches 124 and protrusions 126 based on the design of the underlying semiconductor die. In some embodiments, the trenches 124 in the interlayer dielectric layer 114 depict a plurality of protrusions 126 extending from the interlayer dielectric layer 114 and including one or more uppermost vias 110a. For example, a single through-hole 110b in the uppermost through-hole 110a may couple a first conductive pad 116a to the interconnect structure 106 in a first protrusion 126a, while multiple through-holes may couple second conductive pads 116b to the interconnect structure 106 in a second protrusion 126b. In some embodiments, the uppermost through-hole 110a has a rectangular outline when viewed from a top view. In other embodiments, the uppermost through-hole 110a has a square or circular outline when viewed from a top view.

[0024] In some embodiments, vias coupled to the plurality of conductive pads 116 couple individual conductive pads to multiple conductive paths within the interconnect structure 106. Thus, the plurality of conductive pads 116 can function as additional line layers, extending horizontally across the interconnect structure to couple conductive paths otherwise separated by the interlayer dielectric layer 114. Furthermore, in some embodiments, certain protrusions 126 are not covered by the conductive pads among the plurality of conductive pads 116 and do not include vias.

[0025] like Figure 1C As shown in cross-sectional view 100c, in some embodiments, a first portion 128 of the plurality of trenches 124 has a wider width than a second portion 130 of the plurality of trenches 124. In some embodiments, portions of the plurality of trenches 124 extend from a first outer sidewall of the interlayer dielectric layer 114 to a second outer sidewall of the interlayer dielectric layer. That is, portions of the plurality of trenches 124 extend across the semiconductor die. In a further embodiment, the plurality of trenches partially extend across the semiconductor die and extend to one outer sidewall of the semiconductor die but not to the second outer sidewall of the semiconductor die. In some embodiments, the first portion 128 of the plurality of trenches 124 has a bottom surface at a fourth height 129 above the substrate 102, while the second portion 130 of the plurality of trenches 124 has a bottom surface at a fifth height 131 above the substrate 102, wherein the fourth height 129 is smaller than the fifth height 131.

[0026] In some embodiments, the interlayer dielectric layer 114 surrounding the interconnect structure 106 includes a first surface 115a at a sixth height 115b above the substrate, a second surface 117a at a seventh height 117b above the substrate, and a third surface 125a at an eighth height 125b above the substrate 102, wherein the seventh height 117b is smaller than the sixth height 115b and the eighth height 125b.

[0027] like Figure 1D As shown in the cross-sectional view 100d, in some embodiments, a plurality of protrusions 126 extend between the conductive pads of a plurality of conductive pads 116. In a further embodiment, a first portion of the plurality of protrusions 126 is a line segment extending along a first direction 132, while a second portion of the plurality of protrusions 126 is a line segment extending along a second direction 134 perpendicular to the first direction 132. The second line segment extends between the first line segments, based on a redistribution layer pattern for probe testing using known good die methods (see...). Figure 2A , Figure 2B , Figure 2C and Figure 2DFor example, the first protrusion 126a and the second protrusion 126b extend parallel to the third protrusion 126c and are intersected by a fourth protrusion 126d (shown in dashed lines) that extends perpendicularly to the first protrusion 126a, the second protrusion 126b and the third protrusion 126c.

[0028] like Figure 1E As shown in the cross-sectional view 100e, in some embodiments, this is an intermediate step prior to semiconductor die dicing (see...). Figure 21 Additional protrusions 136 extend between semiconductor dies. In some embodiments, additional protrusions 136 extend across a plurality of semiconductor dies in a first direction 132, and vertical protrusions 138 (shown in dashed lines) extend from additional protrusions 136 to semiconductor dies in a second direction 134.

[0029] Figure 2A , Figure 2B , Figure 2C and Figure 2D Top views 200a, 200b, 200c, and 200d illustrate the redistribution layers in the intermediate steps of the known-good-die (KGD) method for testing multiple integrated circuits at once.

[0030] like Figure 2A As shown in top view 200a, in some embodiments, a redistribution layer (RDL) 202 is formed on the interlayer dielectric layer 114 prior to the formation of a plurality of conductive pads 116 (shown in dashed lines). The RDL 202 couples vias of a plurality of semiconductor dies to each other and to a plurality of metal pads 204. In some embodiments, the plurality of metal pads are arranged on one or more sides of the wafer, and each metal pad is coupled to more than 100 semiconductor dies. The repeating pattern of the semiconductor dies allows more than 100 semiconductor dies to be tested simultaneously in subsequent probing tests. If a probing test of a set of interconnected semiconductor dies fails (e.g., the voltage or current between two metal pads is higher or lower than expected), the semiconductor die coupled to the metal pad 204 is discarded.

[0031] For example, first semiconductor die 140a, second semiconductor die 140b, and third semiconductor die 140c are located directly beneath two conductors of RDL 202, and their uppermost via 110a is coupled to the first conductor 202a and the second conductor 202b of RDL 202. When the first metal pad 204a coupled to the first conductor 202a and the second metal pad 204b coupled to the second conductor are probed, the voltage measured between the two pads is unexpectedly low. Therefore, first semiconductor die 140a, second semiconductor die 140b, third semiconductor die 140c, or another semiconductor die 140 coupled to the first conductor 202a and the second conductor 202b may have a faulty circuit component or improper connection, causing the semiconductor die coupled to the first conductor 202a and the second conductor 202b to be discarded. While this does reduce the yield of the wafer being tested, testing hundreds of semiconductor dies simultaneously reduces wafer testing time and increases the speed of the final chip manufacturing process.

[0032] RDL 202 is formed by depositing a conformal metal layer on the interlayer dielectric layer 114, and then patterning the conformal metal layer into RDL 202 and multiple metal pads 204 (see [link]). Figure 9 , Figure 10A and Figure 10B When the conformal metal layer is patterned, the material of the interlayer dielectric layer 114 beneath it is also removed, resulting in trenches 124 forming around RDL 202. Therefore, the multiple trenches 124 surrounding the vias in the uppermost layer of the multiple via layers 110 indicate that the KGD method has been performed.

[0033] like Figure 2B As shown in top view 200b, in some embodiments, the number of conductive pads 116 (not yet formed in this figure) in each semiconductor die 140 may be more or less than six, depending on the function and design of the semiconductor die 140. For example, as shown, the number of conductive pads 116 in each semiconductor die 140 may be four. Figure 2C As shown in the top view 200c, the conductors of RDL 202 may follow different patterns to more effectively utilize the limited space on the semiconductor die and increase the spacing between conductors, further isolating them from each other. For example... Figure 2D As shown in top view 200d, the conductors of RDL 202 may cross the semiconductor die 140 in a direction perpendicular to the uppermost via 110a. For example, the conductors of RDL 202 extend in a first direction 132, while the uppermost via 110a has its longest dimension extending in a second direction 134. It is understood that other conductor patterns can be used to couple corresponding vias of different semiconductor dies to a conductor of RDL 202 and one of the plurality of metal pads 204.

[0034] Figure 3 illustrate Figure 2A The conductive pads of multiple integrated circuits are shown in a top view 300 after testing.

[0035] After performing electrical tests, remove the RDL (see [link]). Figure 2A RDL 202), and a conductive pad 116 is formed on the uppermost via 110a (shown in dashed lines). The trench 124 and protrusion 126 resulting from the formation of RDL 202 remain on the upper surface of the interlayer dielectric layer 114, such that the conductive pad 116 has multiple upper surfaces of different heights. The protrusion 126 extends along the RDL (see RDL 202). Figure 2A Following the same path as 202), the groove 124 extends between the protrusions 126. For example, the first set of through holes 110a and the second set of through holes 110b are located directly below the first conductive pad 116a. The first protrusion 126a extends along the first set of through holes 110a, and the second protrusion 126b extends along the second set of through holes 110b in the first direction 132. The third protrusion 126c extends in the second direction 134 between the first protrusion 126a and the second protrusion 126b, resulting in the first, second, and third protrusions 126a, 126b, and 126c forming a "U" shape. One of the grooves 124 extends between the first protrusion 126a and the second protrusion 126b, filling the "U" shape. Based on RDL (see...) Figure 2A The conductive pad 116 has a unique protrusion extending into a "U" shape, as shown in pattern 202. In different RDLs (see...) Figure 2A In other embodiments of the 202) pattern or the uppermost via 110a pattern, the protrusions extend on the semiconductor die 140 in different patterns.

[0036] Figure 4 A cross-sectional view 400 illustrating an integrated circuit coupled to a second integrated circuit via a conductive pad in some embodiments is shown.

[0037] In some embodiments, a plurality of conductive pads 116 couple the interconnect structure 106 to a second interconnect structure 402. In some embodiments, the second interconnect structure 402 is coupled to a plurality of micro-LEDs 404, other suitable light-emitting devices, or any combination thereof disposed on the second interconnect structure 402. The second interconnect structure 402 is or includes a redistribution layer 403 that contacts the plurality of conductive pads 116. In some embodiments, one or more via layers extend between the redistribution layer 403 and the plurality of conductive pads 116. In other embodiments, the one or more via layers are omitted, and the redistribution layer 403 directly contacts the plurality of conductive pads 116.

[0038] In some embodiments, the plurality of micro LEDs 404 are or include a first electrode 406, a second electrode 408, and a semiconductor layer 410 extending between the first electrode 406 and the second electrode 408. In some embodiments, the first electrode 406 and the second electrode 408 are formed separately from the redistribution layer 403. In other embodiments, the first electrode 406 and the second electrode 408 are part of the redistribution layer 403.

[0039] In some embodiments, the first electrode 406 is or comprises a reflective conductive material, extends beneath the semiconductor layer 410, and acts as a reflector. In other embodiments, the first electrode 406 is or comprises a conductive material and / or does not act as a reflector. In some embodiments, the second electrode 408 covers the semiconductor layer 410. In a further embodiment, the second electrode 408 is or comprises a transparent conductive material, such as a transparent conducting oxide (TCO) (e.g., indium tin oxide (ITO)). In other embodiments, the second electrode 408 does not cover the semiconductor layer 410 and / or comprises a conductive material, such as gold (Au), copper (Cu), titanium (Ti), titanium nitride (TiN), aluminum (Al), or similar materials. In some embodiments, the semiconductor layer 410 covers the first electrode 406 and the second electrode 408. In other embodiments, the first electrode 406 is on a first side of the semiconductor layer 410, and the second electrode 408 is on a second side of the semiconductor layer 410 opposite to the first side. The semiconductor layer 410 is configured to emit light when current passes between the first electrode 406 and the second electrode 408.

[0040] Figure 5 This illustrates a through-hole cross-sectional view 500 coupled to the conductive pad of the integrated device in some embodiments.

[0041] In some embodiments, the uppermost via 110a is surrounded by a first barrier layer 502. The first barrier layer 502 extends around the bottom and sidewalls of the via. In some embodiments, the first barrier layer 502 has an uppermost surface substantially flush with the uppermost surface of the via. In some embodiments, the first barrier layer 502 is or comprises one or more tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), or other similar materials. The first barrier layer 502 is configured to separate the via from the interlayer dielectric layer 114, preventing via material from diffusing into the interlayer dielectric layer 114 material.

[0042] In some embodiments, the plurality of conductive pads 116 are separated from the interlayer dielectric layer 114 by a second barrier layer 504. The second barrier layer 504 covers the bottom surface of the conductive pads 116. In some embodiments, the second barrier layer 504 is or comprises one or more tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), or other similar materials. In some embodiments, the second barrier layer 504 is configured to attach the plurality of conductive pads 116 to the interlayer dielectric layer 114 and the uppermost via 110a.

[0043] In some embodiments, during an intermediate step, a third barrier layer 506 is formed on the conductive pad 116 and the interlayer dielectric layer to prevent interference with the dicing of the semiconductor die, transport of the semiconductor die, and attachment of the carrier wafer to the substrate (see [link to documentation]). Figure 1A 102) to cause damage to the semiconductor die during the process of transporting it. In some embodiments, the third barrier layer 506 is or comprises one or more aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), silicon nitride (Si3N4), titanium nitride (TiN), other similar materials, or combinations thereof.

[0044] Figure 6 A top view 600 illustrates the integrated conductive pads and trenches 124 introduced during redistribution layer patterning in some embodiments. In some embodiments, the width of the protrusion 126 is greater than the width of the trench 124. In a further embodiment, the protrusion 126 extends to a plurality of adjacent conductive pads 116. For example, Figure 6 The protrusion 126 shown extends from the first conductive pad 116a to the second conductive pad 116b. In some embodiments, the second upper surface 120 of the first conductive pad 116a extends from the first outer sidewall of the first conductive pad 116a to the second outer sidewall of the first conductive pad 116a.

[0045] Figures 7-9 , Figures 10A-10B and Figures 11-21 This section illustrates a series of cross-sectional views of some embodiments of forming integrated devices using the Known Good Die (KGD) method. Although Figures 7-9 , Figures 10A-10B and Figures 11-21 The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some actions described and / or illustrated may be omitted in whole or in part. Figure 10A The sectional view 1000a is along Figure 10B The line A-A' is taken in the top view 1000b.

[0046] like Figure 7As shown in cross-sectional view 700, a plurality of semiconductor devices 104 are formed on substrate 102. The plurality of semiconductor devices 104 include one or more transistors (e.g., planar field-effect transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) devices, etc.), circuit components (e.g., resistors, capacitors, diodes, etc.), or the like. Forming the plurality of semiconductor devices 104 includes forming the transistors and circuit components using one or more physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etching and implantation processes, or similar processes.

[0047] like Figure 8 As shown in cross-sectional view 800, in some embodiments, an interconnect structure 106 is formed over a plurality of semiconductor devices 104. The interconnect structure 106 includes a plurality of line layers 108, a plurality of via layers 110, and a plurality of contacts 112 coupling the interconnect structure 106 to the plurality of semiconductor devices 104. An interlayer dielectric layer 114 surrounds the plurality of line layers 108 and the plurality of via layers 110. In some embodiments, the plurality of line layers 108, the plurality of via layers 110, and the plurality of contacts 112 are or comprise one or more of aluminum (Al), copper (Cu), aluminum-copper alloys, tungsten (W), tantalum nitride (TaN), or the like. In some embodiments, the interlayer dielectric layer 114 is or comprises an insulating material, such as one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), or the like.

[0048] In some embodiments, the interconnect structure 106 is formed by depositing a portion 114a of an interlayer dielectric layer 114, etching openings corresponding to the line layer and via layer in the interlayer dielectric layer 114, forming a metal layer to fill the openings using one or more PVD, ALD, CVD, or similar methods, and then removing the portion of the metal layer above the upper surface of the portion of the interlayer dielectric layer 114. This method is repeated to form additional portions 114b, 114c of the interlayer dielectric layer until the interconnect structure 106 is completed. In some embodiments, multiple semiconductor devices 104 and the interconnect structure 106 are configured to form an LED driving circuit. In some embodiments, the uppermost via layer of multiple via layers 110 is formed using a single damascene process.

[0049] like Figure 9As shown in the cross-sectional view 900, a first conformal metal layer 902 is formed on the interconnect structure 106. The first conformal metal layer 902 is or contains one or more aluminum (Al), gold (Au), titanium (Ti), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), or the like. In some embodiments, the first conformal metal layer 902 is formed using one or more PVD, ALD, CVD, or similar methods.

[0050] like Figure 10A Sectional view 1000a and Figure 10B As shown in top view 1000b, a first mask 1004 is formed on substrate 102 and subsequently patterned. In some embodiments, the first mask 1004 comprises a photoresist and is patterned using a photolithography process. After the first mask 1004 is patterned, a first conformal metal layer (see...) is formed. Figure 9 The 902) is patterned to form an RDL 202 and a plurality of metal pads 204. The pattern of the RDL 202 is configured to couple the corresponding uppermost vias 110a in the discrete semiconductor die to each other and to one of the plurality of metal pads 204.

[0051] In some embodiments, patterning is performed using a dry etching process 1002. The dry etching process 1002 removes the first conformal metal layer not covered by the first mask 1004 (see...). Figure 9 (902) portion. In addition, the interlayer dielectric layer 114 is partially etched away by the dry etching process 1002, resulting in the formation of trenches 124 and protrusions 126 on the upper surface of the interlayer dielectric layer 114. The first mask 1004 is then removed.

[0052] After the first mask 1004 is removed, electrical tests are performed on the plurality of semiconductor dies 140. In some embodiments, the electrical tests are performed by probing the individual metal pads 204 coupled to the plurality of semiconductor dies 140 and measuring the voltage and current between the probed metal pads 204. The resulting measurements are used to determine the semiconductor dies to be retained after the dicing process and used in the final product.

[0053] like Figure 11 As shown in the sectional view 1100, RDL (see Figure 2A 202) and multiple metal pads (see 202) Figure 2B 204) is removed. In some embodiments, removal is performed using a combination of etching (e.g., dry or wet etching) and planarization processes (e.g., chemical mechanical planarization (CMP)). The removal process results in the exposure of the uppermost via 110a, while the protrusion 126 and trench 124 remain on the uppermost surface of the interlayer dielectric layer 114.

[0054] like Figure 12As shown in the cross-sectional view 1200, a second conformal metal layer 1202 is formed on the uppermost surface of the interlayer dielectric layer 114. In some embodiments, the second conformal metal layer 1202 is or comprises aluminum (Al), gold (Au), titanium (Ti), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), the like, or combinations thereof. The second conformal metal layer 1202 conforms to the protrusions 126 and trenches 124 on the uppermost surface of the interlayer dielectric layer 114, resulting in the second conformal metal layer 1202 having multiple upper surfaces at different heights above the substrate 102. In some embodiments, the second conformal metal layer 1202 is formed using a deposition process such as PVD, ALD, CVD, or similar.

[0055] like Figure 13 As shown in the cross-sectional view 1300, a second mask 1304 is formed over the interconnect structure 106 and subsequently patterned. In some embodiments, the second mask 1304 includes a photoresist and is patterned using photolithography. After the second mask 1304 is patterned, a second conformal metal layer (see...) is formed. Figure 12 The 1202) is patterned to form multiple conductive pads 116. The pattern of the multiple conductive pads 116 configured to couple the uppermost via 110a together is based on the layout of an integrated circuit.

[0056] In some embodiments, patterning is performed using a dry etching process 1302. The dry etching process 1302 removes the second conformal metal layer not covered by the second mask 1304 (see...). Figure 12 In some embodiments, the interlayer dielectric layer 114 is partially etched away by a dry etching process 1302, causing the trench 124 to extend further into the interlayer dielectric layer 114, and causing the first portion 128 of the trench 124 to have a height above the upper surface of the substrate 102 less than the height of the bottom upper surface of the second portion 130 of the trench 124 below the conductive pad 116. The second mask 1304 is then removed.

[0057] like Figure 14 As shown in cross-sectional view 1400, a third barrier layer 506 is formed over a plurality of conductive pads 116 and an interlayer dielectric layer 114. In some embodiments, the third barrier layer 506 is or is composed of the following materials: alumina (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), silicon nitride (Si3N4), titanium nitride (TiN), another similar material or combination thereof. In some embodiments, the third barrier layer 506 is formed using deposition processes such as PVD, ALD, CVD, etc.

[0058] like Figure 15As shown in the cross-sectional view 1500, an insulating layer 1502 is formed over the third barrier layer 506. In some embodiments, the insulating layer 1502 is or comprises an insulating material such as silicon dioxide (SiO2), silicon nitride (Si3N4), or the like. In some embodiments, the insulating layer 1502 is formed using a deposition process such as PVD, ALD, CVD, or similar, and then subsequently planarized using CMP or similar methods.

[0059] like Figure 16 As shown in the cross-sectional view 1600, a first carrier wafer 1602 is bonded to an insulating layer 1502. In some embodiments, the first carrier wafer 1602 is or comprises silicon, silicon germanium (SiGe) or the like, or comprises a silicon-on-insulator (SOI) substrate. In some embodiments, the first carrier wafer 1602 is bonded to the insulating layer 1502 using a direct bonding method.

[0060] like Figure 17 As shown in cross-sectional view 1700, a portion of substrate 102 is removed to achieve a specified thickness. In some embodiments, this portion of substrate 102 is removed using a polishing process. In some embodiments, the specified thickness is approximately between 3 and 10 micrometers, between 2 and 7 micrometers, between 4 and 13 micrometers, or in another similar range.

[0061] like Figure 18 As shown in cross-sectional view 1800, a second carrier wafer 1802 is bonded to a substrate 102. In some embodiments, the second carrier wafer 1802 is or comprises silicon, silicon germanium (SiGe), or the like, or comprises a silicon on insulator (SOI) substrate. The second carrier wafer 1802 is bonded to the substrate 102 by an adhesive layer 1804. The adhesive layer 1804 and the second carrier wafer 1802 are configured to... Figure 19 and Figure 20 The method steps shown involve holding the semiconductor die (see...). Figure 2A (140).

[0062] like Figure 19 As shown in the cross-sectional view 1900, the first carrier wafer (see...) Figure 16 1602) is removed from insulating layer 1502. In some embodiments, the first carrier wafer (see 1602) is removed from insulating layer 1502. Figure 16 1602) is removed using a grinding or thinning process. For example... Figure 20 As shown in the cross-sectional view 2000, in some embodiments, the insulating layer (see...) Figure 19 Remove 1502 from substrate 102. Remove the insulating layer (see 1502). Figure 19 (1502) exposes the third barrier layer 506. In some embodiments, the insulating layer (see 1502) Figure 19Part of 1502) is removed from the first carrier wafer (see 1502). Figure 16 The 1602) is removed in the same grinding or thinning process. In some embodiments, the insulating layer (see 1602) is removed. Figure 19 Part of 1502) uses the insulation layer (see Figure 19 The 1502 material is selectively removed using an etching process. In some embodiments, the insulating layer (see...) Figure 19 The 1502 layer is not removed, but instead serves as a dielectric layer surrounding the via layer to be formed later.

[0063] like Figure 21 As shown in the cross-sectional view 2100, openings are etched in the third barrier layer 506, and a second interconnect structure 402 is formed on a plurality of conductive pads 116. Subsequently, a micro-light-emitting diode 404 is formed on the second interconnect structure 402. In some embodiments, a plurality of semiconductor dies 140 are cut before the formation of the second interconnect structure 402 and the micro-light-emitting diode 404, separating the semiconductor dies 140 from each other. In some embodiments, the plurality of semiconductor dies 140 are cut using a selective etching process. The semiconductor dies 140 are then removed from the adhesive layer (see...) Figure 18 The 1804) is transferred (e.g., using a batch transfer technique) to form a second interconnect structure 402 and a micro-light-emitting diode 404. In some embodiments, portions of the semiconductor die 140 that fail electrical testing (or through a redistribution layer (see 1804)) are transferred to form a second interconnect structure 402 and a micro-light-emitting diode 404. Figure 2C 202) Electrically coupled to the semiconductor die 140 that failed the electrical test, a miniature light-emitting diode is not formed on the plurality of conductive pads 116. In other embodiments, the portion of the semiconductor die 140 that failed the electrical test forms a miniature light-emitting diode 404 on the plurality of conductive pads 116 before the defective die is discarded. In some embodiments, the plurality of miniature light-emitting diodes 404 are omitted, and other suitable light-emitting devices are formed on the plurality of conductive pads 116 instead.

[0064] Figure 22 Flowchart 2200 illustrates some embodiments of forming an integrated device using a known good die (KGD) method. While this method and other methods illustrated and / or described herein are illustrated as a series of actions or events, it should be understood that the invention is not limited to the illustrated sequence or actions. Therefore, in some embodiments, actions may be performed in a different order than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

[0065] In box 2202, a semiconductor device is formed on the substrate. An example illustration of this step can be found in [image / description]. Figure 7 .

[0066] In box 2204, an interconnect structure coupled to a semiconductor device and surrounded by an interlayer dielectric layer is formed on the substrate. The interconnect structure includes multiple vias located on the top surface of the interlayer dielectric layer. An illustrated example of this step can be found in [image / document / reference needed]. Figure 8 .

[0067] In box 2206, a first conformal metal layer is formed on the interlayer dielectric layer. An example illustration of this step can be found in [image / description]. Figure 9 .

[0068] In box 2208, the first conformal metal layer is patterned into a plurality of metal pads and a redistribution layer covering a plurality of vias. This patterning results in the formation of a first trench between the first vias and the second vias of the plurality of vias. An iconual example illustrating this step can be found in [link to icon]. Figure 10A .

[0069] In box 2210, electrical tests are performed on the redistribution layer and interconnect structure by probing the metal pads. An example illustration of this step can be found in [link to diagram]. Figure 10B .

[0070] In box 2212, remove the redistributed layer. An example icon illustrating this step can be found in [link to icon]. Figure 11 .

[0071] In box 2214, conductive pads are formed that couple to the first and second vias, wherein the conductive pads extend into the first trench. An iconual example illustrating this step can be found in [image / document / reference needed]. Figures 12-13 .

[0072] Some embodiments relate to an integrated circuit including: a substrate having a top surface; a semiconductor device on the substrate; an interconnect structure covering the substrate and coupled to the semiconductor device; and a first conductive pad coupled to the interconnect structure, wherein the first conductive pad has a first upper surface at a first height above the top surface of the substrate and a second upper surface at a second height above the top surface of the substrate, wherein the first height is greater than the second height.

[0073] In some embodiments, the first conductive pad has a third upper surface located at a third height, the third height being greater than the second height, and wherein the second upper surface is located between the first upper surface and the third upper surface.

[0074] In some embodiments, the second upper surface extends from the first sidewall of the first conductive pad to the second sidewall of the first conductive pad.

[0075] In some embodiments, the first conductive pad is coupled to the interconnect structure at a first lower surface directly below the first upper surface and at a second lower surface directly below the third upper surface.

[0076] In some embodiments, the first conductive pad is coupled to the interconnect structure via a topmost via, wherein the bottom surface of the first conductive pad extends below the upper surface of the topmost via.

[0077] In some embodiments, the integrated circuit further includes a second conductive pad coupled to the interconnect structure, wherein the second conductive pad includes a third upper surface located at a first height above the top surface of the substrate, and a fourth upper surface located at a second height above the top surface of the substrate.

[0078] Other embodiments relate to an integrated device including: a substrate; a plurality of semiconductor devices above the substrate; an interconnect structure coupled to the plurality of semiconductor devices; an interlayer dielectric layer surrounding the interconnect structure, the interlayer dielectric layer including a first surface at a first height above the substrate, a second surface at a second height above the substrate, and a third surface at a third height above the substrate, the second height being smaller than the first and third heights; and a first conductive pad including a lower surface conforming to the first, second, and third surfaces of the interlayer dielectric layer and coupled to the interconnect structure through the first surface of the interlayer dielectric layer.

[0079] In some embodiments, the integrated device further includes a second conductive pad located on the interlayer dielectric layer, wherein a trench in the interlayer dielectric layer separates the first conductive pad from the second conductive pad, and wherein the interlayer dielectric layer includes a fourth surface located at the bottom of the trench at a fourth height above the substrate, the fourth height not being higher than the second height.

[0080] In some embodiments, the first conductive pad has a first upper surface directly above the first surface of the interlayer dielectric layer, a second upper surface directly above the second surface of the interlayer dielectric layer, and a third upper surface directly above the third surface of the interlayer dielectric layer, wherein the second upper surface is located below the first upper surface and the third upper surface.

[0081] In some embodiments, the first conductive pad is coupled to the interconnect structure through the third surface of the interlayer dielectric layer.

[0082] In some embodiments, the first conductive pad is coupled to the interconnect structure through the first surface using a plurality of first vias, and wherein the first conductive pad is coupled to the interconnect structure through the third surface using a plurality of second vias.

[0083] In some embodiments, the second surface extends between the first surface and the third surface and extends to the outer wall of the interlayer dielectric layer.

[0084] Other embodiments relate to a method of forming an integrated device, the method comprising: forming a semiconductor device on a substrate; forming an interconnect structure on the substrate coupled to the semiconductor device and surrounded by an interlayer dielectric layer, the interconnect structure including a plurality of uppermost vias located on the top surface of the interlayer dielectric layer; forming a first conformal metal layer on the interlayer dielectric layer; patterning the first conformal metal layer into a plurality of metal pads and a redistribution layer covering the plurality of uppermost vias, the patterning causing a first trench to be formed between a first via and a second via of the plurality of uppermost vias; performing electrical testing on the redistribution layer and the interconnect structure by probing the metal pads; removing the redistribution layer; and forming conductive pads coupled to the first and second vias, wherein the conductive pads extend into the first trench.

[0085] In some embodiments, the method further includes cutting the substrate and the interconnect structure to separate multiple semiconductor dies from the integrated device.

[0086] In some embodiments, forming the conductive pad further includes: forming a second conformal metal layer on the plurality of uppermost vias; forming and patterning a mask on the second conformal metal layer, wherein the mask is patterned to expose a portion of the conformal metal layer located within a second trench formed during the patterning of the first conformal metal layer; and patterning the conformal metal layer to leave the conductive pad on the interlayer dielectric layer.

[0087] In some embodiments, after the conductive pad is formed, the first trench extends beyond the outer wall of the conductive pad.

[0088] In some embodiments, the method further includes: forming a barrier layer on the conductive pad and the interlayer dielectric layer; forming an insulating layer on the barrier layer; bonding a first carrier wafer to the insulating layer; removing a portion of the substrate to expose a lower surface of the substrate; bonding a second carrier wafer to the lower surface of the substrate; and removing the first carrier wafer, the insulating layer, and the barrier layer to expose the conductive pad and the interlayer dielectric layer.

[0089] In some embodiments, the second carrier wafer is bonded to the lower surface of the substrate using an adhesive layer.

[0090] In some embodiments, after the portion of the substrate is removed, the substrate has a thickness between 3 and 10 micrometers.

[0091] In some embodiments, the plurality of uppermost vias of the interconnect structure are formed using a single damascene process.

[0092] It should be understood that the terms "first," "second," "third," etc., used herein and in the claims are merely general identifiers for ease of explanation, used to distinguish different components of a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the components, and are not intended to describe corresponding components in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0093] The features of the above embodiments are beneficial for those skilled in the art to understand various aspects of the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design or modify other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit, characterized in that, include: Substrate, including the top surface; A semiconductor device is located on the substrate; An interconnect structure covers the substrate and is coupled to the semiconductor device; as well as A first conductive pad is coupled to the interconnect structure, wherein the first conductive pad has a first upper surface at a first height above the top surface of the substrate, and a second upper surface at a second height above the top surface of the substrate, wherein the first height is greater than the second height.

2. The integrated circuit according to claim 1, characterized in that, The first conductive pad has a third upper surface located at a third height, the third height being greater than the second height, and wherein the second upper surface is located between the first upper surface and the third upper surface.

3. The integrated circuit according to claim 2, characterized in that, The first conductive pad is coupled to the interconnect structure at a first lower surface directly below the first upper surface, and at a second lower surface directly below the third upper surface.

4. The integrated circuit according to claim 1, characterized in that, The first conductive pad is coupled to the interconnect structure via a topmost through-hole, wherein the bottom surface of the first conductive pad extends below the upper surface of the topmost through-hole.

5. The integrated circuit according to claim 1, characterized in that, It also includes a second conductive pad coupled to the interconnect structure, wherein the second conductive pad includes a third upper surface located at a first height above the top surface of the substrate, and a fourth upper surface located at a second height above the top surface of the substrate.

6. An integrated device, characterized in that, include: Substrate; Multiple semiconductor devices are located above the substrate; An interconnect structure is coupled to the plurality of semiconductor devices; An interlayer dielectric layer surrounds the interconnect structure and includes a first surface at a first height above the substrate, a second surface at a second height above the substrate, and a third surface at a third height above the substrate, wherein the second height is smaller than the first height and the third height. as well as A first conductive pad includes a lower surface that conforms to the first surface, the second surface, and the third surface of the interlayer dielectric layer, and is coupled to the interconnect structure through the first surface of the interlayer dielectric layer.

7. The integrated device according to claim 6, characterized in that, It also includes a second conductive pad located on the interlayer dielectric layer, wherein a trench in the interlayer dielectric layer separates the first conductive pad from the second conductive pad, and wherein the interlayer dielectric layer includes a fourth surface located at the bottom of the trench at a fourth height above the substrate, the fourth height not being higher than the second height.

8. The integrated device according to claim 6, characterized in that, The first conductive pad has a first upper surface directly above the first surface of the interlayer dielectric layer, a second upper surface directly above the second surface of the interlayer dielectric layer, and a third upper surface directly above the third surface of the interlayer dielectric layer, wherein the second upper surface is located below the first upper surface and the third upper surface.

9. The integrated device according to claim 6, characterized in that, The first conductive pad is coupled to the interconnect structure through the third surface of the interlayer dielectric layer.

10. The integrated device according to claim 9, characterized in that, The first conductive pad is coupled to the interconnect structure through the first surface using a plurality of first through holes, and wherein the first conductive pad is coupled to the interconnect structure through the third surface using a plurality of second through holes.

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