Semiconductor device and integrated circuit

Abstract

The application relates to a semiconductor device and an integrated circuit. The semiconductor device comprises a substrate, a conductor layer and a pin structure. The conductor layer is arranged on one side of the substrate along the thickness direction of the substrate and comprises a first conductor part, a second conductor part and a third conductor part which are spaced apart. The pin structure comprises a first pin, a second pin and a third pin which are spaced apart. The first pin is connected to the first conductor part, the second pin is connected to the second conductor part, and the third pin is connected to the third conductor part. The semiconductor device comprises a first device and a second device. Both the first device and the second device comprise the second conductor part. The semiconductor device and the integrated circuit provided by the application can simplify the manufacturing process while ensuring the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor equipment technology, and more particularly to a semiconductor device and integrated circuit. Background Technology

[0002] Semiconductor devices are the core of modern integrated circuits. Through different functional combinations, they can control the on / off state of integrated circuits at different locations based on their own performance, thereby realizing various tasks from simple logic to complex processing.

[0003] In actual manufacturing, semiconductor devices generally include a conductor, a chip, and corresponding leads and pins to achieve specific circuit functions. Utility Model Content

[0004] The semiconductor devices and integrated circuits provided in this application can simplify the manufacturing process while ensuring the performance of the semiconductor devices.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, including: substrate; A conductor layer is disposed on one side of the substrate along its thickness direction and includes a first conductor portion, a second conductor portion, and a third conductor portion spaced apart. The pin structure includes a first pin, a second pin, and a third pin spaced apart, wherein the first pin is connected to the first conductor portion, the second pin is connected to the second conductor portion, and the third pin is connected to the third conductor portion; The semiconductor device includes a first device and a second device, both of which include a second conductor portion.

[0006] In some embodiments, the first pin, the second pin, and the third pin are spaced apart along a first direction; The projection of the second conductor portion in the second direction overlaps with the projection of the first conductor portion in the second direction, and the projection of the second conductor portion in the second direction overlaps with the projection of the third conductor portion in the second direction. The first direction, the second direction, and the thickness direction intersect each other.

[0007] In some embodiments, the second conductor portion is further connected to a fourth pin, the first device includes a first pin and a second pin, and the second device includes a third pin and a fourth pin.

[0008] In some embodiments, the conductor layer further includes a fourth conductor portion that is spaced apart from the first conductor portion, the second conductor portion, and the third conductor portion, and the pin structure further includes a fifth pin connected to the fourth conductor portion; The first device includes the first pin, the second pin, and the fifth pin.

[0009] In some embodiments, the first device includes a first chip, the first chip includes a first electrode, a second electrode and a third electrode, the first chip is connected to the second conductor portion, and the second electrode is connected to the second conductor portion; The semiconductor device further includes a lead structure, which includes a first lead and a second lead. The first lead is connected between the fourth conductor portion and the first electrode, and the second lead is connected between the first conductor portion and the third electrode.

[0010] In some embodiments, the first device further includes a second chip, the second chip including a fourth electrode and a fifth electrode, the second chip being connected to the second conductor portion, and the fourth electrode being in contact with the second conductor portion; The lead structure also includes a third lead, which is connected between the fifth electrode and the first conductor portion.

[0011] In some embodiments, the second device includes a third chip, the third chip including a sixth electrode and a seventh electrode, the third chip being connected to the third conductor portion, and the sixth electrode being conductive to the third conductor portion; The semiconductor device further includes a lead structure, which includes a fourth lead connected between the seventh electrode and the second conductor portion.

[0012] In some embodiments, a packaging structure is further included, the packaging structure covering the conductor layer and the pin structure, a portion of the pin structure extending out of the packaging structure, the first pin, the second pin, and the third pin being spaced apart along a first direction, the first direction intersecting the thickness direction; The package structure has an inwardly recessed groove on the side where the pin structure extends, the groove being located between the first pin and the second pin along a first direction, and / or the groove being located between the second pin and the third pin along a first direction.

[0013] In some embodiments, the second conductor portion is further connected to a fourth pin, and the first pin, the second pin, the third pin, and the fourth pin are spaced apart along the first direction; The groove is located between the third pin and the fourth pin along the first direction.

[0014] Secondly, embodiments of this application provide an integrated circuit, including the aforementioned semiconductor device.

[0015] According to the semiconductor device and integrated circuit provided in this application, the semiconductor device, after packaging, includes a first device and a second device, which are two relatively independent functional devices. The semiconductor device includes a substrate, a conductor layer, and a lead structure. The substrate supports the remaining structures in the semiconductor device, providing a foundation for their arrangement. The conductor layer is disposed on one side of the substrate along its thickness direction, forming a part of the device. The conductor layer includes a first conductor portion, a second conductor portion, and a third conductor portion spaced apart. The lead structure includes a first pin, a second pin, and a third pin spaced apart. The first pin is connected to the first conductor portion, the second pin is connected to the second conductor portion, and the third pin is connected to the third conductor portion. The semiconductor device includes both a first device and a second device, both of which include a second conductor portion. That is, the second conductor portion constitutes part of both the first and second devices, serving as part of the circuitry within the first device and the second device, serving as part of the circuitry within the second device. The first and second devices share the second conductor portion, which reduces the number of conductor portions required during the fabrication of the conductor layer, simplifies the fabrication process, and improves fabrication efficiency. When the first device and the second device share the second conductor portion, the first device and the second device can also share the second pin connected to the second conductor portion. In the process of preparing the pin structure, the number of pin structures prepared is reduced, the preparation process is simplified, and the preparation efficiency is improved. Attached Figure Description

[0016] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of the front structure of a semiconductor device provided for some embodiments of this application; Figure 2 A schematic diagram of the back structure of a semiconductor device provided for some embodiments of this application; Figure 3 A schematic diagram of the first internal structure of a semiconductor device provided in some embodiments of this application; Figure 4 A schematic diagram of the second internal structure of a semiconductor device provided in some embodiments of this application; Figure 5 This application provides a schematic diagram of the structure of a substrate, conductor layer, and solder paste in a semiconductor device, as shown in some embodiments. Figure 6 This application provides a schematic diagram of the pin structure in a semiconductor device according to some embodiments; Figure 7 This application provides a schematic diagram of the structure of a substrate and conductor layer in a semiconductor device, as shown in some embodiments. Figure 8This is a schematic diagram of the back structure of a substrate in a semiconductor device provided for some embodiments of this application.

[0018] Marker explanation: 100. Semiconductor devices; 10. Substrate; 20. Conductor layer; 21. First conductor section; 22. Second conductor section; 23. Third conductor section; 24. Fourth conductor section; 30. Pin structure; 31. First pin; 32. Second pin; 33. Third pin; 34. Fourth pin; 35. Fifth pin; 40. Lead structure; 41. First lead; 42. Second lead; 43. Third lead; 44. Fourth lead; 51. First chip; 52. Second chip; 53. Third chip; 60. Packaging structure; A1, groove; G. Solder paste; X, the first direction; Y, the second direction.

[0019] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation

[0020] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] In actual fabrication, semiconductor devices generally include a conductor, a chip, and corresponding leads and pins to form a specific circuit.

[0023] In many cases, a packaged semiconductor device typically includes multiple devices with different functions. During the fabrication process, different devices have different conductors, chips, leads, and pins due to their different functions, making the actual fabrication process quite complicated.

[0024] In view of this, firstly, please refer to Figure 1 , Figure 2 and Figure 3 This application provides a semiconductor device 100, which includes a substrate 10, a conductor layer 20, and a lead structure 30. The conductor layer 20 is disposed on one side of the substrate 10 along its thickness direction and includes a first conductor portion 21, a second conductor portion 22, and a third conductor portion 23 spaced apart. The lead structure 30 includes a first lead 31, a second lead 32, and a third lead 33 spaced apart. The first lead 31 is connected to the first conductor portion 21, the second lead 32 is connected to the second conductor portion 22, and the third lead 33 is connected to the third conductor portion 23. The semiconductor device 100 includes a first device and a second device, both of which include a second conductor portion 22.

[0025] The semiconductor device 100 provided in this application embodiment includes a first device and a second device after packaging. The first device and the second device are two relatively independent functional devices. Taking common transistors and diodes as examples, in the semiconductor device 100 of this application embodiment, the first device and the second device can both be configured as diodes, or both can be configured as transistors, or the first device can be configured as a diode and the second device as a transistor. There are no restrictions on the type and function of the first device and the second device, only the number of devices is limited to two or more. It is understood that the semiconductor device 100 provided in this application embodiment includes at least two devices. The technical solution proposed in this application aims to simplify the manufacturing process of packaging two devices into a semiconductor device 100 while ensuring the performance of the two devices.

[0026] In related technologies, when a semiconductor device 100 includes two or more devices, the relevant structure of each device is in a relatively independent state. It is simply a matter of stacking multiple devices without changing the structure of each device. In terms of the fabrication process, multiple devices are fabricated separately. When multiple devices are packaged in the semiconductor device 100, the fabrication efficiency will be affected, and the more devices there are, the greater the impact will be.

[0027] Specifically, the semiconductor device 100 includes a substrate 10, a conductor layer 20, and lead structures 30. The substrate 10 supports the remaining structures in the semiconductor device 100 and provides a foundation for the arrangement of the remaining structures. The conductor layer 20 is disposed on one side of the substrate 10 along its thickness direction, and the conductor layer 20 forms part of the device. Generally, the conductor layer 20 includes a plurality of spaced conductor portions, and the lead structures 30 are connected to the conductor portions. The number of conductor portions and the number of lead structures 30 vary from device to device.

[0028] In this embodiment, the conductor layer 20 includes a first conductor portion 21, a second conductor portion 22, and a third conductor portion 23 spaced apart. The pin structure 30 includes a first pin 31, a second pin 32, and a third pin 33 spaced apart. The first pin 31 is connected to the first conductor portion 21, the second pin 32 is connected to the second conductor portion 22, and the third pin 33 is connected to the third conductor portion 23. The semiconductor device 100 includes a first device and a second device, both of which include a second conductor portion 22. That is, the second conductor portion 22 constitutes part of both the first and second devices, serving as part of the circuitry within the first and second devices. The shared second conductor portion 22 between the first and second devices reduces the number of conductor portions required for the formation of the conductor layer 20, simplifies the fabrication process, and improves fabrication efficiency.

[0029] Optionally, the pin structure 30 serves as an extension of the conductor portion. One end of the pin structure 30 is exposed within the packaged semiconductor device 100 to facilitate connection with other structures and achieve corresponding circuit functions. Specifically, the first pin 31 is connected to the first conductor portion 21. After packaging, the first conductor portion 21 and the end of the first pin 31 connected to the first conductor portion 21 are encapsulated internally, while the end of the first pin 31 away from the first conductor portion 21 is exposed for easy connection with other structures. When the first device and the second device share the second conductor portion 22, they can also share the second pin 32 connected to the second conductor portion 22. This reduces the number of pin structures 30 to be fabricated, simplifies the fabrication process, and improves fabrication efficiency.

[0030] For example, if both the first device and the second device are diodes, for a diode, two spaced conductor portions and two pins need to be formed on the substrate 10, and the pins are connected to the conductor portions accordingly.

[0031] In related technologies, when the first device and the second device are packaged into a single semiconductor device 100, four spaced conductor portions and four pins are provided. Two conductor portions and two pins form a group, and two groups of conductor portions and pins respectively form two diodes. In the fabrication process of related technologies, four spaced conductor portions need to be fabricated during the fabrication of the conductor portions, and four spaced pins need to be fabricated during the fabrication of the pin structure 30. The four pins and the four conductor portions are then connected accordingly.

[0032] In this embodiment, the first device and the second device can share a single conductor portion. That is, for two diodes, only three spaced conductor portions and three pins are needed. The first conductor portion 21 and the first pin 31 connected to it, along with the second conductor portion 22 and the second pin 32 connected to it, can form an input / output structure for a diode. Similarly, the third conductor portion 23 and the third pin 33 connected to it, along with the second conductor portion 22 and the second pin 32 connected to it, can also form an input / output structure for a diode. Based on the fabrication of the semiconductor device 100 structure in this embodiment, only three spaced conductor portions need to be fabricated during the fabrication of the conductor portions, and only three spaced pins need to be fabricated during the fabrication of the pin structure 30, with the three pins and the three conductor portions correspondingly connected. Compared to the fabrication process in related technologies, the semiconductor device 100 structure in this embodiment simplifies and reduces the number of conductor portions and pins to be fabricated, simplifying the fabrication process and improving fabrication efficiency.

[0033] In summary, in this embodiment, the semiconductor device 100, after packaging, includes a first device and a second device, which are two relatively independent functional devices. The semiconductor device 100 includes a substrate 10, a conductor layer 20, and a lead structure 30. The substrate 10 supports the remaining structures in the semiconductor device 100, providing a foundation for their arrangement. The conductor layer 20 is disposed on one side of the substrate 10 along its thickness direction, forming a portion of the device. The conductor layer 20 includes a first conductor portion 21, a second conductor portion 22, and a third conductor portion 23 spaced apart. The lead structure 30 includes a first lead 31, a second lead 32, and a third lead 33 spaced apart. The first lead 31 is connected to the first conductor portion 21, the second lead 32 is connected to the second conductor portion 22, and the third lead 33 is connected to the third conductor portion 23. The semiconductor device 100 includes both the first and second devices, and both the first and second devices include a second conductor portion 22. In other words, the second conductor portion 22 constitutes part of both the first and second devices, serving as a part of their respective circuitry. The sharing of the second conductor portion 22 between the first and second devices reduces the number of conductor portions required for fabrication during the formation of the conductor layer 20, simplifying the fabrication process and improving efficiency. Furthermore, the shared second conductor portion 22 also allows the first and second devices to share the second pin 32 connected to it. This reduces the number of pin structures 30 required for fabrication, simplifies the fabrication process, and improves fabrication efficiency.

[0034] In some embodiments, please refer to Figure 1 , Figure 2 and Figure 3 The first pin 31, the second pin 32, and the third pin 33 are spaced apart along the first direction X. The projection of the second conductor portion 22 in the second direction Y overlaps with the projection of the first conductor portion 21 in the second direction Y, and the projection of the second conductor portion 22 in the second direction Y overlaps with the projection of the third conductor portion 23 in the second direction Y. The first direction X, the second direction Y, and the thickness direction intersect each other.

[0035] In the semiconductor device 100, to facilitate subsequent connection with other structures, the pin structures 30 are spaced apart along the same direction. The first pin 31, the second pin 32, and the third pin 33 are spaced apart along the first direction X. However, considering that corresponding chips will also be disposed in the conductor section, and the area of ​​the conductor section is set in different forms depending on the area of ​​the corresponding chip.

[0036] In other words, the area and shape of the conductor portion need to accommodate both chip and pin connections. In this embodiment, the second conductor portion 22 is a shared portion of the first and second devices. The second conductor portion 22 is staggered in a certain direction with the first conductor portion 21 and the third conductor portion 23 to facilitate structural connections on the second conductor portion 22. Specifically, the projection of the second conductor portion 22 in the second direction Y overlaps with the projection of the first conductor portion 21 in the second direction Y, and the projection of the second conductor portion 22 in the second direction Y overlaps with the projection of the third conductor portion 23 in the second direction Y. At least a portion of the first conductor portion 21, the second conductor portion 22, and the third conductor portion 23 extends to one end of the substrate 10 along the second direction Y and is spaced apart in the first direction X to facilitate the corresponding connection of the first pin 31, the second pin 32, and the third pin 33.

[0037] During the connection process between the pin structure 30 and the conductor portion, multiple pins can be pre-connected to each other as an integral structure. After each pin is connected to the corresponding conductor portion, the multiple pins are then disconnected from each other to ensure the independence of each pin, thereby simplifying the fabrication process of the semiconductor device 100 and improving the fabrication efficiency of the semiconductor device 100.

[0038] In some embodiments, please refer to Figure 3 and Figure 4 The second conductor portion 22 is also connected to a fourth pin 34. The first device includes a first pin 31 and a second pin 32, and the second device includes a third pin 33 and a fourth pin 34.

[0039] Considering that the pins not only connect to the internal conductors of the semiconductor device 100, but also need to connect to other external structures, the pin configuration must facilitate connection with these other structures. Therefore, to improve the compatibility of the semiconductor device 100, the second conductor 22 is also provided with a fourth pin 34 to facilitate compatible connection with other structures.

[0040] Specifically, the first device includes a first pin 31 and a second pin 32, and the second device includes a third pin 33 and a fourth pin 34. Optionally, the first device may also have a first pin 31 and a fourth pin 34, and the second device may include a third pin 33 and a second pin 32. Optionally, the first device may include a first pin 31 and a second pin 32, and the second device may include a third pin 33 and a second pin 32, with the fourth pin 34 left idle. Optionally, the first device may include a first pin 31 and a fourth pin 34, and the second device may include a third pin 33 and a fourth pin 34, with the second pin 32 left idle.

[0041] It is understood that the fourth pin 34 is only provided to facilitate connection with other external structures and has no specific function for the semiconductor device 100. The addition of the fourth pin 34 on the second conductor portion 22 enables the semiconductor device 100 provided in this application embodiment to directly replace the semiconductor device 100 in the related art and connect with other external structures without being affected by the number of pins, thereby improving the adaptability of the semiconductor device 100 provided in this application embodiment.

[0042] In some embodiments, please refer to Figure 3 and Figure 4 The conductor layer 20 also includes a fourth conductor portion 24 that is spaced apart from the first conductor portion 21, the second conductor portion 22, and the third conductor portion 23. The pin structure 30 also includes a fifth pin 35 connected to the fourth conductor portion 24. The first device includes a first pin 31, a second pin 32, and a fifth pin 35.

[0043] The conductor layer 20 includes a first conductor portion 21, a second conductor portion 22, and a fourth conductor portion 24 spaced apart. The fourth conductor portion 24 is connected to a fifth pin 35. The first conductor portion 21 and the first pin 31, the second conductor portion 22 and the second pin 32, and the fifth conductor portion and the fifth pin 35 enable the first device to have a basic structure for forming a transistor, thereby increasing the variety and functionality of the semiconductor device 100 provided in the embodiments of this application.

[0044] In some embodiments, please refer to Figure 3 and Figure 4 The first device includes a first chip 51, which includes a first electrode, a second electrode, and a third electrode. The first chip 51 is connected to a second conductor portion 22, and the second electrode is electrically connected to the second conductor portion 22. The semiconductor device 100 also includes a lead structure 40, which includes a first lead 41 and a second lead 42. The first lead 41 is connected between the fourth conductor portion 24 and the first electrode, and the second lead 42 is connected between the first conductor portion 21 and the third electrode.

[0045] When the first device is configured as a transistor, it includes a first chip 51. The first chip 51 implements the basic function of a transistor, namely, the signal at the first terminal can control the switching between the second and third terminals. The first chip 51 is connected to the second conductor portion 22, and one of the terminals of the first chip 51 facilitates the conduction of the second conductor portion 22, extending through the second pin 32. Taking the second terminal of the first chip 51 being connected to the second conductor portion 22 as an example, the other two terminals of the first chip 51 are connected to the remaining conductor portions through the lead structure 40. For example, the first lead 41 connects the first terminal to the fourth conductor portion 24 and extends through the fifth pin 35; the second pin 32 connects the third terminal to the first conductor portion 21 and extends through the first pin 31. This allows the first device to form a transistor with the first pin 31, the second pin 32, and the fifth pin 35 as connection pins, where the signal at the fifth pin 35 can control the switching between the first pin 31 and the second pin 32.

[0046] In some embodiments, please refer to Figure 3 and Figure 4 The first device also includes a second chip 52, which includes a fourth electrode and a fifth electrode. The second chip 52 is connected to the second conductor portion 22, and the fourth electrode is conductive to the second conductor portion 22. The lead structure 40 also includes a third lead 43, which is connected between the fifth electrode and the first conductor portion 21.

[0047] Furthermore, the first device may also include a second chip 52, which is also connected to the second conductor portion 22, forming a parallel circuit with the first chip 51. Based on the first chip 51 performing the basic function of a transistor, and the second chip 52 performing the basic function of a diode, connecting the second chip 52 in parallel with the first chip 51 allows for a certain degree of reverse surge protection for the first chip 51, which performs the basic function of a transistor, through the unidirectional conduction characteristic of the diode.

[0048] Specifically, the second chip 52 includes a fourth electrode and a fifth electrode, which have forward conduction and reverse cutoff characteristics. When the second chip 52 is connected to the second conductor portion 22, the fourth electrode is conductive to the second conductor portion 22 and extends through the second pin 32 or the fourth pin 34; the third lead 43 conducts between the fifth electrode and the first conductor portion 21 and extends through the first pin 31. After the semiconductor device 100 is packaged, the first device includes two chips arranged in parallel, and the unidirectional conduction characteristic of the diode can provide a certain degree of protection for the transistor.

[0049] In some embodiments, please refer to Figure 3 and Figure 4The second device includes a third chip 53, which includes a sixth electrode and a seventh electrode. The third chip 53 is connected to the third conductor portion 23, and the sixth electrode is electrically connected to the third conductor portion 23. The semiconductor device 100 also includes a lead structure 40, which includes a fourth lead 44 connected between the seventh electrode and the second conductor portion 22.

[0050] The second device can be configured as a diode. The second device includes a third chip 53, which has a sixth terminal and a seventh terminal, exhibiting forward conduction and reverse cutoff characteristics. When the third chip 53 is connected to the third conductor portion 23, the sixth terminal conducts through the third conductor portion 23 and extends outwards through the third pin 33. The fourth lead 44 conducts between the seventh terminal and the second conductor portion 22 and extends outwards through the second pin 32 or the fourth pin 34, thereby realizing the diode function of the second device.

[0051] In some embodiments, please refer to Figure 1 , Figure 3 and Figure 4 The semiconductor device 100 also includes a package structure 60, which covers the conductor layer 20 and the lead structure 30. A portion of the lead structure 30 extends out of the package structure 60. A first lead 31, a second lead 32, and a third lead 33 are spaced apart along a first direction X, which intersects the thickness direction. A groove A1 is formed inwardly recessed on the side of the lead structure 30 where it extends. The groove A1 is located between the first lead 31 and the second lead 32 along the first direction X, and / or, the groove A1 is located between the second lead 32 and the third lead 33 along the first direction X.

[0052] After the conductor layer 20, chip, lead structure 40, and pin structure 30 form a specific circuit, the package structure 60 covers and encapsulates the conductor layer 20, lead structure 40, and pin structure 30 to ensure insulation between unconnected structures. To facilitate the connection of the semiconductor device 100 with other structures, the end of the pin structure 30 that is not connected to the conductor layer is outside the package structure 60. That is, after the semiconductor device 100 is packaged, only a few pins are exposed to facilitate connection with other structures.

[0053] Specifically, in this embodiment, the semiconductor device 100 includes at least a first device and a second device, and the pin structure 30 includes at least a first pin 31 connected to the first conductor portion 21, a second pin 32 connected to the second conductor portion 22, and a third pin 33 connected to the third conductor portion 23. Partial structures of the first pin 31, the second pin 32, and the third pin 33 are exposed in the package structure 60 and spaced apart along the first direction X. To ensure the insulation reliability of the partial structures of the first pin 31, the second pin 32, and the third pin 33 along the first direction X, the package structure 60 has a recessed groove A1 on the side where the pin structure 30 extends. The groove A1 increases the creepage distance between adjacent pins, reduces the probability of arcing caused by water vapor and pollutant particles in the environment, and ensures the performance of the semiconductor device 100.

[0054] When the semiconductor device 100 includes a first conductor portion 21, a second conductor portion 22, and a third conductor portion 23, with the first conductor portion 21 connected to a first pin 31, the second conductor portion 22 connected to a second pin 32, and the third conductor portion 23 connected to a third pin 33, the groove A1 can be disposed between the first pin 31 and the second pin 32 along the first direction X, or the groove A1 can be disposed between the second pin 32 and the third pin 33 along the first direction X. Preferably, the groove A1 is disposed between pin structures 30 connected to different conductor portions to reduce the probability of arcing caused by water vapor pollution particles in the environment on adjacent pin structures 30 connected to different conductor portions, thereby ensuring the performance of the semiconductor device 100.

[0055] In some embodiments, please refer to Figure 1 , Figure 3 and Figure 4 The second conductor portion 22 is also connected to a fourth pin 34. The first pin 31, the second pin 32, the third pin 33, and the fourth pin 34 are spaced apart along the first direction X. The groove A1 is located between the third pin 33 and the fourth pin 34 along the first direction X.

[0056] When the semiconductor device 100 includes a first conductor portion 21, a second conductor portion 22, a third conductor portion 23, and a fourth conductor portion 24, with the first conductor portion 21 connected to a first pin 31, the second conductor portion 22 connected to a second pin 32 and a fourth pin 34, and the third conductor portion 23 connected to a third pin 33, the groove A1 can be disposed between the first pin 31 and the second pin 32 along the first direction X, or the groove A1 can be disposed between the third pin 33 and the fourth pin 34 along the first direction X. The groove A1 can be omitted between adjacent pin structures 30 connected to the same conductor portion, and only disposed between pin structures 30 connected to different conductor portions. This reduces the probability of arcing caused by water vapor contamination particles in the environment affecting adjacent pin structures 30 connected to different conductor portions, thus ensuring the performance of the semiconductor device 100.

[0057] Please see Figures 1 to 8 In the fabrication process of the semiconductor device 100 provided in this application embodiment, the first device and the second device share a common conductor portion. This allows for the fabrication of a relatively small number of conductor portions, simplifying the fabrication process and improving efficiency. After the conductor portions are formed, solder paste G is applied at different positions on different conductor portions to facilitate the subsequent connection of the chip and the lead structure 30. During the connection of the lead structure 30 to the conductor portion, multiple leads can be interconnected into a single structure so that multiple leads simultaneously connect to their respective conductor portions. Then, the multiple leads can be disconnected to form relatively independent structures. After the chip and the lead structure 30 are connected to the conductor portion, a lead structure 40 is connected between the chip and the corresponding lead structure 30 to complete the relevant circuit connection. Subsequently, the conductor portion, chip, lead structure 30, and lead structure 40 are packaged using a packaging structure 60, and a groove A1 is provided at the desired position on the packaging structure 60 to fabricate the semiconductor device 100 provided in this application embodiment.

[0058] Secondly, embodiments of this application provide an integrated circuit, including the semiconductor device 100 provided in any embodiment of the first aspect of this application. The integrated circuit includes all the technical features of the semiconductor device 100 and has all the technical effects of the semiconductor device 100, which will not be repeated here.

[0059] Although the present invention has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of the invention. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: substrate; A conductor layer is disposed on one side of the substrate along its thickness direction and includes a first conductor portion, a second conductor portion, and a third conductor portion spaced apart. The pin structure includes a first pin, a second pin, and a third pin spaced apart, wherein the first pin is connected to the first conductor portion, the second pin is connected to the second conductor portion, and the third pin is connected to the third conductor portion; The semiconductor device includes a first device and a second device, both of which include a second conductor portion.

2. The semiconductor device according to claim 1, characterized in that, The first pin, the second pin, and the third pin are spaced apart along a first direction; The projection of the second conductor portion in the second direction overlaps with the projection of the first conductor portion in the second direction, and the projection of the second conductor portion in the second direction overlaps with the projection of the third conductor portion in the second direction. The first direction, the second direction, and the thickness direction intersect each other.

3. The semiconductor device according to claim 1, characterized in that, The second conductor portion is also connected to a fourth pin. The first device includes a first pin and a second pin, and the second device includes a third pin and a fourth pin.

4. The semiconductor device according to claim 1, characterized in that, The conductor layer further includes a fourth conductor portion that is spaced apart from the first conductor portion, the second conductor portion and the third conductor portion, and the pin structure further includes a fifth pin connected to the fourth conductor portion; The first device includes the first pin, the second pin, and the fifth pin.

5. The semiconductor device according to claim 4, characterized in that, The first device includes a first chip, the first chip includes a first electrode, a second electrode and a third electrode, the first chip is connected to the second conductor portion, and the second electrode is connected to the second conductor portion; The semiconductor device further includes a lead structure, which includes a first lead and a second lead. The first lead is connected between the fourth conductor portion and the first electrode, and the second lead is connected between the first conductor portion and the third electrode.

6. The semiconductor device according to claim 5, characterized in that, The first device further includes a second chip, which includes a fourth electrode and a fifth electrode. The second chip is connected to the second conductor portion, and the fourth electrode is in contact with the second conductor portion. The lead structure also includes a third lead, which is connected between the fifth electrode and the first conductor portion.

7. The semiconductor device according to claim 1, characterized in that, The second device includes a third chip, the third chip including a sixth electrode and a seventh electrode, the third chip being connected to the third conductor portion, and the sixth electrode being electrically connected to the third conductor portion; The semiconductor device further includes a lead structure, the lead structure including a fourth lead, the fourth lead being connected between the seventh electrode and the second conductor portion.

8. The semiconductor device according to claim 1, characterized in that, It also includes a packaging structure that covers the conductor layer and the pin structure, with a portion of the pin structure extending out of the packaging structure. The first pin, the second pin, and the third pin are spaced apart along a first direction, which intersects the thickness direction. The package structure has an inwardly recessed groove on the side where the pin structure extends, the groove being located between the first pin and the second pin along a first direction, and / or the groove being located between the second pin and the third pin along a first direction.

9. The semiconductor device according to claim 8, characterized in that, The second conductor portion is also connected to a fourth pin, and the first pin, the second pin, the third pin and the fourth pin are spaced apart along the first direction; The groove is located between the third pin and the fourth pin along the first direction.

10. An integrated circuit, characterized in that, Includes the semiconductor device according to any one of claims 1-9.

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