Chip package structure

Abstract

This utility model discloses a chip packaging structure, including a first chip and a circuit board electrically connected. The circuit board includes a first surface, a mounting groove, and a first soldering area. The mounting groove is recessed from the first surface, and the first soldering area is disposed on the bottom surface of the mounting groove. The first chip is disposed on the first surface. At least one second chip is disposed in the mounting groove. The second chip includes a second functional surface and a second pad. The second pad is disposed on the second functional surface, which is opposite to the bottom surface of the mounting groove. The second pad is electrically connected to the first soldering area. The second chip is located within the mounting groove along the height direction, reducing space occupation and decreasing the size of the chip packaging structure.

Description

Technical Field

[0001] This utility model relates to the field of chip manufacturing and packaging, and in particular to a chip packaging structure. Background Technology

[0002] With the rapid development of various cutting-edge technologies, the demand for computing power is exploding, placing higher demands on chip performance, energy efficiency, and integration. Traditional multi-chip two-dimensional planar integrated packaging modes result in large package sizes, which cannot meet the requirements for miniaturization and thinning. In existing technologies, multi-chip vertical stacking packaging is also widely used, but it also occupies a large space along the height direction, resulting in a large package structure size. Utility Model Content

[0003] One of the objectives of this invention is to provide a chip packaging structure to solve the technical problem of large size in existing multi-chip packaging structures.

[0004] To achieve one of the above-mentioned objectives of the utility model, one embodiment of the present utility model provides a chip packaging structure, including: a first chip; The circuit board is electrically connected to the first chip; the circuit board includes a first surface, a mounting groove and a first soldering area, the mounting groove is recessed from the first surface, the first soldering area is disposed on the bottom surface of the mounting groove, and the first chip is disposed on the first surface; At least one second chip is disposed in the mounting slot. The second chip includes a second functional surface and a second pad. The second pad is disposed on the second functional surface, which is opposite to the bottom surface of the mounting slot. The second pad is electrically connected to the first soldering area.

[0005] As a further improvement of one embodiment of the present invention, the surface of the second chip facing away from the second pad is not higher than the first surface.

[0006] As a further improvement of one embodiment of the present invention, the second chip includes a first alignment mark, the circuit board includes a second alignment mark, the second alignment mark is disposed in the mounting groove, and the first alignment mark and the second alignment mark are aligned and engaged.

[0007] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a filling layer, which fills the mounting groove and surrounds the second chip, and the surface of the filling layer is not higher than the first surface.

[0008] As a further improvement of one embodiment of the present invention, the size of the first chip is larger than the size of the second chip, the first chip has a vertical projection area on the circuit board, and the second chip is located within the vertical projection area.

[0009] As a further improvement of one embodiment of the present invention, the first chip includes a first pad, the circuit board includes a second soldering area, the second soldering area is disposed on the first surface, the first pad is electrically connected to the second soldering area, and the first soldering area and the second soldering area are electrically connected.

[0010] As a further improvement of one embodiment of the present invention, the first chip includes a first functional surface and a first non-functional surface, the first pad is disposed on the third functional surface, the third functional surface is away from the circuit board, and the third non-functional surface is connected to the circuit board.

[0011] As a further improvement of one embodiment of the present invention, the third chip includes a functional area and a dam surrounding the functional area, the first pad is disposed outside the dam, the chip packaging structure includes a cover plate, the cover plate is bonded to the dam, and the cover plate is located on the side of the first chip away from the circuit board.

[0012] As a further improvement of one embodiment of the present invention, the first chip is an image sensor chip, and the second chip is a logic chip and / or a memory chip.

[0013] As a further improvement of one embodiment of the present invention, the circuit board is provided with a third soldering area on the side opposite to the first chip, and the third soldering area is used for electrical connection to an external circuit. Compared with the prior art, the present invention provides a chip packaging structure in which a first chip is disposed on the first side of a circuit board and electrically connected to the circuit board, a second chip is disposed in a mounting slot of the circuit board, a second pad faces the bottom surface of the mounting slot and is electrically connected to the first soldering area, and the second chip is located in the mounting slot along the height direction, thereby reducing space occupation and reducing the size of the chip packaging structure. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the chip packaging structure in one embodiment of the present invention.

[0015] Figure 2 This is a schematic diagram of a circuit board provided in one embodiment of the present invention.

[0016] Figure 3 This is a schematic diagram illustrating the steps of setting the second chip on the circuit board in one embodiment of the present invention.

[0017] Figure 4 This is a schematic diagram illustrating the steps of setting the first chip on the circuit board in one embodiment of the present invention.

[0018] Figure 5This is a schematic diagram of the steps of bonding the first chip to the circuit board in one embodiment of the present invention.

[0019] Figure 6 This is a schematic diagram of the steps for manufacturing the molding layer and the third welding area in one embodiment of this utility model. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present invention.

[0021] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.

[0023] Please see Figure 1 This is a schematic diagram of a chip packaging structure 100 provided in an embodiment of the present invention.

[0024] The chip packaging structure 100 includes: a first chip 10; The circuit board 30 is electrically connected to the first chip 10. The circuit board 30 includes a first surface 31, a mounting groove 32 and a first soldering area 33. The mounting groove 32 is recessed from the first surface 31. The first soldering area 33 is disposed on the bottom surface 321 of the mounting groove 32. The first chip 10 is disposed on the first surface 31. At least one second chip 20 is disposed in the mounting slot 32. The second chip 20 includes a second functional surface 22 and a second pad 21. The second pad 21 is disposed on the second functional surface 22. The second functional surface 22 is opposite to the bottom surface 321 of the mounting slot. The second pad 21 is electrically connected to the first soldering area 33. The second chip 20 is located in the mounting slot along the height direction, which reduces the space occupied and the package size of the chip package structure 100, which is beneficial to the miniaturization and thinning of the chip package structure 100.

[0025] Specifically, when the first chip 10 and the second chip 20 are integrated into a package, a two-dimensional planar integrated packaging mode is not required, reducing the length and width dimensions of the chip package structure 100 in the horizontal direction. The circuit board 10 is provided with a mounting slot 32, and the second chip 20 is placed in the mounting slot 32, reducing the vertical space occupied when stacked vertically and reducing the height dimension of the chip package structure 100. The bottom surface 321 of the mounting slot 32 is provided with a first soldering area 33, and the second solder pad 21 of the second chip 20 faces the first soldering area 33 and is electrically connected to the first soldering area 33. In other words, the second chip 20 is flip-chip mounted in the mounting slot 32, and the second chip 20 does not need to lead out an electrical connection structure upward, reducing space occupation, saving installation space for other devices, reducing the size of the chip package structure 100, and improving the compactness of the chip package structure 100.

[0026] In one embodiment, the first chip 10 is an image sensing chip, and the second chip 20 is a logic chip and / or a memory chip. When the chip package structure 100 includes only one second chip 20, the second chip 20 is selected as either a logic chip or a memory chip according to actual needs. When the chip package structure 100 includes two or more second chips 20, the second chip 20 is selected as a combination of logic chips and memory chips according to actual needs.

[0027] In other embodiments, the first chip 10 and the second chip 20 can be selected from other chip types, as long as they need to be integrated together to form a multifunctional chip package structure 100.

[0028] In a specific embodiment, when the chip package structure 100 includes two second chips 20, the two second chips 20 are arranged at intervals and flip-chip disposed in the mounting slot 32, and the two second chips 30 are respectively connected to the first soldering area 33. It can be understood that two or more second chips 20, even if they are of different types, can be mounted in the mounting slot 32 using the same mounting process.

[0029] The surface of the second chip 20 facing away from the second pad 21 is not higher than the first surface 31, reducing the space occupied along the height direction and reducing the height dimension of the chip package structure 100. The second chip 20 does not need to lead out electrical connection structures from the surface facing away from the second pad 21, and the surface of the second chip 20 facing away from the second pad 21 does not protrude from the first surface 31, thus occupying only the space of the mounting slot 32, and the second chip 20 does not occupy any space outside the mounting slot 32.

[0030] When the second chip 20 is flip-mounted in the mounting slot 32, the second pad 21 of the second chip 20 is connected to the first soldering area 33 through solder balls, which can be gold balls or solder balls.

[0031] The second chip 20 includes a first alignment mark, and the circuit board 30 includes a second alignment mark. The second alignment mark is disposed in the mounting groove 32. The first alignment mark and the second alignment mark are aligned and cooperate to improve the accuracy of the electrical connection between the second chip 20 and the first soldering area 33.

[0032] It is understandable that when the second chip 20 is flip-mounted in the mounting slot 32, there are certain requirements for the flip-mounting position. The second pad 21 should be accurately aligned and connected with the first soldering area 31 to ensure the stability of the electrical connection.

[0033] In one embodiment, when at least two second chips 20 are installed in the same mounting slot 32, each second chip 20 is provided with a first alignment mark, and the circuit board 30 is provided with a second alignment mark in the mounting slot 32 corresponding to the first alignment mark of each second chip, so that the two second chips 20 are installed upside down in the accurate position of the mounting slot 32, preventing installation errors from causing functional malfunctions.

[0034] The chip packaging structure 100 includes a filler layer 40, which fills the mounting groove 32 and surrounds the second chip 20. The surface of the filler layer 40 is not higher than the first surface 31, protecting the internal structure of the mounting groove 32 and ensuring the stability of the second chip 20 structure within the mounting groove 32. In a specific embodiment, the surface of the filler layer 40 is preferably flush with the first surface 31 to facilitate the subsequent connection and fixation of the first chip 10 and the circuit board 30.

[0035] When the second chip 20 is flipped onto the bottom surface 321, the second pad 21 and the first soldering area 33 are connected by solder balls. The solder balls usually have a certain height, so that there is a certain gap between the second functional surface 22 and the bottom surface 321. The filling layer 40 fills the gap to ensure the stability of the electrical connection between the second pad 21, the solder balls and the first soldering area 33.

[0036] The size of the first chip 10 is larger than that of the second chip 20. The first chip 10 has a vertical projection area on the circuit board 30, and the second chip 20 is located within the vertical projection area, thereby improving the compactness of the chip package structure 100.

[0037] In one embodiment, at least one second chip 20 is mounted in a mounting slot 32, and the size of the first chip 10 is larger than the size of the mounting slot 32. The entire mounting slot 32 is located within the vertical projection area of ​​the first chip 10. After the first chip 10 is placed on the first surface 31, it can just cover the mounting slot 32, thus completely concealing the mounting slot 32.

[0038] In other embodiments, the size of the first chip 10 is smaller than the size of the mounting slot 32, the second chip 20 is located within the vertical projection area of ​​the first chip 10, and the surrounding area of ​​the mounting slot 32 is not covered by the first chip 10.

[0039] The first chip 10 includes a first pad 11, and the circuit board 30 includes a second soldering area 34. The second soldering area 34 is disposed on the first surface 31. The first pad 11 is electrically connected to the second soldering area 34, and the first soldering area and the second soldering area 34 are electrically connected.

[0040] The first soldering area 34 and the second soldering area 34 are formed on the same redistribution layer and are electrically connected. The first soldering area 33 is located on the bottom surface 321 of the mounting groove 32, and the second soldering area 34 is located on the second surface. The first soldering area 33 is used to electrically connect to the second chip 20, and the second soldering area 34 is used to electrically connect to the first chip 10. The first chip 10 and the second chip 20 realize signal transmission through the circuit board 30. There is no need to set an electrical connection structure between the first chip 10 and the second chip 20, which simplifies the structure and optimizes the process.

[0041] The first chip 10 includes a first functional surface and a first non-functional surface. The first pad 11 is disposed on the first functional surface. The first functional surface is away from the circuit board 30. The first non-functional surface is connected to the circuit board 30 to realize the bonding connection between the first chip 10 and the circuit board 30.

[0042] In one embodiment, the first pad 11 can be electrically connected to the second soldering area 34 via wire bonding. The second soldering area 34 is located on the outer periphery of the first chip 10 and is exposed outward, which facilitates wire bonding between the first pad 11 and the second soldering area 34.

[0043] In one embodiment, the first pad 11 is electrically connected to the second soldering area 34 via a through-silicon via (TSV) process. The second soldering area 34 corresponds to the first pad 11 along the height direction. The second soldering area 34 is covered by the first chip 10. The first chip 10 performs TSV and redistribution in advance on the corresponding first pad 11, thereby forming an electrical connection pad on the first non-functional surface of the first chip 10. The electrical connection pad is electrically connected to the first pad 11 and the second soldering area 34.

[0044] The first non-functional surface is connected to the surface of the first surface 31 and the filler layer 40 via adhesive 50. When the first pad 11 and the second solder area 34 are wire bonded, the adhesive 50 is an insulating adhesive. When the first pad 11 is electrically connected to the second solder area 34 via a through-silicon via (TSV) process, the corresponding electrical connection pad and the second solder area 34 can be bonded together using conductive adhesive. The first chip 10 includes a functional area 12 and a dam 13 surrounding the functional area 12. The first pad 11 is disposed outside the dam 13. The chip package structure 100 includes a cover plate 14, which is bonded to the dam 13. The cover plate 14 is located on the side of the first chip 10 away from the circuit board 30.

[0045] Specifically, the first chip 10 is an image sensor chip, the functional area 12 is a photosensitive area, and the cover plate 14 is a transparent cover plate for transmitting specific light. The functional area 12, the dam 13, and the cover plate 14 are all disposed away from the circuit board 30. In other embodiments, when the first chip 10 is another type of chip, the dam 13 and the cover plate 14 may not be required.

[0046] The circuit board 30 has a third soldering area 35 on the side opposite to the first chip 10. The third soldering area 35 is used for electrical connection to an external circuit so that both the first chip 10 and the second chip 20 are connected to the external circuit. The chip package structure 100 includes solder balls disposed in the third soldering area 35. The solder balls are preferably tin balls, and the solder balls connect the third soldering area and the external circuit.

[0047] The chip package structure 100 includes a molding layer 60, which molds and protects the first chip 10 and the circuit board 30, as well as the bonding wires, to ensure the stability of the electrical connection between the first chip 10 and the circuit board 30.

[0048] The following will combine Figure 2-6 The packaging method of chip package structure 100 is described in detail.

[0049] Reference Figure 2A circuit board 30 is provided, the circuit board 30 having a first surface 31, a mounting groove 32 and a first soldering area 33, the mounting groove 32 being recessed from the first surface 31, and the first soldering area 33 being disposed on the bottom surface 321 of the mounting groove 32; equivalently, a customized version of the circuit board 30 with the mounting groove 32 is provided.

[0050] The circuit board 30 includes a second soldering area 34, which is formed on the first surface 31. The first soldering area 33 and the second soldering area 34 are formed on the same redistribution layer, and the first soldering area 33 and the second soldering area 34 are electrically connected.

[0051] The circuit board 30 has a third soldering area 35 on the side opposite to the first soldering area 33. The third soldering area 35 is used for electrical connection to an external circuit. The first soldering area 33, the second soldering area 34, and the third soldering area 35 are electrically connected so that the electrical signals of the first chip 10 and the second chip 20 can be simultaneously connected to the external circuit through the circuit board 30.

[0052] Reference Figure 3 A second chip 20 is provided, the second chip 20 includes a second functional surface 22 and a second pad 21, the second pad 21 being disposed on the second functional surface 22; The second chip 20 is mounted in the mounting slot 32, with the second functional surface 22 facing the bottom surface 321 of the mounting slot, and the second pad 21 electrically connected to the first soldering area 33; in other words, the second chip 20 is flip-chip mounted in the mounting slot 32, so that the second chip 20 does not need to be led out to the top for electrical connection structure, reducing space occupation, reducing the size of the chip package structure 100, and improving the compactness of the chip package structure 100.

[0053] Specifically, the second pad 21 is electrically connected to the first soldering area 33 via solder balls, which can be either tin balls or gold balls and have excellent conductivity.

[0054] When the second chip 20 is installed in the mounting slot 32, the second chip includes a first alignment mark, and the circuit board includes a second alignment mark set in the mounting slot. The first alignment mark and the second alignment mark are aligned and matched to ensure that the second chip 20 is accurately flipped into the mounting slot 32.

[0055] After the second chip 20 is installed in the mounting slot 32, the steps include: making a filling layer 40 in the mounting slot 32, the filling layer 40 covering the second chip 20, thereby improving the stability of the electrical connection between the second chip 20 and the circuit board 30.

[0056] Reference Figure 4-5A first chip 10 is provided and electrically connected to a circuit board 30; thus, the first chip 10 and the second chip 20 are integrated on the circuit board 30, and the package size of the chip package structure 100 is reduced. In a specific embodiment, the first chip 10 is an image sensor chip, and the second chip 20 is a memory chip and / or a logic chip.

[0057] Electrically connecting the first chip 10 to the circuit board 30 includes the step of: electrically connecting the first pad 11 to the second soldering area 34 of the circuit board 30 via wire bonding or through-silicon via (TSV) technology. The first chip 10 includes a first pad 11 and a first functional surface, with the first pad 11 disposed on the first functional surface, and both the first functional surface and the first pad 11 facing away from the circuit board 30. The first chip 10 is directly connected to the circuit board 30, and the second chip 20 is also directly connected to the circuit board 30; no separate electrical connection structure is required between the first chip 10 and the second chip 20.

[0058] Before electrically connecting the first chip 10 to the circuit board 30, the process includes: fixing the first chip 10 to the circuit board 30; the first chip 10 has a first non-functional surface, the first non-functional surface and the first functional surface are disposed opposite to each other, and the first non-functional surface is connected to the surface of the first surface 31 and the filler layer 40 by adhesive 50. In this way, the first chip 10 and the circuit board 30 are fixedly connected first, and then the first pad 11 and the second soldering area 34 are wire bonded.

[0059] Before electrically connecting the first chip 10 to the circuit board 30, the following steps are included: forming a dam 13 on the first functional surface of the first chip 10, with the functional area 12 located inside the dam 13 and the first pad 11 located outside the dam 13. A cover plate 14 is provided, and a dam 13 is connected to the cover plate 14. A sealed cavity is formed between the cover plate 14, the dam 13 and the first chip 10, and the functional area 12 is located in the sealed cavity.

[0060] The process involves first encapsulating the first chip 10 and the cover plate 14, and then mounting the first chip 10 and the cover plate 14 together onto the circuit board 30.

[0061] Reference Figure 6 A molding compound 60 is fabricated to encapsulate the first chip 10 and the circuit board 30. The molding compound 60 covers the upper surface of the circuit board 30 and the outer peripheral surface of the first chip 10. Solder balls are fabricated in the third soldering area 35 of the circuit board 30 for electrical connection with external circuits.

[0062] The beneficial effects of this utility model are as follows: the first chip 10 is electrically connected to the circuit board 30, the second chip 20 is electrically connected to the circuit board 30, the first chip 10 and the second chip 20 are integrated on the circuit board 30, the second chip 20 is flip-chip disposed in the mounting slot 32 of the circuit board 30, the second chip 20 does not need to be led out to the top for electrical connection structure, reducing space occupation and reducing the size of the chip package structure 100; the surface of the second chip 20 facing away from the second pad 21 is not higher than the first surface 31, the second chip 20 is completely located in the mounting slot 32, and does not occupy any space outside the mounting slot 32.

[0063] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.

[0064] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0065] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this utility model, and are not intended to limit the scope of protection of this utility model. All equivalent implementations or modifications made without departing from the spirit of this utility model should be included within the scope of protection of this utility model.

Claims

1. A chip packaging structure, characterized in that, include: First chip; The circuit board is electrically connected to the first chip; the circuit board includes a first surface, a mounting groove and a first soldering area, the mounting groove is recessed from the first surface, the first soldering area is disposed on the bottom surface of the mounting groove, and the first chip is disposed on the first surface; At least one second chip is disposed in the mounting slot. The second chip includes a second functional surface and a second pad. The second pad is disposed on the second functional surface, which is opposite to the bottom surface of the mounting slot. The second pad is electrically connected to the first soldering area.

2. The chip packaging structure according to claim 1, characterized in that, The surface of the second chip facing away from the second pad is not higher than the first surface.

3. The chip packaging structure according to claim 1, characterized in that, The second chip includes a first alignment mark, and the circuit board includes a second alignment mark. The second alignment mark is disposed in the mounting slot, and the first alignment mark and the second alignment mark are aligned and engaged.

4. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure includes a filling layer that fills the mounting groove and surrounds the second chip, wherein the surface of the filling layer is not higher than the first surface.

5. The chip packaging structure according to claim 1, characterized in that, The size of the first chip is larger than the size of the second chip, the first chip has a vertical projection area on the circuit board, and the second chip is located within the vertical projection area.

6. The chip packaging structure according to claim 1, characterized in that, The first chip includes a first pad, the circuit board includes a second soldering area, the second soldering area is disposed on the first surface, the first pad is electrically connected to the second soldering area, and the first soldering area and the second soldering area are electrically connected.

7. The chip packaging structure according to claim 6, characterized in that, The first chip includes a first functional surface and a first non-functional surface. The first pad is disposed on the first functional surface, the first functional surface is away from the circuit board, and the first non-functional surface is connected to the circuit board.

8. The chip packaging structure according to claim 6, characterized in that, The first chip includes a functional area and a barrier surrounding the functional area. The first pad is disposed outside the barrier. The chip packaging structure includes a cover plate, which is bonded to the barrier. The cover plate is located on the side of the first chip away from the circuit board.

9. The chip packaging structure according to claim 1, characterized in that, The first chip is an image sensor chip, and the second chip is a logic chip and / or a memory chip.

10. The chip packaging structure according to claim 1, characterized in that, The circuit board has a third soldering area on the side opposite to the first chip, and the third soldering area is used for electrical connection to an external circuit.

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